C8051F380/1/2/3/4/5/6/7/C
Full Speed USB Flash MCU Family
Analog Peripherals
- 10-Bit ADC (C8051F380/1/2/3/C only)
• Up to 500 ksps
• Built-in analog multiplexer with single-ended and
instructions in 1 or 2 system clocks
differential mode
VREF from external pin, internal reference, or VDD
Built-in temperature sensor
External conversion start input option
- Two comparators
- Internal voltage reference (C8051F380/1/2/3/C only)
- Brown-out detector and POR Circuitry
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intru-
-
ANALOG
PERIPHERALS
TEMP
SENSOR
+
-
enhanced UART serial ports
Six general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five capture/compare modules
External Memory Interface (EMIF)
Clock Sources
- Internal Oscillator: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
Low Frequency (80 kHz) Internal Oscillator
Can switch between clock sources on-the-fly
Packages
- 48-pin TQFP (C8051F380/2/4/6)
- 32-pin LQFP (C8051F381/3/5/7/C)
- 5x5 mm 32-pin QFN (C8051F381/3/5/7/C)
Temperature Range: –40 to +85 °C
Voltage Regulators
10-bit
500 ksps
ADC
-
-
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 2.7 to 5.25 V supported using On-Chip
A
M
U
X
512-byte sectors
Digital Peripherals
- 40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, two I2C/SMBus™, and two
+
-
VREG
VREF
DIGITAL I/O
UART0
UART1
SPI
SMBus0
SMBus1
PCA
6 Timers
Port 0
CROSSBAR
-
sive in-system debug (No emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Up to 48 MIPS operation
- Expanded interrupt handler
Memory
- 4352 or 2304 Bytes RAM
- 64, 32, or 16 kB Flash; In-system programmable in
48 Pin Only
Ext. Memory I/F
•
•
•
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
Port 1
Port 2
Port 3
Port 4
C8051F380/1/2/3 Only
PRECISION INTERNAL
OSCILLATORS
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
Rev. 1.5 3/19
8051 CPU
48 MIPS
DEBUG
CIRCUITRY
4/2 kB RAM
POR
Copyright © 2019 by Silicon Laboratories
WDT
C8051F380/1/2/3/4/5/6/7/C
C8051F380/1/2/3/4/5/6/7/C
2
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table of Contents
1. System Overview ..................................................................................................... 16
2. C8051F34x Compatibility ........................................................................................ 20
2.1. Hardware Incompatibilities ................................................................................ 21
3. Pinout and Package Definitions ............................................................................. 22
4. Typical Connection Diagrams ................................................................................ 34
4.1. Power ............................................................................................................ 34
4.2. USB
............................................................................................................ 36
4.3. Voltage Reference (VREF)................................................................................ 36
5. Electrical Characteristics ........................................................................................ 37
5.1. Absolute Maximum Specifications..................................................................... 37
5.2. Electrical Characteristics ................................................................................... 38
6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only) ......................................................... 46
6.1. Output Code Formatting .................................................................................... 47
6.3. Modes of Operation ........................................................................................... 50
6.3.1. Starting a Conversion................................................................................ 50
6.3.2. Tracking Modes......................................................................................... 51
6.3.3. Settling Time Requirements...................................................................... 52
6.4. Programmable Window Detector....................................................................... 56
6.4.1. Window Detector Example........................................................................ 58
6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only) ........................................ 59
7. Voltage Reference Options ..................................................................................... 62
8. Comparator0 and Comparator1.............................................................................. 64
8.1. Comparator Multiplexers ................................................................................... 71
9. Voltage Regulators (REG0 and REG1)................................................................... 74
9.1. Voltage Regulator (REG0)................................................................................. 74
9.1.1. Regulator Mode Selection......................................................................... 74
9.1.2. VBUS Detection ........................................................................................ 74
9.2. Voltage Regulator (REG1)................................................................................. 74
10. Power Management Modes................................................................................... 76
10.1. Idle Mode......................................................................................................... 76
10.2. Stop Mode ....................................................................................................... 77
10.3. Suspend Mode ................................................................................................ 77
11. CIP-51 Microcontroller........................................................................................... 79
11.1. Instruction Set.................................................................................................. 80
11.1.1. Instruction and CPU Timing .................................................................... 80
11.2. CIP-51 Register Descriptions .......................................................................... 85
12. Prefetch Engine...................................................................................................... 88
13. Memory Organization ............................................................................................ 89
13.1. Program Memory............................................................................................. 91
13.2. Data Memory ................................................................................................... 91
13.3. General Purpose Registers ............................................................................. 92
13.4. Bit Addressable Locations ............................................................................... 92
13.5. Stack ............................................................................................................ 92
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3
C8051F380/1/2/3/4/5/6/7/C
14. External Data Memory Interface and On-Chip XRAM ......................................... 93
14.1. Accessing XRAM............................................................................................. 93
14.1.1. 16-Bit MOVX Example ............................................................................ 93
14.1.2. 8-Bit MOVX Example .............................................................................. 93
14.2. Accessing USB FIFO Space ........................................................................... 94
14.3. Configuring the External Memory Interface ..................................................... 95
14.4. Port Configuration............................................................................................ 95
14.5. Multiplexed and Non-multiplexed Selection..................................................... 98
14.5.1. Multiplexed Configuration........................................................................ 98
14.5.2. Non-multiplexed Configuration................................................................ 98
14.6. Memory Mode Selection................................................................................ 100
14.6.1. Internal XRAM Only .............................................................................. 100
14.6.2. Split Mode without Bank Select............................................................. 100
14.6.3. Split Mode with Bank Select.................................................................. 101
14.6.4. External Only......................................................................................... 101
14.7. Timing .......................................................................................................... 102
14.7.1. Non-multiplexed Mode .......................................................................... 104
14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 104
14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 105
14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 106
14.7.2. Multiplexed Mode .................................................................................. 107
14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 107
14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 108
14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 109
15. Special Function Registers................................................................................. 111
15.1. 13.1. SFR Paging .......................................................................................... 111
16. Interrupts .............................................................................................................. 118
16.1. MCU Interrupt Sources and Vectors.............................................................. 119
16.1.1. Interrupt Priorities.................................................................................. 119
16.1.2. Interrupt Latency ................................................................................... 119
16.2. Interrupt Register Descriptions ...................................................................... 119
16.3. INT0 and INT1 External Interrupt Sources .................................................... 127
17. Reset Sources ...................................................................................................... 129
17.1. Power-On Reset ............................................................................................ 130
17.2. Power-Fail Reset / VDD Monitor ................................................................... 131
17.3. External Reset ............................................................................................... 132
17.4. Missing Clock Detector Reset ....................................................................... 132
17.5. Comparator0 Reset ....................................................................................... 132
17.6. PCA Watchdog Timer Reset ......................................................................... 133
17.7. Flash Error Reset .......................................................................................... 133
17.8. Software Reset .............................................................................................. 133
17.9. USB Reset..................................................................................................... 133
18. Flash Memory....................................................................................................... 135
18.1. Programming The Flash Memory .................................................................. 135
18.1.1. Flash Lock and Key Functions .............................................................. 135
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C8051F380/1/2/3/4/5/6/7/C
18.1.2. Flash Erase Procedure ......................................................................... 135
18.1.3. Flash Write Procedure .......................................................................... 136
18.2. Non-Volatile Data Storage............................................................................. 137
18.3. Security Options ............................................................................................ 137
19. Oscillators and Clock Selection ......................................................................... 142
19.1. System Clock Selection................................................................................. 143
19.2. USB Clock Selection ..................................................................................... 143
19.3. Programmable Internal High-Frequency (H-F) Oscillator .............................. 145
19.3.1. Internal Oscillator Suspend Mode ......................................................... 145
19.4. Clock Multiplier .............................................................................................. 147
19.5. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 148
19.5.1. Calibrating the Internal L-F Oscillator.................................................... 148
19.6. External Oscillator Drive Circuit..................................................................... 149
19.6.1. External Crystal Mode........................................................................... 149
19.6.2. External RC Example............................................................................ 151
19.6.3. External Capacitor Example.................................................................. 151
20. Port Input/Output ................................................................................................. 153
20.1. Priority Crossbar Decoder ............................................................................. 154
20.2. Port I/O Initialization ...................................................................................... 158
20.3. General Purpose Port I/O .............................................................................. 161
21. Universal Serial Bus Controller (USB0) ............................................................. 172
21.1. Endpoint Addressing ..................................................................................... 172
21.2. USB Transceiver ........................................................................................... 173
21.3. USB Register Access .................................................................................... 175
21.4. USB Clock Configuration............................................................................... 179
21.5. FIFO Management ........................................................................................ 181
21.5.1. FIFO Split Mode .................................................................................... 181
21.5.2. FIFO Double Buffering .......................................................................... 182
21.5.1. FIFO Access ......................................................................................... 182
21.6. Function Addressing...................................................................................... 183
21.7. Function Configuration and Control............................................................... 183
21.8. Interrupts ....................................................................................................... 186
21.9. The Serial Interface Engine ........................................................................... 193
21.10. Endpoint0 .................................................................................................... 193
21.10.1. Endpoint0 SETUP Transactions ......................................................... 193
21.10.2. Endpoint0 IN Transactions.................................................................. 193
21.10.3. Endpoint0 OUT Transactions.............................................................. 194
21.11. Configuring Endpoints1-3 ............................................................................ 196
21.12. Controlling Endpoints1-3 IN......................................................................... 197
21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode.............................................. 197
21.12.2. Endpoints1-3 IN Isochronous Mode.................................................... 198
21.13. Controlling Endpoints1-3 OUT..................................................................... 201
21.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode.......................................... 201
21.13.2. Endpoints1-3 OUT Isochronous Mode................................................ 201
22. SMBus0 and SMBus1 (I2C Compatible)............................................................. 205
Rev. 1.5
5
C8051F380/1/2/3/4/5/6/7/C
22.1. Supporting Documents .................................................................................. 206
22.2. SMBus Configuration..................................................................................... 206
22.3. SMBus Operation .......................................................................................... 206
22.3.1. Transmitter Vs. Receiver....................................................................... 207
22.3.2. Arbitration.............................................................................................. 207
22.3.3. Clock Low Extension............................................................................. 207
22.3.4. SCL Low Timeout.................................................................................. 207
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 208
22.4. Using the SMBus........................................................................................... 208
22.4.1. SMBus Configuration Register.............................................................. 208
22.4.2. SMBus Timing Control Register............................................................ 210
22.4.3. SMBnCN Control Register .................................................................... 214
22.4.3.1. Software ACK Generation ............................................................ 214
22.4.3.2. Hardware ACK Generation ........................................................... 214
22.4.4. Hardware Slave Address Recognition .................................................. 217
22.4.5. Data Register ........................................................................................ 221
22.5. SMBus Transfer Modes................................................................................. 223
22.5.1. Write Sequence (Master) ...................................................................... 223
22.5.2. Read Sequence (Master) ...................................................................... 224
22.5.3. Write Sequence (Slave) ........................................................................ 225
22.5.4. Read Sequence (Slave) ........................................................................ 226
22.6. SMBus Status Decoding................................................................................ 226
23. UART0 ................................................................................................................... 232
23.1. Enhanced Baud Rate Generation.................................................................. 233
23.2. Operational Modes ........................................................................................ 234
23.2.1. 8-Bit UART ............................................................................................ 234
23.2.2. 9-Bit UART ............................................................................................ 235
23.3. Multiprocessor Communications ................................................................... 236
24. UART1 ................................................................................................................... 240
24.1. Baud Rate Generator .................................................................................... 241
24.2. Data Format................................................................................................... 242
24.3. Configuration and Operation ......................................................................... 243
24.3.1. Data Transmission ................................................................................ 243
24.3.2. Data Reception ..................................................................................... 243
24.3.3. Multiprocessor Communications ........................................................... 244
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 250
25.1. Signal Descriptions........................................................................................ 251
25.1.1. Master Out, Slave In (MOSI)................................................................. 251
25.1.2. Master In, Slave Out (MISO)................................................................. 251
25.1.3. Serial Clock (SCK) ................................................................................ 251
25.1.4. Slave Select (NSS) ............................................................................... 251
25.2. SPI0 Master Mode Operation ........................................................................ 251
25.3. SPI0 Slave Mode Operation .......................................................................... 253
25.4. SPI0 Interrupt Sources .................................................................................. 254
25.5. Serial Clock Phase and Polarity .................................................................... 254
6
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
25.6. SPI Special Function Registers ..................................................................... 256
26. Timers ................................................................................................................... 263
26.1. Timer 0 and Timer 1 ...................................................................................... 266
26.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 266
26.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 267
26.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 267
26.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 268
26.2. Timer 2 .......................................................................................................... 274
26.2.1. 16-bit Timer with Auto-Reload............................................................... 274
26.2.2. 8-bit Timers with Auto-Reload............................................................... 275
26.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ..... 275
26.3. Timer 3 .......................................................................................................... 281
26.3.1. 16-bit Timer with Auto-Reload............................................................... 281
26.3.2. 8-bit Timers with Auto-Reload............................................................... 282
26.3.3. Timer 3 Capture Modes: USB Start-of-Frame or LFO Falling Edge ..... 282
26.4. Timer 4 .......................................................................................................... 288
26.4.1. 16-bit Timer with Auto-Reload............................................................... 288
26.4.2. 8-bit Timers with Auto-Reload............................................................... 289
26.5. Timer 5 .......................................................................................................... 293
26.5.1. 16-bit Timer with Auto-Reload............................................................... 293
26.5.2. 8-bit Timers with Auto-Reload............................................................... 294
27. Programmable Counter Array............................................................................. 298
27.1. PCA Counter/Timer ....................................................................................... 299
27.2. PCA0 Interrupt Sources................................................................................. 300
27.3. Capture/Compare Modules ........................................................................... 301
27.3.1. Edge-triggered Capture Mode............................................................... 302
27.3.2. Software Timer (Compare) Mode.......................................................... 303
27.3.3. High-Speed Output Mode ..................................................................... 304
27.3.4. Frequency Output Mode ....................................................................... 305
27.3.5. 8-bit Pulse Width Modulator Mode ....................................................... 306
27.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 307
27.4. Watchdog Timer Mode .................................................................................. 308
27.4.1. Watchdog Timer Operation ................................................................... 308
27.4.2. Watchdog Timer Usage ........................................................................ 309
27.5. Register Descriptions for PCA0..................................................................... 311
28. C2 Interface .......................................................................................................... 316
28.1. C2 Interface Registers................................................................................... 316
28.2. C2 Pin Sharing .............................................................................................. 319
Document Change List.............................................................................................. 320
Contact Information................................................................................................... 321
Rev. 1.5
7
C8051F380/1/2/3/4/5/6/7/C
List of Figures
Figure 1.1. C8051F380/2/4/6 Block Diagram .......................................................... 18
Figure 1.2. C8051F381/3/5/7/C Block Diagram ....................................................... 19
Figure 3.1. TQFP-48 Pinout Diagram (Top View) ................................................... 25
Figure 3.2. TQFP-48 Package Diagram .................................................................. 26
Figure 3.3. TQFP-48 Recommended PCB Land Pattern ........................................ 27
Figure 3.4. LQFP-32 Pinout Diagram (Top View) .................................................... 28
Figure 3.5. LQFP-32 Package Diagram .................................................................. 29
Figure 3.6. LQFP-32 Recommended PCB Land Pattern ........................................ 30
Figure 3.7. QFN-32 Pinout Diagram (Top View) ..................................................... 31
Figure 3.8. QFN-32 Package Drawing .................................................................... 32
Figure 3.9. QFN-32 Recommended PCB Land Pattern .......................................... 33
Figure 4.1. Connection Diagram with Voltage Regulator Used and No USB .......... 34
Figure 4.2. Connection Diagram with Voltage Regulator Not Used and No USB ... 34
Figure 4.3. Connection Diagram with Voltage Regulator Used and USB Connected
(Bus-Powered) ................................................................................................... 35
Figure 4.4. Connection Diagram with Voltage Regulator Used and USB Connected
(Self-Powered) ................................................................................................... 35
Figure 4.5. Connection Diagram for USB Pins ........................................................ 36
Figure 4.6. Connection Diagram for Internal Voltage Reference ............................. 36
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 46
Figure 6.2. Typical Temperature Sensor Transfer Function .................................... 48
Figure 6.3. Temperature Sensor Error with 1-Point Calibration .............................. 49
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing ............................. 51
Figure 6.5. ADC0 Equivalent Input Circuits ............................................................. 52
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 58
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 58
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 62
Figure 8.1. Comparator0 Functional Block Diagram ............................................... 64
Figure 8.2. Comparator1 Functional Block Diagram ............................................... 65
Figure 8.3. Comparator Hysteresis Plot .................................................................. 66
Figure 8.4. Comparator Input Multiplexer Block Diagram ........................................ 71
Figure 11.1. CIP-51 Block Diagram ......................................................................... 79
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F380/1/4/5) ............. 89
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F382/3/6/7) ............. 90
Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C) ..................... 91
Figure 14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ ... 94
Figure 14.2. Multiplexed Configuration Example ..................................................... 98
Figure 14.3. Non-multiplexed Configuration Example ............................................. 99
Figure 14.4. EMIF Operating Modes ..................................................................... 100
Figure 14.5. Non-Multiplexed 16-bit MOVX Timing ............................................... 104
Figure 14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 105
Figure 14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 106
Figure 14.8. Multiplexed 16-bit MOVX Timing ....................................................... 107
Rev. 1.5
8
C8051F380/1/2/3/4/5/6/7/C
Figure 14.9. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 108
Figure 14.10. Multiplexed 8-bit MOVX with Bank Select Timing ........................... 109
Figure 17.1. Reset Sources ................................................................................... 129
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 130
Figure 18.1. Flash Program Memory Map and Security Byte ................................ 137
Figure 19.1. Oscillator Options .............................................................................. 142
Figure 19.2. External Crystal Example .................................................................. 150
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 153
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 154
Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 155
Figure 20.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped) ............................................................................................ 156
Figure 20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
............................................................................................................. 157
Figure 21.1. USB0 Block Diagram ......................................................................... 172
Figure 21.2. USB0 Register Access Scheme ........................................................ 175
Figure 21.3. USB FIFO Allocation ......................................................................... 181
Figure 22.1. SMBus Block Diagram ...................................................................... 205
Figure 22.2. Typical SMBus Configuration ............................................................ 206
Figure 22.3. SMBus Transaction ........................................................................... 207
Figure 22.4. Typical SMBus SCL Generation ........................................................ 209
Figure 22.5. Typical Master Write Sequence ........................................................ 223
Figure 22.6. Typical Master Read Sequence ........................................................ 224
Figure 22.7. Typical Slave Write Sequence .......................................................... 225
Figure 22.8. Typical Slave Read Sequence .......................................................... 226
Figure 23.1. UART0 Block Diagram ...................................................................... 232
Figure 23.2. UART0 Baud Rate Logic ................................................................... 233
Figure 23.3. UART Interconnect Diagram ............................................................. 234
Figure 23.4. 8-Bit UART Timing Diagram .............................................................. 234
Figure 23.5. 9-Bit UART Timing Diagram .............................................................. 235
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 236
Figure 24.1. UART1 Block Diagram ...................................................................... 240
Figure 24.2. UART1 Timing Without Parity or Extra Bit ......................................... 242
Figure 24.3. UART1 Timing With Parity ................................................................ 242
Figure 24.4. UART1 Timing With Extra Bit ............................................................ 242
Figure 24.5. Typical UART Interconnect Diagram ................................................. 243
Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 244
Figure 25.1. SPI Block Diagram ............................................................................ 250
Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 252
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
............................................................................................................. 252
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
............................................................................................................. 253
Figure 25.5. Master Mode Data/Clock Timing ....................................................... 255
Figure 25.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 255
9
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 256
Figure 25.8. SPI Master Timing (CKPHA = 0) ....................................................... 260
Figure 25.9. SPI Master Timing (CKPHA = 1) ....................................................... 260
Figure 25.10. SPI Slave Timing (CKPHA = 0) ....................................................... 261
Figure 25.11. SPI Slave Timing (CKPHA = 1) ....................................................... 261
Figure 26.1. T0 Mode 0 Block Diagram ................................................................. 267
Figure 26.2. T0 Mode 2 Block Diagram ................................................................. 268
Figure 26.3. T0 Mode 3 Block Diagram ................................................................. 269
Figure 26.4. Timer 2 16-Bit Mode Block Diagram ................................................. 274
Figure 26.5. Timer 2 8-Bit Mode Block Diagram ................................................... 275
Figure 26.6. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 276
Figure 26.7. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 277
Figure 26.8. Timer 3 16-Bit Mode Block Diagram ................................................. 281
Figure 26.9. Timer 3 8-Bit Mode Block Diagram ................................................... 282
Figure 26.10. Timer 3 Capture Mode (T3SPLIT = 0) ............................................. 283
Figure 26.11. Timer 3 Capture Mode (T3SPLIT = 0) ............................................. 284
Figure 26.12. Timer 4 16-Bit Mode Block Diagram ............................................... 288
Figure 26.13. Timer 4 8-Bit Mode Block Diagram ................................................. 289
Figure 26.14. Timer 5 16-Bit Mode Block Diagram ............................................... 293
Figure 26.15. Timer 5 8-Bit Mode Block Diagram ................................................. 294
Figure 27.1. PCA Block Diagram ........................................................................... 298
Figure 27.2. PCA Counter/Timer Block Diagram ................................................... 299
Figure 27.3. PCA Interrupt Block Diagram ............................................................ 300
Figure 27.4. PCA Capture Mode Diagram ............................................................. 302
Figure 27.5. PCA Software Timer Mode Diagram ................................................. 303
Figure 27.6. PCA High-Speed Output Mode Diagram ........................................... 304
Figure 27.7. PCA Frequency Output Mode ........................................................... 305
Figure 27.8. PCA 8-Bit PWM Mode Diagram ........................................................ 306
Figure 27.9. PCA 16-Bit PWM Mode ..................................................................... 307
Figure 27.10. PCA Module 4 with Watchdog Timer Enabled ................................ 308
Figure 28.1. Typical C2 Pin Sharing ...................................................................... 319
Rev. 1.5
10
C8051F380/1/2/3/4/5/6/7/C
List of Tables
Table 1.1. Product Selection Guide ......................................................................... 17
Table 2.1. C8051F38x Replacement Part Numbers ................................................ 20
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C ................................. 22
Table 3.2. TQFP-48 Package Dimensions .............................................................. 26
Table 3.3. TQFP-48 PCB Land Pattern Dimensions ............................................... 27
Table 3.4. LQFP-32 Package Dimensions .............................................................. 29
Table 3.5. LQFP-32 PCB Land Pattern Dimensions ............................................... 30
Table 3.6. QFN-32 Package Dimensions ................................................................ 32
Table 3.7. QFN-32 PCB Land Pattern Dimensions ................................................. 33
Table 5.1. Absolute Maximum Ratings .................................................................... 37
Table 5.2. Global Electrical Characteristics ............................................................. 38
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 39
Table 5.4. Reset Electrical Characteristics .............................................................. 39
Table 5.5. Internal Voltage Regulator Electrical Characteristics ............................. 40
Table 5.6. Flash Electrical Characteristics .............................................................. 40
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics ................. 41
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics ................. 41
Table 5.9. External Oscillator Electrical Characteristics .......................................... 41
Table 5.10. ADC0 Electrical Characteristics ............................................................ 42
Table 5.11. Temperature Sensor Electrical Characteristics .................................... 43
Table 5.12. Voltage Reference Electrical Characteristics ....................................... 43
Table 5.13. Comparator Electrical Characteristics .................................................. 44
Table 5.14. USB Transceiver Electrical Characteristics .......................................... 45
Table 11.1. CIP-51 Instruction Set Summary .......................................................... 81
Table 14.1. AC Parameters for External Memory Interface ................................... 110
Table 15.1. Special Function Register (SFR) Memory Map .................................. 112
Table 15.2. Special Function Registers ................................................................. 113
Table 16.1. Interrupt Summary .............................................................................. 120
Table 21.1. Endpoint Addressing Scheme ............................................................ 173
Table 21.2. USB0 Controller Registers ................................................................. 178
Table 21.3. FIFO Configurations ........................................................................... 182
Table 22.1. SMBus Clock Source Selection .......................................................... 209
Table 22.2. Minimum SDA Setup and Hold Times ................................................ 210
Table 22.3. Sources for Hardware Changes to SMBnCN ..................................... 217
Table 22.4. Hardware Address Recognition Examples (EHACK = 1) ................... 218
Table 22.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) ...... 227
Table 22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) ...... 229
Table 23.1. Timer Settings for Standard Baud Rates Using Internal Oscillator ..... 238
Table 24.1. Baud Rate Generator Settings for Standard Baud Rates ................... 241
Table 25.1. SPI Slave Timing Parameters ............................................................ 262
Table 27.1. PCA Timebase Input Options ............................................................. 299
Table 27.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules ............. 301
Table 27.3. Watchdog Timer Timeout Intervals1 ................................................... 310
Rev. 1.5
11
C8051F380/1/2/3/4/5/6/7/C
List of Registers
SFR Definition 6.1. ADC0CF: ADC0 Configuration ...................................................... 53
SFR Definition 6.2. ADC0H: ADC0 Data Word MSB .................................................... 54
SFR Definition 6.3. ADC0L: ADC0 Data Word LSB ...................................................... 54
SFR Definition 6.4. ADC0CN: ADC0 Control ................................................................ 55
SFR Definition 6.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 56
SFR Definition 6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 56
SFR Definition 6.7. ADC0LTH: ADC0 Less-Than Data High Byte ................................ 57
SFR Definition 6.8. ADC0LTL: ADC0 Less-Than Data Low Byte ................................. 57
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select ..................................... 60
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select ................................. 61
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 63
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 67
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 68
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 69
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 70
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 72
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 73
SFR Definition 9.1. REG01CN: Voltage Regulator Control .......................................... 75
SFR Definition 10.1. PCON: Power Control .................................................................. 78
SFR Definition 11.1. DPL: Data Pointer Low Byte ........................................................ 85
SFR Definition 11.2. DPH: Data Pointer High Byte ....................................................... 85
SFR Definition 11.3. SP: Stack Pointer ......................................................................... 86
SFR Definition 11.4. ACC: Accumulator ....................................................................... 86
SFR Definition 11.5. B: B Register ................................................................................ 86
SFR Definition 11.6. PSW: Program Status Word ........................................................ 87
SFR Definition 12.1. PFE0CN: Prefetch Engine Control .............................................. 88
SFR Definition 14.1. EMI0CN: External Memory Interface Control .............................. 96
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration ..................... 97
SFR Definition 14.3. EMI0TC: External Memory TIming Control ................................ 103
SFR Definition 15.1. SFRPAGE: SFR Page ............................................................... 111
SFR Definition 16.1. IE: Interrupt Enable .................................................................... 121
SFR Definition 16.2. IP: Interrupt Priority .................................................................... 122
SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 ............................................ 123
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1 ............................................ 124
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2 ............................................ 125
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2 ............................................ 126
SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO ........................................... 128
SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 132
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 134
SFR Definition 18.1. PSCTL: Program Store R/W Control ......................................... 139
SFR Definition 18.2. FLKEY: Flash Lock and Key ...................................................... 140
SFR Definition 18.3. FLSCL: Flash Scale ................................................................... 141
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 144
Rev. 1.5
12
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration .............................. 145
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control ................................... 146
SFR Definition 19.4. CLKMUL: Clock Multiplier Control ............................................. 147
SFR Definition 19.5. OSCLCN: Internal L-F Oscillator Control ................................... 148
SFR Definition 19.6. OSCXCN: External Oscillator Control ........................................ 152
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 159
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 160
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2 .......................................... 161
SFR Definition 20.4. P0: Port 0 ................................................................................... 162
SFR Definition 20.5. P0MDIN: Port 0 Input Mode ....................................................... 162
SFR Definition 20.6. P0MDOUT: Port 0 Output Mode ................................................ 163
SFR Definition 20.7. P0SKIP: Port 0 Skip ................................................................... 163
SFR Definition 20.8. P1: Port 1 ................................................................................... 164
SFR Definition 20.9. P1MDIN: Port 1 Input Mode ....................................................... 164
SFR Definition 20.10. P1MDOUT: Port 1 Output Mode .............................................. 165
SFR Definition 20.11. P1SKIP: Port 1 Skip ................................................................. 165
SFR Definition 20.12. P2: Port 2 ................................................................................. 166
SFR Definition 20.13. P2MDIN: Port 2 Input Mode ..................................................... 166
SFR Definition 20.14. P2MDOUT: Port 2 Output Mode .............................................. 167
SFR Definition 20.15. P2SKIP: Port 2 Skip ................................................................. 167
SFR Definition 20.16. P3: Port 3 ................................................................................. 168
SFR Definition 20.17. P3MDIN: Port 3 Input Mode ..................................................... 168
SFR Definition 20.18. P3MDOUT: Port 3 Output Mode .............................................. 169
SFR Definition 20.19. P3SKIP: Port 3 Skip ................................................................. 169
SFR Definition 20.20. P4: Port 4 ................................................................................. 170
SFR Definition 20.21. P4MDIN: Port 4 Input Mode ..................................................... 170
SFR Definition 20.22. P4MDOUT: Port 4 Output Mode .............................................. 171
SFR Definition 21.1. USB0XCN: USB0 Transceiver Control ...................................... 174
SFR Definition 21.2. USB0ADR: USB0 Indirect Address ........................................... 176
SFR Definition 21.3. USB0DAT: USB0 Data .............................................................. 177
USB Register Definition 21.4. INDEX: USB0 Endpoint Index ..................................... 179
USB Register Definition 21.5. CLKREC: Clock Recovery Control .............................. 180
USB Register Definition 21.6. FIFOn: USB0 Endpoint FIFO Access .......................... 182
USB Register Definition 21.7. FADDR: USB0 Function Address ............................... 183
USB Register Definition 21.8. POWER: USB0 Power ................................................ 185
USB Register Definition 21.9. FRAMEL: USB0 Frame Number Low ......................... 186
USB Register Definition 21.10. FRAMEH: USB0 Frame Number High ...................... 186
USB Register Definition 21.11. IN1INT: USB0 IN Endpoint Interrupt ......................... 187
USB Register Definition 21.12. OUT1INT: USB0 OUT Endpoint Interrupt ................. 188
USB Register Definition 21.13. CMINT: USB0 Common Interrupt ............................. 189
USB Register Definition 21.14. IN1IE: USB0 IN Endpoint Interrupt Enable ............... 190
USB Register Definition 21.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable ....... 191
USB Register Definition 21.16. CMIE: USB0 Common Interrupt Enable .................... 192
USB Register Definition 21.17. E0CSR: USB0 Endpoint0 Control ............................. 195
USB Register Definition 21.18. E0CNT: USB0 Endpoint0 Data Count ....................... 196
13
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.19. EENABLE: USB0 Endpoint Enable ........................... 197
USB Register Definition 21.20. EINCSRL: USB0 IN Endpoint Control Low ............... 199
USB Register Definition 21.21. EINCSRH: USB0 IN Endpoint Control High .............. 200
USB Register Definition 21.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 202
USB Register Definition 21.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte ....
203
USB Register Definition 21.24. EOUTCNTL: USB0 OUT Endpoint Count Low ......... 203
USB Register Definition 21.25. EOUTCNTH: USB0 OUT Endpoint Count High ........ 204
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration ...................................... 211
SFR Definition 22.2. SMB1CF: SMBus Clock/Configuration ...................................... 212
SFR Definition 22.3. SMBTC: SMBus Timing Control ................................................ 213
SFR Definition 22.4. SMB0CN: SMBus Control .......................................................... 215
SFR Definition 22.5. SMB1CN: SMBus Control .......................................................... 216
SFR Definition 22.6. SMB0ADR: SMBus0 Slave Address .......................................... 218
SFR Definition 22.7. SMB0ADM: SMBus0 Slave Address Mask ................................ 219
SFR Definition 22.8. SMB1ADR: SMBus1 Slave Address .......................................... 219
SFR Definition 22.9. SMB1ADM: SMBus1 Slave Address Mask ................................ 220
SFR Definition 22.10. SMB0DAT: SMBus Data .......................................................... 221
SFR Definition 22.11. SMB1DAT: SMBus Data .......................................................... 222
SFR Definition 23.1. SCON0: Serial Port 0 Control .................................................... 237
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 238
SFR Definition 24.1. SCON1: UART1 Control ............................................................ 245
SFR Definition 24.2. SMOD1: UART1 Mode .............................................................. 246
SFR Definition 24.3. SBUF1: UART1 Data Buffer ...................................................... 247
SFR Definition 24.4. SBCON1: UART1 Baud Rate Generator Control ...................... 248
SFR Definition 24.5. SBRLH1: UART1 Baud Rate Generator High Byte ................... 248
SFR Definition 24.6. SBRLL1: UART1 Baud Rate Generator Low Byte ..................... 249
SFR Definition 25.1. SPI0CFG: SPI0 Configuration ................................................... 257
SFR Definition 25.2. SPI0CN: SPI0 Control ............................................................... 258
SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate ....................................................... 259
SFR Definition 25.4. SPI0DAT: SPI0 Data ................................................................. 259
SFR Definition 26.1. CKCON: Clock Control .............................................................. 264
SFR Definition 26.2. CKCON1: Clock Control 1 ......................................................... 265
SFR Definition 26.3. TCON: Timer Control ................................................................. 270
SFR Definition 26.4. TMOD: Timer Mode ................................................................... 271
SFR Definition 26.5. TL0: Timer 0 Low Byte ............................................................... 272
SFR Definition 26.6. TL1: Timer 1 Low Byte ............................................................... 272
SFR Definition 26.7. TH0: Timer 0 High Byte ............................................................. 273
SFR Definition 26.8. TH1: Timer 1 High Byte ............................................................. 273
SFR Definition 26.9. TMR2CN: Timer 2 Control ......................................................... 278
SFR Definition 26.10. TMR2RLL: Timer 2 Reload Register Low Byte ........................ 279
SFR Definition 26.11. TMR2RLH: Timer 2 Reload Register High Byte ...................... 279
SFR Definition 26.12. TMR2L: Timer 2 Low Byte ....................................................... 279
SFR Definition 26.13. TMR2H Timer 2 High Byte ....................................................... 280
SFR Definition 26.14. TMR3CN: Timer 3 Control ....................................................... 285
Rev. 1.5
14
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 26.15. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 286
SFR Definition 26.16. TMR3RLH: Timer 3 Reload Register High Byte ...................... 286
SFR Definition 26.17. TMR3L: Timer 3 Low Byte ....................................................... 286
SFR Definition 26.18. TMR3H Timer 3 High Byte ....................................................... 287
SFR Definition 26.19. TMR4CN: Timer 4 Control ....................................................... 290
SFR Definition 26.20. TMR4RLL: Timer 4 Reload Register Low Byte ........................ 291
SFR Definition 26.21. TMR4RLH: Timer 4 Reload Register High Byte ...................... 291
SFR Definition 26.22. TMR4L: Timer 4 Low Byte ....................................................... 291
SFR Definition 26.23. TMR4H Timer 4 High Byte ....................................................... 292
SFR Definition 26.24. TMR5CN: Timer 5 Control ....................................................... 295
SFR Definition 26.25. TMR5RLL: Timer 5 Reload Register Low Byte ........................ 296
SFR Definition 26.26. TMR5RLH: Timer 5 Reload Register High Byte ...................... 296
SFR Definition 26.27. TMR5L: Timer 5 Low Byte ....................................................... 296
SFR Definition 26.28. TMR5H Timer 5 High Byte ....................................................... 297
SFR Definition 27.1. PCA0CN: PCA Control .............................................................. 311
SFR Definition 27.2. PCA0MD: PCA Mode ................................................................ 312
SFR Definition 27.3. PCA0CPMn: PCA Capture/Compare Mode .............................. 313
SFR Definition 27.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 314
SFR Definition 27.5. PCA0H: PCA Counter/Timer High Byte ..................................... 314
SFR Definition 27.6. PCA0CPLn: PCA Capture Module Low Byte ............................. 315
SFR Definition 27.7. PCA0CPHn: PCA Capture Module High Byte ........................... 315
C2 Register Definition 28.1. C2ADD: C2 Address ...................................................... 316
C2 Register Definition 28.2. DEVICEID: C2 Device ID ............................................... 317
C2 Register Definition 28.3. REVID: C2 Revision ID .................................................. 317
C2 Register Definition 28.4. FPCTL: C2 Flash Programming Control ........................ 318
C2 Register Definition 28.5. FPDAT: C2 Flash Programming Data ............................ 318
15
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
1. System Overview
C8051F380/1/2/3/4/5/6/7/C devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated
transceiver, and 1 kB FIFO RAM
Supply Voltage Regulator
True 10-bit 500 ksps differential / single-ended ADC with analog multiplexer
On-chip Voltage Reference and Temperature Sensor
On-chip Voltage Comparators (2)
Precision internal calibrated 48 MHz internal oscillator
Internal low-frequency oscillator for additional power savings
Up to 64 kB of on-chip Flash memory
Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
External Memory Interface (EMIF) available on 48-pin versions.
2 I2C/SMBus, 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
Up to 40 Port I/O (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F380/1/2/3/4/5/6/7/C devices are truly stand-alone System-on-a-Chip solutions. The Flash memory
can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for
USB communication. The Port I/O and RST pins are tolerant of input signals up to 5 V. C8051F380/1/2/3/
4/5/6/7/C devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See Table 1.1,
“Product Selection Guide,” on page 20 for feature and package choices.
Rev. 1.5
19
C8051F380/1/2/3/4/5/6/7/C
64k
4352
2
2
6
25
— 2
LQFP32
C8051F381-GM
48
64k
4352
2
2
6
25
— 2
QFN32
C8051F382-GQ
48
32k
2304
2
2
6
40
2
TQFP48
C8051F383-GQ
48
32k
2304
2
2
6
25
— 2
LQFP32
C8051F383-GM
48
32k
2304
2
2
6
25
— 2
QFN32
C8051F384-GQ
48
64k
4352
2
2
6
40
— — — 2
TQFP48
C8051F385-GQ
48
64k
4352
2
2
6
25
— — — — 2
LQFP32
C8051F385-GM
48
64k
4352
2
2
6
25
— — — — 2
QFN32
C8051F386-GQ
48
32k
2304
2
2
6
40
— — — 2
TQFP48
C8051F387-GQ
48
32k
2304
2
2
6
25
— — — — 2
LQFP32
C8051F387-GM
48
32k
2304
2
2
6
25
— — — — 2
QFN32
C8051F38C-GQ
48
16k
2304
2
2
6
25
— 2
LQFP32
C8051F38C-GM
48
16k
2304
2
2
6
25
— 2
QFN32
20
Rev. 1.5
Package
48
Analog Comparators
C8051F381-GQ
Voltage Reference
TQFP48
Temperature Sensor
2
10-bit 500ksps ADC
Programmable Counter Array
40
Digital Port I/O
Timers (16-bit)
6
UARTs
2
Enhanced SPI
2
SMBus/I2C
4352
Supply Voltage Regulator
RAM
64k
USB with 1k Endpoint RAM
Flash Memory (Bytes)
48
Low Frequency Oscillator
MIPS (Peak)
C8051F380-GQ
Calibrated Internal Oscillator
Ordering Part Number
External Memory Interface (EMIF)
Table 1.1. Product Selection Guide
C8051F380/1/2/3/4/5/6/7/C
C2D
Port I/O Configuration
Debug / Programming
Hardware
C2CK/RST
UART0
Reset
Power-On
Reset
Supply
Monitor
VDD
Power
Net
VREG
Voltage
Regulators
Port 0
Drivers
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Port 3
Drivers
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 4
Drivers
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Digital Peripherals
CIP-51 8051
Controller Core
UART1
Timers 0, 1,
2, 3, 4, 5
64/32k Byte ISP FLASH
Program Memory
Priority
Crossbar
Decoder
PCA/WDT
SMBus0
256 Byte RAM
SMBus1
SPI
4/2k Byte XRAM
Crossbar Control
GND
System Clock Setup
XTAL1
XTAL2
SFR
Bus
External Memory
Interface
External Oscillator
P1
Control
P2 / P3
Address
Internal Oscillator
P4
Data
Clock
Recovery
Low Freq.
Oscillator
Analog Peripherals
CP0
VREF
USB Peripheral
D+
D-
VBUS
Full / Low
Speed
Transceiver
VDD
VREF
+
+
-
2 Comparators
Controller
1k Byte
RAM
CP1
10-bit
500ksps
ADC
A
M
U
X
VDD
AIN0 - AIN19
Temp
Sensor
Figure 1.1. C8051F380/2/4/6 Block Diagram
Rev. 1.5
21
C8051F380/1/2/3/4/5/6/7/C
C2D
Port I/O Configuration
Debug / Programming
Hardware
C2CK/RST
UART0
Reset
Power-On
Reset
Supply
Monitor
VDD
Power
Net
VREG
Voltage
Regulators
CIP-51 8051
Controller Core
Port 1
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 2
Drivers
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
UART1
Timers 0, 1,
2, 3, 4, 5
64/32/16 kB ISP FLASH
Program Memory
Priority
Crossbar
Decoder
PCA/WDT
256 Byte RAM
SMBus0
SMBus1
4/2 kB XRAM
SPI
GND
System Clock Setup
XTAL1
XTAL2
Port 0
Drivers
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
Digital Peripherals
SFR
Bus
Crossbar Control
P3.0/C2D
Port 3
Drivers
External Oscillator
Internal Oscillator
Clock
Recovery
Low Freq.
Oscillator
Analog Peripherals
CP0
VREF
USB Peripheral
D+
D-
VBUS
Full / Low
Speed
Transceiver
VDD
VREF
+
+
-
2 Comparators
Controller
1 kB RAM
CP1
10-bit
500 ksps
ADC
A
M
U
X
VDD
AIN0 - AIN20
Temp
Sensor
Figure 1.2. C8051F381/3/5/7/C Block Diagram
22
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
2. C8051F34x Compatibility
The C8051F38x family is designed to be a pin and code compatible replacement for the C8051F34x
device family, with an enhanced feature set. The C8051F38x device should function as a drop-in replacement for the C8051F34x devices in most applications. Table 2.1 lists recommended replacement part
numbers for C8051F34x devices. See “2.1. Hardware Incompatibilities” to determine if any changes are
necessary when upgrading an existing C8051F34x design to the C8051F38x.
Table 2.1. C8051F38x Replacement Part Numbers
C8051F34x Part Number
C8051F38x Part Number
C8051F340-GQ
C8051F380-GQ
C8051F341-GQ
C8051F382-GQ
C8051F342-GQ
C8051F381-GQ
C8051F342-GM
C8051F381-GM
C8051F343-GQ
C8051F383-GQ
C8051F343-GM
C8051F383-GM
C8051F344-GQ
C8051F380-GQ
C8051F345-GQ
C8051F382-GQ
C8051F346-GQ
C8051F381-GQ
C8051F346-GM
C8051F381-GM
C8051F347-GQ
C8051F383-GQ
C8051F347-GM
C8051F383-GM
C8051F348-GQ
C8051F386-GQ
C8051F349-GQ
C8051F387-GQ
C8051F349-GM
C8051F387-GM
C8051F34A-GQ
C8051F381-GQ
C8051F34A-GM
C8051F381-GM
C8051F34B-GQ
C8051F383-GQ
C8051F34B-GM
C8051F383-GM
C8051F34C-GQ
C8051F384-GQ
C8051F34D-GQ
C8051F385-GQ
Rev. 1.5
23
C8051F380/1/2/3/4/5/6/7/C
2.1. Hardware Incompatibilities
While the C8051F38x family includes a number of new features not found on the C8051F34x family, there
are some differences that should be considered for any design port.
Clock Multiplier: The C8051F38x does not include the 4x clock multiplier from the C8051F34x device
families. This change only impacts systems which use the clock multiplier in conjunction with an
external oscillator source.
External Oscillator C and RC Modes: The C and RC modes of the oscillator have a divide-by-2 stage
on the C8051F38x to aid in noise immunity. This was not present on the C8051F34x device family, and
any clock generated with C or RC mode will change accordingly.
Fab Technology: The C8051F38x is manufactured using a different technology process than the
C8051F34x. As a result, many of the electrical performance parameters will have subtle differences.
These differences should not affect most systems but it is nonetheless important to review the electrical
parameters for any blocks that are used in the design, and ensure they are compatible with the existing
hardware.
24
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
3. Pinout and Package Definitions
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C
Name
Pin Numbers
Type
Description
48-pin 32-pin
VDD
10
6
Power In 2.7–3.6 V Power Supply Voltage Input.
Power
Out
GND
7
3
RST/
13
9
C2CK
3.3 V Voltage Regulator Output.
Ground.
D I/O
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs.
D I/O
Clock signal for the C2 Debug Interface.
C2D
14
—
D I/O
Bi-directional data signal for the C2 Debug Interface.
P3.0 /
—
10
D I/O
Port 3.0. See Section 20 for a complete description of Port 3.
D I/O
Bi-directional data signal for the C2 Debug Interface.
C2D
REGIN
11
7
Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.
VBUS
12
8
D In
VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indicates a USB network connection.
D+
8
4
D I/O
USB D+.
D–
9
5
D I/O
USB D–.
P0.0
6
2
D I/O or Port 0.0. See Section 20 for a complete description of Port 0.
A In
P0.1
5
1
D I/O or Port 0.1.
A In
P0.2
4
32
D I/O or Port 0.2.
A In
P0.3
3
31
D I/O or Port 0.3.
A In
P0.4
2
30
D I/O or Port 0.4.
A In
P0.5
1
29
D I/O or Port 0.5.
A In
P0.6
48
28
D I/O or Port 0.6.
A In
Rev. 1.5
25
C8051F380/1/2/3/4/5/6/7/C
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C (Continued)
Name
Pin Numbers
Type
Description
48-pin 32-pin
P0.7
47
27
D I/O or Port 0.7.
A In
P1.0
46
26
D I/O or Port 1.0. See Section 20 for a complete description of Port 1.
A In
P1.1
45
25
D I/O or Port 1.1.
A In
P1.2
44
24
D I/O or Port 1.2.
A In
P1.3
43
23
D I/O or Port 1.3.
A In
P1.4
42
22
D I/O or Port 1.4.
A In
P1.5
41
21
D I/O or Port 1.5.
A In
P1.6
40
20
D I/O or Port 1.6.
A In
P1.7
39
19
D I/O or Port 1.7.
A In
P2.0
38
18
D I/O or Port 2.0. See Section 20 for a complete description of Port 2.
A In
P2.1
37
17
D I/O or Port 2.1.
A In
P2.2
36
16
D I/O or Port 2.2.
A In
P2.3
35
15
D I/O or Port 2.3.
A In
P2.4
34
14
D I/O or Port 2.4.
A In
P2.5
33
13
D I/O or Port 2.5.
A In
P2.6
32
12
D I/O or Port 2.6.
A In
P2.7
31
11
D I/O or Port 2.7.
A In
P3.0
30
—
D I/O or Port 3.0. See Section 20 for a complete description of Port 3.
A In
26
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table 3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C (Continued)
Name
Pin Numbers
Type
Description
48-pin 32-pin
P3.1
29
—
D I/O or Port 3.1.
A In
P3.2
28
—
D I/O or Port 3.2.
A In
P3.3
27
—
D I/O or Port 3.3.
A In
P3.4
26
—
D I/O or Port 3.4.
A In
P3.5
25
—
D I/O or Port 3.5.
A In
P3.6
24
—
D I/O or Port 3.6.
A In
P3.7
23
—
D I/O or Port 3.7.
A In
P4.0
22
—
D I/O or Port 4.0. See Section 20 for a complete description of Port 4.
A In
P4.1
21
—
D I/O or Port 4.1.
A In
P4.2
20
—
D I/O or Port 4.2.
A In
P4.3
19
—
D I/O or Port 4.3.
A In
P4.4
18
—
D I/O or Port 4.4.
A In
P4.5
17
—
D I/O or Port 4.5.
A In
P4.6
16
—
D I/O or Port 4.6.
A In
P4.7
15
—
D I/O or Port 4.7.
A In
Rev. 1.5
27
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
48
47
46
45
44
43
42
41
40
39
38
37
C8051F380/1/2/3/4/5/6/7/C
P0.5
1
36
P2.2
P0.4
2
35
P2.3
P0.3
3
34
P2.4
P0.2
4
33
P2.5
P0.1
5
32
P2.6
P0.0
6
31
P2.7
GND
7
30
P3.0
D+
8
29
P3.1
D-
9
28
P3.2
VDD
10
27
P3.3
REGIN
11
26
P3.4
VBUS
12
25
P3.5
20
21
22
23
24
P4.2
P4.1
P4.0
P3.7
P3.6
17
P4.5
19
16
P4.6
P4.3
15
P4.7
18
14
C2D
P4.4
13
RST / C2CK
C8051F380/2/4/6-GQ
Top View
Figure 3.1. TQFP-48 Pinout Diagram (Top View)
28
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Figure 3.2. TQFP-48 Package Diagram
Table 3.2. TQFP-48 Package Dimensions
Dimension
Min
Nom
Max
Dimension
A
A1
A2
b
c
D
D1
e
—
0.05
0.95
0.17
0.09
—
—
1.00
0.22
—
9.00 BSC
7.00 BSC
0.50 BSC
1.20
0.15
1.05
0.27
0.20
E
E1
L
aaa
bbb
ccc
ddd
q
Min
0.45
0°
Nom
9.00 BSC
7.00 BSC
0.60
0.20
0.20
0.08
0.08
3.5°
Max
0.75
7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation ABC.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.5
29
C8051F380/1/2/3/4/5/6/7/C
Figure 3.3. TQFP-48 Recommended PCB Land Pattern
Table 3.3. TQFP-48 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
C2
E
X1
Y1
8.30
8.30
8.40
8.40
0.50 BSC
0.20
1.40
0.30
1.50
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
30
Rev. 1.5
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
32
31
30
29
28
27
26
25
C8051F380/1/2/3/4/5/6/7/C
P0.1
1
24
P1.2
P0.0
2
23
P1.3
GND
3
22
P1.4
D+
4
21
P1.5
D–
5
20
P1.6
VDD
6
19
P1.7
REGIN
7
18
P2.0
VBUS
8
17
P2.1
14
15
16
P2.3
P2.2
12
P2.6
P2.4
11
P2.7
13
10
P3.0 / C2D
P2.5
9
RST / C2CK
C8051F381/3/5/7/C-GQ
Top View
Figure 3.4. LQFP-32 Pinout Diagram (Top View)
Rev. 1.5
31
C8051F380/1/2/3/4/5/6/7/C
Figure 3.5. LQFP-32 Package Diagram
Table 3.4. LQFP-32 Package Dimensions
Dimension
Min
Nom
Max
Dimension
A
A1
A2
b
c
D
D1
e
—
0.05
1.35
0.30
0.09
—
—
1.40
0.37
—
9.00 BSC
7.00 BSC
0.80 BSC
1.60
0.15
1.45
0.45
0.20
E
E1
L
aaa
bbb
ccc
ddd
q
Min
0.45
0°
Nom
9.00 BSC
7.00 BSC
0.60
0.20
0.20
0.10
0.20
3.5°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
32
Rev. 1.5
Max
0.75
7°
C8051F380/1/2/3/4/5/6/7/C
Figure 3.6. LQFP-32 Recommended PCB Land Pattern
Table 3.5. LQFP-32 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
C2
E
X1
Y1
8.40
8.40
8.50
8.50
0.80 BSC
0.40
1.25
0.50
1.35
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.5
33
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
32
31
30
29
28
27
26
25
C8051F380/1/2/3/4/5/6/7/C
P0.1
1
24
P1.2
P0.0
2
23
P1.3
GND
3
22
P1.4
D+
4
21
P1.5
D–
5
20
P1.6
VDD
6
19
P1.7
REGIN
7
18
P2.0
VBUS
8
17
P2.1
C8051F381/3/5/7/C-GM
Top View
13
14
15
16
P2.5
P2.4
P2.3
P2.2
11
P2.7
12
10
P3.0 / C2D
P2.6
9
RST / C2CK
GND (optional)
Figure 3.7. QFN-32 Pinout Diagram (Top View)
34
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Figure 3.8. QFN-32 Package Drawing
Table 3.6. QFN-32 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
A1
b
D
D2
e
E
0.80
0.00
0.18
0.85
0.02
0.25
5.00 BSC
3.30
0.50 BSC
5.00 BSC
0.90
0.05
0.30
E2
L
aaa
bbb
ddd
eee
3.20
0.35
—
—
—
—
3.30
0.40
—
—
—
—
3.40
0.45
0.10
0.10
0.05
0.08
3.20
3.40
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.5
35
C8051F380/1/2/3/4/5/6/7/C
Figure 3.9. QFN-32 Recommended PCB Land Pattern
Table 3.7. QFN-32 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
X1
4.80
4.80
4.90
4.90
X2
Y1
Y2
3.20
0.75
3.20
3.40
0.85
3.40
0.50 BSC
0.20
0.30
Notes:
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure
the proper paste volume.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
36
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
4. Typical Connection Diagrams
This section provides typical connection diagrams for C8051F38x devices.
4.1. Power
Figure 4.1 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator is in use and USB is not used.
C8051F38x Device
3.6-5.25 V (in)
REGIN
3.3 V (out)
1 µF and 0.1 µF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
Voltage
Regulator
VDD
VBUS
GND
Figure 4.1. Connection Diagram with Voltage Regulator Used and No USB
Figure 4.2 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator and USB are not used.
C8051F38x Device
2.7-3.6 V (in)
REGIN
1 µF and 0.1 µF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
Voltage
Regulator
VDD
VBUS
GND
Figure 4.2. Connection Diagram with Voltage Regulator Not Used and No USB
Figure 4.3 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator used and USB is connected (bus-powered). The VBUS signal is used to detect when
Rev. 1.5
38
C8051F380/1/2/3/4/5/6/7/C
USB is connected to a host device and is shown with a 100 Ω current-limiting resistor. This current-limiting
resistor is recommended for systems that may experience electrostatic discharge (ESD), latch-up, and
have a greater opportunity to share signals with systems that do not have the same ground potential. This
is not a required component for most applications.
Recommended,
not required
USB 5 V (in)
C8051F38x Device
100 ȍ
VBUS
REGIN
3.3 V (out)
1 μF and 0.1 μF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
Voltage
Regulator
VDD
GND
Figure 4.3. Connection Diagram with Voltage Regulator Used and USB Connected
(Bus-Powered)
Figure 4.4 shows a typical connection diagram for the power pins of the C8051F38x devices when the
internal regulator used and USB is connected (self-powered). The VBUS signal is used to detect when
USB is connected to a host device and is shown with a 100 Ω current-limiting resistor. This current-limiting
resistor is recommended for systems that may experience electrostatic discharge (ESD), latch-up, and
have a greater opportunity to share signals with systems that do not have the same ground potential. This
is not a required component for most applications.
USB 5 V
(sense)
Recommended,
not required
3.6-5.25 V (in)
1 μF and 0.1 μF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
C8051F38x Device
100 ȍ
VBUS
3.3 V (out)
REGIN
Voltage
Regulator
VDD
GND
Figure 4.4. Connection Diagram with Voltage Regulator Used and USB Connected
(Self-Powered)
39
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
4.2. USB
Figure 4.5 shows a typical connection diagram for the USB pins of the C8051F38x devices including a
100 Ω current-limiting resistor on the VBUS sense pin and ESD protection diodes on the USB pins. This
current-limiting resistor is recommended for systems that may experience electrostatic discharge (ESD),
latch-up, and have a greater opportunity to share signals with systems that do not have the same ground
potential. This is not a required component for most applications.
Recommended,
not required
USB
Connector
C8051F38x Device
100 ȍ
VBUS
VBUS
D+
USB
D+
D-
D-
Signal GND
SP0503BAHT or
equivalent USB
ESD protection
diodes
GND
Figure 4.5. Connection Diagram for USB Pins
4.3. Voltage Reference (VREF)
Figure 4.6 shows a typical connection diagram for the voltage reference (VREF) pin of the C8051F38x
devices when using the internal voltage reference. When using an external voltage reference, consult the
appropriate device’s data sheet for connection recommendations.
C8051F38x Device
2.42 V (out)
4.7 µF and 0.1 µF
capacitors recommended
for internal voltage
reference.
VREF
Voltage
Reference
GND
Figure 4.6. Connection Diagram for Internal Voltage Reference
Rev. 1.5
40
C8051F380/1/2/3/4/5/6/7/C
5. Electrical Characteristics
5.1. Absolute Maximum Specifications
Table 5.1. Absolute Maximum Ratings
Parameter
Min
Typ
Max
Units
Junction Temperature Under Bias
–55
—
125
°C
Storage Temperature
–65
—
150
°C
VDD > 2.2 V
VDD < 2.2 V
–0.3
–0.3
—
—
5.8
VDD + 3.6
V
V
Regulator1 in Normal Mode
Regulator1 in Bypass Mode
–0.3
–0.3
—
—
4.2
1.98
V
V
Maximum Total Current through
VDD or GND
—
—
500
mA
Maximum Output Current sunk by
RST or any Port Pin
—
—
100
mA
Voltage on RST, VBUS, or any
Port I/O Pin with Respect to GND
Voltage on VDD with Respect to
GND
Conditions
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
41
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Digital Supply
Test Condition
Voltage1
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)2
Specified Operating
Temperature Range
Min
Typ
Max
Unit
VRST1
3.3
3.6
V
—
1.5
—
V
0
—
48
MHz
–40
—
+85
°C
14
mA
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD3
SYSCLK = 48 MHz, VDD = 3.3 V
—
12
SYSCLK = 24 MHz, VDD = 3.3 V
—
7
8
mA
SYSCLK = 1 MHz, VDD = 3.3 V
—
0.45
0.85
mA
SYSCLK = 80 kHz, VDD = 3.3 V
—
280
—
µA
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle IDD3
Digital Supply Current
(Stop or Suspend Mode, shutdown)
Digital Supply Current for USB
Module
(USB Active Mode4)
SYSCLK = 48 MHz, VDD = 3.3 V
—
6.5
8
mA
SYSCLK = 24 MHz, VDD = 3.3 V
—
3.5
5
mA
SYSCLK = 1 MHz, VDD = 3.3 V
—
0.35
—
mA
SYSCLK = 80 kHz, VDD = 3.3 V
—
220
—
µA
Oscillator not running (STOP mode),
Internal Regulators OFF, VDD = 3.3 V
—
1
—
µA
Oscillator not running (STOP or SUSPEND mode), REG0 and REG1 both in
low power mode, VDD = 3.3 V.
—
100
—
µA
Oscillator not running (STOP or SUSPEND mode), REG0 OFF, VDD = 3.3 V.
—
150
—
µA
USB Clock = 48 MHz, VDD = 3.3 V
—
8
—
mA
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Includes normal mode bias current for REG0 and REG1. Does not include current from internal oscillators,
USB, or other analog peripherals.
4. An additional 220uA is sourced by the D+ or D- pull-up to the USB bus when the USB pull-up is active.
Rev. 1.5
42
C8051F380/1/2/3/4/5/6/7/C
Table 5.3. Port I/O DC Electrical Characteristics
VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
Output High Voltage
IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
VDD – 0.7
VDD – 0.1
—
—
—
VDD – 0.8
—
—
—
V
Output Low Voltage
IOL = 8.5 mA
IOL = 10 µA
IOL = 25 mA
—
—
—
—
—
1.0
0.6
0.1
—
V
Input High Voltage
2.0
—
—
V
Input Low Voltage
—
—
0.8
V
—
—
—
15
±1
50
µA
Input Leakage
Current
Weak Pullup Off
Weak Pullup On, VIN = 0 V
Table 5.4. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
IOL = 8.5 mA,
VDD = 2.7 V to 3.6 V
—
—
0.6
V
RST Input High Voltage
0.7 x VDD
—
—
V
RST Input Low Voltage
—
—
0.3 x VDD
V
—
15
40
µA
2.60
2.65
2.70
V
Time from last system clock
rising edge to reset initiation
80
580
800
µs
Delay between release of any
reset source and code
execution at location 0x0000
—
—
250
µs
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
VDD Monitor Turn-on Time
—
—
100
µs
VDD Monitor Supply Current
—
15
50
µA
RST Output Low Voltage
RST Input Pullup Current
RST = 0.0 V
VDD Monitor Threshold (VRST)
Missing Clock Detector Timeout
Reset Time Delay
43
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table 5.5. Internal Voltage Regulator Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
2.7
—
5.25
V
3.0
3.3
3.6
V
—
—
100
mA
—
1
—
mV/mA
1.8
—
3.6
V
Voltage Regulator (REG0)
Input Voltage Range1
Output Voltage (VDD)
2
Output Current = 1 to 100 mA
2
Output Current
Dropout Voltage (VDO
)3
Voltage Regulator (REG1)
Input Voltage Range
Notes:
1. Input range specified for regulation. When an external regulator is used, should be tied to VDD.
2. Output current is total regulator output, including any current required by the C8051F380/1/2/3/4/5/6/7/C.
3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater.
Table 5.6. Flash Electrical Characteristics
Parameter
Flash Size
Test Condition
Min
Typ
Max
Unit
C8051F380/1/4/5*
C8051F382/3/6/7
65536*
32768
—
—
Bytes
Bytes
10k
100k
—
Erase/Write
Endurance
Erase Cycle Time
25 MHz System Clock
10
15
22.5
ms
Write Cycle Time
25 MHz System Clock
10
15
20
µs
Notes:
1. 1024 bytes at location 0xFC00 to 0xFFFF are not available for program storage.
2. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Rev. 1.5
44
C8051F380/1/2/3/4/5/6/7/C
Table 5.7. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Test Condition
Min
Typ
Max
Unit
IFCN = 11b
47.3
48
48.7
MHz
Oscillator Supply Current
(from VDD)
25 °C, VDD = 3.0 V,
OSCICN.7 = 1,
OCSICN.5 = 0
—
900
—
µA
Power Supply Sensitivity
Constant Temperature
—
110
—
ppm/V
Temperature Sensitivity
Constant Supply
—
25
—
ppm/°C
Oscillator Frequency
Table 5.8. Internal Low-Frequency Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Test Condition
Min
Typ
Max
Unit
OSCLD = 11b
75
80
85
kHz
Oscillator Supply Current
(from VDD)
25 °C, VDD = 3.0 V,
OSCLCN.7 = 1
—
4
—
µA
Power Supply Sensitivity
Constant Temperature
—
0.05
—
%/V
Temperature Sensitivity
Constant Supply
—
65
—
ppm/°C
Min
Typ
Max
Unit
0.02
—
30
MHz
0
—
48
MHz
Oscillator Frequency
Table 5.9. External Oscillator Electrical Characteristics
VDD = 2.7 to 3.6 V; TA = –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
External Crystal Frequency
External CMOS Oscillator
Frequency
45
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table 5.10. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
DC Accuracy
Resolution
10
Integral Nonlinearity
bits
—
±0.5
±1
LSB
—
±0.5
±1
LSB
Offset Error
–2
0
2
LSB
Full Scale Error
–5
–2
0
LSB
Offset Temperature Coefficient
—
0.005
—
LSB/°C
Differential Nonlinearity
Guaranteed Monotonic
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion
55
58
—
dB
—
–73
—
dB
—
78
—
dB
—
—
8.33
MHz
13
11
—
—
—
—
clocks
clocks
300
—
—
ns
—
—
500
ksps
Single Ended (AIN+ – GND)
0
—
VREF
V
Differential (AIN+ – AIN–)
–VREF
—
VREF
V
Single Ended or Differential
0
—
VDD
V
Sampling Capacitance
—
30
—
pF
Input Multiplexer Impedance
—
5
—
k
—
750
1000
µA
—
1
—
mV/V
Total Harmonic Distortion
Up to the 5th harmonic
Spurious-Free Dynamic Range
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
Track/Hold Acquisition Time
Throughput Rate
Analog Inputs
ADC Input Voltage Range
Absolute Pin Voltage with respect
to GND
Power Specifications
Power Supply Current
(VDD supplied to ADC0)
Operating Mode, 500 ksps
Power Supply Rejection
Note: Represents one standard deviation from the mean.
Rev. 1.5
46
C8051F380/1/2/3/4/5/6/7/C
Table 5.11. Temperature Sensor Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
Linearity
—
± 0.5
—
°C
Slope
—
2.87
—
mV/°C
Slope Error*
—
±120
—
µV/°C
Offset
Temp = 0 °C
—
764
—
mV
Offset Error*
Temp = 0 °C
—
±15
—
mV
Note: Represents one standard deviation from the mean.
Table 5.12. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
25 °C ambient
2.38
2.42
2.46
V
VREF Short-Circuit Current
—
—
8
mA
VREF Temperature
Coefficient
—
35
—
ppm/°C
Load = 0 to 200 µA to GND
—
1.5
—
ppm/µA
VREF Turn-on Time 1
4.7 µF tantalum, 0.1 µF ceramic bypass
—
3
—
ms
VREF Turn-on Time 2
0.1 µF ceramic bypass
—
100
—
µs
—
140
—
ppm/V
1
—
VDD
V
—
9
—
µA
—
75
—
µA
Internal Reference (REFBE = 1)
Output Voltage
Load Regulation
Power Supply Rejection
External Reference (REFBE = 0)
Input Voltage Range
Input Current
Sample Rate = 500 ksps; VREF = 3.0 V
Power Specifications
Supply Current
47
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table 5.13. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
Parameter
Response Time:
Mode 0, Vcm* = 1.5 V
Response Time:
Mode 1, Vcm* = 1.5 V
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V
Test Condition
Min
Typ
Max
Unit
CP0+ – CP0– = 100 mV
—
100
—
ns
CP0+ – CP0– = –100 mV
—
250
—
ns
CP0+ – CP0– = 100 mV
—
175
—
ns
CP0+ – CP0– = –100 mV
—
500
—
ns
CP0+ – CP0– = 100 mV
—
320
—
ns
CP0+ – CP0– = –100 mV
—
1100
—
ns
CP0+ – CP0– = 100 mV
—
1050
—
ns
CP0+ – CP0– = –100 mV
—
5200
—
ns
—
1.5
4
mV/V
Common-Mode Rejection Ratio
Positive Hysteresis 1
CP0HYP1–0 = 00
—
0
1
mV
Positive Hysteresis 2
CP0HYP1–0 = 01
2
5
10
mV
Positive Hysteresis 3
CP0HYP1–0 = 10
7
10
20
mV
Positive Hysteresis 4
CP0HYP1–0 = 11
15
20
30
mV
Negative Hysteresis 1
CP0HYN1–0 = 00
—
0
1
mV
Negative Hysteresis 2
CP0HYN1–0 = 01
2
5
10
mV
Negative Hysteresis 3
CP0HYN1–0 = 10
7
10
20
mV
Negative Hysteresis 4
CP0HYN1–0 = 11
15
20
30
mV
–0.25
—
VDD + 0.25
V
Input Capacitance
—
4
—
pF
Input Bias Current
—
0.001
—
nA
–10
—
+10
mV
Power Supply Rejection
—
0.1
—
mV/V
Power-up Time
—
10
—
µs
Mode 0
—
20
—
µA
Mode 1
—
10
—
µA
Mode 2
—
4
—
µA
Mode 3
—
1
—
µA
Inverting or Non-Inverting Input
Voltage Range
Input Offset Voltage
Power Supply
Supply Current at DC
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.5
48
C8051F380/1/2/3/4/5/6/7/C
Table 5.14. USB Transceiver Electrical Characteristics
VDD = 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Test Condition
Min
Typ
Max
Unit
Output High Voltage (VOH)
2.8
—
—
V
Output Low Voltage (VOL)
—
—
0.8
V
VBUS Detection Input Low
Voltage
—
—
1.0
VBUS Detection Input High
Voltage
3.0
—
—
1.3
—
2.0
V
Transmitter
Output Crossover Point
(VCRS)
V
V
Output Impedance (ZDRV)
Driving High
Driving Low
—
—
38
38
—
—
W
Pull-up Resistance (RPU)
Full Speed (D+ Pull-up)
Low Speed (D– Pull-up)
1.425
1.5
1.575
k
Output Rise Time (TR)
Low Speed
Full Speed
75
4
—
—
300
20
ns
Output Fall Time (TF)
Low Speed
Full Speed
75
4
—
—
300
20
ns
| (D+) – (D–) |
0.2
—
—
V
0.8
—
2.5
V
—
0x0080). Figure 6.7 shows an example using left-justified data with the same comparison values.
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
0x03FF
0x03FF
AD0WINT
not affected
AD0WINT=1
0x0081
VREF x (128/1024)
0x0080
0x0081
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x007F
0x0080
0x007F
AD0WINT=1
VREF x (64/1024)
0x0041
0x0040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x003F
0x0041
0x0040
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x003F
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
Figure 6.6. ADC Window Compare Example: Right-Justified Data
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(AIN - GND)
VREF x (1023/
1024)
Input Voltage
(AIN - GND)
0xFFC0
VREF x (1023/
1024)
0xFFC0
AD0WINT
not affected
AD0WINT=1
0x2040
VREF x (128/1024)
0x2000
0x2040
ADC0LTH:ADC0LTL
VREF x (128/1024)
0x1FC0
0x2000
0x1FC0
AD0WINT=1
0x1040
VREF x (64/1024)
0x1000
0x1040
ADC0GTH:ADC0GTL
VREF x (64/1024)
0x0FC0
0x1000
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x0FC0
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
Figure 6.7. ADC Window Compare Example: Left-Justified Data
Rev. 1.5
62
C8051F380/1/2/3/4/5/6/7/C
6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only)
AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to
individual Port pins, the on-chip temperature sensor, or the positive power supply (VDD). The negative
input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential Mode.
The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition
6.9 and SFR Definition 6.10.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1
the corresponding bit in register PnSKIP. See Section “20. Port Input/Output” on page 153 for more Port
I/O configuration details.
63
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 6.9. AMX0P: AMUX0 Positive Channel Select
Bit
7
6
5
4
3
Name
1
0
0
0
AMX0P[5:0]
Type
R
R
Reset
0
0
R/W
0
0
0
SFR Address = 0xBB; SFR Page = All Pages
Bit
Name
7:6
2
Unused
0
Function
Read = 00b; Write = don’t care.
5:0 AMX0P[5:0] AMUX0 Positive Input Selection.
AMX0P
32-pin
Packages
48-pin
Packages
AMX0P
000000: P1.0
P2.0
010010: P0.1
P0.4
000001: P1.1
P2.1
010011:
P0.4
P1.1
000010: P1.2
P2.2
010100: P0.5
P1.2
000011:
P1.3
P2.3
010101: Reserved
P1.0
000100: P1.4
P2.5
010110:
Reserved
P1.3
000101: P1.5
P2.6
010111:
Reserved
P1.6
000110:
P1.6
P3.0
011000:
Reserved
P1.7
000111:
P1.7
P3.1
011001:
Reserved
P2.4
001000: P2.0
P3.4
011010:
Reserved
P2.7
001001: P2.1
P3.5
011011:
Reserved
P3.2
001010: P2.2
P3.7
011100:
Reserved
P3.3
001011:
P2.3
P4.0
011101:
Reserved
P3.6
001100:
P2.4
P4.3
011110:
Temp Sensor
Temp Sensor
001101:
P2.5
P4.4
011111:
VDD
VDD
001110:
P2.6
P4.5
100000: Reserved
P4.1
001111:
P2.7
P4.6
100001: Reserved
P4.2
010000: P3.0
Reserved
100010: Reserved
P4.7
010001: P0.0
P0.3
100011 - Reserved
111111:
Reserved
Rev. 1.5
32-pin
Packages
48-pin
Packages
64
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 6.10. AMX0N: AMUX0 Negative Channel Select
Bit
7
6
5
4
Name
2
1
0
0
0
AMX0N[5:0]
Type
R
R
Reset
0
0
R/W
0
0
SFR Address = 0xBA; SFR Page = All Pages
Bit
Name
7:6
3
Unused
0
0
Function
Read = 00b; Write = don’t care.
5:0 AMX0N[5:0] AMUX0 Negative Input Selection.
AMX0N
65
32-pin
Packages
48-pin
Packages
AMX0N
000000: P1.0
P2.0
010010: P0.1
P0.4
000001: P1.1
P2.1
010011:
P0.4
P1.1
000010: P1.2
P2.2
010100: P0.5
P1.2
000011:
P1.3
P2.3
010101: Reserved
P1.0
000100: P1.4
P2.5
010110:
Reserved
P1.3
000101: P1.5
P2.6
010111:
Reserved
P1.6
000110:
P1.6
P3.0
011000:
Reserved
P1.7
000111:
P1.7
P3.1
011001:
Reserved
P2.4
001000: P2.0
P3.4
011010:
Reserved
P2.7
001001: P2.1
P3.5
011011:
Reserved
P3.2
001010: P2.2
P3.7
011100:
Reserved
P3.3
001011:
P2.3
P4.0
011101:
Reserved
P3.6
001100:
P2.4
P4.3
011110:
VREF
VREF
001101:
P2.5
P4.4
011111:
GND
GND
(Single-Ended (Single-Ended
Measurement) Measurement)
001110:
P2.6
P4.5
100000: Reserved
P4.1
001111:
P2.7
P4.6
100001: Reserved
P4.2
010000: P3.0
Reserved
100010: Reserved
P4.7
010001: P0.0
P0.3
100011 - Reserved
111111:
Reserved
Rev. 1.5
32-pin
Packages
48-pin
Packages
C8051F380/1/2/3/4/5/6/7/C
7. Voltage Reference Options
The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply
voltage (VDD), or the regulated 1.8 V internal supply (see Figure 7.1). The REFSL bit in the Reference
Control register (REF0CN, SFR Definition 7.1) selects the reference source for the ADC. For an external
source or the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use VDD as the reference source, REFSL should be set to 1. To override this selection and use the internal regulator as the
reference source, the REGOVR bit can be set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by many of the analog peripherals on the device. This bias is automatically enabled when any peripheral which requires it is enabled, and
it does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the
BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in
Table 5.12.
The C8051F380/1/2/3/C devices also include an on-chip voltage reference circuit which consists of a
1.2 V, temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier. The buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN. On the 1x gain
setting the output voltage is nominally 1.2 V, and on the 2x gain setting the output voltage is nominally
2.4 V. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register
REF0CN to a 1. The maximum load seen by the VREF pin must be less than 200 µA to GND. Bypass
capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND, and a minimum of 0.1uF is
required. If the on-chip reference is not used, the REFBE bit should be cleared to 0. Electrical specifications for the on-chip voltage reference are given in Table 5.12.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip reference circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “20. Port Input/Output” on page 153 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar.
REGOVR
REFSL
TEMPE
BIASE
REFBE
REFBGS
REF0CN
EN
To ADC, IDAC,
Internal Oscillators,
Reference,
TempSensor
Bias Generator
IOSCEN
VDD
EN
External
Voltage
Reference
Circuit
R1
VREF
1x/2x
Temp Sensor
1.2V Reference
To Analog Mux
EN
REFBE
REFBGS
GND
0
0
4.7F
+
0.1F
Recommended Bypass
Capacitors
VDD
VREF
(to ADC)
1
Internal
Regulator
1
REGOVR
Figure 7.1. Voltage Reference Functional Block Diagram
Rev. 1.5
66
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 7.1. REF0CN: Reference Control
Bit
7
6
Name
REFBGS
Type
R/W
R
Reset
0
0
5
4
3
2
1
0
REGOVR
REFSL
TEMPE
BIASE
REFBE
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
SFR Address = 0xD1; SFR Page = All Pages
Bit
Name
7
Function
REFBGS Reference Buffer Gain Select.
This bit selects between 1x and 2x gain for the on-chip voltage reference buffer.
0: 2x Gain
1: 1x Gain
6:5
4
Unused
Read = 00b; Write = don’t care.
REGOVR Regulator Reference Override.
This bit “overrides” the REFSL bit, and allows the internal regulator to be used as a reference source.
0: The voltage reference source is selected by the REFSL bit.
1: The internal regulator is used as the voltage reference.
3
REFSL
Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
2
TEMPE
Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
1
BIASE
Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0
REFBE
On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin.
67
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
8. Comparator0 and Comparator1
C8051F380/1/2/3/4/5/6/7/C devices include two on-chip programmable voltage comparators: Comparator0
is shown in Figure 8.1, Comparator1 is shown in Figure 8.2. The two comparators operate identically with
the following exceptions: (1) Their input selections differ as described in Section “8.1. Comparator Multiplexers” on page 71; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “20.2. Port I/O Initialization” on page 158). Comparator0 may also be used as a
reset source (see Section “17.5. Comparator0 Reset” on page 132).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“8.1. Comparator Multiplexers” on page 71.
CPT0CN
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
VDD
CP0 +
+
Comparator
Input Mux
CP0 -
CP0
D
-
SET
CLR
D
Q
Q
SET
CLR
Q
Q
Crossbar
(SYNCHRONIZER)
CP0A
GND
CPT0MD
CP0FIE
CP0RIE
CP0MD1
CP0MD0
Reset
Decision
Tree
CP0RIF
CP0FIF
0
CP0EN
EA
1
0
0
0
1
1
CP0
Interrupt
1
Figure 8.1. Comparator0 Functional Block Diagram
Rev. 1.5
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CPT1CN
CP1EN
CP1FIF
CP1OUT
CP1RIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
VDD
CP1 +
+
Comparator
Input Mux
CP1 -
CP1
D
-
SET
CLR
Q
D
Q
SET
CLR
Q
Q
Crossbar
(SYNCHRONIZER)
CP1A
GND
CPT1MD
CP1FIE
CP1RIE
CP1MD1
CP1MD0
CP1RIF
CP1FIF
0
CP1EN
EA
1
0
0
0
1
1
CP1
Interrupt
1
Figure 8.2. Comparator1 Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “20.1. Priority Crossbar Decoder” on
page 154 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Section “5. Electrical Characteristics” on page 41.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition 8.2 and SFR Definition 8.4). Selecting a longer response time reduces the Comparator supply current.
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VIN+
VIN-
CPn+
CPn-
+
CPn
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CPnHYP Bits)
VIN-
INPUTS
Negative Hysteresis Voltage
(Programmed by CPnHYN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled
Maximum
Negative Hysteresis
Maximum
Positive Hysteresis
Figure 8.3. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN
(for n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits 3–0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 8.1). The amount of negative hysteresis voltage is determined by the settings of
the CPnHYN bits. Settings of 20, 10 or 5 mV of nominal negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the
setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “16.1. MCU Interrupt Sources and Vectors” on page 119). The
CPnFIF flag is set to logic 1 upon a Comparator falling-edge occurrence, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CPnRIE to a logic 1. The Comparator falling-edge interrupt mask is enabled by setting CPnFIE to a logic 1.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
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SFR Definition 8.1. CPT0CN: Comparator0 Control
Bit
7
6
5
4
Name
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP[1:0]
CP0HYN[1:0]
Type
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
SFR Address = 0x9B; SFR Page = All Pages
Bit
Name
7
CP0EN
3
2
0
0
1
0
0
0
Function
Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6
CP0OUT
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5
CP0RIF
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4
CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
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SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection
Bit
7
6
Name
5
4
3
CP0RIE
CP0FIE
2
R
R
R/W
R/W
R
R
Reset
0
0
0
0
0
0
R/W
1
0
Function
7:6
Unused
Read = 00b, Write = don’t care.
5
CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4
CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2
Unused
Read = 00b, Write = don’t care.
1:0
0
CP0MD[1:0]
Type
SFR Address = 0x9D; SFR Page = All Pages
Bit
Name
1
CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.5
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SFR Definition 8.3. CPT1CN: Comparator1 Control
Bit
7
6
5
4
Name
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP[1:0]
CP1HYN[1:0]
Type
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
SFR Address = 0x9A; SFR Page = All Pages
Bit
Name
7
CP1EN
3
2
0
0
1
0
0
0
Function
Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6
CP1OUT
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5
CP1RIF
Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4
CP1FIF
Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
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SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection
Bit
7
6
Name
5
4
3
CP1RIE
CP1FIE
2
R
R
R/W
R/W
R
R
Reset
0
0
0
0
0
0
R/W
1
0
Function
7:6
Unused
Read = 00b, Write = don’t care.
5
CP1RIE
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4
CP1FIE
Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2
Unused
Read = 00b, Write = don’t care.
1:0
0
CP1MD[1:0]
Type
SFR Address = 0x9C; SFR Page = All Pages
Bit
Name
1
CP1MD[1:0] Comparator1 Mode Select.
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
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8.1. Comparator Multiplexers
C8051F380/1/2/3/4/5/6/7/C devices include an analog input multiplexer to connect Port I/O pins to the
comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 8.5 and
SFR Definition 8.6). The CMXnP2–CMXnP0 bits select the Comparator positive input; the CMXnN2–CMXnN0 bits select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “20.3. General Purpose Port I/O” on page 161).
VDD
VDD
CP0 +
CP1 +
+
CP0 -
+
CP1 -
-
CPT0MX
CMX1P2
CMX1P1
CMX1P0
CMX1N2
CMX1N1
CMX1N0
GND
CMX0P2
CMX0P1
CMX0P0
CMX0N2
CMX0N1
CMX0N0
GND
CPT1MX
Figure 8.4. Comparator Input Multiplexer Block Diagram
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SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection
Bit
7
6
Name
5
4
3
CMX0N[2:0]
Type
R
Reset
0
R/W
0
6:4
3
2:0
Unused
1
R
0
0
CMX0P[2:0]
0
0
SFR Address = 0x9F; SFR Page = All Pages
Bit
Name
7
2
R/W
0
0
0
Function
Read = 0b; Write = don’t care.
CMX0N[2:0] Comparator0 Negative Input MUX Selection.
Unused
Selection
32-pin Package
48-pin Package
000:
P1.1
P2.1
001:
P1.5
P2.6
010:
P2.1
P3.5
011:
P2.5
P4.4
100:
P0.1
P0.4
101-111:
Reserved
Reserved
Read = 0b; Write = don’t care.
CMX0P[2:0] Comparator0 Positive Input MUX Selection.
Selection
32-pin Package
48-pin Package
000:
P1.0
P2.0
001:
P1.4
P2.5
010:
P2.0
P3.4
011:
P2.4
P4.3
100:
P0.0
P0.3
101-111:
Reserved
Reserved
Rev. 1.5
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SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection
Bit
7
6
Name
5
4
R
Reset
0
R/W
0
3
2:0
77
Unused
1
R
0
0
0
R/W
0
0
Function
Read = 0b; Write = don’t care.
CMX1N[2:0] Comparator1 Negative Input MUX Selection.
Unused
0
CMX1P[2:0]
SFR Address = 0x9E; SFR Page = All Pages
Bit
Name
6:4
2
CMX1N[2:0]
Type
7
3
Selection
32-pin Package
48-pin Package
000:
P1.3
P2.3
001:
P1.7
P3.1
010:
P2.3
P4.0
011:
Reserved
P4.6
100:
P0.5
P1.2
101-111:
Reserved
Reserved
Read = 0b; Write = don’t care.
CMX1P[2:0] Comparator1 Positive Input MUX Selection.
Selection
32-pin Package
48-pin Package
000:
P1.2
P2.2
001:
P1.6
P3.0
010:
P2.2
P3.7
011:
Reserved
P4.5
100:
P0.4
P1.1
101-111:
Reserved
Reserved
Rev. 1.5
0
C8051F380/1/2/3/4/5/6/7/C
9. Voltage Regulators (REG0 and REG1)
C8051F380/1/2/3/4/5/6/7/C devices include two internal voltage regulators: one regulates a voltage source
on REGIN to 3.3 V (REG0), and the other regulates the internal core supply to 1.8 V from a VDD supply of
1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the VDD pin and can be used to power
external devices. REG0 can be enabled/disabled by software using bit REG0DIS in register REG01CN
(SFR Definition 9.1). REG1 has two power-saving modes built into the regulator to help reduce current
consumption in low-power applications. These modes are accessed through the REG01CN register. Electrical characteristics for the on-chip regulators are specified in Table 5.5 on page 44.
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered
function. REG0 configuration options are shown in “4. Typical Connection Diagrams” Figure 4.1–
Figure 4.4.
9.1. Voltage Regulator (REG0)
See “4. Typical Connection Diagrams” for typical connection diagrams using the REG0 voltage regulator.
9.1.1. Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is
degraded. See Table 5.5 for normal and low power mode supply current specifications. The REG0 mode
selection is controlled via the REG0MD bit in register REG01CN.
9.1.2. VBUS Detection
When the USB Function Controller is used (see section Section “21. Universal Serial Bus Controller
(USB0)” on page 172), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG01CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal has either a falling or rising edge. The VBUS interrupt is edge-sensitive, and
has no associated interrupt pending flag. See Table 5.5 for VBUS input parameters.
Important Note: When USB is selected as a reset source, a system reset will be generated when a falling
or rising edge occurs on the VBUS pin. See Section “17. Reset Sources” on page 129 for details on selecting USB as a reset source.
9.2. Voltage Regulator (REG1)
Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode.
This allows any enabled reset source to generate a reset for the device and bring the device out of STOP
mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the internal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin
and a full power cycle of the device are the only methods of generating a reset.
REG1 offers an additional low power mode intended for use when the device is in suspend mode. This low
power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled.
See Table 5.5 for normal and low power mode supply current specifications. The REG1 mode selection is
controlled via the REG1MD bit in register REG01CN.
Important Note: At least 12 clock instructions must occur after placing REG1 in low power mode before
the Internal High Frequency Oscillator is Suspended (OSCICN.5 = 1b).
Rev. 1.5
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SFR Definition 9.1. REG01CN: Voltage Regulator Control
Bit
7
Name REG0DIS
6
5
4
3
2
1
0
VBSTAT
Reserved
REG0MD
STOPCF
Reserved
REG1MD
Reserved
Type
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC9; SFR Page = All Pages
Bit
Name
7
Function
REG0DIS Voltage Regulator (REG0) Disable.
This bit enables or disables the REG0 Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
6
VBSTAT
VBUS Signal Status.
This bit indicates whether the device is connected to a USB network.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
5
Reserved Must Write 0b.
4
REG0MD Voltage Regulator (REG0) Mode Select.
This bit selects the Voltage Regulator mode for REG0. When REG0MD is set to 1, the
REG0 voltage regulator operates in lower power (suspend) mode.
0: REG0 Voltage Regulator in normal mode.
1: REG0 Voltage Regulator in low power mode.
3
STOPCF Stop Mode Configuration (REG1).
This bit configures the REG1 regulator’s behavior when the device enters STOP mode.
0: REG1 Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: REG1 Regulator is shut down in STOP mode. Only the RST pin or power cycle can
reset the device.
2
Reserved Must Write 0b.
1
REG1MD Voltage Regulator (REG1) Mode.
This bit selects the Voltage Regulator mode for REG1. When REG1MD is set to 1, the
REG1 voltage regulator operates in lower power mode.
0: REG1 Voltage Regulator in normal mode.
1: REG1 Voltage Regulator in low power mode.
This bit should not be set to '1' if the REG0 Voltage Regulator is disabled.
0
79
Reserved Must Write 0b.
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
10. Power Management Modes
The C8051F380/1/2/3/4/5/6/7/C devices have three software programmable power management modes:
Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by the high-speed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Suspend mode is similar to stop mode in that the internal oscillator is halted, but the device can wake on activity with the USB transceiver. The CPU is not halted in suspend mode, so it can run on another oscillator, if
desired. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode and suspend
mode consume the least power because the majority of the device is shut down with no clocks active. SFR
Definition 10.1 describes the Power Control Register (PCON) used to control the C8051F380/1/2/3/4/5/6/
7/C's Stop and Idle power management modes. Suspend mode is controlled by the SUSPEND bit in the
OSCICN register (SFR Definition 19.3).
Although the C8051F380/1/2/3/4/5/6/7/C has Idle, Stop, and suspend modes available, more control over
the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off oscillators lowers power consumption considerably, at the expense of reduced functionality.
10.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01;
PCON = PCON;
// set IDLE bit
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
MOV PCON, PCON
; set IDLE bit
; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “17.6. PCA Watchdog Timer
Rev. 1.5
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Reset” on page 133 for more information on the use and configuration of the WDT.
10.2. Stop Mode
Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be configured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition 9.1).
If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of
resetting the device.
10.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator
and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. The CPU is not halted in Suspend, so code can still be executed using an oscillator other than the internal high-frequency oscillator.
Suspend mode can be terminated by resume signalling on the USB data pins, or a device reset event.
When suspend mode is terminated, if the oscillator source is the internal high-frequency oscillator, the
device will continue execution on the instruction following the one that set the SUSPEND bit. If the wake
event was configured to generate an interrupt, the interrupt will be serviced upon waking the device. If suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
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SFR Definition 10.1. PCON: Power Control
Bit
7
6
5
4
3
2
1
0
Name
GF[5:0]
STOP
IDLE
Type
R/W
R/W
R/W
0
0
Reset
0
0
0
SFR Address = 0x87; SFR Page = All Pages
Bit
Name
7:2
GF[5:0]
0
0
0
Function
General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1
STOP
Stop Mode Select.
Setting this bit will place the CIP-51 in stop mode. This bit will always be read as 0.
1: CPU goes into stop mode (internal oscillator stopped).
0
IDLE
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
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11. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 28), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 11.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set
48 MIPS Peak Throughput with 48 MHz Clock
0 to 48 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
D8
D8
ACCUMULATOR
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
D8
D8
D8
ALU
SRAM
D8
DATA BUS
B REGISTER
D8
D8
D8
DATA BUS
DATA BUS
SFR_ADDRESS
BUFFER
D8
D8
DATA POINTER
D8
SFR
BUS
INTERFACE
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
DATA BUS
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
MEM_ADDRESS
D8
MEM_CONTROL
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
RESET
D8
CONTROL
LOGIC
SYSTEM_IRQs
CLOCK
D8
STOP
IDLE
POWER CONTROL
REGISTER
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
Figure 11.1. CIP-51 Block Diagram
83
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With the CIP-51's maximum system clock at 48 MHz, it has a peak throughput of 48 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execution time.
Clocks to Execute
1
2
2/4
3
3/5
4
5
4/6
6
8
Number of Instructions
26
50
5
10
6
5
2
2
2
1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “28. C2 Interface” on page 316.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available.
11.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
11.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 11.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
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Table 11.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Logical Operations
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
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Table 11.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Description
Bytes
Clock
Cycles
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
3
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
1
2
1
2
1
2
1
2
1
2
1
2
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Boolean Manipulation
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
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Table 11.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
Description
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Bytes
Clock
Cycles
2
2
2
2
2
2
2
2
2
2
2
2
Program Flow
Timings are listed with the PFE on and FLRT = 0. Extra cycles are required for branches if FLRT = 1.
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
87
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Rev. 1.5
2
2
3
3
3
2
3
1
1
2
3
2
1
2
2
3
3
3
2/4
2/4
3/5
3/5
3/5
4
5
6
6
4
5
4
4
2/4
2/4
4/6
3/5
3/5
3
4/6
2
3
1
2/4
3/5
1
C8051F380/1/2/3/4/5/6/7/C
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Rev. 1.5
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11.2. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should always be written to the value indicated in the SFR description. Future product versions may use
these bits to implement new features in which case the reset value of the bit will be the indicated value,
selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
SFR Definition 11.1. DPL: Data Pointer Low Byte
Bit
7
6
5
4
Name
DPL[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x82; SFR Page = All Pages
Bit
Name
7:0
DPL[7:0]
3
2
1
0
0
0
0
0
3
2
1
0
0
0
0
0
Function
Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR.
SFR Definition 11.2. DPH: Data Pointer High Byte
Bit
7
6
5
4
Name
DPH[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x83; SFR Page = All Pages
Bit
Name
7:0
DPH[7:0]
Function
Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR.
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SFR Definition 11.3. SP: Stack Pointer
Bit
7
6
5
4
Name
SP[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0x81; SFR Page = All Pages
Bit
Name
7:0
SP[7:0]
3
2
1
0
0
1
1
1
Function
Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 11.4. ACC: Accumulator
Bit
7
6
5
4
Name
ACC[7:0]
Type
R/W
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7:0
ACC[7:0]
Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 11.5. B: B Register
Bit
7
6
5
4
Name
B[7:0]
Type
R/W
Reset
0
0
0
0
3
2
1
0
0
0
0
0
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7:0
B[7:0]
B Register.
This register serves as a second accumulator for certain arithmetic operations.
Rev. 1.5
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SFR Definition 11.6. PSW: Program Status Word
Bit
7
6
5
Name
CY
AC
F0
Type
R/W
R/W
R/W
Reset
0
0
0
4
3
2
1
0
RS[1:0]
OV
F1
PARITY
R/W
R/W
R/W
R
0
0
0
0
0
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3
RS[1:0]
Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An
ADD, ADDC, or SUBB instruction causes a sign-change overflow.
MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
A
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
0
PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
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12. Prefetch Engine
The C8051F380/1/2/3/4/5/6/7/C family of devices incorporate a 2-byte prefetch engine. Because the
access time of the Flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch
engine is necessary for code execution above 25 MHz. When operating at speeds greater than 25 MHz,
the prefetch engine must be enabled by setting PFE0CN.PFEN and FLSCL.FLRT to 1. Instructions are
read from Flash memory two bytes at a time by the prefetch engine and given to the CIP-51 processor
core to execute. When running linear code (code without any jumps or branches), the prefetch engine
allows instructions to be executed at full speed. When a code branch occurs, the processor may be stalled
for up to two clock cycles while the next set of code bytes is retrieved from Flash memory. It is recommended that the prefetch be used for optimal code execution timing.
Note: The prefetch engine can be disabled when the device is in suspend mode to save power.
SFR Definition 12.1. PFE0CN: Prefetch Engine Control
Bit
7
6
Name
5
4
3
2
1
PFEN
0
FLBWE
Type
R
R
R/W
R
R
R
R
R/W
Reset
0
0
1
0
0
0
0
0
SFR Address = 0xAF; SFR Page = All Pages
Bit
Name
7:6
Unused
5
PFEN
Function
Read = 00b, Write = don’t care.
Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
4:1
Unused
Read = 0000b. Write = don’t care.
0
FLBWE
Flash Block Write Enable.
This bit allows block writes to Flash memory from software.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
Rev. 1.5
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13. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 13.1 and Figure 13.2.
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
0xFF
RESERVED
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
EXTERNAL DATA ADDRESS SPACE
0x0000
0xFFFF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x1000
0x0FFF
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
USB FIFOs
1024 Bytes
0x0000
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F380/1/4/5)
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0x0400
C8051F380/1/2/3/4/5/6/7/C
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
PROGRAM/DATA MEMORY
(FLASH)
0x7FFF
0xFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x0800
0x07FF
XRAM - 2048 Bytes
(Accessable using MOVX
instruction)
USB FIFOs
1024 Bytes
0x07FF
0x0400
0x0000
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F382/3/6/7)
Rev. 1.5
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DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
PROGRAM/DATA MEMORY
(FLASH)
0xFF
0x3FFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x80
0x7F
(Direct and Indirect
Addressing)
0x30
0x2F
0x20
0x1F
0x00
0x0000
Upper 128 RAM
(Indirect Addressing
Only)
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x0800
0x07FF
XRAM - 2048 Bytes
(Accessable using MOVX
instruction)
USB FIFOs
1024 Bytes
0x07FF
0x0400
0x0000
Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C)
13.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F380/1/2/3/4/5/6/7/C implements
64 kB, 32 kB, or 16 kB of this program memory space as in-system, re-programmable Flash memory. Note
that on the C8051F380/1/4/5 (64 kB version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature
provides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to Section “18. Flash Memory” on page 135 for further details.
13.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.
Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
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The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 13.1 illustrates the data memory organization of the CIP-51.
13.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 11.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
13.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
13.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
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14. External Data Memory Interface and On-Chip XRAM
4 kB (C8051F380/1/4/5) or 2 kB (C8051F382/3/6/7/C) of RAM are included on-chip, and mapped into the
external data memory space (XRAM). The 1 kB of USB FIFO space can also be mapped into XRAM
address space for additional general-purpose data storage. Additionally, an External Memory Interface
(EMIF) is available on the C8051F380/2/4/6 devices, which can be used to access off-chip data memories
and memory-mapped devices connected to the GPIO ports. The external memory space may be accessed
using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect
addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as
@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in SFR Definition 14.1). Note: the MOVX instruction can also be used for writing to
the FLASH memory. See Section “18. Flash Memory” on page 135 for details. The MOVX instruction
accesses XRAM by default.
14.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
14.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV
MOVX
DPTR, #1234h
A, @DPTR
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
14.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper
8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of
the effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
97
EMI0CN, #12h
R0, #34h
a, @R0
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
14.2. Accessing USB FIFO Space
The C8051F380/1/2/3/4/5/6/7/C include 1k of RAM which functions as USB FIFO space. Figure 14.1
shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB
FIFO registers; see Section “21.5. FIFO Management” on page 181 for more information on accessing
these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to 1, and (2) the USB clock must be greater than or equal to
twice the SYSCLK (USBCLK > 2 x SYSCLK). When this bit is set, the USB FIFO space is mapped into
XRAM space at addresses 0x0400 to 0x07FF. The normal XRAM (on-chip or external) at the same
addresses cannot be accessed when the USBFAE bit is set to 1.
Important Note: The USB clock must be active when accessing FIFO space.
0xFFFF
On/Off-Chip XRAM
0x0800
0x07FF
Endpoint0
(64 bytes)
0x07C0
0x07BF
Endpoint1
(128 bytes)
0x0740
0x073F
Endpoint2
(256 bytes)
USB FIFO Space
0x0640
0x063F
(USB Clock Domain)
Endpoint3
(512 bytes)
0x0440
0x043F
Free
(64 bytes)
0x0400
0x03FF
On/Off-Chip XRAM
0x0000
Figure 14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’
Rev. 1.5
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14.3. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
most common), and skip the associated pins in the crossbar.
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
5. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 14.5.
14.4. Port Configuration
The External Memory Interface appears on Ports 4, 3, 2, and 1 when it is used for off-chip memory access.
When the EMIF is used, the Crossbar should be configured to skip over the control lines P1.7 (WR), P1.6
(RD), and if multiplexed mode is selected P1.3 (ALE) using the P1SKIP register. For more information
about configuring the Crossbar, see Section “Figure 20.1. Port I/O Functional Block Diagram (Port 0
through Port 3)” on page 153.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar settings for those pins. See Section “20. Port Input/Output” on page 153 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
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SFR Definition 14.1. EMI0CN: External Memory Interface Control
Bit
7
6
5
4
3
Name
PGSEL[7:0]
Type
R/W
Reset
0
0
0
SFR Address = 0xAA; SFR Page = All Pages
Bit
Name
7:0
PGSEL[7:0]
0
0
2
1
0
0
0
0
Function
XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte
page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
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SFR Definition 14.2. EMI0CF: External Memory Interface Configuration
Bit
7
Name
6
5
USBFAE
4
3
2
1
0
EMD2
EMD[1:0]
EALE[1:0]
R/W
R/W
Type
R
R/W
R
R/W
Reset
0
0
0
0
SFR Address = 0x85; SFR Page = All Pages
Bit
Name
0
0
1
1
Function
7
Unused
Read = 0b; Write = don’t care.
6
USBFAE
USB FIFO Access Enable.
0: USB FIFO RAM not available through MOVX instructions.
1: USB FIFO RAM available using MOVX instructions. The 1k of USB RAM will be
mapped in XRAM space at addresses 0x0400 to 0x07FF. The USB clock must be
active and greater than or equal to twice the SYSCLK (USBCLK > 2 x
SYSCLK) to access this area with MOVX instructions.
5
Unused
Read = 0b; Write = don’t care.
4
EMD2
EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
3:2
EMD[1:0]
EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses
alias to on-chip memory space.
01: Split Mode without Bank Select: Accesses below the on-chip XRAM boundary
are directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the current contents of the Address
High port latches to resolve upper address byte. Note that in order to access
off-chip space, EMI0CN must be set to a page that is not contained in the on-chip
address space.
10: Split Mode with Bank Select: Accesses below the on-chip XRAM boundary are
directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine
the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.
1:0
EALE[1:0]
ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
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14.5. Multiplexed and Non-multiplexed Selection
The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode,
depending on the state of the EMD2 (EMI0CF.4) bit.
14.5.1. Multiplexed Configuration
In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins:
AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits
of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is
driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in
Figure 14.2.
In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “14.7.2. Multiplexed Mode” on page 111 for more information.
A[15:8]
A[15:8]
ADDRESS BUS
74HC373
E
M
I
F
ALE
AD[7:0]
G
ADDRESS/DATA BUS
D
Q
A[7:0]
VDD
64K X 8
SRAM
(Optional)
8
I/O[7:0]
CE
WE
OE
WR
RD
Figure 14.2. Multiplexed Configuration Example
14.5.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a
Non-multiplexed Configuration is shown in Figure 14.3. See Section “14.7.1. Non-multiplexed Mode” on
page 108 for more information about Non-multiplexed operation.
Rev. 1.5
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C8051F380/1/2/3/4/5/6/7/C
E
M
I
F
A[15:0]
A[15:0]
ADDRESS BUS
VDD
(Optional)
8
D[7:0]
DATA BUS
64K X 8
SRAM
I/O[7:0]
CE
WE
OE
WR
RD
Figure 14.3. Non-multiplexed Configuration Example
103
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14.6. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 14.4, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 14.5). These modes are summarized below.
More information about the different modes can be found in Section “14.7. Timing” on page 106.
EMI0CF[3:2] = 00
EMI0CF[3:2] = 01
0xFFFF
EMI0CF[3:2] = 11
EMI0CF[3:2] = 10
0xFFFF
0xFFFF
0xFFFF
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
0x0000
0x0000
0x0000
Figure 14.4. EMIF Operating Modes
14.6.1. Internal XRAM Only
When EMI0CF.[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the device.
Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries (depending
on the RAM available on the device). As an example, the addresses 0x1000 and 0x2000 both evaluate to
address 0x0000 in on-chip XRAM space.
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
14.6.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and
off-chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
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14.6.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and
off-chip space.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is
on-chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the
lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus
A[15:0] are driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
14.6.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
105
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14.7. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 14.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 for ALE + 1 for RD or WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 14.1 lists the AC parameters for the External
Memory Interface, and Figure 14.5 through Figure 14.10 show the timing diagrams for the different External Memory Interface modes and MOVX operations.
Rev. 1.5
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SFR Definition 14.3. EMI0TC: External Memory TIming Control
Bit
7
6
5
4
3
2
1
0
Name
EAS[1:0]
EWR[3:0]
EAH[1:0]
Type
R/W
R/W
R/W
Reset
1
1
1
1
SFR Address = 0x84; SFR Page = All Pages
Bit
Name
7:6
EAS[1:0]
1
1
Function
EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
5:2
EWR[3:0]
EMIF WR and RD Pulse-Width Control Bits.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0
EAH[1:0]
EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
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C8051F380/1/2/3/4/5/6/7/C
14.7.1. Non-multiplexed Mode
14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111
Nonmuxed 16-bit WRITE
ADDR[15:8]
P2
EMIF ADDRESS (8 MSBs) from DPH
P2
ADDR[7:0]
P3
EMIF ADDRESS (8 LSBs) from DPL
P3
DATA[7:0]
P4
EMIF WRITE DATA
P4
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
WR
P1.7
P1.7
RD
P1.6
P1.6
Nonmuxed 16-bit READ
ADDR[15:8]
P2
EMIF ADDRESS (8 MSBs) from DPH
P2
ADDR[7:0]
P3
EMIF ADDRESS (8 LSBs) from DPL
P3
DATA[7:0]
P4
EMIF READ DATA
P4
T
RDS
T
ACS
T
ACW
T
RDH
T
ACH
RD
P1.6
P1.6
WR
P1.7
P1.7
Figure 14.5. Non-Multiplexed 16-bit MOVX Timing
Rev. 1.5
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14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111
Nonmuxed 8-bit WRITE without Bank Select
ADDR[15:8]
P2
ADDR[7:0]
P3
EMIF ADDRESS (8 LSBs) from R0 or R1
P3
DATA[7:0]
P4
EMIF WRITE DATA
P4
T
T
WDS
T
WDH
T
ACS
T
ACW
ACH
WR
P1.7
P1.7
RD
P1.6
P1.6
Nonmuxed 8-bit READ without Bank Select
ADDR[15:8]
P2
ADDR[7:0]
P3
DATA[7:0]
P4
EMIF ADDRESS (8 LSBs) from R0 or R1
EMIF READ DATA
T
RDS
T
T
ACS
ACW
P4
T
RDH
T
ACH
RD
P1.6
P1.6
WR
P1.7
P1.7
Figure 14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing
109
P3
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14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110
Muxed 8-bit WRITE with Bank Select
ADDR[15:8]
P3
AD[7:0]
P4
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ALE
P3
EMIF WRITE DATA
P4
T
ALEL
P1.3
P1.3
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
WR
P1.7
P1.7
RD
P1.6
P1.6
Muxed 8-bit READ with Bank Select
ADDR[15:8]
P3
AD[7:0]
P4
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ALE
P3
EMIF READ DATA
T
T
ALEL
RDS
P4
T
RDH
P1.3
P1.3
T
ACS
T
ACW
T
ACH
RD
P1.6
P1.6
WR
P1.7
P1.7
Figure 14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing
Rev. 1.5
110
C8051F380/1/2/3/4/5/6/7/C
14.7.2. Multiplexed Mode
14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011
Muxed 16-bit WRITE
ADDR[15:8]
P3
AD[7:0]
P4
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
ALE
P3
EMIF WRITE DATA
P4
T
ALEL
P1.3
P1.3
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
WR
P1.7
P1.7
RD
P1.6
P1.6
Muxed 16-bit READ
ADDR[15:8]
P3
AD[7:0]
P4
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
ALE
P3
EMIF READ DATA
T
T
ALEL
RDS
T
RDH
P1.3
P1.3
T
ACS
T
ACW
T
ACH
RD
P1.6
P1.6
WR
P1.7
P1.7
Figure 14.8. Multiplexed 16-bit MOVX Timing
111
P4
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Muxed 8-bit WRITE Without Bank Select
ADDR[15:8]
AD[7:0]
P3
P4
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ALE
EMIF WRITE DATA
P4
T
ALEL
P1.3
P1.3
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
WR
P1.7
P1.7
RD
P1.6
P1.6
Muxed 8-bit READ Without Bank Select
ADDR[15:8]
AD[7:0]
P3
P4
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ALE
EMIF READ DATA
T
T
ALEL
RDS
P4
T
RDH
P1.3
P1.3
T
ACS
T
ACW
T
ACH
RD
P1.6
P1.6
WR
P1.7
P1.7
Figure 14.9. Multiplexed 8-bit MOVX without Bank Select Timing
Rev. 1.5
112
C8051F380/1/2/3/4/5/6/7/C
14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010
Muxed 8-bit WRITE with Bank Select
ADDR[15:8]
P3
AD[7:0]
P4
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ALE
P3
EMIF WRITE DATA
P4
T
ALEL
P1.3
P1.3
T
T
WDS
T
ACS
WDH
T
T
ACW
ACH
WR
P1.7
P1.7
RD
P1.6
P1.6
Muxed 8-bit READ with Bank Select
ADDR[15:8]
P3
AD[7:0]
P4
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
ALE
P3
EMIF READ DATA
T
T
ALEL
RDS
T
RDH
P1.3
P1.3
T
ACS
T
ACW
T
ACH
RD
P1.6
P1.6
WR
P1.7
P1.7
Figure 14.10. Multiplexed 8-bit MOVX with Bank Select Timing
113
P4
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table 14.1. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
Units
TACS
Address/Control Setup Time
0
3 x TSYSCLK
ns
TACW
Address/Control Pulse Width
1 x TSYSCLK
16 x TSYSCLK
ns
TACH
Address/Control Hold Time
0
3 x TSYSCLK
ns
TALEH
Address Latch Enable High Time
1 x TSYSCLK
4 x TSYSCLK
ns
TALEL
Address Latch Enable Low Time
1 x TSYSCLK
4 x TSYSCLK
ns
TWDS
Write Data Setup Time
1 x TSYSCLK
19 x TSYSCLK
ns
TWDH
Write Data Hold Time
0
3 x TSYSCLK
ns
TRDS
Read Data Setup Time
20
ns
TRDH
Read Data Hold Time
0
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 1.5
114
C8051F380/1/2/3/4/5/6/7/C
15. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F380/1/2/3/4/5/6/7/C's resources
and peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as
well as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F380/1/2/3/4/5/6/7/C. This allows the addition of new functionality while retaining compatibility with
the MCS-51™ instruction set. Table 15.1 lists the SFRs implemented in the C8051F380/1/2/3/4/5/6/7/C
device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 15.2, for a detailed description of each register.
15.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F380/1/2/3/4/5/6/7/C devices utilize two SFR pages: 0x0,
and 0xF. Most SFRs are available on both pages. SFR pages are selected using the Special Function
Register Page Selection register, SFRPAGE. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
Important Note: When reading or writing SFRs that are not available on all pages within an ISR, it is recommended to save the state of the SFRPAGE register on ISR entry, and restore state on exit.
SFR Definition 15.1. SFRPAGE: SFR Page
Bit
7
6
5
4
3
Name
SFRPAGE[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xBF; SFR Page = All Pages
Bit
Name
7:0
SFRPAGE[7:0]
0
2
1
0
0
0
0
Function
SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
115
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Page
Address
Table 15.1. Special Function Register (SFR) Memory Map
F8
F0
E8
E0
0
F
D8
D0
0
F
0
C0
F
0
B8
F
B0
A8
A0
98
0
90
F
88
80
C8
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
SPI0CN PCA0L
PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4
B
P0MDIN
P1MDIN
P2MDIN
P3MDIN
P4MDIN
EIP1
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3
IT01CF
ACC
XBR0
XBR1
XBR2
SMOD1
EIE1
CKCON1
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
PSW
REF0CN
SCON1
SBUF1
P0SKIP
P1SKIP
P2SKIP
TMR2CN
TMR2RLL TMR2RLH
TMR2L
TMR2H SMB0ADM
REG01CN
TMR5CN
TMR5RLL TMR5RLH
TMR5L
TMR5H SMB1ADM
SMB0CN SMB0CF SMB0DAT
ADC0GTL ADC0GTH ADC0LTL ADC0LTH
SMB1CN SMB1CF SMB1DAT
CLKMUL
ADC0CF
IP
AMX0N
AMX0P
ADC0L
ADC0H
SMBTC
P3
OSCXCN OSCICN
OSCICL
SBRLL1
SBRLH1
FLSCL
IE
CLKSEL
EMI0CN
SBCON1
P4MDOUT
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT
SCON0
SBUF0
CPT1CN
CPT0CN
CPT1MD
CPT0MD
CPT1MX
TMR3CN TMR3RLL TMR3RLH
TMR3L
TMR3H
P1
USB0ADR
TMR4CN TMR4RLL TMR4RLH
TMR4L
TMR4H
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P0
SP
DPL
DPH
EMI0TC
EMI0CF
OSCLCN
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
VDM0CN
EIP2
RSTSRC
EIE2
P3SKIP
USB0XCN
SMB0ADR
SMB1ADR
P4
SFRPAGE
FLKEY
PFE0CN
P3MDOUT
CPT0MX
USB0DAT
PSCTL
PCON
7(F)
Notes:
1. SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
2. Unless indicated otherwise, SFRs are available on both page 0 and page F.
Rev. 1.5
116
C8051F380/1/2/3/4/5/6/7/C
Table 15.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Page
Description
Page
ACC
0xE0
All Pages Accumulator
90
ADC0CF
0xBC
All Pages ADC0 Configuration
57
ADC0CN
0xE8
All Pages ADC0 Control
59
ADC0GTH
0xC4
All Pages ADC0 Greater-Than Compare High
60
ADC0GTL
0xC3
All Pages ADC0 Greater-Than Compare Low
60
ADC0H
0xBE
All Pages ADC0 High
58
ADC0L
0xBD
All Pages ADC0 Low
58
ADC0LTH
0xC6
All Pages ADC0 Less-Than Compare Word High
61
ADC0LTL
0xC5
All Pages ADC0 Less-Than Compare Word Low
61
AMX0N
0xBA
All Pages AMUX0 Negative Channel Select
65
AMX0P
0xBB
All Pages AMUX0 Positive Channel Select
64
B
0xF0
All Pages B Register
90
CKCON
0x8E
All Pages Clock Control
264
CKCON1
0xE4
F
Clock Control 1
265
CLKMUL
0xB9
0
Clock Multiplier
147
CLKSEL
0xA9
All Pages Clock Select
144
CPT0CN
0x9B
All Pages Comparator0 Control
71
CPT0MD
0x9D
All Pages Comparator0 Mode Selection
72
CPT0MX
0x9F
All Pages Comparator0 MUX Selection
76
CPT1CN
0x9A
All Pages Comparator1 Control
73
CPT1MD
0x9C
All Pages Comparator1 Mode Selection
74
CPT1MX
0x9E
All Pages Comparator1 MUX Selection
77
DPH
0x83
All Pages Data Pointer High
89
DPL
0x82
All Pages Data Pointer Low
89
EIE1
0xE6
All Pages Extended Interrupt Enable 1
123
EIE2
0xE7
All Pages Extended Interrupt Enable 2
125
EIP1
0xF6
All Pages Extended Interrupt Priority 1
124
EIP2
0xF7
All Pages Extended Interrupt Priority 2
126
EMI0CF
0x85
All Pages External Memory Interface Configuration
101
EMI0CN
0xAA
All Pages External Memory Interface Control
100
EMI0TC
0x84
All Pages External Memory Interface Timing
107
FLKEY
0xB7
All Pages Flash Lock and Key
140
FLSCL
0xB6
All Pages Flash Scale
141
117
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Page
Description
Page
IE
0xA8
All Pages Interrupt Enable
121
IP
0xB8
All Pages Interrupt Priority
122
IT01CF
0xE4
OSCICL
0xB3
All Pages Internal Oscillator Calibration
145
OSCICN
0xB2
All Pages Internal Oscillator Control
146
OSCLCN
0x86
All Pages Internal Low-Frequency Oscillator Control
148
OSCXCN
0xB1
All Pages External Oscillator Control
152
P0
0x80
All Pages Port 0 Latch
162
P0MDIN
0xF1
All Pages Port 0 Input Mode Configuration
162
P0MDOUT
0xA4
All Pages Port 0 Output Mode Configuration
163
P0SKIP
0xD4
All Pages Port 0 Skip
163
P1
0x90
All Pages Port 1 Latch
164
P1MDIN
0xF2
All Pages Port 1 Input Mode Configuration
164
P1MDOUT
0xA5
All Pages Port 1 Output Mode Configuration
165
P1SKIP
0xD5
All Pages Port 1 Skip
165
P2
0xA0
All Pages Port 2 Latch
166
P2MDIN
0xF3
All Pages Port 2 Input Mode Configuration
166
P2MDOUT
0xA6
All Pages Port 2 Output Mode Configuration
167
P2SKIP
0xD6
All Pages Port 2 Skip
167
P3
0xB0
All Pages Port 3 Latch
168
P3MDIN
0xF4
All Pages Port 3 Input Mode Configuration
168
P3MDOUT
0xA7
All Pages Port 3 Output Mode Configuration
169
P3SKIP
0xDF
All Pages Port 3Skip
169
P4
0xC7
All Pages Port 4 Latch
170
P4MDIN
0xF5
All Pages Port 4 Input Mode Configuration
170
P4MDOUT
0xAE
All Pages Port 4 Output Mode Configuration
171
PCA0CN
0xD8
All Pages PCA Control
311
PCA0CPH0
0xFC
All Pages PCA Capture 0 High
315
PCA0CPH1
0xEA
All Pages PCA Capture 1 High
315
PCA0CPH2
0xEC
All Pages PCA Capture 2 High
315
PCA0CPH3
0xEE
All Pages PCA Capture 3High
315
PCA0CPH4
0xFE
All Pages PCA Capture 4 High
315
PCA0CPL0
0xFB
All Pages PCA Capture 0 Low
315
PCA0CPL1
0xE9
All Pages PCA Capture 1 Low
315
0
INT0/INT1 Configuration
Rev. 1.5
128
118
C8051F380/1/2/3/4/5/6/7/C
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
PCA0CPL2
0xEB
All Pages PCA Capture 2 Low
315
PCA0CPL3
0xED
All Pages PCA Capture 3 Low
315
PCA0CPL4
0xFD
All Pages PCA Capture 4 Low
315
PCA0CPM0
0xDA
All Pages PCA Module 0 Mode Register
313
PCA0CPM1
0xDB
All Pages PCA Module 1 Mode Register
313
PCA0CPM2
0xDC
All Pages PCA Module 2 Mode Register
313
PCA0CPM3
0xDD
All Pages PCA Module 3 Mode Register
313
PCA0CPM4
0xDE
All Pages PCA Module 4 Mode Register
313
PCA0H
0xFA
All Pages PCA Counter High
314
PCA0L
0xF9
All Pages PCA Counter Low
314
PCA0MD
0xD9
All Pages PCA Mode
312
PCON
0x87
All Pages Power Control
82
PFE0CN
0xAF
All Pages Prefetch Engine Control
92
PSCTL
0x8F
All Pages Program Store R/W Control
139
PSW
0xD0
All Pages Program Status Word
91
REF0CN
0xD1
All Pages Voltage Reference Control
67
REG01CN
0xC9
All Pages Voltage Regulator 0 and 1 Control
79
RSTSRC
0xEF
All Pages Reset Source Configuration/Status
134
SBCON1
0xAC
All Pages UART1 Baud Rate Generator Control
248
SBRLH1
0xB5
All Pages UART1 Baud Rate Generator High
248
SBRLL1
0xB4
All Pages UART1 Baud Rate Generator Low
249
SBUF0
0x99
All Pages UART0 Data Buffer
238
SBUF1
0xD3
All Pages UART1 Data Buffer
247
SCON0
0x98
All Pages UART0 Control
237
SCON1
0xD2
All Pages UART1 Control
245
SFRPAGE
0xBF
All Pages SFR Page Select
115
SMB0ADM
0xCE
0
SMBus0 Address Mask
219
SMB0ADR
0xCF
0
SMBus0 Address
218
SMB0CF
0xC1
0
SMBus0 Configuration
211
SMB0CN
0xC0
0
SMBus0 Control
215
SMB0DAT
0xC2
0
SMBus0 Data
221
SMB1ADM
0xCE
F
SMBus1 Address Mask
220
SMB1ADR
0xCF
F
SMBus1 Address
219
SMB1CF
0xC1
F
SMBus1 Configuration
211
119
Page
Description
Rev. 1.5
Page
C8051F380/1/2/3/4/5/6/7/C
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Page
Description
SMB1CN
0xC0
F
SMBus1 Control
216
SMB1DAT
0xC2
F
SMBus1 Data
222
SMBTC
0xB9
F
SMBus0/1 Timing Control
213
SMOD1
0xE5
All Pages UART1 Mode
246
SP
0x81
All Pages Stack Pointer
90
SPI0CFG
0xA1
All Pages SPI Configuration
257
SPI0CKR
0xA2
All Pages SPI Clock Rate Control
259
SPI0CN
0xF8
All Pages SPI Control
258
SPI0DAT
0xA3
All Pages SPI Data
259
TCON
0x88
All Pages Timer/Counter Control
270
TH0
0x8C
All Pages Timer/Counter 0 High
273
TH1
0x8D
All Pages Timer/Counter 1 High
273
TL0
0x8A
All Pages Timer/Counter 0 Low
272
TL1
0x8B
All Pages Timer/Counter 1 Low
272
TMOD
0x89
All Pages Timer/Counter Mode
271
TMR2CN
0xC8
0
Timer/Counter 2 Control
278
TMR2H
0xCD
0
Timer/Counter 2 High
280
TMR2L
0xCC
0
Timer/Counter 2 Low
279
TMR2RLH
0xCB
0
Timer/Counter 2 Reload High
279
TMR2RLL
0xCA
0
Timer/Counter 2 Reload Low
279
TMR3CN
0x91
0
Timer/Counter 3 Control
285
TMR3H
0x95
0
Timer/Counter 3 High
287
TMR3L
0x94
0
Timer/Counter 3 Low
286
TMR3RLH
0x93
0
Timer/Counter 3 Reload High
286
TMR3RLL
0x92
0
Timer/Counter 3 Reload Low
286
TMR4CN
0x91
F
Timer/Counter 4 Control
290
TMR4H
0x95
F
Timer/Counter 4 High
292
TMR4L
0x94
F
Timer/Counter 4 Low
291
TMR4RLH
0x93
F
Timer/Counter 4 Reload High
291
TMR4RLL
0x92
F
Timer/Counter 4 Reload Low
291
TMR5CN
0xC8
F
Timer/Counter 5 Control
295
TMR5H
0xCD
F
Timer/Counter 5 High
297
TMR5L
0xCC
F
Timer/Counter 5 Low
296
TMR5RLH
0xCB
F
Timer/Counter 5 Reload High
296
Rev. 1.5
Page
120
C8051F380/1/2/3/4/5/6/7/C
Table 15.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Page
TMR5RLL
0xCA
F
USB0ADR
0x96
All Pages USB0 Indirect Address Register
176
USB0DAT
0x97
All Pages USB0 Data Register
177
USB0XCN
0xD7
All Pages USB0 Transceiver Control
174
VDM0CN
0xFF
132
XBR0
0xE1
All Pages VDD Monitor Control
All Pages Port I/O Crossbar Control 0
XBR1
0xE2
All Pages Port I/O Crossbar Control 1
160
XBR2
0xE3
All Pages Port I/O Crossbar Control 2
161
121
Description
Timer/Counter 5 Reload Low
Rev. 1.5
Page
296
159
C8051F380/1/2/3/4/5/6/7/C
16. Interrupts
The C8051F380/1/2/3/4/5/6/7/C include an extended interrupt system supporting multiple interrupt sources
with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs
pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE, EIE1, or EIE2). However, interrupts must first be globally enabled by setting the
EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0
disables all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. Using EA (global interrupt enable) as an example:
// in 'C':
EA = 0; // clear EA bit.
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction
which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the enable bit will return a 0 inside the interrupt service
routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
Rev. 1.5
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C8051F380/1/2/3/4/5/6/7/C
16.1. MCU Interrupt Sources and Vectors
The C8051F380/1/2/3/4/5/6/7/C MCUs support several interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt
request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending
flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in
Table 16.1. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
16.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 16.1.
16.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write operations and USB FIFO MOVX accesses. Interrupt service latency will be increased for interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount
of time the CPU is stalled.
16.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
123
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Priority
Order
Reset
0x0000
Top
External Interrupt 0
(INT0)
Timer 0 Overflow
External Interrupt 1
(INT1)
Timer 1 Overflow
UART0
0x0003
0
0x000B
0x0013
Pending Flag
None
by HW?
Interrupt
Vector
Bit
Interrupt Source
Address?
Cleared
Table 16.1. Interrupt Summary
Enable
Flag
Priority
Control
N/A
N/A
IE0 (TCON.1)
Y
Y
Always
Always
Enabled
Highest
EX0 (IE.0) PX0 (IP.0)
1
2
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
0x001B
0x0023
3
4
Y
Y
Y
N
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
0x002B
5
Y
N
ET2 (IE.5) PT2 (IP.5)
SPI0
0x0033
6
Y
N
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
0x003B
7
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
N
USB0
0x0043
8
Special
N
N
ADC0 Window Compare
ADC0 Conversion
Complete
Programmable
Counter Array
Comparator0
0x004B
9
Y
N
0x0053
10
AD0WINT
(ADC0CN.3)
AD0INT (ADC0CN.5)
Y
N
0x005B
11
Y
N
0x0063
12
N
N
Comparator1
0x006B
13
N
N
Timer 3 Overflow
0x0073
14
N
N
VBUS Level
0x007B
15
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N/A
N/A
N/A
UART1
0x0083
16
N
N
Reserved
SMB1
0x008B
0x0093
17
18
N/A
Y
N/A
N
Timer 4 Overflow
0x009B
19
N
N
Timer 5 Overflow
0x00A3
20
Y
N
ESMB0
(EIE1.0)
EUSB0
(EIE1.1)
EWADC0
(EIE1.2)
EADC0
(EIE1.3)
EPCA0
(EIE1.4)
ECP0
(EIE1.5)
ECP1
(EIE1.6)
ET3
(EIE1.7)
EVBUS
(EIE2.0)
ES1
(EIE2.1)
N/A
ESMB1
(EIE2.3)
ET4
(EIE2.4)
ET5
(EIE2.5)
PSMB0
(EIP1.0)
PUSB0
(EIP1.1)
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PCP1
(EIP1.6)
PT3
(EIP1.7)
PVBUS
(EIP2.0)
PS1
(EIP2.1)
N/A
PSMB1
(EIP2.3)
PT4
(E!P2.4)
PT5
(E!P2.5)
RI1 (SCON1.0)
TI1 (SCON1.1)
N/A
SI (SMB1CN.0)
TF4H (TMR4CN.7)
TF4L (TMR4CN.6)
TF5H (TMR5CN.7)
TF5L (TMR5CN.6)
Rev. 1.5
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C8051F380/1/2/3/4/5/6/7/C
SFR Definition 16.1. IE: Interrupt Enable
Bit
7
6
5
4
3
2
1
0
Name
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
EA
6
ESPI0
5
ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4
ES0
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3
ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2
EX1
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1
ET0
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0
EX0
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
125
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 16.2. IP: Interrupt Priority
Bit
7
Name
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
0
0
SFR Address = 0xB8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
Unused
Read = 1b, Write = Don't Care.
6
PSPI0
5
PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4
PS0
UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3
PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2
PX1
External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1
PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0
PX0
External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Rev. 1.5
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SFR Definition 16.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
5
4
3
2
1
0
Name
ET3
ECP1
ECP0
EPCA0
EADC0
EWADC0
EUSB0
ESMB0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE6; SFR Page = All Pages
Bit
Name
Function
7
ET3
6
ECP1
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
5
ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4
EPCA0
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3
EADC0
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1
EUSB0
Enable USB (USB0) Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
0
ESMB0
Enable SMBus0 Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
127
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 16.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
Name
PT3
PCP1
PCP0
PPCA0
PADC0
PWADC0
PUSB0
PSMB0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF6; SFR Page = All Pages
Bit
Name
Function
7
PT3
Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6
PCP1
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5
PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4
PPCA0
Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3
PADC0
ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2
PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1
PUSB0
USB (USB0) Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
0
PSMB0
SMBus0 Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
Rev. 1.5
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SFR Definition 16.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
Name
5
4
3
ET5
ET4
ESMB1
2
1
0
ES1
EVBUS
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE7; SFR Page = All Pages
Bit
Name
7:6
Unused
5
ET5
Function
Read = 00b, Write = Don't Care.
Enable Timer 5 Interrupt.
This bit sets the masking of the Timer 5 interrupt.
0: Disable Timer 5 interrupts.
1: Enable interrupt requests generated by the TF5L or TF5H flags.
4
ET4
Enable Timer 4 Interrupt.
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4interrupts.
1: Enable interrupt requests generated by the TF4L or TF4H flags.
3
2
ESMB1
Reserved Must Write 0b.
1
ES1
0
EVBUS
129
Enable SMBus1 Interrupt.
This bit sets the masking of the SMB1 interrupt.
0: Disable all SMB1 interrupts.
1: Enable interrupt requests generated by SMB1.
Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interrupt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.
Rev. 1.5
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
Name
5
4
3
PT5
PT4
PSMB1
2
1
0
PS1
PVBUS
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF7; SFR Page = All Pages
Bit
Name
Function
:6
Unused
5
PT5
Timer 5 Interrupt Priority Control.
This bit sets the priority of the Timer 5 interrupt.
0: Timer 5 interrupt set to low priority level.
1: Timer 5 interrupt set to high priority level.
4
PT4
Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low priority level.
1: Timer 4 interrupt set to high priority level.
3
PSMB1
2
Read = 00b, Write = Don't Care.
SMBus1 Interrupt Priority Control.
This bit sets the priority of the SMB1 interrupt.
0: SMB1 interrupt set to low priority level.
1: SMB1 interrupt set to high priority level.
Reserved Must Write 0b.
1
PS1
UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
0
PVBUS
VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
Rev. 1.5
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C8051F380/1/2/3/4/5/6/7/C
16.3. INT0 and INT1 External Interrupt Sources
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “26.1. Timer 0 and Timer 1” on page 266) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
1
0
1
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
Active low, edge sensitive
1
0
Active low, edge sensitive
1
Active high, edge sensitive
1
1
Active high, edge sensitive
0
0
Active low, level sensitive
0
0
Active low, level sensitive
0
1
Active high, level sensitive
0
1
Active high, level sensitive
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 16.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register PnSKIP (see Section “20.1. Priority Crossbar
Decoder” on page 154 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external interrupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
131
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SFR Definition 16.7. IT01CF: INT0/INT1 ConfigurationO
Bit
7
6
5
Name
IN1PL
IN1SL[2:0]
IN0PL
IN0SL[2:0]
Type
R/W
R/W
R/W
R/W
Reset
0
0
0
SFR Address = 0xE4; SFR Page = 0
Bit
Name
7
6:4
3
2:0
IN1PL
4
3
0
0
2
0
1
0
0
1
Function
INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
Rev. 1.5
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17. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Program execution begins at location 0x0000.
VDD
Power On
Reset
Supply
Monitor
Px.x
Px.x
+
-
Comparator 0
0
Enable
(wired-OR)
+
C0RSEF
Missing
Clock
Detector
(oneshot)
EN
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
Internal
Oscillator
XTAL1
XTAL2
External
Oscillator
Drive
System
Clock
Clock Select
Errant Flash
Operation
WDT
Enable
MCD
Enable
EN
Low
Frequency
Oscillator
CIP-51
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Figure 17.1. Reset Sources
133
Rev. 1.5
RST
C8051F380/1/2/3/4/5/6/7/C
17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 17.2. plots the
power-on and VDD monitor event timing. The maximum VDD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before VDD reaches the VRST level. For ramp times less than
1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
Supply Voltage
On exit from a power-on or VDD monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor
is enabled following a power-on reset.
VDD
VD
D
VRST
t
Logic HIGH
RST
TPORDelay
Logic LOW
VDD
Monitor
Reset
Power-On
Reset
Figure 17.2. Power-On and VDD Monitor Reset Timing
Rev. 1.5
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17.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the
VDD monitor will still be disabled after the reset.
Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is shown below:
1. Enable the VDD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the VDD monitor to stabilize (see Table 5.4 for the VDD Monitor turn-on time).
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 17.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Table 5.4 for complete electrical characteristics of the VDD monitor.
135
Rev. 1.5
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SFR Definition 17.1. VDM0CN: VDD Monitor Control
Bit
7
6
5
4
3
2
1
0
Name
VDMEN
VDDSTAT
Type
R/W
R
R
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xFF; SFR Page = All Pages
Bit
Name
7
VDMEN
Function
VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 17.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source. See Table 5.4 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6
VDDSTAT
VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
5:0
Unused
Read = 000000b; Write = Don’t care.
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset,
the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads
0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of
the RST pin is unaffected by this reset.
17.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
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17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “27.4. Watchdog Timer Mode” on
page 308; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash program read, write, or erase operation targets an illegal address, a system reset is generated.
This may occur due to any of the following:
Programming hardware attempts to write or erase a Flash location which is above the user code space
address limit.
A Flash read from firmware is attempted above user code space. This occurs when a MOVC operation
is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
A Flash read, write, or erase attempt is restricted due to a Flash security setting.
A Flash write or erase is attempted when the VDD monitor is not enabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
17.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset.
17.9. USB Reset
Writing 1 to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be
enabled for RESET signaling to be detected. See Section “21. Universal Serial Bus Controller (USB0)”
on page 172 for information on the USB Function Controller.
2. A falling or rising voltage on the VBUS pin.
The USBRSF bit will read 1 following a USB reset. The state of the RST pin is unaffected by this reset.
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SFR Definition 17.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
Name
USBRSF
FERROR
C0RSEF
SWRSF
WDTRSF
MCDRSF
PORSF
PINRSF
Type
R/W
R
R/W
R/W
R
R/W
R/W
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xEF; SFR Page = All Pages
Bit
Name
Description
Write
Read
7
USBRSF USB Reset Flag
Writing a 1 enables USB
as a reset source.
Set to 1 if USB caused the
last reset.
6
FERROR Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
5
C0RSEF Comparator0 Reset Enable
and Flag.
Writing a 1 enables Com- Set to 1 if Comparator0
parator0 as a reset source caused the last reset.
(active-low).
4
SWRSF
Writing a 1 forces a system reset.
Software Reset Force and
Flag.
3
WDTRSF Watchdog Timer Reset Flag. N/A
2
MCDRSF Missing Clock Detector
Enable and Flag.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Writing a 1 enables the
Set to 1 if Missing Clock
Missing Clock Detector.
Detector timeout caused
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1
PORSF
Power-On / VDD Monitor
Writing a 1 enables the
Reset Flag, and VDD monitor VDD monitor as a reset
source.
Reset Enable.
Writing 1 to this bit
before the VDD monitor
is enabled and stabilized
may cause a system
reset.
0
PINRSF
HW Pin Reset Flag.
N/A
Set to 1 anytime a poweron or VDD monitor reset
occurs.
When set to 1 all other
RSTSRC flags are indeterminate.
Set to 1 if RST pin caused
the last reset.
Note: Do not use read-modify-write operations on this register
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18. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes would
typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation.
18.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “28. C2 Interface” on
page 316.
To ensure the integrity of Flash contents, it is strongly recommended that the VDD monitor be left enabled
in any system which writes or erases Flash memory from code. It is also crucial to ensure that the FLRT bit
in register FLSCL be set to '1' if a clock speed higher than 25 MHz is being used for the device.
18.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 18.2.
18.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) Writing the Flash key codes in sequence to the Flash Lock
register (FLKEY); and (2) Setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1 (this
directs the MOVX writes to target Flash memory). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed must be erased before a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSEE bit (register PSCTL).
5. Set the PSWE bit (register PSCTL).
6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
7. Clear the PSWE bit (register PSCTL).
8. Clear the PSEE bit (register PSCTI).
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18.1.3. Flash Write Procedure
Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register
PFE0CN (SFR Definition ) controls whether a single byte or a block of two bytes is written to Flash during
a write operation. When FLBWE is cleared to 0, the Flash will be written one byte at a time. When FLBWE
is set to 1, the Flash will be written in two-byte blocks. Block writes are performed in the same amount of
time as single-byte writes, which can save time when storing large amounts of data to Flash memory.During a single-byte write to Flash, bytes are written individually, and a Flash write will be performed
after each MOVX write instruction. The recommended procedure for writing Flash in single bytes is:
1. Disable interrupts.
2. Clear the FLBWE bit (register PFE0CN) to select single-byte write mode.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
8. Clear the PSWE bit.
9. Re-enable interrupts.
Steps 5-7 must be repeated for each byte to be written.
For block Flash writes, the Flash write procedure is only performed after the last byte of each block is written with the MOVX write instruction. A Flash write block is two bytes long, from even addresses to odd
addresses. Writes must be performed sequentially (i.e. addresses ending in 0b and 1b must be written in
order). The Flash write will be performed following the MOVX write that targets the address ending in 1b. If
a byte in the block does not need to be updated in Flash, it should be written to 0xFF. The recommended
procedure for writing Flash in blocks is:
1. Disable interrupts.
2. Set the FLBWE bit (register PFE0CN) to select block write mode.
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write the first data byte to the even block location (ending in 0b).
8. Write the first key code to FLKEY: 0xA5.
9. Write the second key code to FLKEY: 0xF1.
10.Using the MOVX instruction, write the second data byte to the odd block location (ending in 1b).
11. Clear the PSWE bit.
12.Re-enable interrupts.
Steps 5–10 must be repeated for each block to be written.
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18.2. Non-Volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
18.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1s complement number represented by the Security Lock Byte. Note that the page
containing the Flash Security Lock Byte is also locked when any other Flash pages are locked. See example below.
Security Lock Byte:
1s Complement:
Flash pages locked:
Addresses locked:
11111101b
00000010b
3 (2 + Flash Lock Byte Page)
First two pages of Flash: 0x0000 to 0x03FF
Flash Lock Byte Page: (0xFA00 to 0xFBFF for 64k devices; 0x7E00 to
0x7FFF for 32k devices, 0x3E00 to 0x3FFF for 16k devices)
C8051F380/2/4/6
Locked when any
other FLASH pages
are locked
Reserved
0xFC00
Lock Byte
0xFBFF
0xFBFE
0xFA00
FLASH memory
organized in 512-byte
pages
C8051F381/3/5/7
Lock Byte
Unlocked FLASH Pages
0x7FFF
C8051F38C
0x7FFE
0x7E00
Lock Byte
Unlocked FLASH Pages
0x3FFE
0x3E00
Unlocked FLASH Pages
0x0000
0x0000
0x3FFF
0x0000
Access limit set
according to the
FLASH security lock
byte
Figure 18.1. Flash Program Memory Map and Security Byte
The level of FLASH security depends on the FLASH access method. The three FLASH access methods
that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing
on unlocked pages, and user firmware executing on locked pages.
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Accessing FLASH from the C2 debug interface:
1. Any unlocked page may be read, written, or erased.
2. Locked pages cannot be read, written, or erased.
3. The page containing the Lock Byte may be read, written, or erased if it is unlocked.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
6. Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) requires the C2 Device Erase command,
which erases all FLASH pages including the page containing the Lock Byte and the Lock Byte itself.
7. The Reserved Area cannot be read, written, or erased.
Accessing FLASH from user firmware executing on an unlocked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Locked pages cannot be read, written, or erased.
3. The page containing the Lock Byte cannot be erased. It may be read or written only if it is unlocked.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
6. Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any
other locked page, will result in a FLASH Error device reset.
Accessing FLASH from user firmware executing on a locked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Any locked page except the page containing the Lock Byte may be read, written, or erased.
3. The page containing the Lock Byte cannot be erased. It may only be read or written.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing 1s to 0s in the Lock Byte) is not permitted.
6. Unlocking FLASH pages (changing 0s to 1s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any
other locked page, will result in a FLASH Error device reset.
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SFR Definition 18.1. PSCTL: Program Store R/W Control
Bit
7
6
5
4
3
2
Name
1
0
PSEE
PSWE
Type
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address =0x8F; SFR Page = All Pages
Bit
Name
7:2
1
Function
Reserved Must write 000000b.
PSEE
Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0
PSWE
Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
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SFR Definition 18.2. FLKEY: Flash Lock and Key
Bit
7
6
5
4
3
Name
FLKEY[7:0]
Type
R/W
Reset
0
0
0
0
SFR Address = 0xB7; SFR Page = All Pages
Bit
Name
7:0
0
2
1
0
0
0
0
Function
FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is attempted while these operations are disabled, the Flash will be permanently
locked from writes or erasures until the next device reset. If an application never
writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
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SFR Definition 18.3. FLSCL: Flash Scale
Bit
7
6
5
Name
FOSE
Reserved
FLRT
Reserved
Type
R/W
R/W
R/W
R/W
Reset
1
0
0
4
0
SFR Address = 0xB6; SFR Page = All Pages
Bit
Name
7
FOSE
3
0
2
0
1
0
0
0
Function
Flash One-shot Enable.
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads. At system
clock frequencies below 10 MHz, disabling the Flash one-shot will increase system
power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
6:5
Reserved
4
FLRT
Must write 00b.
FLASH Read Time.
This bit should be programmed to the smallest allowed value, according to the system
clock speed.
0: SYSCLK