C8051F410-GDI
Tested Flash MCU Die in Wafer Form
512 byte sectors
- 64 bytes battery-backed RAM (smaRTClock)
Digital Peripherals
- 24 port I/O; push-pull or open-drain, up to 5.25 V
Two 12-Bit Current Mode DACs
Two Comparators
Programmable hysteresis and response time
Configurable as wake-up or reset source
- POR/Brownout Detector
- Voltage Reference—1.5, 2.2 V (programmable)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
-
intrusive in-system debug (No emulator required)
-
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Supply Voltage 2.0 to 5.25 V
- Built-in LDO regulator: 2.1 or 2.5 V
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
UART operation; clock multiplier up to 50 MHz
External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
smaRTClock oscillator: 32 kHz Crystal or
self-resonant oscillator
Can switch between clock sources on-the-fly
-
Temperature Range: –40 to +85 °C
Full Technical Data Sheet
- C8051F410/1/2/3
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instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with
50 MHz system clock
Expanded interrupt handler
Clock Sources
- Internal oscillators: 24.5 MHz 2% accuracy supports
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-
tolerance
Hardware SMBus™ (I2C™ Compatible), SPI™, and
UART serial ports available concurrently
Four general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with six
capture/compare modules, WDT
Hardware smaRTClock operates down to 1 V with
64 bytes battery-backed RAM and backup voltage
regulator
-
D
•
•
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-
±1 LSB INL; no missing codes
Programmable throughput up to 200 ksps
Up to 24 external inputs
Data dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
ANALOG
PERIPHERALS
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A
M
U
X
Rev. 1.2 10/12
12-bit
IDAC
12-bit
200 ksps
ADC
TEMP
SENSOR
VREF
VREG
12-bit
IDAC
+
+
-
-
VOLTAGE
COMPARATORS
24.5 MHz PRECISION
INTERNAL OSCILLATOR
WITH CLOCK MULTIPLIER
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
CROSSBAR
•
•
•
•
•
Memory
- 2304 bytes internal data RAM (256 + 2048)
- 32/16 kB Flash; In-system programmable in
es
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ns
Analog Peripherals
- 12-Bit ADC
Port 0
Port 1
Port 2
LOW FREQUENCY
INTERNAL OSCILLATOR
HARDWARE smaRTClock
HIGH-SPEED CONTROLLER CORE
32/16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
2368 B
SRAM
POR
Copyright © 2012 by Silicon Laboratories
WDT
C8051F410-GDI
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Flash Memory (kB)
RAM (Bytes)
SmaRTClock Real Time Clock
SMBus/I2C
UART
SPI
Timers (16-bit)
Programmable Counter Array
32
2368
1
1
1
4
C8051F410-G1DI 50
32
2368
1
1
2
1
4
Rev. 1.2
12-Bit ADC
24
24
1
Tested
Die in
Wafer
Form
12 mil
10
1
Tested
Die in
Wafer
Form
No
backgrind
Wafer Thickness
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ns
Table 1.1. Product Selection Guide
Package
10
D
Lead-Free (RoHS-Compliant)
Two 12-bit Current Output DACs
Internal Voltage Reference
Digital Port I/Os
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MIPS (Peak)
50
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Ordering Part Number
C8051F410-GDI
Temperature Sensor
Analog Comparators
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C8051F410-GDI
1. Ordering Information
C8051F410-GDI
2. Pin Definitions
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Table 2.1 lists the pin definitions for the C8051F410-GDI. For a full description of each pin, refer to the
C8051F410/1/2/3 data sheet.
Table 2.1. Pin Definitions for C8051F410-GDI
Name
Physical Pad
Number
VDD
10, 11
Core Supply Voltage.
VIO
1, 41
I/O Supply Voltage.
GND
8, 9
Ground.
VRTC-BACKUP
5
VREGIN
12, 13
D
SmaRTClock Backup Supply Voltage.
On-Chip Voltage Regulator Input.
C2CK
D I/O
P2.7/
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Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1 k pullup to VIO is
recommended.
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D I/O
RST/
Description
N
ew
Type
Clock signal for the C2 Debug Interface.
D I/O
Port 2.7.
D I/O
Bi-directional data signal for the C2 Debug Interface.
7
A In
smaRTClock Oscillator Crystal Input.
6
A Out
smaRTClock Oscillator Crystal Input.
39
C2D
XTAL3
XTAL4
P0.0/
om
23
IDAC0
ec
P0.1/
R
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P0.3
A Out
IDAC0 Output.
D I/O or Port 0.1.
A In
24
IDAC1
P0.2
D I/O or Port 0.0.
A In
A Out
IDAC1 Output.
25
D I/O or Port 0.2.
A In
26
D I/O or Port 0.3.
A In
Rev. 1.2
3
C8051F410-GDI
Table 2.1. Pin Definitions for C8051F410-GDI (Continued)
Physical Pad
Number
Type
Description
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ns
Name
D I/O or Port 0.4.
A In
P0.4/
27
TX
D Out
UART TX Pin.
D I/O or Port 0.5.
A In
P0.5/
D In
UART RX Pin.
D I/O or Port 0.6.
A In
P0.6/
29
CNVSTR
D In
30
D I/O or Port 0.7.
A In
14
D I/O or Port 1.0.
A In
External Clock Input. This pin is the external oscillator return
A In
for a crystal or resonator.
P1.1/
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P1.0/
XTAL1
D I/O or
A In
15
XTAL2
A O or
D In
om
P1.2
16
ec
VREF
Port 1.1.
External Clock Output. This pin is the excitation driver for an
external crystal or resonator, or an external clock input for
CMOS, capacitor, or RC oscillator configurations.
D I/O or Port 1.2.
A In
A In
External VREF Input.
17
D I/O or Port 1.3.
A In
P1.4
18
D I/O or Port 1.4.
A In
P1.5
19
D I/O or Port 1.5.
A In
P1.6
20
D I/O or Port 1.6.
A In
P1.7
21
D I/O or Port 1.7.
A In
R
P1.3
N
ot
4
External Convert Start Input for ADC0, IDA0, and IDA1.
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P0.7
N
ew
RX
D
28
Rev. 1.2
C8051F410-GDI
Table 2.1. Pin Definitions for C8051F410-GDI (Continued)
Name
Physical Pad
Number
P2.0
31
D I/O or Port 2.0.
A In
P2.1
32
D I/O or Port 2.1.
A In
P2.2
33
D I/O or Port 2.2.
A In
P2.3
34
D I/O or Port 2.3.
A In
P2.4
36
D I/O or Port 2.4.
A In
P2.5
37
D I/O or Port 2.5.
A In
P2.6
38
D I/O or Port 2.6.
A In
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Description
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Type
Rev. 1.2
5
C8051F410-GDI
3. Bonding Instructions
Physical Pad
Number
Example Package
Pin Number
(LQFP32)
Package Pin Name
Physical Pad X
(um)
Physical Pad Y
(um)
1
1
VIO
-1099.49
1063.135
2
2
\RST/C2CK
-1099.49
3
NA
Reserved*
-1099.49
794.055
4
NA
Reserved*
-1099.49
719.055
5
3
VRTC-BACKUP
-1099.49
232.125
6
4
XTAL4
-1099.49
42.685
7
5
XTAL3
-1099.49
-97.695
8
6
GND
-1099.49
-230.665
9
6
GND
-1099.49
-344.135
10
7
VDD
-1099.49
-445.735
11
7
VDD
-1099.49
-519.735
12
8
VREGIN
-1099.49
-957.615
8
VREGIN
-1099.49
-1031.615
9
P1.0/XTAL1
-863.93
-1211.435
10
P1.1/XTAL2
-430.55
-1211.435
11
P1.2/VREF
-244.03
-1211.435
12
P1.3
-76.39
-1211.435
13
P1.4
290.13
-1211.435
14
P1.5
457.77
-1211.435
20
om
15
P1.6
644.29
-1211.435
21
16
P1.7
811.93
-1211.435
22
ec
NA
Reserved*
951.19
-1211.435
23
17
P0.0/IDAC0
1099.49
-1001.495
24
18
P0.1/IDAC1
1099.49
-833.855
25
19
P0.2
1099.49
-618.575
26
20
P0.3
1099.49
-450.935
27
21
P0.4/TX
1099.49
450.935
28
22
P0.5/RX
1099.49
618.575
29
23
P0.6/CNVSTR
1099.49
833.855
14
15
16
17
18
N
ot
R
19
*Note: Pins marked “Reserved” should not be connected.
Rev. 1.2
923.875
D
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ew
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13
6
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ns
Table 3.1. Bond Pad Coordinates (Relative to Center of Die)
C8051F410-GDI
Table 3.1. Bond Pad Coordinates (Relative to Center of Die) (Continued)
24
P0.7
1099.49
1001.495
31
25
P2.0
903.93
1211.435
32
26
P2.1
736.29
33
27
P2.2
535.39
34
28
P2.3
367.75
35
NA
Reserved*
-29.77
36
29
P2.4
-198.13
37
30
P2.5
-365.77
1211.435
38
31
P2.6
-552.29
1211.435
39
32
P2.7/C2D
40
NA
Reserved*
41
1
VIO
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ig
ns
30
1211.435
1211.435
1211.435
1211.435
N
ew
D
1211.435
-719.93
1211.435
-859.19
1211.435
-951.19
1211.435
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*Note: Pins marked “Reserved” should not be connected.
Rev. 1.2
7
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D
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C8051F410-GDI
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Figure 3.1. Die Bonding (LQFP-32)
8
Rev. 1.2
C8051F410-GDI
Table 3.2. Wafer and Die Information
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8 in
Wafer Dimensions
2.4 mm x 2.63 mm
Wafer Thickness
12 mil ±1 mil (C8051F410-GDI)
No backgrind (C8051F410-G1DI)
Wafer Identification
Notch
Scribe Line Width
80 µm
Contact Sales for info
Die Per Wafer*
Wafer Jar
Wafer Packaging Detail
60 µm x 60 µm
Bond Pad Dimensions
250 °C
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Maximum Processing Temperature
Bond Pad Pitch Minimum
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ew
Standard
Passivation
Electronic Die Map Format
D
Die Dimensions
.txt
75 µm
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*Note: This is the Expected Known Good Die yielded per wafer and represents the
batch order quantity (one wafer).
Rev. 1.2
9
C8051F410-GDI
4. Wafer Storage Guidelines
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ns
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.
Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
Wafers must be stored at a temperature of 18–24 °C.
Wafers must be stored in a humidity-controlled environment with a relative humidity of
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