C8051F975-A-GM

C8051F97x Low Power Capacitive Sensing MCU with up to 32 kB of Flash High-Speed CIP-51 µC Core - Efficient, pipelined instruction architecture - Up to 25 MIPS throughput with 25 MHz clock - Uses standard 8051 instruction set - Expanded interrupt handler - 1-cycle 16 x 16 MAC Engine - 7-channel Direct Memory Access (DMA) module es ig ns Low Power Consumption - 200 µA/MHz in active mode (24.5 MHz clock) - 2 µs wakeup time - 55 nA sleep mode with brownout detector - 280 nA sleep mode with LFO - 600 nA sleep mode with external crystal Capacitance Sense Interface - Supports buttons, sliders, wheels, and proximity sensing - Fast 40 µs per channel conversion time - 16-bit resolution, up to 43 input channels - Auto scan and wake-on-touch - Auto-accumulate up to 64x samples D Memory - Up to 32 kB flash - Flash is in-system programmable in 512-Byte sectors - Up to 8 kB RAM General-Purpose I/O - Up to 43 pins with high sink current and programmable drive - Crossbar-enabled N ew 10-Bit Analog-to-Digital Converter - Up to 43 external pin input channels, up to 300 ksps - Internal VREF or external VREF supported Timer/Counters and PWM - 4 general purpose 16-bit timer/counters - 16-bit Programmable Counter Array (PCA) with three channels Clock Sources - Internal oscillators: 24.5 MHz, ±2% accuracy supports UART - SmaRTClock oscillator: 32 kHz Crystal or internal LFO - Can switch between clock sources on-the-fly; useful in implementing various power-saving modes of PWM, capture/compare, or frequency output capability, and watchdog timer fo r operation; 20 MHz low power oscillator requires very little bias current. External oscillator: Crystal, RC, C, or CMOS Clock low digital core voltage m en de d - 2 supply monitors (brownout detector) for sleep and active On-Chip Debug - On-chip debug circuitry facilitates full speed, non-intrusive in- system debug (no emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Unique Identifier - 128-bit unique key for each device 16-bit CRC CIP-51 (25 MHz) 7 ch. DMA Core LDO Digital Peripherals UART I2C / SMBus HS I2C Slave Supply Monitor SPI 16 x 16 MAC 4 x 16-bit Timers 3-Channel PCA / Watchdog 24.5 MHz Precision Oscillator 20 MHz Low Power Oscillator smaRTClock with 16.4 kHz LFO External Oscillator Rev 1.1 12/16 Analog Peripherals SAR ADC (10-bit 300 ksps) Capacitive Sensing Voltage Reference Temperature Sensor Copyright © 2016 by Silicon Laboratories Flexible Pin Muxing Clocking / Oscillators Clock Selection N ot R C2 Serial Debug / Programming 43 Multi-Function I/O Pins om ec 4-8 kB RAM Package Options - 24-pin QFN (4x4 mm) - 32-pin QFN (5x5 mm) - 48-pin QFN (6x6 mm) Temperature Ranges: –40 to +85 °C Core / Memory / Support 16-32 kB Flash modes Priority Crossbar Encoder - Supply Voltage: 1.8 to 3.6 V - Built-in LDO regulator allows a high analog supply voltage and C8051F97x N ot R ec om m en de d fo r N ew D es ig ns 1. Electrical Characteristics .................................................................................................. 10 1.1. Electrical Characteristics .............................................................................................. 10 1.2. Thermal Conditions ...................................................................................................... 21 1.3. Absolute Maximum Ratings..........................................................................................21 2. System Overview ...............................................................................................................22 2.1. Power ........................................................................................................................... 24 2.1.1. Voltage Supply Monitor (VMON0) ....................................................................... 24 2.1.2. Device Power Modes........................................................................................... 24 2.1.3. Suspend Mode..................................................................................................... 25 2.1.4. Sleep Mode.......................................................................................................... 25 2.1.5. Low Power Active Mode ...................................................................................... 26 2.1.6. Low Power Idle Mode ..........................................................................................26 2.2. I/O................................................................................................................................. 26 2.2.1. General Features.................................................................................................26 2.2.2. Crossbar .............................................................................................................. 26 2.3. Clocking........................................................................................................................ 27 2.4. Counters/Timers and PWM ..........................................................................................27 2.4.1. Programmable Counter Array (PCA0) ................................................................. 27 2.4.2. Timers (Timer 0, Timer 1, Timer 2, and Timer 3)................................................. 27 2.5. Communications and other Digital Peripherals ............................................................ 28 2.5.1. Universal Asynchronous Receiver/Transmitter (UART0) .................................... 28 2.5.2. Serial Peripheral Interface (SPI0) ........................................................................ 28 2.5.3. System Management Bus / I2C (SMBus0) .......................................................... 28 2.5.4. High-Speed I2C Slave (I2CSLAVE0)................................................................... 29 2.5.5. 16/32-bit CRC (CRC0)......................................................................................... 29 2.6. Analog Peripherals ....................................................................................................... 29 2.6.1. 10-Bit Analog-to-Digital Converter (ADC0) .......................................................... 29 2.7. Digital Peripherals ........................................................................................................30 2.7.1. Direct Memory Access (DMA0) ........................................................................... 30 2.7.2. Multiply and Accumulate (MAC0) ........................................................................ 30 2.8. Reset Sources..............................................................................................................30 2.9. Unique Identifier ........................................................................................................... 30 2.10.On-Chip Debugging ..................................................................................................... 30 3. Pin Definitions.................................................................................................................... 31 3.1. C8051F970/3 QFN-48 Pin Definitions.......................................................................... 31 3.2. C8051F971/4 QFN-32 Pin Definitions.......................................................................... 35 3.3. C8051F972/5 QFN-24 Pin Definitions.......................................................................... 38 4. Ordering Information .........................................................................................................41 5. QFN-48 Package Specifications ...................................................................................... 43 5.1. QFN-48 Package Marking............................................................................................ 45 6. QFN-32 Package Specifications ....................................................................................... 46 6.1. QFN-32 Package Marking............................................................................................ 49 7. QFN-24 Package Specifications ....................................................................................... 50 7.1. QFN-24 Package Marking............................................................................................ 53 8. Memory Organization ........................................................................................................54 8.1. Program Memory.......................................................................................................... 55 Rev 1.1 2 N ot R ec om m en de d fo r N ew D es ig ns 8.1.1. MOVX Instruction and Program Memory............................................................. 55 8.2. Data Memory................................................................................................................ 55 8.2.1. Internal RAM........................................................................................................55 8.2.2. External RAM....................................................................................................... 56 8.2.3. Special Function Registers .................................................................................. 56 9. Special Function Register Memory Map.......................................................................... 57 10. Flash Memory..................................................................................................................... 65 10.1.Security Options........................................................................................................... 65 10.2.Programming the Flash Memory.................................................................................. 67 10.2.1.Flash Lock and Key Functions ............................................................................67 10.2.2.Flash Erase Procedure........................................................................................ 67 10.2.3.Flash Write Procedure......................................................................................... 67 10.3.Non-volatile Data Storage............................................................................................ 68 10.4.Flash Write and Erase Guidelines ............................................................................... 68 10.4.1.Voltage Supply Maintenance and the Supply Monitor.........................................68 10.4.2.PSWE Maintenance ............................................................................................ 68 10.4.3.System Clock....................................................................................................... 69 10.5.Flash Control Registers ............................................................................................... 70 11. On-Chip XRAM ................................................................................................................... 74 11.1.Accessing XRAM ......................................................................................................... 74 11.1.1.16-Bit MOVX Example......................................................................................... 74 11.1.2.8-Bit MOVX Example........................................................................................... 74 11.2.External Memory Interface Registers........................................................................... 75 12. Device Identification and Unique Identifier .....................................................................76 12.1.Device Identification Registers..................................................................................... 77 13. Interrupts ............................................................................................................................ 79 13.1.MCU Interrupt Sources and Vectors ............................................................................79 13.1.1.Interrupt Priorities ................................................................................................ 79 13.1.2.Interrupt Latency.................................................................................................. 79 13.2.Interrupt Control Registers........................................................................................... 82 14. External Interrupts (INT0 and INT1).................................................................................. 91 14.1.External Interrupt Control Registers............................................................................. 92 15. Voltage Regulator (VREG0)............................................................................................... 93 15.1.Voltage Regulator Control Registers ........................................................................... 93 16. Power Management ........................................................................................................... 94 16.1.Normal Active Mode..................................................................................................... 95 16.2.Idle Mode ..................................................................................................................... 96 16.3.Stop Mode.................................................................................................................... 97 16.4.Suspend Mode............................................................................................................. 97 16.5.Sleep Mode.................................................................................................................. 97 16.6.Low Power Active Mode .............................................................................................. 98 16.7.Low Power Idle Mode .................................................................................................. 98 16.8.Configuring Wakeup Sources ...................................................................................... 99 16.9.Determining the Event that Caused the Last Wakeup ................................................. 99 16.10.Power Control Registers .......................................................................................... 100 17. Analog-to-Digital Converter (ADC0)............................................................................... 104 3 Rev 1.1 N ot R ec om m en de d fo r N ew D es ig ns 17.1.ADC0 Analog Multiplexer........................................................................................... 105 17.2.Output Code Formatting ............................................................................................ 106 17.3.Modes of Operation ................................................................................................... 107 17.3.1.Starting a Conversion ........................................................................................107 17.3.2.Tracking Modes ................................................................................................. 108 17.3.3.Burst Mode ........................................................................................................ 109 17.3.4.Settling Time Requirements .............................................................................. 110 17.3.5.Gain Setting....................................................................................................... 110 17.4.8-Bit Mode.................................................................................................................. 110 17.5.Low Power Mode ....................................................................................................... 111 17.6.Window Detector In Single-Ended Mode ...................................................................111 17.7.Voltage Reference ..................................................................................................... 112 17.7.1.External Voltage Reference............................................................................... 112 17.7.2.Internal Voltage Reference................................................................................ 113 17.8.Temperature Sensor .................................................................................................. 113 17.8.1.Calibration ......................................................................................................... 113 17.9.ADC Control Registers...............................................................................................114 17.10.Voltage Reference Registers ................................................................................... 127 17.11.Temperature Sensor Registers................................................................................ 128 18. Capacitive Sense (CS0) ................................................................................................... 130 18.1.Configuring Port Pins as Capacitive Sense Inputs .................................................... 131 18.2.Initializing the Capacitive Sensing Peripheral ............................................................131 18.3.Capacitive Sense Start-Of-Conversion Sources........................................................ 131 18.4.CS0 Multiple Channel Enable .................................................................................... 132 18.5.CS0 Gain Adjustment ................................................................................................ 132 18.6.Wake from Suspend .................................................................................................. 132 18.7.Using CS0 in Applications that Utilize Sleep Mode.................................................... 132 18.8.Automatic Scanning (Method 1—CS0SMEN = 0) .....................................................132 18.9.Automatic Scanning (Method 2—CS0SMEN = 1) .....................................................134 18.10.CS0 Comparator ......................................................................................................134 18.11.CS0 Conversion Accumulator.................................................................................. 135 18.12.CS0 Pin Monitor....................................................................................................... 136 18.13.Adjusting CS0 For Special Situations ...................................................................... 137 18.13.1.Adjusting the CS0 Reset Timing...................................................................... 137 18.13.2.Adjusting Primary Reset Timing: CS0DT ........................................................ 137 18.13.3.Adjusting Secondary Reset Timing: CS0DR ................................................... 138 18.13.4.Adjusting CS0 Ramp Timing: CS0IA ............................................................... 138 18.13.5.Low-Pass Filter Adjustments ........................................................................... 139 18.13.6.Adjusting CS0 Ramp Timing: CS0RP ............................................................. 139 18.13.7.Adjusting CS0LP for Non-Default CS0RP Settings ......................................... 139 18.13.8.Other Options for Adjusting CS0LP................................................................. 139 18.14.CS0 Analog Multiplexer ........................................................................................... 140 18.14.1.Pin Configuration for CS0 Measurements Method .......................................... 142 18.15.Capacitive Sense Register....................................................................................... 143 19. Analog Multiplexer (AMUX0)........................................................................................... 157 19.1.AMUX Control Registers............................................................................................ 158 Rev 1.1 4 N ot R ec om m en de d fo r N ew D es ig ns 20. CIP-51 Microcontroller Core ........................................................................................... 164 20.1.Performance .............................................................................................................. 164 20.2.Programming and Debugging Support ...................................................................... 165 20.3.Instruction Set ............................................................................................................ 165 20.3.1.Instruction and CPU Timing............................................................................... 165 20.4.SFR Paging................................................................................................................170 20.5.CPU Core Registers .................................................................................................. 177 21. Direct Memory Access (DMA0)....................................................................................... 187 21.1.DMA0 Architecture..................................................................................................... 188 21.2.DMA0 Arbitration........................................................................................................ 188 21.2.1.DMA0 Memory Access Arbitration..................................................................... 188 21.2.2.DMA0 channel arbitration .................................................................................. 189 21.3.DMA0 Operation in Low Power Modes...................................................................... 189 21.4.Transfer Configuration ...............................................................................................189 21.5.DMA0 Registers......................................................................................................... 190 22. Multiply and Accumulate (MAC0) ................................................................................... 202 22.1.Special Function Registers ........................................................................................203 22.2.Integer and Fractional Math ....................................................................................... 203 22.3.Operating in Multiply and Accumulate Mode ............................................................. 204 22.4.Operating in Multiply Only Mode................................................................................ 204 22.5.MCU Mode Operation ................................................................................................ 205 22.6.DMA Mode Operation ................................................................................................ 205 22.7. Accumulator 1-Bit Shift Operations........................................................................... 207 22.8.Multi-Bit Shift Accumulator Operation ........................................................................ 208 22.9.Accumulator Alignment (Right Byte Shift).................................................................. 209 22.10.Rounding and Saturation ......................................................................................... 209 22.11.Usage Examples......................................................................................................211 22.11.1.Multiply and Accumulate in Fractional Mode ................................................... 211 22.11.2.Multiply Only in Integer Mode ..........................................................................211 22.11.3.Initializing Memory Block Using DMA0 and MAC0.......................................... 212 22.12.MAC0 Registers....................................................................................................... 213 23. Cyclic Redundancy Check Unit (CRC0)......................................................................... 232 23.1.CRC Algorithm ........................................................................................................... 232 23.2.Preparing for a CRC Calculation................................................................................ 234 23.3.Performing a CRC Calculation................................................................................... 234 23.4.Accessing the CRC0 Result....................................................................................... 234 23.5.CRC0 Bit Reverse Feature ........................................................................................234 23.6.CRC Control Registers .............................................................................................. 235 24. Clocking Sources.............................................................................................................241 24.1.Programmable Precision Internal Oscillator............................................................... 242 24.2.Low Power Internal Oscillator .................................................................................... 242 24.3.External Oscillator Drive Circuit .................................................................................242 24.3.1.External Crystal Mode ....................................................................................... 242 24.3.2.External RC Mode ............................................................................................. 243 24.3.3.External Capacitor Mode ................................................................................... 245 24.3.4.External CMOS Clock Mode.............................................................................. 245 5 Rev 1.1 N ot R ec om m en de d fo r N ew D es ig ns 24.4.Special Function Registers for Selecting and Configuring the System Clock............ 246 24.5.Clock Selection Control Registers ............................................................................. 247 24.6.High Frequency Oscillator Registers ......................................................................... 250 24.7.External Oscillator Registers...................................................................................... 252 25. SmaRTClock (Real Time Clock, RTC0) ..........................................................................253 25.1.SmaRTClock Interface...............................................................................................254 25.1.1.Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers... 254 25.1.2.RTC0ADR Short Strobe Feature ....................................................................... 254 25.1.3.SmaRTClock Interface Autoread Feature ......................................................... 255 25.1.4.RTC0ADR Autoincrement Feature .................................................................... 255 25.2.SmaRTClock Clocking Sources.................................................................................256 25.2.1.Using the SmaRTClock Oscillator with a Crystal............................................... 256 25.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode ................................. 257 25.2.3.Using the Low Frequency Oscillator (LFO) ....................................................... 257 25.2.4.Programmable Load Capacitance ..................................................................... 258 25.2.5.Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling 259 25.2.6.Missing SmaRTClock Detector..........................................................................261 25.2.7.SmaRTClock Oscillator Crystal Valid Detector.................................................. 261 25.3.SmaRTClock Timer and Alarm Function ...................................................................261 25.3.1.Setting and Reading the SmaRTClock Timer Value ......................................... 261 25.3.2.Setting a SmaRTClock Alarm............................................................................ 262 25.3.3.Software Considerations for Using the SmaRTClock Timer and Alarm ............ 263 25.4.RTC0 Control Registers............................................................................................. 264 26. Port I/O (Port 0, Port 1, Port 2, Port 3, Port 4, Port 5, Port 6, Crossbar, and Port Match) 277 26.1.General Port I/O Initialization ..................................................................................... 278 26.2.Assigning Port I/O Pins to Analog and Digital Functions ........................................... 279 26.2.1.Assigning Port I/O Pins to Analog Functions.....................................................279 26.2.2.Assigning Port I/O Pins to Digital Functions ...................................................... 280 26.2.3.Assigning Port I/O Pins to Fixed Digital Functions ............................................ 280 26.3.Priority Crossbar Decoder.......................................................................................... 281 26.4.Port I/O Modes of Operation ...................................................................................... 283 26.4.1.Configuring Port Pins For Analog Modes .......................................................... 283 26.4.2.Configuring Port Pins For Digital Modes ........................................................... 283 26.4.3.Port Drive Strength ............................................................................................ 283 26.5.Port Match.................................................................................................................. 284 26.6.Direct Read/Write Access to Port I/O Pins................................................................. 284 26.7.Port Configuration Registers...................................................................................... 285 26.8.Port I/O Control Registers.......................................................................................... 287 27. Reset Sources and Supply Monitor ............................................................................... 322 27.1.Power-On Reset ........................................................................................................ 323 27.2.Power-Fail Reset / Supply Monitor ............................................................................ 324 27.3.Enabling the VDD Monitor ......................................................................................... 325 27.4.External Reset ........................................................................................................... 325 27.5.Missing Clock Detector Reset.................................................................................... 325 27.6.PCA Watchdog Timer Reset...................................................................................... 325 Rev 1.1 6 N ot R ec om m en de d fo r N ew D es ig ns 27.7.Flash Error Reset....................................................................................................... 325 27.8.Software Reset .......................................................................................................... 325 27.9.Reset Sources Control Registers............................................................................... 326 27.10.Supply Monitor Control Registers ............................................................................ 327 28. Serial Peripheral Interface (SPI0) ................................................................................... 328 28.1.Signal Descriptions .................................................................................................... 329 28.1.1.Master Out, Slave In (MOSI) ............................................................................. 329 28.1.2.Master In, Slave Out (MISO) ............................................................................. 329 28.1.3.Serial Clock (SCK)............................................................................................. 329 28.1.4.Slave Select (NSS)............................................................................................ 329 28.2.SPI0 Master Mode Operation .................................................................................... 330 28.3.SPI0 Slave Mode Operation ...................................................................................... 332 28.4.SPI0 Interrupt Sources...............................................................................................332 28.5.Serial Clock Phase and Polarity.................................................................................332 28.6.SPI Special Function Registers .................................................................................334 28.7.SPI Control Registers ................................................................................................ 338 29. System Management Bus / I2C (SMBus0) ..................................................................... 342 29.1.Supporting Documents .............................................................................................. 343 29.2.SMBus Configuration ................................................................................................. 343 29.3.SMBus Operation....................................................................................................... 343 29.3.1.Transmitter vs. Receiver.................................................................................... 344 29.3.2.Arbitration .......................................................................................................... 344 29.3.3.Clock Low Extension ......................................................................................... 344 29.3.4.SCL Low Timeout .............................................................................................. 344 29.3.5.SCL High (SMBus Free) Timeout...................................................................... 345 29.4.Using the SMBus ....................................................................................................... 345 29.4.1.SMBus Configuration Register ..........................................................................345 29.4.2.SMBus Pin Swap...............................................................................................347 29.4.3.SMBus Timing Control....................................................................................... 347 29.4.4.SMB0CN Control Register.................................................................................347 29.4.5.Hardware Slave Address Recognition............................................................... 349 29.4.6.Data Register..................................................................................................... 349 29.5.SMBus Transfer Modes ............................................................................................. 350 29.5.1.Write Sequence (Master)................................................................................... 350 29.5.2.Read Sequence (Master) .................................................................................. 351 29.5.3.Write Sequence (Slave)..................................................................................... 352 29.5.4.Read Sequence (Slave) .................................................................................... 353 29.6.SMBus Status Decoding ............................................................................................ 353 29.7.I2C / SMBus Control Registers .................................................................................. 358 30. I2C Slave ...........................................................................................................................364 30.1.Supporting Documents .............................................................................................. 365 30.2.The I2C Configuration................................................................................................ 365 30.3.I2CSLAVE0 Operation ...............................................................................................365 30.3.1.Transmitter vs. Receiver.................................................................................... 366 30.3.2.Clock Stretching ................................................................................................ 366 30.3.3.SCL Low Timeout .............................................................................................. 367 7 Rev 1.1 N ot R ec om m en de d fo r N ew D es ig ns 30.3.4.HS-mode ........................................................................................................... 367 30.3.5.DMA and CPU Mode Operations ...................................................................... 368 30.4.Using the I2CSLAVE0 Module................................................................................... 368 30.4.1.I2C0CNTL Control Register............................................................................... 368 30.4.2.I2C0STAT Status Register ................................................................................ 368 30.4.3.I2C0SLAD Slave Address Register ...................................................................369 30.4.4.I2C0DIN Received Data Register...................................................................... 369 30.4.5.I2C0DOUT Transmit Data Register...................................................................369 30.5.I2C Transfer Modes ................................................................................................... 370 30.5.1.I2C Write Sequence (CPU mode) ..................................................................... 370 30.5.2.I2C Read Sequence (CPU mode) ..................................................................... 371 30.5.3.I2C Write Sequence (DMA mode) ..................................................................... 371 30.5.4.I2C Read Sequence (DMA Mode)..................................................................... 373 30.6.I2CSLAVE0 Slave Registers...................................................................................... 374 31. Universal Asynchronous Receiver/Transmitter (UART0) ............................................ 380 31.1.Enhanced Baud Rate Generation .............................................................................. 380 31.2.Operational Modes..................................................................................................... 382 31.2.1.8-Bit UART ........................................................................................................ 382 31.2.2.9-Bit UART ........................................................................................................ 383 31.3.Multiprocessor Communications................................................................................ 384 31.4.UART Control Registers ............................................................................................ 386 32. Timers (Timer0, Timer1, Timer2, and Timer3) ............................................................... 389 32.1.Timer 0 and Timer 1................................................................................................... 390 32.1.1.Mode 0: 13-bit Counter/Timer............................................................................ 391 32.1.2.Mode 1: 16-bit Counter/Timer............................................................................ 391 32.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload ................................................. 392 32.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ............................................ 393 32.2.Timer 2....................................................................................................................... 394 32.3.Timer 3....................................................................................................................... 397 32.4.Timer Control Registers ............................................................................................. 400 32.5.Timer 0/1 Registers.................................................................................................... 404 32.6.Timer 2 Registers....................................................................................................... 408 32.7.Timer 3 Registers....................................................................................................... 414 33. Programmable Counter Array (PCA0)............................................................................ 420 33.1.PCA Counter/Timer.................................................................................................... 421 33.2.PCA0 Interrupt Sources ............................................................................................. 422 33.3.Capture/Compare Modules........................................................................................423 33.3.1.Edge-triggered Capture Mode ........................................................................... 424 33.3.2.Software Timer (Compare) Mode ...................................................................... 425 33.3.3.High-Speed Output Mode.................................................................................. 426 33.3.4.Frequency Output Mode.................................................................................... 427 33.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes............................. 427 33.3.6. 8-Bit Pulse Width Modulator Mode ...................................................................428 33.3.7. 9/10/11-bit Pulse Width Modulator Mode ......................................................... 429 33.3.8. 16-Bit Pulse Width Modulator Mode ................................................................. 430 33.4.Watchdog Timer Mode...............................................................................................431 Rev 1.1 8 N ot R ec om m en de d fo r N ew D es ig ns 33.4.1.Watchdog Timer Operation ............................................................................... 431 33.4.2.Watchdog Timer Usage..................................................................................... 432 33.5.PCA0 Control Registers............................................................................................. 433 34. C2 Interface ...................................................................................................................... 447 34.1.C2 Pin Sharing........................................................................................................... 447 34.2.C2 Interface Registers ...............................................................................................448 Document Change List ......................................................................................................... 453 Revision 1.0 to Revision 1.1 ................................................................................................. 453 Revision 0.1 to Revision 1.0 ................................................................................................. 453 Contact Information .............................................................................................................. 454 9 Rev 1.1 1. Electrical Characteristics Throughout the Electrical Characteristics chapter, “VDD” refers to the Supply Voltage. 1.1. Electrical Characteristics Table 1.1. Recommended Operating Conditions Parameter Symbol Temperature Range Supply Voltage Conditions es ig ns All electrical parameters in all tables are specified under the conditions listed in Table 1.1, unless stated otherwise. Min Typ Max Units TA –40 25 85 °C VDD 1.8 3 3.6 V D *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. N ew Table 1.2. Global Electrical Characteristics Min Typ Max units 1.8 3.0 3.6 V — 1.4 — V 0 — 25 MHz 18 — — ns TSYSL (SYSCLK Low Time) 18 — — ns Specified Operating Temperature Range –40 — +85 °C –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions RAM Data Retention Voltage1 SYSCLK (System Clock)2 m en de d TSYSH (SYSCLK High Time) fo r Supply Voltage (VDD) N ot R ec om Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. See the power measurement code examples for more information. 4. Includes oscillator and regulator supply current. Rev 1.1 10 Table 1.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max units — 5 VDD = 1.8–3.6 V, Freq = 20 MHz (includes low power oscillator current) — 4 VDD = 1.8 V, Freq = 1 MHz (includes external CMOS oscillator / GPIO current) — 420 mA — mA — µA — 440 — µA VDD = 1.8–3.6 V, Freq = 32.768 kHz (includes RTC current) — 95 — µA VDD = 1.8-3.6 V, T = 25 °C, Freq < 14 MHz (Flash oneshot active) — 230 — µA/MHz VDD = 1.8-3.6 V, T = 25 °C, Freq > 14 MHz (Flash oneshot bypassed) — 130 — µA/MHz fo r VDD = 3.6 V, Freq = 1 MHz (includes external CMOS oscillator / GPIO current) m en de d IDD Frequency Sensitivity1, 3, 6 D VDD = 1.8–3.6 V, Freq = 24.5 MHz (includes precision oscillator current) N ew IDD3, 4 es ig ns Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) N ot R ec om Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. See the power measurement code examples for more information. 4. Includes oscillator and regulator supply current. 11 Rev 1.1 Table 1.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max units IDD Frequency Sensitivity1 — 3.3 4.5 mA VDD = 1.8–3.6 V, Freq = 20 MHz (includes low power oscillator current) — 2.5 — mA VDD = 1.8–3.6 V, Freq = 32.768 kHz (includes RTC current) — 90 — µA — µA/MHz D VDD = 1.8–3.6 V, Freq = 24.5 MHz (includes precision oscillator current) N ew IDD4 es ig ns Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) VDD = 1.8-3.6 V, T = 25 °C — 110 N ot R ec om m en de d fo r Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. See the power measurement code examples for more information. 4. Includes oscillator and regulator supply current. Rev 1.1 12 Table 1.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Min Typ VDD = 1.8–3.6 V — 80 — µA VDD = 1.8 V, T = 25 °C — 0.6 — µA VDD = 3.3 V, T = 25 °C — 0.7 — µA VDD = 3.6 V, T = 25 °C — 0.8 — µA VDD = 1.8 V, T = 85 °C — VDD = 3.3 V, T = 85 °C — D Digital Supply Current  (Sleep Mode, RTC 32 kHz Crystal Running, includes RTC and  VDDMON) 1 — µA 1.3 — µA N ew Digital Supply Current  (Suspend Mode) units es ig ns Digital Supply Current—Suspend and Sleep Mode Max — 1.5 — µA Digital Supply Current (Sleep Mode, RTC Int LFO running, includes RTC and VDDMON) VDD = 1.8 V, T = 25 °C — 0.28 — µA Digital Supply Current  (Sleep Mode, includes VDDMON) VDD = 1.8 V, T = 25 °C — 0.05 — µA VDD = 3.3 V, T = 25 °C — 0.06 — µA VDD = 3.6 V, T = 25 °C — 0.11 — µA VDD = 1.8 V, T = 85 °C — 0.8 — µA VDD = 3.3 V, T = 85 °C — 0.9 — µA VDD = 3.6 V, T = 85 °C — 1.0 — µA m en de d fo r VDD = 3.6 V, T = 85 °C N ot R ec om Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. See the power measurement code examples for more information. 4. Includes oscillator and regulator supply current. 13 Rev 1.1 Table 1.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Min Typ IOH = –3 mA, Port I/O push-pull VDD – 0.7 — IOH = –10 µA VDD – 0.1 — IOH = –10 mA — see chart — IOH = –1 mA VDD – 0.7 — — V IOH = –10 µA VDD – 0.1 — — V IOH = –3 mA — see chart — V Output Low Voltage  (High Drive Strength,  PnDRV.n = 1) IOL = 8.5 mA — — 0.7 V Output Low Voltage  (Low Drive Strength,  PnDRV.n = 0) IOL = 1.4 mA Output High Voltage  (Low Drive Strength,  PnDRV.n = 0) IOL = 25 mA Units — V — V — see chart — V — — 0.7 V — see chart — V VDD = 2.0 to 3.6 V VDD – 0.6 — — V Input Low Voltage VDD = 2.0 to 3.6 V — — 0.6 V Input Leakage Current Weak Pull–up Off — — 0.5 µA Weak Pull-up On, VIN=0 V, VDD = 1.8 V — 4 — µA Weak Pull-up On, VIN = 0 V, VDD = 3.6 V — 23 — µA m en de d Input High Voltage fo r IOL = 4 mA D Output High Voltage  (High Drive Strength,  PnDRV.n = 1) Max es ig ns Conditions N ew Parameter Table 1.4. I2C Slave Electrical Characteristics VDD Range om Parameter Internal I2C pull-ups Condition Min Typ Max units Required to meet I2C spec 1.8 — 3.6 V Required to meet I2C spec — 6 — k N ot R ec Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev 1.1 14 es ig ns D N ew fo r m en de d om ec R N ot Figure 1.1. Typical VOH Curves, 1.8–3.6 V 15 Rev 1.1 es ig ns D N ew fo r m en de d om ec R N ot Figure 1.2. Typical VOL Curves, 1.8–3.6 V Rev 1.1 16 Table 1.5. Reset Electrical Characteristics Min Typ IOL = 1.4 mA — 0.1 — V RST input High Voltage VDD = 2.0 to 3.6 V VDD – 0.6 — — V RST input Low Voltage VDD = 2.0 to 3.6 V — — 0.6 V RST = 0 V, VDD = 3.6 V — 22 — µA VDD Monitor Threshold (VRST) Early Warning — 1.85 — V VDD Monitor Threshold (VRST) Reset Trigger (all modes ex. Sleep) — — V POR Monitor Threshold (VPOR) Initial Power-On POR Monitor Threshold (VPOR) Brownout Condition POR Monitor Threshold (VPOR) Recovery from Brownout RST Output Low Voltage RST Input Pull-up Current Max D Parameter Unit es ig ns Conditions N ew VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. 1.75 1.6 — V — 1.6 — V — 1.0 — V Time from last system clock rising edge to reset initiation 100 650 1000 µs System clock frequency which triggers a missing clock detector timeout — 7 — kHz — — 30 µs Minimum RST Low Time to Generate System Reset — 15 — µs VDD Monitor Turn-on Time — 300 — ns VDD Monitor Supply Current — 20 — µA Missing Clock Detector  Timeout Delay between release of any reset source and code execution at location 0x0000 N ot R ec om Reset Time Delay m en de d Minimum Sys Clock with Missing Clock Detector Enabled fo r — 17 Rev 1.1 Table 1.6. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Conditions Min Typ Max Units 2 — 3 SYSCLKs Low power oscillator — 400 — ns Precision oscillator — 1.3 — µs — 2 — µs Idle Mode Wake-up Time Suspend Mode Wake-up Time Sleep Mode Wake-up Time D Table 1.7. Flash Electrical Characteristics Conditions Typ Max Units 16384 — 32768 bytes 20k 100k — 20 30 40 ms 60 70 µs N ew Flash Size Min fo r VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter See ordering information for flash sizes of all C8051F97x devices Endurance Erase Cycle Time Write Cycle Time es ig ns Parameter 50 Table 1.8. Internal Precision Oscillator Electrical Characteristics Parameter Oscillator Frequency m en de d VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Oscillator Supply Current  (from VDD) Conditions Min Typ Max Units –40 to +85 °C, VDD = 1.8–3.6 V 24 24.5 25 MHz 25 °C; includes bias current of 90–100 µA — 300 — µA Table 1.9. Internal Low-Power Oscillator Electrical Characteristics om VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Conditions Min Typ Max Units Oscillator Frequency (Low Power Oscillator) –40 to +85 °C, VDD = 1.8–3.6 V 18 20 22 MHz 25 °C No separate bias current required — 100 — µA Max 22 Units kHz ec Parameter R Oscillator Supply Current  (from VDD) N ot Table 1.10. SmaRTClock Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency (LFO) Conditions Rev 1.1 Min 11 Typ 16.4 18 Table 1.11. ADC0 Electrical Characteristics VDD = 1.8 to 3.6 V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Conditions Min Typ DC Accuracy Resolution 10 Max Units es ig ns Parameter bits — ±0.5 ±1 LSB Differential Nonlinearity (Guaranteed Monotonic) — ±0.5 ±1 LSB Offset Error — ±0x8000 Any value ACC41[31:16] + 1 0x8000 Any value X41[30:16] All bits = X41[39] –20 °C When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure that the chosen crystal will oscillate under the worst case condition to which the system will be exposed. The worst case condition that should result in the least robust oscillation is at the following system conditions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias current (AGC enabled, Bias Double Disabled). N ew D Load m en de d fo r To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robustness. As shown in Figure 25.2, duty cycles less than 55% indicate a robust oscillation. As the duty cycle approaches 60%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very low temperatures or high supply voltage will vary from results taken at room temperature or low supply voltage. Safe Operating Zone 25% Low Risk of Clock Failure 55% High Risk of Clock Failure 60% Duty Cycle om Figure 25.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ec As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at the cost of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will provide the crystal oscillator with higher immunity against external factors which may lead to clock failure. Automatic Gain Control must be disabled if using the SmaRTClock oscillator in self-oscillate mode. N ot R Table 25.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows the self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor environmental conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting BIASX2 (RTC0XCN.5) to 1. Rev 1.1 259 . Self-Oscillate Power Consumption Bias Double Off, AGC On Lowest 600 nA Bias Double Off, AGC Off Low 800 nA Bias Double On, AGC On High Bias Double On, AGC Off Highest Bias Double Off Low N ot R ec om m en de d fo r Bias Double On 260 Rev 1.1 D Crystal Setting N ew Mode es ig ns Table 25.3. SmaRTClock Bias Settings High 25.2.6. Missing SmaRTClock Detector The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKINT (RTC0CN.6) to 1. When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if SmaRTClock oscillator remains high or low for more than 100 µs. es ig ns A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power mode, or reset the device. See Section “13. Interrupts” on page 79, Section “16. Power Management” on page 94, and Section “27. Reset Sources and Supply Monitor” on page 322 for more information. Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in RTC0XCN. 25.2.7. SmaRTClock Oscillator Crystal Valid Detector D The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during crystal startup to determine when oscillation has started and is nearly stable. The output of this detector can be read from the CLKVLD bit (RTX0XCN.4). 25.3. SmaRTClock Timer and Alarm Function N ew Notes: 1. The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal oscillator, the output of CLKVLD is not valid. 2. This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure. The missing SmaRTClock detector (CLKFAIL) should be used for this purpose. fo r The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt, wake the device from a low power mode, or reset the device at a specific time. See Section “13. Interrupts” on page 79, Section “16. Power Management” on page 94, and Section “27. Reset Sources and Supply Monitor” on page 322 for more information. m en de d The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one SmaRTClock cycle after an alarm occurs. When using Auto Reset, the Alarm match value should always be set to 1 count less than the desired match value. Auto Reset can be enabled by writing a 1 to ALRM (RTC0CN.2). 25.3.1. Setting and Reading the SmaRTClock Timer Value The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the timer does not need to be stopped before reading or setting its value. The following steps can be used to set the timer value: 1. Write the desired 32-bit set value to the CAPTUREn registers. 2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRTClock timer. 3. Operation is complete when RTC0SET is cleared to 0 by hardware. om The following steps can be used to read the current timer value: 1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers. 2. Poll RTC0CAP until it is cleared to 0 by hardware. N ot R ec 3. A snapshot of the timer value can be read from the CAPTUREn registers Rev 1.1 261 25.3.2. Setting a SmaRTClock Alarm The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers. If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm event. es ig ns The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or generate an interrupt. See Section “13. Interrupts” on page 79, Section “16. Power Management” on page 94, and Section “27. Reset Sources and Supply Monitor” on page 322 for more information. The following steps can be used to set up a SmaRTClock Alarm: 1. Disable SmaRTClock Alarm Events (RTC0AINT = 0). 2. Set the ALARMn registers to the desired value. 3. Enable SmaRTClock Alarm Events (RTC0AINT = 1). D When using the SmaRTClock in Self-Oscillate or Crystal Modes, the alarm is triggered every N + 2 RTC cycles except for the first alarm, which triggers after N RTC cycles. N is the value written into the 32-bit ALARM register. N ew When using the SmaRTClock with the internal LFO, the alarm is triggered every N/2 + 2 RTC cycles except for the first alarm, which triggers after N/2 RTC cycles. N is the value written into the 32-bit ALARM register. If N is odd, then the hardware uses N/2 rounded down. N ot R ec om m en de d fo r Notes: 1. The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm Events (RTC0AINT = 0). 2. If AutoReset is disabled, disabling (RTC0AINT = 0) then Re-enabling Alarm Events (RTC0AINT = 1) after a SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next alarm after 2^32 SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal). 3. The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “16. Power Management” on page 94 for information on how to capture a SmaRTClock Alarm event using a flag which is not automatically cleared by hardware. 4. When an external clock is used as the SmaRTClock source, the system clock speed must be more than 9 times the SmaRTClock speed for the SmaRTClock alarm functionality to work correctly. 5. When an external clock source is used as the SmaRTClock source, the system clock speed must be more than 5 times the SmaRTClock speed for the SmaRTClock alarm functionality to work correctly. 262 Rev 1.1 25.3.3. Software Considerations for Using the SmaRTClock Timer and Alarm The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes are described below: es ig ns Mode 1: The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36 hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software managed and is added to the ALRMn registers by software after each alarm. This allows the alarm match value to always stay ahead of the timer by one software managed interval. If software uses 32-bit unsigned addition to increment the alarm match value, then it does not need to handle overflows since both the timer and the alarm match value will overflow in the same manner. D This mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a need for a perpetual timebase. An example of an application that needs a perpetual timebase is one whose wake-up interval is constantly changing. For these applications, software can keep track of the number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year) perpetual timebase. N ew Mode 2: The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero by hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn registers. Software only needs to set the alarm interval once during device initialization. After each alarm, software should keep a count of the number of alarms that have occurred in order to keep track of time. fo r This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm interval. This mode is the most power efficient since it requires less CPU time per alarm. N ot R ec om m en de d Important Note: The alarm interval will be 2 more SmaRTClock cycles than the expected value because 1 cycle holds the alarm signal high and another cycle is used to reset the alarm. Rev 1.1 263 25.4. RTC0 Control Registers Bit 7 6 5 4 Name BUSY AUTORD Reserved SHORT ADDR Type RW RW R RW RW Reset 0 0 0 0 0 SFR Page = 0x0; SFR Address: 0xAC Name 7 BUSY Function RTC Interface Busy Indicator. 0 1 0 0 0 N ew Bit 2 D 3 es ig ns Register 25.1. RTC0ADR: RTC Address This bit indicates the RTC interface status. Writing a 1 to this bit initiates an indirect read. 6 AUTORD RTC Interface Autoread Enable. 5 Reserved 4 SHORT m en de d fo r When autoread is enabled, firmware should set the BUSY bit once at the beginning of each series of consecutive reads. Firmware must check if the RTC Interface is busy prior to reading RTC0DAT. 0: Disable autoread. Firmware must write the BUSY bit for each RTC indirect read operation. 1: Enable autoread. The next RTC indirect read operation is initiated when firmware reads the RTC0DAT register. Must write reset value. Short Strobe Enable. Enables/disables the Short Strobe feature. 0: Disable short strobe. 1: Enable short strobe. 3:0 ADDR RTC Indirect Register Address. om Sets the currently-selected RTC internal register. N ot R ec Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn internal RTC register. 264 Rev 1.1 Register 25.2. RTC0DAT: RTC Data 6 5 4 Name RTC0DAT Type RW Reset 0 0 0 0 3 2 0 0 SFR Page = 0x0; SFR Address: 0xAD Bit Name 7:0 RTC0DAT Function RTC Data. 1 0 0 0 es ig ns 7 D Bit N ew Holds data transferred to/from the internal RTC register selected by RTC0ADR. N ot R ec om m en de d fo r Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register. Rev 1.1 265 Register 25.3. RTC0CN: RTC Control 6 5 4 3 2 Name RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN ALRM Type RW RW RW RW RW RW Reset 0 0 X 0 0 0 Indirect Address: 0x04 Bit Name 7 RTC0EN Function RTC Enable. 1 0 RTC0SET RTC0CAP RW RW 0 0 es ig ns 7 D Bit 6 MCLKEN Missing RTC Detector Enable. N ew Enables/disables the RTC oscillator and associated bias currents. 0: Disable RTC oscillator. 1: Enable RTC oscillator. 5 OSCFAIL fo r Enables/disables the missing RTC detector. 0: Disable missing RTC detector. 1: Enable missing RTC detector. RTC Oscillator Fail Event Flag. 4 RTC0TR m en de d Set by hardware when a missing RTC detector timeout occurs. Must be cleared by firmware. The value of this bit is not defined when the RTC oscillator is disabled. RTC Timer Run Control. Controls if the RTC timer is running or stopped (holds current value). 0: RTC timer is stopped. 1: RTC timer is running. 3 RTC0AEN RTC Alarm Enable. om Enables/disables the RTC alarm function. Also clears the ALRM flag. 0: Disable RTC alarm. 1: Enable RTC alarm. RTC0SET R 1 ALRM ec 2 N ot 0 RTC0CAP RTC Alarm Event Flag and Auto Reset Enable. Reads return the state of the alarm event flag. Writes enable/disable the Auto Reset function. RTC Timer Set. Writing 1 initiates a RTC timer set operation. This bit is cleared to 0 by hardware to indicate that the timer set operation is complete. RTC Timer Capture. Writing 1 initiates a RTC timer capture operation. This bit is cleared to 0 by hardware to indicate that the timer capture operation is complete. Note: The ALRM flag will remain asserted for a maximum of one RTC cycle. 266 Rev 1.1 Register 25.4. RTC0XCN: RTC Oscillator Control 6 5 4 3 Name AGCEN XMODE BIASX2 CLKVLD LFOEN Type RW RW RW R R Reset 0 0 0 0 0 2 R 0 7 AGCEN Function RTC Oscillator Automatic Gain Control (AGC) Enable. 0: Disable AGC. 1: Enable AGC. 6 XMODE RTC Oscillator Mode. 5 BIASX2 0 fo r Selects Crystal or Self Oscillate Mode. 0: Self-Oscillate Mode selected. 1: Crystal Mode selected. 0 N ew Name 0 Reserved Indirect Address: 0x05 Bit 1 es ig ns 7 D Bit RTC Oscillator Bias Double Enable. 4 CLKVLD m en de d Enables/disables the Bias Double feature. 0: Disable the Bias Double feature. 1: Enable the Bias Double feature. RTC Oscillator Crystal Valid Indicator. Indicates if oscillation amplitude is sufficient for maintaining oscillation. 0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation. 1: Sufficient oscillation amplitude detected. 3 LFOEN Low Frequency Oscillator Enable and Select. Reserved Must write reset value. N ot R ec 2:0 om Overrides XMODE and selects the internal low frequency oscillator (LFOSC) as the RTC oscillator source. 0: XMODE determines RTC oscillator source. 1: LFOSC enabled and selected as RTC oscillator source. Rev 1.1 267 Register 25.5. RTC0XCF: RTC Oscillator Configuration 6 5 AUTOSTP LOADRDY Type RW R Reset 0 0 4 3 Reserved LOADCAP R RW 0 0 X Indirect Address: 0x06 Bit Name 7 AUTOSTP 2 Function Automatic Load Capacitance Stepping Enable. X 1 0 X X es ig ns Name 7 D Bit 6 LOADRDY Load Capacitance Ready Indicator. N ew Enables/disables automatic load capacitance stepping. 0: Disable load capacitance stepping. 1: Enable load capacitance stepping. fo r Set by hardware when the load capacitance matches the programmed value. 0: Load capacitance is currently stepping. 1: Load capacitance has reached it programmed value. Reserved Must write reset value. 3:0 LOADCAP Load Capacitance Programmed Value. m en de d 5:4 N ot R ec om Holds the desired load capacitance value. 268 Rev 1.1 Register 25.6. CAPTURE0: RTC Timer Capture 0 6 5 4 3 Name CAPTURE0 Type RW Reset 0 0 0 0 0 Indirect Address: 0x00 Bit 7:0 Name Function CAPTURE0 RTC Timer Capture 0. 2 0 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The CAPTURE3-CAPTURE0 registers are used to read or set the 32-bit RTC timer. Data is transferred to or from the RTC timer when the RTC0SET or RTC0CAP bits are set. Rev 1.1 269 Register 25.7. CAPTURE1: RTC Timer Capture 1 6 5 4 3 Name CAPTURE1 Type RW Reset 0 0 0 0 0 Indirect Address: 0x01 Bit 7:0 Name Function CAPTURE1 RTC Timer Capture 1. 2 0 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The CAPTURE3-CAPTURE0 registers are used to read or set the 32-bit RTC timer. Data is transferred to or from the RTC timer when the RTC0SET or RTC0CAP bits are set. 270 Rev 1.1 Register 25.8. CAPTURE2: RTC Timer Capture 2 6 5 4 3 Name CAPTURE2 Type RW Reset 0 0 0 0 0 Indirect Address: 0x02 Bit 7:0 Name Function CAPTURE2 RTC Timer Capture 2. 2 0 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The CAPTURE3-CAPTURE0 registers are used to read or set the 32-bit RTC timer. Data is transferred to or from the RTC timer when the RTC0SET or RTC0CAP bits are set. Rev 1.1 271 Register 25.9. CAPTURE3: RTC Timer Capture 3 6 5 4 3 Name CAPTURE3 Type RW Reset 0 0 0 0 0 Indirect Address: 0x03 Bit 7:0 Name Function CAPTURE3 RTC Timer Capture 3. 2 0 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The CAPTURE3-CAPTURE0 registers are used to read or set the 32-bit RTC timer. Data is transferred to or from the RTC timer when the RTC0SET or RTC0CAP bits are set. 272 Rev 1.1 Register 25.10. ALARM0: RTC Alarm Programmed Value 0 6 5 4 Name ALARM0 Type RW Reset 0 0 0 0 3 2 0 0 Indirect Address: 0x08 Bit Name 7:0 ALARM0 Function RTC Alarm Programmed Value 0. 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The ALARM3-ALARM0 registers are used to set an alarm event for the RTC timer. The RTC alarm should be disabled (RTC0AEN=0) when updating these registers. Rev 1.1 273 Register 25.11. ALARM1: RTC Alarm Programmed Value 1 6 5 4 Name ALARM1 Type RW Reset 0 0 0 0 3 2 0 0 Indirect Address: 0x09 Bit Name 7:0 ALARM1 Function RTC Alarm Programmed Value 1. 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The ALARM3-ALARM0 registers are used to set an alarm event for the RTC timer. The RTC alarm should be disabled (RTC0AEN=0) when updating these registers. 274 Rev 1.1 Register 25.12. ALARM2: RTC Alarm Programmed Value 2 6 5 4 Name ALARM2 Type RW Reset 0 0 0 0 3 2 0 0 Indirect Address: 0x0A Bit Name 7:0 ALARM2 Function RTC Alarm Programmed Value 2. 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The ALARM3-ALARM0 registers are used to set an alarm event for the RTC timer. The RTC alarm should be disabled (RTC0AEN=0) when updating these registers. Rev 1.1 275 Register 25.13. ALARM3: RTC Alarm Programmed Value 3 6 5 4 Name ALARM3 Type RW Reset 0 0 0 0 3 2 0 0 Indirect Address: 0x0B Bit Name 7:0 ALARM3 Function RTC Alarm Programmed Value 3. 1 0 0 0 es ig ns 7 D Bit N ot R ec om m en de d fo r N ew The ALARM3-ALARM0 registers are used to set an alarm event for the RTC timer. The RTC alarm should be disabled (RTC0AEN=0) when updating these registers. 276 Rev 1.1 26. Port I/O (Port 0, Port 1, Port 2, Port 3, Port 4, Port 5, Port 6, Crossbar, and Port Match) es ig ns Digital and analog resources on the C8051F97x family are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar, or assigned to an analog function. Port pins P3.0-P6.1 can be used as GPIO. Port pin P5.2 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a priority crossbar decoder. Note that the state of a port I/O pin can always be read in the corresponding port latch, regardless of the crossbar settings. The crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 26.2 and Figure 26.3). The registers XBR0 and XBR1 are used to select internal digital functions. N ew D The port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Additionally, each bank of port pins (P0, P1, P2, P3, P4, and P5) have two selectable drive strength settings. The P6 pins only support digital open-drain mode and cannot be configured as digital push-pull pins. 2 SMBus0 Priority Crossbar Decoder 4 SPI0 fo r 2 UART0 1 m en de d SYSCLK 3 PCA (CEXn) 1 PCA (ECI) 1 Timer 0 Port Match Port 0 Control & Config Port 1 Control & Config Port 2 Control & Config Port 3 Control & Config 1 INT0 / INT1 ADC0 In CS0 In I2C0 Slave In / Out N ot Port 4 Control & Config Port 5 Control & Config Port 6 Control & Config R ec om Timer 1 P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.7 P4.0 P4.7 P5.0 P5.1 P5.2 P6.0 P6.1 Figure 26.1. Port I/O Functional Block Diagram Rev 1.1 277 26.1. General Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all port pins, using the Port Input Mode register (PnMDIN). es ig ns 2. Select the output mode (open-drain or push-pull) for all port pins, using the Port Output Mode register (PnMDOUT). 3. Select any pins to be skipped by the I/O crossbar using the Port Skip registers (PnSKIP). 4. Assign port pins to desired peripherals. 5. Enable the crossbar (XBARE = ‘1’). D All port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. N ew Additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. fo r The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each port output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. When the WEAKPUD bit in XBR1 is ‘0’, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an output that is driving a ‘0’ to avoid unnecessary power dissipation. m en de d Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR2 to ‘1’ enables the crossbar. Until the crossbar is enabled, the external pins remain as standard port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, Silicon Labs provides configuration utility software to determine the port I/O pin-assignments based on the crossbar register settings. N ot R ec om The crossbar must be enabled to use port pins as standard port I/O in output mode. Port output drivers of all crossbar pins are disabled whenever the crossbar is disabled. 278 Rev 1.1 26.2. Assigning Port I/O Pins to Analog and Digital Functions 26.2.1. Assigning Port I/O Pins to Analog Functions es ig ns Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The port pins assigned to analog functions should be configured for analog I/O, and port pins assigned to digital or external interrupt functions should be configured for digital I/O. Table 26.1 shows all available analog functions that require port I/O assignments. Table 26.1 shows the potential mapping of port I/O to each analog function. Table 26.1. Port I/O Assignment for Analog Functions Analog Function Potentially Assignable Port Pins SFR(s) used for Assignment QFN-32 QFN-24 ADC Input P0.0 – P5.2 P0.0 – P3.2, P5.2 P0.0 – P2.1, P5.2 PnMDIN, AMUX0Pn, Pn, ADC0 Registers Capacitive Sense Input P0.0 – P5.2 P0.0 – P3.2, P5.2 P0.0 – P2.1, P5.2 PnMDIN, AMUX0Pn, Pn, CS0 Registers Voltage Reference (VREF) P0.0 P0.0 P0.0 REF0CN, PnSKIP, P0.0 bit set, PnMDIN External Oscillator Input (XTAL1) P1.0 External Oscillator Input (XTAL2) fo r N ew D QFN-48 OSCXCN, AMUX0Pn (cleared), Pn bit set, PnMDIN P1.1 P0.6 OSCXCN, AMUX0Pn (cleared), P0.1 bit set, PnMDIN SmaRTClock Oscillator Input (XTAL3) P0.6 P0.3 RTC0CN, AMUX0Pn (cleared), P0.0 bit set, PnMDIN SmaRTClock Oscillator Input (XTAL4) P0.7 P0.4 RTC0CN, AMUX0Pn (cleared), P0.1 bit set, PnMDIN N ot R ec om m en de d P0.5 Rev 1.1 279 26.2.2. Assigning Port I/O Pins to Digital Functions Table 26.2. Port I/O Assignment for Digital Functions Digital Function Potentially Assignable Port Pins QFN-48 QFN-32 QFN-24 Any port pin available for assignment by the crossbar. This includes P0.0 – P2.7 pins which have their PnSKIP bit set to ‘0’. Any pin used for GPIO P0.0 – P5.2, P6.0 – P6.1 SFR(s) Used for Assignment XBR0, XBR1, XBR2 D SMBus0, UART0, SPI0, SYSCLK, PCA0 (CEX0-2 and ECI), T0, or T1. es ig ns Any port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most digital functions rely on the crossbar for pin assignment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. Table 26.2 shows all digital functions available through the crossbar and the potential mapping of port I/O to each function. P0.0 – P2.1, P5.2, P6.0 – P6.1 N ew P0.0 – P3.2, P5.2, P6.0 – P6.1 26.2.3. Assigning Port I/O Pins to Fixed Digital Functions P0SKIP, P1SKIP, P2SKIP m en de d fo r Fixed digital functions include external clock input as well as external event trigger functions, which can be used to trigger events such as an ADC conversion, fire an interrupt or wake the device from idle mode when a transition occurs on a digital I/O pin. The fixed digital functions do not require dedicated pins and will function on both GPIO pins and pins in use by the crossbar. Fixed digital functions cannot be used on pins configured for analog I/O. Table 26.3 shows all available fixed digital functions and the potential mapping of port I/O to each function. Table 26.3. Port I/O Assignment for Fixed Digital Functions Function Potentially Assignable Port Pins QFN-48 External Interrupt 0 External Interrupt 1 QFN-32 P0.0 - P0.7 IT01CF P0.0 - P0.7 IT01CF P0.6 ADC0CN ec om Conversion Start (CNVSTR) Port Match P0.0 - P2.7 P6.0, P6.1 N ot R I2C Slave 0 P0.0 - P2.7 280 QFN-24 SFR(s) used for Assignment Rev 1.1 P0.0 - P2.1 P0MASK, P0MAT P1MASK, P1MAT P2MASK, P2MAT I2C0CN 26.3. Priority Crossbar Decoder es ig ns The priority crossbar decoder assigns a priority to each I/O function in order from top to bottom. When a digital resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. Additionally, the crossbar will skip port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a port pin is claimed by a peripheral without use of the crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, XTAL1, XTAL2, XTAL3, or XTAL4 pins on a QFN-32 or QFN-48 package, P0.6 if the ADC is configured to use the external conversion start signal (CNVSTR), and any selected ADC or comparator inputs. The crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. P4 P5 P6 4 5 6 7 X X X X 0 0 0 0 fo r XTAL2 / CNVSTR P3 3 N/A 2 N/A 1 N/A 0 N/A 7 N/A 6 N/A P2 5 N/A 4 N/A 0 3 N/A XTAL2 0 2 N/A 1 N/A 0 XTAL1 XTAL1 7 m en de d VREF QFN-48 Package 6 CNVSTR 5 XTAL4 4 XTAL3 / CNVSTR P1 3 VREF QFN-32 Package VREF QFN-24 Package 2 XTAL4 P0 1 XTAL3 Port Pin Number 0 N ew D Figure 26.2 shows all of the potential peripheral-to-pin assignments available to the crossbar. Note that this does not mean any peripheral can always be assigned to the highlighted pins. The actual pin assignments are determined by the priority of the enabled peripherals. SMB0-SDA SMB0-SCL UART0-TX Pins Not Available on Crossbar UART0-RX SPI0-SCK SPI0-MISO SPI0-MOSI SPI0-NSS* om SYSCLK PCA0-CEX0 PCA0-CEX1 PCA0-CEX2 ec PCA0-ECI Timer0-T0 N ot R Timer1-T1 Pin Skip Settings 0 0 0 0 0 0 0 0 0 0 P0SKIP 0 0 P1SKIP 0 0 0 0 0 0 P2SKIP The crossbar peripherals are assigned in priority order from top to bottom. These boxes represent Port pins which can potentially be assigned to a peripheral. Special Function Signals are not assigned by the crossbar. When these signals are enabled, the Crossbar should be manually configured to skip the corresponding port pins. Pins can be “skipped” by setting the corresponding bit in PnSKIP to1. * NSS is only pinned out when the SPI is in 4-wire mode. Figure 26.2. Crossbar Priority Decoder—Possible Pin Assignments Rev 1.1 281 Registers XBR0 and XBR1are used to assign the digital I/O resources to the physical I/O port pins. Note that when the SMBus is selected, the crossbar assigns both pins associated with the SMBus (SDA and SCL); when UART0 is selected, the crossbar assigns both pins associated with UART0 (TX and RX). Standard port I/Os appear contiguously after the prioritized functions have been assigned. P2 0 1 P3 3 4 5 6 7 X P4 P5 P6 X X X N ew N/A N/A 2 N/A N/A 7 D 6 N/A 5 N/A 4 N/A XTAL2 3 N/A XTAL1 2 N/A 1 N/A 0 N/A 7 XTAL2 / CNVSTR XTAL3 / CNVSTR VREF QFN-48 Package 6 CNVSTR 5 XTAL4 4 XTAL1 P1 3 VREF QFN-32 Package VREF fo r SMB0-SDA SMB0-SCL UART0-TX UART0-RX Pins Not Available on Crossbar QFN-24 Package 2 XTAL4 P0 1 XTAL3 Port Pin Number 0 es ig ns Figure 26.3 shows an example of the resulting pin assignments of the device with SMBus0, SPI0, and two channels of PCA0 enabled and P0.3, P0.4, P1.0, and P1.1 skipped (P0SKIP = 0x18, P1SKIP = 0x03). SMBus0 is the highest priority and it will be assigned first. The next-highest enabled peripheral is SPI0. P0.2 is available, so SPI0 takes this pin. The next pins, MISO, MOSI, and NSS are routed to P0.5, P0.6, and P0.7, respectively, because P0.3 and P0.4 are skipped. The PCA0 CEX0 and CEX1are then routed to P1.2 and P1.3. The other pins on the device are available for use as general-purpose digital I/O or analog functions. m en de d SPI0-SCK SPI0-MISO SPI0-MOSI SPI0-NSS* SYSCLK PCA0-CEX0 PCA0-CEX1 PCA0-CEX2 PCA0-ECI Timer0-T0 om Timer1-T1 Pin Skip Settings 0 0 0 1 1 0 0 0 1 1 0 0 P0SKIP 0 0 P1SKIP 0 0 0 0 0 0 0 0 0 0 P2SKIP The crossbar peripherals are assigned in priority order from top to bottom. ec These boxes represent Port pins which can potentially be assigned to a peripheral. N ot R Special Function Signals are not assigned by the crossbar. When these signals are enabled, the Crossbar should be manually configured to skip the corresponding port pins. Pins can be “skipped” by setting the corresponding bit in PnSKIP to1. * NSS is only pinned out when the SPI is in 4-wire mode. Figure 26.3. Crossbar Priority Decoder Example Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a port pin. 282 Rev 1.1 26.4. Port I/O Modes of Operation es ig ns Port pins are configured by firmware as digital or analog I/O using the PnMDIN registers. On reset, all port I/O cells default to a high impedance state with weak pull-ups enabled. Until the crossbar is enabled, both the high and low port I/O drive circuits are explicitly disabled on all crossbar pins. Port pins configured as digital I/O may still be used by analog peripherals; however, this practice is not recommended and may result in measurement errors. 26.4.1. Configuring Port Pins For Analog Modes Any pins to be used for analog functions should be configured for analog mode. When a pin is configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins configured for analog functions will always read back a value of ‘0’ in the corresponding Pn Port Latch register. To configure a pin as analog, the following steps should be taken: 1. Clear the bit associated with the pin in the PnMDIN register to ‘0’. This selects analog mode for the pin. D 2. Set the bit associated with the pin in the Pn register to ‘1’. 3. Skip the bit associated with the pin in the PnSKIP register to ensure the crossbar does not attempt to assign a function to the pin. N ew 26.4.2. Configuring Port Pins For Digital Modes Any pins to be used by digital peripherals or as GPIO should be configured as digital I/O (PnMDIN.n = ‘1’). For digital I/O pins, one of two output modes (push-pull or open-drain) must be selected using the PnMDOUT registers. fo r Push-pull outputs (PnMDOUT.n = ‘1’) drive the port pad to the supply rails based on the output logic value of the port pin. Open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to the lowside rail when the output logic value is ‘0’ and become high impedance inputs (both high low drivers turned off) when the output logic value is ‘1’. m en de d When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the highside rail to ensure the digital input is at a defined logic state. Weak pull-ups are disabled when the I/O cell is driven low to minimize power consumption, and they may be globally disabled by setting WEAKPUD to ‘1’. The user should ensure that digital I/O are always internally or externally pulled or driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back the logic state of the port pad, regardless of the output logic value of the port pin. To configure a pin as digital input: 1. Set the bit associated with the pin in the PnMDIN register to ‘1’. This selects digital mode for the pin. 2. Clear the bit associated with the pin in the PnMDOUT register to ‘0’. This configures the pin as open-drain. 3. Set the bit associated with the pin in the Pn register to ‘1’. This tells the output driver to “drive” logic high. Because the pin is configured as open-drain, the high-side driver is not active, and the pin may be used as an input. om Open-drain outputs are configured exactly as digital inputs. However, the pin may be driven low by an assigned peripheral, or by writing ‘0’ to the associated bit in the Pn register if the signal is a GPIO. ec To configure a pin as a digital, push-pull output: 1. Set the bit associated with the pin in the PnMDIN register to ‘1’. This selects digital mode for the pin. 2. Set the bit associated with the pin in the PnMDOUT register to ‘1’. This configures the pin as push-pull. R If a digital pin is to be used as a general-purpose I/O, or with a digital function that is not part of the crossbar, the bit associated with the pin in the PnSKIP register can be set to ‘1’ to ensure the crossbar does not attempt to assign a function to the pin. N ot 26.4.3. Port Drive Strength Port drive strength can be controlled on a pin-by-pin basis using the PnDRV registers. Each pin has a bit in the associated PnDRV register to select the high or low drive strength setting for the pin. By default, all pins are configured for low drive strength. Rev 1.1 283 WEAKPUD (Weak Pull-Up Disable) PxMDOUT.x (1 for push-pull) (0 for open-drain) VDD es ig ns VDD XBARE (Crossbar Enable) (WEAK) PxMDIN.x (1 for digital) (0 for analog) To/From Analog Peripheral N ew GND D PORT PAD Px.x – Output Logic Value (Port Latch or Crossbar) Px.x – Input Logic Value (Reads 0 when pin is configured as an analog I/O) Figure 26.4. Port I/O Cell Block Diagram fo r 26.5. Port Match m en de d Port match functionality allows system events to be triggered by a logic value change on one or more port I/O pins. A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of the associated port pins (for example, P0MATCH.0 would correspond to P0.0). A port mismatch event occurs if the logic levels of the port’s input pins no longer match the software controlled value. This allows software to be notified if a certain change or pattern occurs on the input pins regardless of the XBRn settings. The PnMASK registers can be used to individually select which pins should be compared against the PnMATCH registers. A port mismatch event is generated if (Pn & PnMASK) does not equal (PnMATCH & PnMASK) for all ports with a PnMAT and PnMASK register. A port mismatch event may be used to generate an interrupt or wake the device from idle mode. See the interrupts and power options chapters for more details on interrupt and wake-up sources. 26.6. Direct Read/Write Access to Port I/O Pins N ot R ec om All port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a port SFR. For these instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR. 284 Rev 1.1 26.7. Port Configuration Registers 7 Name ECIE Type RW Reset 0 6 5 3 2 PCA0ME SYSCKE SMB0E RW RW RW 0 0 0 0 4 0 SFR Page = 0xF; SFR Address: 0x95 Bit Name 7 ECIE URT0E RW RW 0 0 PCA0 External Counter Input Enable. PCA Module I/O Enable. fo r PCA0ME SPI0E Function 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. 6:4 0 N ew Table 26.4. XBR0 Register Bit Descriptions 1 D Bit es ig ns Register 26.1. XBR0: Port I/O Crossbar 0 3 SYSCKE m en de d 000: All PCA I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100-111: Reserved. SYSCLK Output Enable. 0: SYSCLK unavailable at Port pin. 1: SYSCLK output routed to Port pin. 2 SMB0E SMBus0 I/O Enable. 0: SMBus0 I/O unavailable at Port pins. 1: SMBus0 I/O routed to Port pins. SPI0E SPI I/O Enable. om 1 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4 GPIO pins. ec URT0E UART I/O Output Enable. 0: UART I/O unavailable at Port pin. 1: UART TX, RX routed to Port pins P0.4 and P0.5. N ot R 0 Rev 1.1 285 Register 26.2. XBR1: Port I/O Crossbar 1 6 5 4 Name WEAKPUD XBARE Reserved Type RW RW RW Reset 0 0 0 3 0 0 2 0 SFR Page = 0xF; SFR Address: 0x96 Table 26.5. XBR1 Register Bit Descriptions Name 7 WEAKPUD Function Port I/O Weak Pullup Disable. N ew Bit 1 0 T1E T0E RW RW 0 0 es ig ns 7 D Bit 0: Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). 1: Weak Pullups disabled. 6 XBARE Crossbar Enable. 5:2 Reserved 1 T1E fo r 0: Crossbar disabled. 1: Crossbar enabled. Must write reset value. T1 Enable. 0 T0E m en de d 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. T0 Enable. N ot R ec om 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. 286 Rev 1.1 26.8. Port I/O Control Registers Bit 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 1 0 B1 B0 RW RW 0 0 D SFR Page = 0xF; SFR Address: 0x8B es ig ns Register 26.3. P0MASK: Port 0 Mask Bit Name 7 B7 N ew Table 26.6. P0MASK Register Bit Descriptions Function Port 0 Bit 7 Mask Value. 0: P0.7 pin logic value is ignored and will not cause a port mismatch event. 1: P0.7 pin logic value is compared to P0MAT.7. B6 Port 0 Bit 6 Mask Value. fo r 6 0: P0.6 pin logic value is ignored and will not cause a port mismatch event. 1: P0.6 pin logic value is compared to P0MAT.6. 5 B5 Port 0 Bit 5 Mask Value. 4 B4 m en de d 0: P0.5 pin logic value is ignored and will not cause a port mismatch event. 1: P0.5 pin logic value is compared to P0MAT.5. Port 0 Bit 4 Mask Value. 0: P0.4 pin logic value is ignored and will not cause a port mismatch event. 1: P0.4 pin logic value is compared to P0MAT.4. 3 B3 Port 0 Bit 3 Mask Value. 0: P0.3 pin logic value is ignored and will not cause a port mismatch event. 1: P0.3 pin logic value is compared to P0MAT.3. B2 Port 0 Bit 2 Mask Value. om 2 0: P0.2 pin logic value is ignored and will not cause a port mismatch event. 1: P0.2 pin logic value is compared to P0MAT.2. B1 ec R 1 N ot 0 B0 Port 0 Bit 1 Mask Value. 0: P0.1 pin logic value is ignored and will not cause a port mismatch event. 1: P0.1 pin logic value is compared to P0MAT.1. Port 0 Bit 0 Mask Value. 0: P0.0 pin logic value is ignored and will not cause a port mismatch event. 1: P0.0 pin logic value is compared to P0MAT.0. Rev 1.1 287 Register 26.4. P0MAT: Port 0 Match 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xF4 Table 26.7. P0MAT Register Bit Descriptions Name 7 B7 Function N ew Bit Port 0 Bit 7 Match Value. 0: P0.7 pin logic value is compared with logic LOW. 1: P0.7 pin logic value is compared with logic HIGH. 6 B6 Port 0 Bit 6 Match Value. 5 B5 Port 0 Bit 5 Match Value. fo r 0: P0.6 pin logic value is compared with logic LOW. 1: P0.6 pin logic value is compared with logic HIGH. 4 B4 m en de d 0: P0.5 pin logic value is compared with logic LOW. 1: P0.5 pin logic value is compared with logic HIGH. Port 0 Bit 4 Match Value. 0: P0.4 pin logic value is compared with logic LOW. 1: P0.4 pin logic value is compared with logic HIGH. 3 B3 Port 0 Bit 3 Match Value. 0: P0.3 pin logic value is compared with logic LOW. 1: P0.3 pin logic value is compared with logic HIGH. 2 B2 Port 0 Bit 2 Match Value. om 0: P0.2 pin logic value is compared with logic LOW. 1: P0.2 pin logic value is compared with logic HIGH. B0 Port 0 Bit 1 Match Value. 0: P0.1 pin logic value is compared with logic LOW. 1: P0.1 pin logic value is compared with logic HIGH. Port 0 Bit 0 Match Value. 0: P0.0 pin logic value is compared with logic LOW. 1: P0.0 pin logic value is compared with logic HIGH. N ot R 0 B1 ec 1 288 Rev 1.1 1 0 B1 B0 RW RW 1 1 es ig ns 7 D Bit Register 26.5. P0: Port 0 Pin Latch 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = ALL; SFR Address: 0x80 (bit-addressable) Table 26.8. P0 Register Bit Descriptions Name 7 B7 Function 0 B1 B0 RW RW 1 1 N ew Bit 1 es ig ns 7 D Bit Port 0 Bit 7 Latch. 0: P0.7 is low. Set P0.7 to drive low. 1: P0.7 is high. Set P0.7 to drive or float high. 6 B6 Port 0 Bit 6 Latch. 5 B5 Port 0 Bit 5 Latch. fo r 0: P0.6 is low. Set P0.6 to drive low. 1: P0.6 is high. Set P0.6 to drive or float high. 4 B4 m en de d 0: P0.5 is low. Set P0.5 to drive low. 1: P0.5 is high. Set P0.5 to drive or float high. Port 0 Bit 4 Latch. 0: P0.4 is low. Set P0.4 to drive low. 1: P0.4 is high. Set P0.4 to drive or float high. 3 B3 Port 0 Bit 3 Latch. 0: P0.3 is low. Set P0.3 to drive low. 1: P0.3 is high. Set P0.3 to drive or float high. 2 B2 Port 0 Bit 2 Latch. om 0: P0.2 is low. Set P0.2 to drive low. 1: P0.2 is high. Set P0.2 to drive or float high. B0 Port 0 Bit 1 Latch. 0: P0.1 is low. Set P0.1 to drive low. 1: P0.1 is high. Set P0.1 to drive or float high. Port 0 Bit 0 Latch. 0: P0.0 is low. Set P0.0 to drive low. 1: P0.0 is high. Set P0.0 to drive or float high. N ot R 0 B1 ec 1 Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. Rev 1.1 289 Register 26.6. P0MDIN: Port 0 Input Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xEC Name 7 B7 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.9. P0MDIN Register Bit Descriptions 1 es ig ns Bit Port 0 Bit 7 Input Mode. 0: P0.7 pin is configured for analog mode. 1: P0.7 pin is configured for digital mode. 6 B6 Port 0 Bit 6 Input Mode. 5 B5 Port 0 Bit 5 Input Mode. fo r 0: P0.6 pin is configured for analog mode. 1: P0.6 pin is configured for digital mode. 4 B4 m en de d 0: P0.5 pin is configured for analog mode. 1: P0.5 pin is configured for digital mode. Port 0 Bit 4 Input Mode. 0: P0.4 pin is configured for analog mode. 1: P0.4 pin is configured for digital mode. 3 B3 Port 0 Bit 3 Input Mode. 0: P0.3 pin is configured for analog mode. 1: P0.3 pin is configured for digital mode. 2 B2 Port 0 Bit 2 Input Mode. om 0: P0.2 pin is configured for analog mode. 1: P0.2 pin is configured for digital mode. B0 Port 0 Bit 1 Input Mode. 0: P0.1 pin is configured for analog mode. 1: P0.1 pin is configured for digital mode. Port 0 Bit 0 Input Mode. 0: P0.0 pin is configured for analog mode. 1: P0.0 pin is configured for digital mode. N ot R 0 B1 ec 1 Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 290 Rev 1.1 Register 26.7. P0MDOUT: Port 0 Output Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xD9 Name 7 B7 Function Port 0 Bit 7 Output Mode. 0: P0.7 output is open-drain. 1: P0.7 output is push-pull. B6 Port 0 Bit 6 Output Mode. 0: P0.6 output is open-drain. 1: P0.6 output is push-pull. 5 B5 Port 0 Bit 5 Output Mode. 4 B4 RW RW 0 0 m en de d 0: P0.5 output is open-drain. 1: P0.5 output is push-pull. B0 fo r 6 B1 N ew Bit 0 D Table 26.10. P0MDOUT Register Bit Descriptions 1 es ig ns Bit Port 0 Bit 4 Output Mode. 0: P0.4 output is open-drain. 1: P0.4 output is push-pull. 3 B3 Port 0 Bit 3 Output Mode. 0: P0.3 output is open-drain. 1: P0.3 output is push-pull. 2 B2 Port 0 Bit 2 Output Mode. om 0: P0.2 output is open-drain. 1: P0.2 output is push-pull. B0 Port 0 Bit 1 Output Mode. 0: P0.1 output is open-drain. 1: P0.1 output is push-pull. Port 0 Bit 0 Output Mode. 0: P0.0 output is open-drain. 1: P0.0 output is push-pull. N ot R 0 B1 ec 1 Rev 1.1 291 Register 26.8. P0SKIP: Port 0 Skip 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xB6 Name 7 B7 Function N ew Bit Port 0 Bit 7 Skip. 0: P0.7 pin is not skipped by the crossbar. 1: P0.7 pin is skipped by the crossbar. 6 B6 Port 0 Bit 6 Skip. 5 B5 Port 0 Bit 5 Skip. fo r 0: P0.6 pin is not skipped by the crossbar. 1: P0.6 pin is skipped by the crossbar. 4 B4 m en de d 0: P0.5 pin is not skipped by the crossbar. 1: P0.5 pin is skipped by the crossbar. Port 0 Bit 4 Skip. 0: P0.4 pin is not skipped by the crossbar. 1: P0.4 pin is skipped by the crossbar. 3 B3 Port 0 Bit 3 Skip. 0: P0.3 pin is not skipped by the crossbar. 1: P0.3 pin is skipped by the crossbar. 2 B2 Port 0 Bit 2 Skip. om 0: P0.2 pin is not skipped by the crossbar. 1: P0.2 pin is skipped by the crossbar. B0 Port 0 Bit 1 Skip. 0: P0.1 pin is not skipped by the crossbar. 1: P0.1 pin is skipped by the crossbar. Port 0 Bit 0 Skip. 0: P0.0 pin is not skipped by the crossbar. 1: P0.0 pin is skipped by the crossbar. N ot R 0 B1 ec 1 292 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.11. P0SKIP Register Bit Descriptions 1 es ig ns Bit Register 26.9. P0DRV: Port 0 Drive Strength 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x99 Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.12. P0DRV Register Bit Descriptions 1 es ig ns Bit Port 0 Bit 7 Drive Strength. 0: P0.7 output has low output drive strength. 1: P0.7 output has high output drive strength. 6 B6 Port 0 Bit 6 Drive Strength. 5 B5 Port 0 Bit 5 Drive Strength. fo r 0: P0.6 output has low output drive strength. 1: P0.6 output has high output drive strength. 4 B4 m en de d 0: P0.5 output has low output drive strength. 1: P0.5 output has high output drive strength. Port 0 Bit 4 Drive Strength. 0: P0.4 output has low output drive strength. 1: P0.4 output has high output drive strength. 3 B3 Port 0 Bit 3 Drive Strength. 0: P0.3 output has low output drive strength. 1: P0.3 output has high output drive strength. 2 B2 Port 0 Bit 2 Drive Strength. om 0: P0.2 output has low output drive strength. 1: P0.2 output has high output drive strength. B0 Port 0 Bit 1 Drive Strength. 0: P0.1 output has low output drive strength. 1: P0.1 output has high output drive strength. Port 0 Bit 0 Drive Strength. 0: P0.0 output has low output drive strength. 1: P0.0 output has high output drive strength. N ot R 0 B1 ec 1 Rev 1.1 293 Register 26.10. P1MASK: Port 1 Mask 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x8C Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.13. P1MASK Register Bit Descriptions 1 es ig ns Bit Port 1 Bit 7 Mask Value. 0: P1.7 pin logic value is ignored and will not cause a port mismatch event. 1: P1.7 pin logic value is compared to P1MAT.7. 6 B6 Port 1 Bit 6 Mask Value. 5 B5 Port 1 Bit 5 Mask Value. fo r 0: P1.6 pin logic value is ignored and will not cause a port mismatch event. 1: P1.6 pin logic value is compared to P1MAT.6. 4 B4 m en de d 0: P1.5 pin logic value is ignored and will not cause a port mismatch event. 1: P1.5 pin logic value is compared to P1MAT.5. Port 1 Bit 4 Mask Value. 0: P1.4 pin logic value is ignored and will not cause a port mismatch event. 1: P1.4 pin logic value is compared to P1MAT.4. 3 B3 Port 1 Bit 3 Mask Value. 0: P1.3 pin logic value is ignored and will not cause a port mismatch event. 1: P1.3 pin logic value is compared to P1MAT.3. 2 B2 Port 1 Bit 2 Mask Value. om 0: P1.2 pin logic value is ignored and will not cause a port mismatch event. 1: P1.2 pin logic value is compared to P1MAT.2. B0 Port 1 Bit 1 Mask Value. 0: P1.1 pin logic value is ignored and will not cause a port mismatch event. 1: P1.1 pin logic value is compared to P1MAT.1. Port 1 Bit 0 Mask Value. 0: P1.0 pin logic value is ignored and will not cause a port mismatch event. 1: P1.0 pin logic value is compared to P1MAT.0. N ot R 0 B1 ec 1 294 Rev 1.1 Register 26.11. P1MAT: Port 1 Match 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xF5 Name 7 B7 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.14. P1MAT Register Bit Descriptions 1 es ig ns Bit Port 1 Bit 7 Match Value. 0: P1.7 pin logic value is compared with logic LOW. 1: P1.7 pin logic value is compared with logic HIGH. 6 B6 Port 1 Bit 6 Match Value. 5 B5 Port 1 Bit 5 Match Value. fo r 0: P1.6 pin logic value is compared with logic LOW. 1: P1.6 pin logic value is compared with logic HIGH. 4 B4 m en de d 0: P1.5 pin logic value is compared with logic LOW. 1: P1.5 pin logic value is compared with logic HIGH. Port 1 Bit 4 Match Value. 0: P1.4 pin logic value is compared with logic LOW. 1: P1.4 pin logic value is compared with logic HIGH. 3 B3 Port 1 Bit 3 Match Value. 0: P1.3 pin logic value is compared with logic LOW. 1: P1.3 pin logic value is compared with logic HIGH. 2 B2 Port 1 Bit 2 Match Value. om 0: P1.2 pin logic value is compared with logic LOW. 1: P1.2 pin logic value is compared with logic HIGH. B0 Port 1 Bit 1 Match Value. 0: P1.1 pin logic value is compared with logic LOW. 1: P1.1 pin logic value is compared with logic HIGH. Port 1 Bit 0 Match Value. 0: P1.0 pin logic value is compared with logic LOW. 1: P1.0 pin logic value is compared with logic HIGH. N ot R 0 B1 ec 1 Rev 1.1 295 Register 26.12. P1: Port 1 Pin Latch 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = ALL; SFR Address: 0x90 (bit-addressable) Table 26.15. P1 Register Bit Descriptions Name 7 B7 Function 0 B1 B0 RW RW 1 1 N ew Bit 1 es ig ns 7 D Bit Port 1 Bit 7 Latch. 0: P1.7 is low. Set P1.7 to drive low. 1: P1.7 is high. Set P1.7 to drive or float high. 6 B6 Port 1 Bit 6 Latch. 5 B5 Port 1 Bit 5 Latch. fo r 0: P1.6 is low. Set P1.6 to drive low. 1: P1.6 is high. Set P1.6 to drive or float high. 4 B4 m en de d 0: P1.5 is low. Set P1.5 to drive low. 1: P1.5 is high. Set P1.5 to drive or float high. Port 1 Bit 4 Latch. 0: P1.4 is low. Set P1.4 to drive low. 1: P1.4 is high. Set P1.4 to drive or float high. 3 B3 Port 1 Bit 3 Latch. 0: P1.3 is low. Set P1.3 to drive low. 1: P1.3 is high. Set P1.3 to drive or float high. 2 B2 Port 1 Bit 2 Latch. om 0: P1.2 is low. Set P1.2 to drive low. 1: P1.2 is high. Set P1.2 to drive or float high. B0 Port 1 Bit 1 Latch. 0: P1.1 is low. Set P1.1 to drive low. 1: P1.1 is high. Set P1.1 to drive or float high. Port 1 Bit 0 Latch. 0: P1.0 is low. Set P1.0 to drive low. 1: P1.0 is high. Set P1.0 to drive or float high. N ot R 0 B1 ec 1 Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. 296 Rev 1.1 Register 26.13. P1MDIN: Port 1 Input Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xED Name 7 B7 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.16. P1MDIN Register Bit Descriptions 1 es ig ns Bit Port 1 Bit 7 Input Mode. 0: P1.7 pin is configured for analog mode. 1: P1.7 pin is configured for digital mode. 6 B6 Port 1 Bit 6 Input Mode. 5 B5 Port 1 Bit 5 Input Mode. fo r 0: P1.6 pin is configured for analog mode. 1: P1.6 pin is configured for digital mode. 4 B4 m en de d 0: P1.5 pin is configured for analog mode. 1: P1.5 pin is configured for digital mode. Port 1 Bit 4 Input Mode. 0: P1.4 pin is configured for analog mode. 1: P1.4 pin is configured for digital mode. 3 B3 Port 1 Bit 3 Input Mode. 0: P1.3 pin is configured for analog mode. 1: P1.3 pin is configured for digital mode. 2 B2 Port 1 Bit 2 Input Mode. om 0: P1.2 pin is configured for analog mode. 1: P1.2 pin is configured for digital mode. B0 Port 1 Bit 1 Input Mode. 0: P1.1 pin is configured for analog mode. 1: P1.1 pin is configured for digital mode. Port 1 Bit 0 Input Mode. 0: P1.0 pin is configured for analog mode. 1: P1.0 pin is configured for digital mode. N ot R 0 B1 ec 1 Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. Rev 1.1 297 Register 26.14. P1MDOUT: Port 1 Output Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xDC Name 7 B7 Function N ew Bit Port 1 Bit 7 Output Mode. 0: P1.7 output is open-drain. 1: P1.7 output is push-pull. B6 Port 1 Bit 6 Output Mode. 0: P1.6 output is open-drain. 1: P1.6 output is push-pull. 5 B5 Port 1 Bit 5 Output Mode. 4 B4 m en de d 0: P1.5 output is open-drain. 1: P1.5 output is push-pull. fo r 6 Port 1 Bit 4 Output Mode. 0: P1.4 output is open-drain. 1: P1.4 output is push-pull. 3 B3 Port 1 Bit 3 Output Mode. 0: P1.3 output is open-drain. 1: P1.3 output is push-pull. 2 B2 Port 1 Bit 2 Output Mode. om 0: P1.2 output is open-drain. 1: P1.2 output is push-pull. B0 Port 1 Bit 1 Output Mode. 0: P1.1 output is open-drain. 1: P1.1 output is push-pull. Port 1 Bit 0 Output Mode. 0: P1.0 output is open-drain. 1: P1.0 output is push-pull. N ot R 0 B1 ec 1 298 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.17. P1MDOUT Register Bit Descriptions 1 es ig ns Bit Register 26.15. P1SKIP: Port 1 Skip 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xC6 Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.18. P1SKIP Register Bit Descriptions 1 es ig ns Bit Port 1 Bit 7 Skip. 0: P1.7 pin is not skipped by the crossbar. 1: P1.7 pin is skipped by the crossbar. 6 B6 Port 1 Bit 6 Skip. 5 B5 Port 1 Bit 5 Skip. fo r 0: P1.6 pin is not skipped by the crossbar. 1: P1.6 pin is skipped by the crossbar. 4 B4 m en de d 0: P1.5 pin is not skipped by the crossbar. 1: P1.5 pin is skipped by the crossbar. Port 1 Bit 4 Skip. 0: P1.4 pin is not skipped by the crossbar. 1: P1.4 pin is skipped by the crossbar. 3 B3 Port 1 Bit 3 Skip. 0: P1.3 pin is not skipped by the crossbar. 1: P1.3 pin is skipped by the crossbar. 2 B2 Port 1 Bit 2 Skip. om 0: P1.2 pin is not skipped by the crossbar. 1: P1.2 pin is skipped by the crossbar. B0 Port 1 Bit 1 Skip. 0: P1.1 pin is not skipped by the crossbar. 1: P1.1 pin is skipped by the crossbar. Port 1 Bit 0 Skip. 0: P1.0 pin is not skipped by the crossbar. 1: P1.0 pin is skipped by the crossbar. N ot R 0 B1 ec 1 Rev 1.1 299 Register 26.16. P1DRV: Port 1 Drive Strength 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x9A Name 7 B7 Function N ew Bit Port 1 Bit 7 Drive Strength. 0: P1.7 output has low output drive strength. 1: P1.7 output has high output drive strength. 6 B6 Port 1 Bit 6 Drive Strength. 5 B5 Port 1 Bit 5 Drive Strength. fo r 0: P1.6 output has low output drive strength. 1: P1.6 output has high output drive strength. 4 B4 m en de d 0: P1.5 output has low output drive strength. 1: P1.5 output has high output drive strength. Port 1 Bit 4 Drive Strength. 0: P1.4 output has low output drive strength. 1: P1.4 output has high output drive strength. 3 B3 Port 1 Bit 3 Drive Strength. 0: P1.3 output has low output drive strength. 1: P1.3 output has high output drive strength. 2 B2 Port 1 Bit 2 Drive Strength. om 0: P1.2 output has low output drive strength. 1: P1.2 output has high output drive strength. B0 Port 1 Bit 1 Drive Strength. 0: P1.1 output has low output drive strength. 1: P1.1 output has high output drive strength. Port 1 Bit 0 Drive Strength. 0: P1.0 output has low output drive strength. 1: P1.0 output has high output drive strength. N ot R 0 B1 ec 1 300 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.19. P1DRV Register Bit Descriptions 1 es ig ns Bit Register 26.17. P2MASK: Port 2 Mask 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x84 Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.20. P2MASK Register Bit Descriptions 1 es ig ns Bit Port 2 Bit 7 Mask Value. 0: P2.7 pin logic value is ignored and will not cause a port mismatch event. 1: P2.7 pin logic value is compared to P2MAT.7. 6 B6 Port 2 Bit 6 Mask Value. 5 B5 Port 2 Bit 5 Mask Value. fo r 0: P2.6 pin logic value is ignored and will not cause a port mismatch event. 1: P2.6 pin logic value is compared to P2MAT.6. 4 B4 m en de d 0: P2.5 pin logic value is ignored and will not cause a port mismatch event. 1: P2.5 pin logic value is compared to P2MAT.5. Port 2 Bit 4 Mask Value. 0: P2.4 pin logic value is ignored and will not cause a port mismatch event. 1: P2.4 pin logic value is compared to P2MAT.4. 3 B3 Port 2 Bit 3 Mask Value. 0: P2.3 pin logic value is ignored and will not cause a port mismatch event. 1: P2.3 pin logic value is compared to P2MAT.3. 2 B2 Port 2 Bit 2 Mask Value. om 0: P2.2 pin logic value is ignored and will not cause a port mismatch event. 1: P2.2 pin logic value is compared to P2MAT.2. B0 Port 2 Bit 1 Mask Value. 0: P2.1 pin logic value is ignored and will not cause a port mismatch event. 1: P2.1 pin logic value is compared to P2MAT.1. Port 2 Bit 0 Mask Value. 0: P2.0 pin logic value is ignored and will not cause a port mismatch event. 1: P2.0 pin logic value is compared to P2MAT.0. N ot R 0 B1 ec 1 Rev 1.1 301 Register 26.18. P2MAT: Port 2 Match 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0x85 Name 7 B7 Function N ew Bit Port 2 Bit 7 Match Value. 0: P2.7 pin logic value is compared with logic LOW. 1: P2.7 pin logic value is compared with logic HIGH. 6 B6 Port 2 Bit 6 Match Value. 5 B5 Port 2 Bit 5 Match Value. fo r 0: P2.6 pin logic value is compared with logic LOW. 1: P2.6 pin logic value is compared with logic HIGH. 4 B4 m en de d 0: P2.5 pin logic value is compared with logic LOW. 1: P2.5 pin logic value is compared with logic HIGH. Port 2 Bit 4 Match Value. 0: P2.4 pin logic value is compared with logic LOW. 1: P2.4 pin logic value is compared with logic HIGH. 3 B3 Port 2 Bit 3 Match Value. 0: P2.3 pin logic value is compared with logic LOW. 1: P2.3 pin logic value is compared with logic HIGH. 2 B2 Port 2 Bit 2 Match Value. om 0: P2.2 pin logic value is compared with logic LOW. 1: P2.2 pin logic value is compared with logic HIGH. B0 Port 2 Bit 1 Match Value. 0: P2.1 pin logic value is compared with logic LOW. 1: P2.1 pin logic value is compared with logic HIGH. Port 2 Bit 0 Match Value. 0: P2.0 pin logic value is compared with logic LOW. 1: P2.0 pin logic value is compared with logic HIGH. N ot R 0 B1 ec 1 302 Rev 1.1 0 B1 B0 RW RW 1 1 D Table 26.21. P2MAT Register Bit Descriptions 1 es ig ns Bit Register 26.19. P2: Port 2 Pin Latch 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = ALL; SFR Address: 0xA0 (bit-addressable) Table 26.22. P2 Register Bit Descriptions Name 7 B7 Function 0 B1 B0 RW RW 1 1 N ew Bit 1 es ig ns 7 D Bit Port 2 Bit 7 Latch. 0: P2.7 is low. Set P2.7 to drive low. 1: P2.7 is high. Set P2.7 to drive or float high. 6 B6 Port 2 Bit 6 Latch. 5 B5 Port 2 Bit 5 Latch. fo r 0: P2.6 is low. Set P2.6 to drive low. 1: P2.6 is high. Set P2.6 to drive or float high. 4 B4 m en de d 0: P2.5 is low. Set P2.5 to drive low. 1: P2.5 is high. Set P2.5 to drive or float high. Port 2 Bit 4 Latch. 0: P2.4 is low. Set P2.4 to drive low. 1: P2.4 is high. Set P2.4 to drive or float high. 3 B3 Port 2 Bit 3 Latch. 0: P2.3 is low. Set P2.3 to drive low. 1: P2.3 is high. Set P2.3 to drive or float high. 2 B2 Port 2 Bit 2 Latch. om 0: P2.2 is low. Set P2.2 to drive low. 1: P2.2 is high. Set P2.2 to drive or float high. B0 Port 2 Bit 1 Latch. 0: P2.1 is low. Set P2.1 to drive low. 1: P2.1 is high. Set P2.1 to drive or float high. Port 2 Bit 0 Latch. 0: P2.0 is low. Set P2.0 to drive low. 1: P2.0 is high. Set P2.0 to drive or float high. N ot R 0 B1 ec 1 Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. Rev 1.1 303 Register 26.20. P2MDIN: Port 2 Input Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xEE Name 7 B7 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.23. P2MDIN Register Bit Descriptions 1 es ig ns Bit Port 2 Bit 7 Input Mode. 0: P2.7 pin is configured for analog mode. 1: P2.7 pin is configured for digital mode. 6 B6 Port 2 Bit 6 Input Mode. 5 B5 Port 2 Bit 5 Input Mode. fo r 0: P2.6 pin is configured for analog mode. 1: P2.6 pin is configured for digital mode. 4 B4 m en de d 0: P2.5 pin is configured for analog mode. 1: P2.5 pin is configured for digital mode. Port 2 Bit 4 Input Mode. 0: P2.4 pin is configured for analog mode. 1: P2.4 pin is configured for digital mode. 3 B3 Port 2 Bit 3 Input Mode. 0: P2.3 pin is configured for analog mode. 1: P2.3 pin is configured for digital mode. 2 B2 Port 2 Bit 2 Input Mode. om 0: P2.2 pin is configured for analog mode. 1: P2.2 pin is configured for digital mode. B0 Port 2 Bit 1 Input Mode. 0: P2.1 pin is configured for analog mode. 1: P2.1 pin is configured for digital mode. Port 2 Bit 0 Input Mode. 0: P2.0 pin is configured for analog mode. 1: P2.0 pin is configured for digital mode. N ot R 0 B1 ec 1 Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 304 Rev 1.1 Register 26.21. P2MDOUT: Port 2 Output Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xDD Name 7 B7 Function Port 2 Bit 7 Output Mode. 0: P2.7 output is open-drain. 1: P2.7 output is push-pull. B6 Port 2 Bit 6 Output Mode. 0: P2.6 output is open-drain. 1: P2.6 output is push-pull. 5 B5 Port 2 Bit 5 Output Mode. 4 B4 RW RW 0 0 m en de d 0: P2.5 output is open-drain. 1: P2.5 output is push-pull. B0 fo r 6 B1 N ew Bit 0 D Table 26.24. P2MDOUT Register Bit Descriptions 1 es ig ns Bit Port 2 Bit 4 Output Mode. 0: P2.4 output is open-drain. 1: P2.4 output is push-pull. 3 B3 Port 2 Bit 3 Output Mode. 0: P2.3 output is open-drain. 1: P2.3 output is push-pull. 2 B2 Port 2 Bit 2 Output Mode. om 0: P2.2 output is open-drain. 1: P2.2 output is push-pull. B0 Port 2 Bit 1 Output Mode. 0: P2.1 output is open-drain. 1: P2.1 output is push-pull. Port 2 Bit 0 Output Mode. 0: P2.0 output is open-drain. 1: P2.0 output is push-pull. N ot R 0 B1 ec 1 Rev 1.1 305 Register 26.22. P2SKIP: Port 2 Skip 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xC7 Name 7 B7 Function N ew Bit Port 2 Bit 7 Skip. 0: P2.7 pin is not skipped by the crossbar. 1: P2.7 pin is skipped by the crossbar. 6 B6 Port 2 Bit 6 Skip. 5 B5 Port 2 Bit 5 Skip. fo r 0: P2.6 pin is not skipped by the crossbar. 1: P2.6 pin is skipped by the crossbar. 4 B4 m en de d 0: P2.5 pin is not skipped by the crossbar. 1: P2.5 pin is skipped by the crossbar. Port 2 Bit 4 Skip. 0: P2.4 pin is not skipped by the crossbar. 1: P2.4 pin is skipped by the crossbar. 3 B3 Port 2 Bit 3 Skip. 0: P2.3 pin is not skipped by the crossbar. 1: P2.3 pin is skipped by the crossbar. 2 B2 Port 2 Bit 2 Skip. om 0: P2.2 pin is not skipped by the crossbar. 1: P2.2 pin is skipped by the crossbar. B0 Port 2 Bit 1 Skip. 0: P2.1 pin is not skipped by the crossbar. 1: P2.1 pin is skipped by the crossbar. Port 2 Bit 0 Skip. 0: P2.0 pin is not skipped by the crossbar. 1: P2.0 pin is skipped by the crossbar. N ot R 0 B1 ec 1 306 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.25. P2SKIP Register Bit Descriptions 1 es ig ns Bit Register 26.23. P2DRV: Port 2 Drive Strength 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x9B Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.26. P2DRV Register Bit Descriptions 1 es ig ns Bit Port 2 Bit 7 Drive Strength. 0: P2.7 output has low output drive strength. 1: P2.7 output has high output drive strength. 6 B6 Port 2 Bit 6 Drive Strength. 5 B5 Port 2 Bit 5 Drive Strength. fo r 0: P2.6 output has low output drive strength. 1: P2.6 output has high output drive strength. 4 B4 m en de d 0: P2.5 output has low output drive strength. 1: P2.5 output has high output drive strength. Port 2 Bit 4 Drive Strength. 0: P2.4 output has low output drive strength. 1: P2.4 output has high output drive strength. 3 B3 Port 2 Bit 3 Drive Strength. 0: P2.3 output has low output drive strength. 1: P2.3 output has high output drive strength. 2 B2 Port 2 Bit 2 Drive Strength. om 0: P2.2 output has low output drive strength. 1: P2.2 output has high output drive strength. B0 Port 2 Bit 1 Drive Strength. 0: P2.1 output has low output drive strength. 1: P2.1 output has high output drive strength. Port 2 Bit 0 Drive Strength. 0: P2.0 output has low output drive strength. 1: P2.0 output has high output drive strength. N ot R 0 B1 ec 1 Rev 1.1 307 Register 26.24. P3: Port 3 Pin Latch 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0x0; SFR Address: 0xE1 Table 26.27. P3 Register Bit Descriptions Name 7 B7 Function 0 B1 B0 RW RW 1 1 N ew Bit 1 es ig ns 7 D Bit Port 3 Bit 7 Latch. 0: P3.7 is low. Set P3.7 to drive low. 1: P3.7 is high. Set P3.7 to drive or float high. 6 B6 Port 3 Bit 6 Latch. 5 B5 Port 3 Bit 5 Latch. fo r 0: P3.6 is low. Set P3.6 to drive low. 1: P3.6 is high. Set P3.6 to drive or float high. 4 B4 m en de d 0: P3.5 is low. Set P3.5 to drive low. 1: P3.5 is high. Set P3.5 to drive or float high. Port 3 Bit 4 Latch. 0: P3.4 is low. Set P3.4 to drive low. 1: P3.4 is high. Set P3.4 to drive or float high. 3 B3 Port 3 Bit 3 Latch. 0: P3.3 is low. Set P3.3 to drive low. 1: P3.3 is high. Set P3.3 to drive or float high. 2 B2 Port 3 Bit 2 Latch. om 0: P3.2 is low. Set P3.2 to drive low. 1: P3.2 is high. Set P3.2 to drive or float high. B0 Port 3 Bit 1 Latch. 0: P3.1 is low. Set P3.1 to drive low. 1: P3.1 is high. Set P3.1 to drive or float high. Port 3 Bit 0 Latch. 0: P3.0 is low. Set P3.0 to drive low. 1: P3.0 is high. Set P3.0 to drive or float high. N ot R 0 B1 ec 1 Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. 308 Rev 1.1 Register 26.25. P3MDIN: Port 3 Input Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xEF Name 7 B7 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.28. P3MDIN Register Bit Descriptions 1 es ig ns Bit Port 3 Bit 7 Input Mode. 0: P3.7 pin is configured for analog mode. 1: P3.7 pin is configured for digital mode. 6 B6 Port 3 Bit 6 Input Mode. 5 B5 Port 3 Bit 5 Input Mode. fo r 0: P3.6 pin is configured for analog mode. 1: P3.6 pin is configured for digital mode. 4 B4 m en de d 0: P3.5 pin is configured for analog mode. 1: P3.5 pin is configured for digital mode. Port 3 Bit 4 Input Mode. 0: P3.4 pin is configured for analog mode. 1: P3.4 pin is configured for digital mode. 3 B3 Port 3 Bit 3 Input Mode. 0: P3.3 pin is configured for analog mode. 1: P3.3 pin is configured for digital mode. 2 B2 Port 3 Bit 2 Input Mode. om 0: P3.2 pin is configured for analog mode. 1: P3.2 pin is configured for digital mode. B0 Port 3 Bit 1 Input Mode. 0: P3.1 pin is configured for analog mode. 1: P3.1 pin is configured for digital mode. Port 3 Bit 0 Input Mode. 0: P3.0 pin is configured for analog mode. 1: P3.0 pin is configured for digital mode. N ot R 0 B1 ec 1 Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. Rev 1.1 309 Register 26.26. P3MDOUT: Port 3 Output Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xDF Name 7 B7 Function N ew Bit Port 3 Bit 7 Output Mode. 0: P3.7 output is open-drain. 1: P3.7 output is push-pull. B6 Port 3 Bit 6 Output Mode. 0: P3.6 output is open-drain. 1: P3.6 output is push-pull. 5 B5 Port 3 Bit 5 Output Mode. 4 B4 m en de d 0: P3.5 output is open-drain. 1: P3.5 output is push-pull. fo r 6 Port 3 Bit 4 Output Mode. 0: P3.4 output is open-drain. 1: P3.4 output is push-pull. 3 B3 Port 3 Bit 3 Output Mode. 0: P3.3 output is open-drain. 1: P3.3 output is push-pull. 2 B2 Port 3 Bit 2 Output Mode. om 0: P3.2 output is open-drain. 1: P3.2 output is push-pull. B0 Port 3 Bit 1 Output Mode. 0: P3.1 output is open-drain. 1: P3.1 output is push-pull. Port 3 Bit 0 Output Mode. 0: P3.0 output is open-drain. 1: P3.0 output is push-pull. N ot R 0 B1 ec 1 310 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.29. P3MDOUT Register Bit Descriptions 1 es ig ns Bit Register 26.27. P3DRV: Port 3 Drive Strength 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x9C Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.30. P3DRV Register Bit Descriptions 1 es ig ns Bit Port 3 Bit 7 Drive Strength. 0: P3.7 output has low output drive strength. 1: P3.7 output has high output drive strength. 6 B6 Port 3 Bit 6 Drive Strength. 5 B5 Port 3 Bit 5 Drive Strength. fo r 0: P3.6 output has low output drive strength. 1: P3.6 output has high output drive strength. 4 B4 m en de d 0: P3.5 output has low output drive strength. 1: P3.5 output has high output drive strength. Port 3 Bit 4 Drive Strength. 0: P3.4 output has low output drive strength. 1: P3.4 output has high output drive strength. 3 B3 Port 3 Bit 3 Drive Strength. 0: P3.3 output has low output drive strength. 1: P3.3 output has high output drive strength. 2 B2 Port 3 Bit 2 Drive Strength. om 0: P3.2 output has low output drive strength. 1: P3.2 output has high output drive strength. B0 Port 3 Bit 1 Drive Strength. 0: P3.1 output has low output drive strength. 1: P3.1 output has high output drive strength. Port 3 Bit 0 Drive Strength. 0: P3.0 output has low output drive strength. 1: P3.0 output has high output drive strength. N ot R 0 B1 ec 1 Rev 1.1 311 Register 26.28. P4: Port 4 Pin Latch 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0x0; SFR Address: 0xE2 Table 26.31. P4 Register Bit Descriptions Name 7 B7 Function 0 B1 B0 RW RW 1 1 N ew Bit 1 es ig ns 7 D Bit Port 4 Bit 7 Latch. 0: P4.7 is low. Set P4.7 to drive low. 1: P4.7 is high. Set P4.7 to drive or float high. 6 B6 Port 4 Bit 6 Latch. 5 B5 Port 4 Bit 5 Latch. fo r 0: P4.6 is low. Set P4.6 to drive low. 1: P4.6 is high. Set P4.6 to drive or float high. 4 B4 m en de d 0: P4.5 is low. Set P4.5 to drive low. 1: P4.5 is high. Set P4.5 to drive or float high. Port 4 Bit 4 Latch. 0: P4.4 is low. Set P4.4 to drive low. 1: P4.4 is high. Set P4.4 to drive or float high. 3 B3 Port 4 Bit 3 Latch. 0: P4.3 is low. Set P4.3 to drive low. 1: P4.3 is high. Set P4.3 to drive or float high. 2 B2 Port 4 Bit 2 Latch. om 0: P4.2 is low. Set P4.2 to drive low. 1: P4.2 is high. Set P4.2 to drive or float high. B0 Port 4 Bit 1 Latch. 0: P4.1 is low. Set P4.1 to drive low. 1: P4.1 is high. Set P4.1 to drive or float high. Port 4 Bit 0 Latch. 0: P4.0 is low. Set P4.0 to drive low. 1: P4.0 is high. Set P4.0 to drive or float high. N ot R 0 B1 ec 1 Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. 312 Rev 1.1 Register 26.29. P4MDIN: Port 4 Input Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 1 1 1 1 1 1 SFR Page = 0xF; SFR Address: 0xF1 Name 7 B7 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.32. P4MDIN Register Bit Descriptions 1 es ig ns Bit Port 4 Bit 7 Input Mode. 0: P4.7 pin is configured for analog mode. 1: P4.7 pin is configured for digital mode. 6 B6 Port 4 Bit 6 Input Mode. 5 B5 Port 4 Bit 5 Input Mode. fo r 0: P4.6 pin is configured for analog mode. 1: P4.6 pin is configured for digital mode. 4 B4 m en de d 0: P4.5 pin is configured for analog mode. 1: P4.5 pin is configured for digital mode. Port 4 Bit 4 Input Mode. 0: P4.4 pin is configured for analog mode. 1: P4.4 pin is configured for digital mode. 3 B3 Port 4 Bit 3 Input Mode. 0: P4.3 pin is configured for analog mode. 1: P4.3 pin is configured for digital mode. 2 B2 Port 4 Bit 2 Input Mode. om 0: P4.2 pin is configured for analog mode. 1: P4.2 pin is configured for digital mode. B0 Port 4 Bit 1 Input Mode. 0: P4.1 pin is configured for analog mode. 1: P4.1 pin is configured for digital mode. Port 4 Bit 0 Input Mode. 0: P4.0 pin is configured for analog mode. 1: P4.0 pin is configured for digital mode. N ot R 0 B1 ec 1 Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. Rev 1.1 313 Register 26.30. P4MDOUT: Port 4 Output Mode 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xC3 Name 7 B7 Function N ew Bit Port 4 Bit 7 Output Mode. 0: P4.7 output is open-drain. 1: P4.7 output is push-pull. B6 Port 4 Bit 6 Output Mode. 0: P4.6 output is open-drain. 1: P4.6 output is push-pull. 5 B5 Port 4 Bit 5 Output Mode. 4 B4 m en de d 0: P4.5 output is open-drain. 1: P4.5 output is push-pull. fo r 6 Port 4 Bit 4 Output Mode. 0: P4.4 output is open-drain. 1: P4.4 output is push-pull. 3 B3 Port 4 Bit 3 Output Mode. 0: P4.3 output is open-drain. 1: P4.3 output is push-pull. 2 B2 Port 4 Bit 2 Output Mode. om 0: P4.2 output is open-drain. 1: P4.2 output is push-pull. B0 Port 4 Bit 1 Output Mode. 0: P4.1 output is open-drain. 1: P4.1 output is push-pull. Port 4 Bit 0 Output Mode. 0: P4.0 output is open-drain. 1: P4.0 output is push-pull. N ot R 0 B1 ec 1 314 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.33. P4MDOUT Register Bit Descriptions 1 es ig ns Bit Register 26.31. P4DRV: Port 4 Drive Strength 7 6 5 4 3 2 Name B7 B6 B5 B4 B3 B2 Type RW RW RW RW RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xB9 Name 7 B7 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.34. P4DRV Register Bit Descriptions 1 es ig ns Bit Port 4 Bit 7 Drive Strength. 0: P4.7 output has low output drive strength. 1: P4.7 output has high output drive strength. 6 B6 Port 4 Bit 6 Drive Strength. 5 B5 Port 4 Bit 5 Drive Strength. fo r 0: P4.6 output has low output drive strength. 1: P4.6 output has high output drive strength. 4 B4 m en de d 0: P4.5 output has low output drive strength. 1: P4.5 output has high output drive strength. Port 4 Bit 4 Drive Strength. 0: P4.4 output has low output drive strength. 1: P4.4 output has high output drive strength. 3 B3 Port 4 Bit 3 Drive Strength. 0: P4.3 output has low output drive strength. 1: P4.3 output has high output drive strength. 2 B2 Port 4 Bit 2 Drive Strength. om 0: P4.2 output has low output drive strength. 1: P4.2 output has high output drive strength. B0 Port 4 Bit 1 Drive Strength. 0: P4.1 output has low output drive strength. 1: P4.1 output has high output drive strength. Port 4 Bit 0 Drive Strength. 0: P4.0 output has low output drive strength. 1: P4.0 output has high output drive strength. N ot R 0 B1 ec 1 Rev 1.1 315 Register 26.32. P5: Port 5 Pin Latch 7 6 5 4 3 2 Reserved B2 Type RW RW Reset 0 0 0 0 0 1 SFR Page = 0x0; SFR Address: 0xE3 Table 26.35. P5 Register Bit Descriptions Name 7:3 Reserved 2 B2 Function B1 B0 RW RW 1 1 N ew Bit 0 D Name 1 es ig ns Bit Must write reset value. Port 5 Bit 2 Latch. 0: P5.2 is low. Set P5.2 to drive low. 1: P5.2 is high. Set P5.2 to drive or float high. B1 Port 5 Bit 1 Latch. fo r 1 0: P5.1 is low. Set P5.1 to drive low. 1: P5.1 is high. Set P5.1 to drive or float high. 0 B0 Port 5 Bit 0 Latch. m en de d 0: P5.0 is low. Set P5.0 to drive low. 1: P5.0 is high. Set P5.0 to drive or float high. N ot R ec om Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. 316 Rev 1.1 Register 26.33. P5MDIN: Port 5 Input Mode 7 6 5 4 3 2 Name Reserved B2 Type RW RW Reset 0 0 0 0 0 1 SFR Page = 0xF; SFR Address: 0xF2 Name 7:3 Reserved 2 B2 Function B1 B0 RW RW 1 1 N ew Bit 0 D Table 26.36. P5MDIN Register Bit Descriptions 1 es ig ns Bit Must write reset value. Port 5 Bit 2 Input Mode. 0: P5.2 pin is configured for analog mode. 1: P5.2 pin is configured for digital mode. B1 Port 5 Bit 1 Input Mode. fo r 1 0: P5.1 pin is configured for analog mode. 1: P5.1 pin is configured for digital mode. 0 B0 Port 5 Bit 0 Input Mode. m en de d 0: P5.0 pin is configured for analog mode. 1: P5.0 pin is configured for digital mode. N ot R ec om Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. Rev 1.1 317 Register 26.34. P5MDOUT: Port 5 Output Mode 7 6 5 4 3 2 Name Reserved B2 Type RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0xFF Name 7:3 Reserved 2 B2 Function N ew Bit Must write reset value. Port 5 Bit 2 Output Mode. 0: P5.2 output is open-drain. 1: P5.2 output is push-pull. B1 Port 5 Bit 1 Output Mode. 0: P5.1 output is open-drain. 1: P5.1 output is push-pull. 0 B0 Port 5 Bit 0 Output Mode. fo r 1 N ot R ec om m en de d 0: P5.0 output is open-drain. 1: P5.0 output is push-pull. 318 Rev 1.1 0 B1 B0 RW RW 0 0 D Table 26.37. P5MDOUT Register Bit Descriptions 1 es ig ns Bit Register 26.35. P5DRV: Port 5 Drive Strength 7 6 5 4 3 2 Name Reserved B2 Type RW RW Reset 0 0 0 0 0 0 SFR Page = 0xF; SFR Address: 0x9D Name 7:3 Reserved 2 B2 Function B1 B0 RW RW 0 0 N ew Bit 0 D Table 26.38. P5DRV Register Bit Descriptions 1 es ig ns Bit Must write reset value. Port 5 Bit 2 Drive Strength. 0: P5.2 output has low output drive strength. 1: P5.2 output has high output drive strength. B1 Port 5 Bit 1 Drive Strength. fo r 1 0: P5.1 output has low output drive strength. 1: P5.1 output has high output drive strength. 0 B0 Port 5 Bit 0 Drive Strength. N ot R ec om m en de d 0: P5.0 output has low output drive strength. 1: P5.0 output has high output drive strength. Rev 1.1 319 Register 26.36. P6: Port 6 Pin Latch 7 6 5 4 Name Reserved Type RW Reset 0 0 0 3 0 0 2 0 Name 7:2 Reserved 1 B1 Function B1 B0 RW RW 1 1 N ew Bit 0 D SFR Page = 0x0; SFR Address: 0xE4 Table 26.39. P6 Register Bit Descriptions 1 es ig ns Bit Must write reset value. Port 6 Bit 1 Latch. 0: P6.1 is low. Set P6.1 to drive low. 1: P6.1 is high. Set P6.1 to drive or float high. B0 Port 6 Bit 0 Latch. fo r 0 0: P6.0 is low. Set P6.0 to drive low. 1: P6.0 is high. Set P6.0 to drive or float high. m en de d Notes: 1. Writing this register sets the port latch logic value for the associated I/O pins configured as digital I/O. 2. Reading this register returns the logic value at the pin, regardless if it is configured as output or input. Register 26.37. P6MDIN: Port 6 Input Mode Bit 7 Type Reset om Name 6 0 0 5 4 1 0 Reserved B1 B0 RW RW RW 1 1 0 3 0 0 2 0 ec SFR Page = 0xF; SFR Address: 0x97 Name 7:2 Reserved N ot R Bit 1 B1 Table 26.40. P6MDIN Register Bit Descriptions Function Must write reset value. Port 6 Bit 1 Input Mode. 0: P6.1 pin is configured for analog mode. 1: P6.1 pin is configured for digital mode. Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 320 Rev 1.1 Table 26.40. P6MDIN Register Bit Descriptions Name 0 B0 Function Port 6 Bit 0 Input Mode. 0: P6.0 pin is configured for analog mode. 1: P6.0 pin is configured for digital mode. es ig ns Bit N ot R ec om m en de d fo r N ew D Note: Port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. Rev 1.1 321 27. Reset Sources and Supply Monitor Reset circuitry allows the controller to be easily placed in a predefined default condition. Upon entering this reset state, the following events occur: CIP-51 es ig ns halts program execution Function Registers (SFRs) are initialized to their defined reset values External port pins are placed in a known state Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered. Special N ew D The Port I/O latches are reset to 0xFF (all logic ones) in open-drain, low-drive mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device exits the reset state. Note that during a power-on event, there may be a short delay before the POR circuitry fires and the RST pin is driven low. During that time, the RST pin will be weakly pulled to the VDD supply pin. On exit from the reset state, the program counter (PC) is reset, the Watchdog Timer is enabled and the system clock defaults to the internal oscillator. Program execution begins at location 0x0000. RST Supply Monitor or Power-up m en de d Missing Clock Detector fo r Reset Sources Watchdog Timer Software Reset system reset SmaRTClock Alarm/Error Figure 27.1. Reset Sources N ot R ec om Flash Error Rev 1.1 322 27.1. Power-On Reset es ig ns During power-up, the POR circuit will fire. When POR fires, the device is held in a reset state and the RST pin is driven low until VDD settles above VRST. Two delays are present during the supply ramp time. First, a delay will occur before the POR circuitry fires and pulls the RST pin low. A second delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 27.2. plots the power-on reset timing. For ramp times less than 1 ms, the power-on reset time (TPOR) is typically less than 0.3 ms. Additionally, the power supply must reach VRST before the POR circuit will release the device from reset. m en de d fo r VD D N ew volts D On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a power-on reset. Logic HIGH RST TPOR Power-On Reset Figure 27.2. Power-on Reset Timing N ot R ec om Logic LOW 323 Rev 1.1 t 27.2. Power-Fail Reset / Supply Monitor C8051F97x devices have a supply monitor that is enabled and selected as a reset source after each power-on or power fail reset. es ig ns When enabled and selected as a reset source, any power down transition or power irregularity that causes VDD to drop below VRST will cause the RST pin to be driven low and the CIP-51 will be held in a reset state (see Figure 27.3). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD supply monitor is enabled and selected as a reset source. The enable state of the VDD supply monitor and its selection as a reset source is only altered by power-on and power-fail resets. For example, if the VDD supply monitor is deselected as a reset source and disabled by software, then a software reset is performed, the VDD supply monitor will remain disabled and deselected after the reset. N ew D In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable life if the device is placed in Sleep Mode prior to a power-fail reset occurring. When the device is in Sleep Mode, the powerfail reset is automatically disabled and the contents of RAM are preserved as long as VDD does not fall below VPOR. A large capacitor can be used to hold the power supply voltage above VPOR while the user is replacing the battery. Upon waking from Sleep mode, the enable and reset source select state of the VDD supply monitor are restored to the value last set by the user. To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when the VDD supply falls below the VWARN threshold. The VDDOK bit can be configured to generate an interrupt. See Section “13. Interrupts” on page 79 for more details. volts m en de d fo r Important Note: To protect the integrity of Flash contents, the VDD supply monitor must be enabled and selected as a reset source if software contains routines which erase or write Flash memory. If the VDD supply monitor is not enabled, any erase or write performed on Flash memory will cause a Flash Error device reset. memory. If the VDD supply monitor is not enabled, any erase or write performed on flash memory will be ignored. VDD N ot R ec om Reset Threshold (VRST) t RST VDD Monitor Reset Figure 27.3. VDD Supply Monitor Threshold Rev 1.1 324 27.3. Enabling the VDD Monitor 1. Enable the VDD supply monitor (VMONEN = 1). 2. Wait for the VDD supply monitor to stabilize (optional). 3. Enable the VDD monitor as a reset source in the RSTSRC register. D 27.4. External Reset es ig ns The VDD supply monitor is enabled by default. However, in systems which disable the supply monitor, it must be enabled before selecting it as a reset source. Selecting the VDD supply monitor as a reset source before it has stabilized may generate a system reset. In systems where this reset would be undesirable, a delay should be introduced between enabling the VDD supply monitor and selecting it as a reset source. No delay should be introduced in systems where software contains routines that erase or write flash memory. The procedure for enabling the VDD supply monitor and selecting it as a reset source is: N ew The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. The PINRSF flag is set on exit from an external reset. 27.5. Missing Clock Detector Reset 27.6. PCA Watchdog Timer Reset fo r The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock remains high or low for more than the MCD time window, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaffected by this reset. m en de d The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in the PCA watchdog timer section. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit is set to ‘1’. The state of the RST pin is unaffected by this reset. 27.7. Flash Error Reset If a flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: A flash write or erase is attempted above user code space. flash read is attempted above user code space. A program read is attempted above user code space (i.e. a branch instruction to the reserved area). A flash read, write or erase attempt is restricted due to a flash security setting. The FERROR bit is set following a flash error reset. The state of the RST pin is unaffected by this reset. ec om A 27.8. SmaRTClock Reset N ot R The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRTClock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn registers. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag (RSTSRC.7). The SmaRTClock reset remains functional even when the device is in the low power Suspend or Sleep mode. The state of the RST pin is unaffected by this reset. 27.9. Software Reset Software may force a reset by writing a 1 to the SWRSF bit. The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset. 325 Rev 1.1 27.10. Reset Sources Control Registers Bit 7 6 5 4 3 2 Name RTC0RE FERROR Reserved SWRSF WDTRSF MCDRSF Type RW RW RW RW RW RW Reset X X X X X X 1 0 PORSF PINRSF RW RW X X D SFR Page = 0x0; SFR Address: 0xEF es ig ns Register 27.1. RSTSRC: Reset Source Bit Name 7 RTC0RE N ew Table 27.1. RSTSRC Register Bit Descriptions Function RTC Reset Enable and Flag. Read: This bit reads 1 if a RTC alarm or oscillator fail caused the last reset. Write: Writing a 1 to this bit enables the RTC as a reset source. FERROR Flash Error Reset Flag. fo r 6 This read-only bit is set to '1' if a flash read/write/erase error caused the last reset. Reserved 4 SWRSF Must write reset value. Software Reset Force and Flag. m en de d 5 Read: This bit reads 1 if last reset was caused by a write to SWRSF. Write: Writing a 1 to this bit forces a system reset. 3 WDTRSF Watchdog Timer Reset Flag. This read-only bit is set to '1' if a watchdog timer overflow caused the last reset. 2 MCDRSF Missing Clock Detector Enable and Flag. om Read: This bit reads 1 if a missing clock detector timeout caused the last reset. Write: Writing a 1 to this bit enables the missing clock detector. The MCD triggers a reset if a missing clock condition is detected. 1 PORSF Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable. 0 ec Read: This bit reads 1 anytime a power-on or supply monitor reset has occurred. Write: Writing a 1 to this bit enables the supply monitor as a reset source. PINRSF HW Pin Reset Flag. This read-only bit is set to '1' if the RST pin caused the last reset. N ot R Notes: 1. Reads and writes of the RSTSRC register access different logic in the device. Reading the register always returns status information to indicate the source of the most recent reset. Writing to the register activates certain options as reset sources. It is recommended to not use any kind of read-modify-write operation on this register. 2. When the PORSF bit reads back '1' all other RSTSRC flags are indeterminate. 3. Writing '1' to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset. Rev 1.1 326 27.11. Supply Monitor Control Registers Bit 7 6 5 4 3 Name VDMEN VDDSTAT VDDOK Reserved VDDOKIE Type RW R R R RW Reset 1 X X 0 1 2 1 0 Reserved R 0 0 0 D SFR Page = 0x0; SFR Address: 0xFF es ig ns Register 27.2. VDM0CN: VDD Supply Monitor Control Bit Name 7 VDMEN N ew Table 27.2. VDM0CN Register Bit Descriptions Function VDD Supply Monitor Enable. 6 VDDSTAT VDD Supply Status. fo r This bit turns the VDD supply monitor circuit on/off. The VDD Supply Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC. 0: Disable the VDD supply monitor. 1: Enable the VDD supply monitor. 5 VDDOK m en de d This bit indicates the current power supply status. 0: VDD is at or below the VRST threshold. 1: VDD is above the VRST threshold. VDD Supply Status (Early Warning). This bit indicates the current VDD power supply status. 0: VDD is at or below the VDDWARN threshold. 1: VDD is above the VDDWARN threshold. 4 Reserved 3 VDDOKIE Must write reset value. VDD Early Warning Interrupt Enable. Reserved Must write reset value. N ot R ec 2:0 om Enables the VDD Early Warning interrupt. 0: Disable the VDD Early Warning interrupt. 1: Enable the VDD Early Warning interrupt. 327 Rev 1.1 28. Serial Peripheral Interface (SPI0) SPI0 SCK Polarity NSS Control D Master or Slave N ew Clock Rate Generator SYSCLK SCK Phase es ig ns The serial peripheral interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. NSS Bus Control fo r Shift Register SCK MISO MOSI m en de d TX Buffer RX Buffer SPI0DAT N ot R ec om Figure 28.1. SPI0 Block Diagram Rev 1.1 328 28.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 28.1.1. Master Out, Slave In (MOSI) es ig ns The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. 28.1.2. Master In, Slave Out (MISO) D The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. N ew 28.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. fo r 28.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: m en de d 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. N ot R ec om See Figure 28.2, Figure 28.3, and Figure 28.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. 329 Rev 1.1 28.2. SPI0 Master Mode Operation es ig ns A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CFG.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmitcomplete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. fo r N ew D When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire singlemaster mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CFG.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins. Figure 28.2 shows a connection diagram between two master devices and a single slave in multiple-master mode. m en de d 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 28.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. N ot R ec om 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 28.4 shows a connection diagram for a master device and a slave device in 4wire mode. Rev 1.1 330 Slave Device SCK SCK MISO MISO MOSI MOSI NSS NSS es ig ns Master Device 1 port pin D Master Device 2 NSS N ew MOSI MISO SCK port pin m en de d Master Device fo r Figure 28.2. Multiple-Master Mode Connection Diagram Slave Device SCK SCK MISO MISO MOSI MOSI om Figure 28.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Slave Device SCK SCK MISO MISO MOSI MOSI NSS NSS N ot R ec Master Device Figure 28.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 331 Rev 1.1 28.3. SPI0 Slave Mode Operation es ig ns When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer. N ew D When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 28.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 28.4. SPI0 Interrupt Sources fo r The 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and re-enabling SPI0 with the SPIEN bit. Figure 28.3 shows a connection diagram between a slave device in 3-wire slave mode and a master device. When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: m en de d All of the following bits must be cleared by software. The ec om SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN bit in SPI0CFG and SPIEN bit in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. 28.5. Serial Clock Phase and Polarity N ot R Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are shown in Figure 28.5. For slave mode, the clock and data relationships are shown in Figure 28.6 and Figure 28.7. Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs C8051 devices. Rev 1.1 332 es ig ns The SPI0 Clock Rate Register (SPI0CKR) controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. D SCK (CKPOL=0, CKPHA=0) N ew SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) fo r SCK (CKPOL=1, CKPHA=1) MSB Bit 6 Bit 5 Bit 4 m en de d MISO/MOSI NSS (Must Remain High in Multi-Master Mode) Bit 3 Bit 2 Bit 1 Bit 0 Figure 28.5. Master Mode Data/Clock Timing om SCK (CKPOL=0, CKPHA=0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R MOSI ec SCK (CKPOL=1, CKPHA=0) N ot MISO NSS (4-Wire Mode) Figure 28.6. Slave Mode Data/Clock Timing (CKPHA = 0) 333 Rev 1.1 SCK (CKPOL=1, CKPHA=1) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0 D MOSI es ig ns SCK (CKPOL=0, CKPHA=1) N ew NSS (4-Wire Mode) Figure 28.7. Slave Mode Data/Clock Timing (CKPHA = 1) 28.6. SPI Special Function Registers m en de d fo r SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. SCK* T T MCKH MCKL T MIS ec MOSI MIH om MISO T Figure 28.8. SPI Master Timing (CKPHA = 0) N ot R * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Rev 1.1 334 SCK* T MCKH es ig ns T MCKL T T MIS MIH D MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. N ew MOSI Figure 28.9. SPI Master Timing (CKPHA = 1) T fo r NSS T CKL SCK* m en de d SE T SD T CKH T SIS MOSI T ec MISO om SEZ T SIH T SOH * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. N ot R Figure 28.10. SPI Slave Timing (CKPHA = 0) 335 Rev 1.1 T SDZ NSS T T T CKL SD es ig ns SE SCK* T CKH T T SIH D SIS MOSI T SOH SEZ N ew T T SLH MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. T SDZ N ot R ec om m en de d fo r Figure 28.11. SPI Slave Timing (CKPHA = 1) Rev 1.1 336 Table 28.1. SPI Slave Timing Parameters Parameter Description Min Max Units TMCKH SCK High Time 1 x TSYSCLK TMCKL SCK Low Time 1 x TSYSCLK TMIS MISO Valid to SCK Shift Edge TMIH SCK Shift Edge to MISO Change es ig ns Master Mode Timing (See Figure 28.8 and Figure 28.9) — ns — ns 1 x TSYSCLK + 20 — ns 0 — ns D Slave Mode Timing (See Figure 28.10 and Figure 28.11) NSS Falling to First SCK Edge 2 x TSYSCLK — ns TSD Last SCK Edge to NSS Rising 2 x TSYSCLK — ns TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK — ns TCKL SCK Low Time 5 x TSYSCLK — ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK — ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK — ns TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns TSLH Last SCK Edge to MISO Change  (CKPHA = 1 ONLY) 6 x TSYSCLK 8 x TSYSCLK ns m en de d fo r N ew TSE N ot R ec om Note: TSYSCLK is equal to one period of the device system clock (SYSCLK). 337 Rev 1.1 28.7. SPI Control Registers Bit 7 6 5 4 3 2 Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN Type R RW RW RW R R Reset 0 0 0 0 0 1 1 0 SRMT RXBMT R R 1 1 D SFR Page = 0x0; SFR Address: 0xA1 es ig ns Register 28.1. SPI0CFG: SPI0 Configuration Table 28.2. SPI0CFG Register Bit Descriptions Name 7 SPIBSY Function N ew Bit SPI Busy. This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode). 6 MSTEN Master Mode Enable. 5 CKPHA fo r 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. SPI0 Clock Phase. 0: Data centered on first edge of SCK period. 1: Data centered on second edge of SCK period. CKPOL SPI0 Clock Polarity. m en de d 4 0: SCK line low in idle state. 1: SCK line high in idle state. 3 SLVSEL Slave Selected Flag. This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. NSSIN NSS Instantaneous Pin Input. om 2 This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. SRMT R ec 1 N ot 0 RXBMT Shift Register Empty. This bit is valid in slave mode only and will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when in Master Mode. Receive Buffer Empty. This bit is valid in slave mode only and will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode. Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. Rev 1.1 338 Register 28.2. SPI0CN: SPI0 Control 7 6 5 4 3 2 Name SPIF WCOL MODF RXOVRN NSSMD Type RW RW RW RW RW Reset 0 0 0 0 0 1 1 SFR Page = 0x0; SFR Address: 0xF8 (bit-addressable) Name 7 SPIF Function SPI0 Interrupt Flag. SPIEN R RW 1 0 N ew Bit TXBMT D Table 28.3. SPI0CN Register Bit Descriptions 0 es ig ns Bit This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by firmware. 6 WCOL Write Collision Flag. MODF Mode Fault Flag. m en de d 5 fo r This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by firmware. This bit is set to logic 1 by hardware when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD = 01). If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by firmware. 4 RXOVRN Receive Overrun Flag. NSSMD R ec 3:2 om This bit is valid for slave mode only and is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This bit is not automatically cleared by hardware, and must be cleared by firmware. N ot 1 0 339 TXBMT Slave Select Mode. Selects between the following NSS operation modes: 00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode. NSS is an input to the device. 10: 4-Wire Single-Master Mode. NSS is an output and logic low. 11: 4-Wire Single-Master Mode. NSS is an output and logic high. Transmit Buffer Empty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. SPIEN SPI0 Enable. 0: Disable the SPI module. 1: Enable the SPI module. Rev 1.1 Register 28.3. SPI0CKR: SPI0 Clock Rate 7 6 5 4 Name SPI0CKR Type RW Reset 0 0 0 0 3 2 0 0 SFR Page = 0x0; SFR Address: 0xA2 Name 7:0 SPI0CKR Function 0 0 N ew Bit 0 D Table 28.4. SPI0CKR Register Bit Descriptions 1 es ig ns Bit SPI0 Clock Rate. fo r These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. m en de d SYSCLK f SCK = ----------------------------------------------2   SPI0CKR + 1  N ot R ec om for 0