C8051F987-C-GMR

C8051F99x-C8051F98x Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU Ultra Low Power Consumption - 150 µA/MHz in active mode (24.5 MHz clock) - 2 µs wakeup time - 10 nA sleep mode with memory retention - 50 nA sleep mode with brownout detector - 300 nA sleep mode with LFO - 600 nA sleep mode with external crystal Supply Voltage 1.8 to 3.6 V - Built-in LDO regulator allows a high analog supply High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 512 bytes RAM - 8 kB (F990/1/6/7, F980/1/6/7), 4 kB (F982/3/8/9), or 2 kB (F985) Flash; in-system programmable voltage and low digital core voltage - 2 built-in supply monitors (brownout detector) for sleep mode and active modes 12-Bit or 10-Bit Analog to Digital Converter - ±1 LSB INL (10-bit mode); ±1.5 LSB INL  (12-bit mode) no missing codes - Programmable throughput up to 300 ksps  (10-bit mode) or 75 ksps (12-bit mode) - Up to 10 external inputs - On-chip voltage reference; 0.5x gain allows measuring voltages up to twice the reference voltage - 16-bit auto-averaging accumulator with burst mode provides increased ADC resolution - Data dependent windowed interrupt generator - Built-in temperature sensor Capacitive Sense Interface (F99x) - Supports buttons, sliders, wheels, and capacitive programmable drive strength Hardware SMBus™/I2C™, SPI™, and UART serial ports available concurrently Four general purpose 16-bit counter/timers Programmable 16-bit counter/timer array with three capture/compare modules and watchdog timer - Clock Sources - Internal oscillators: 24.5 MHz, 2% accuracy supports UART operation; 20 MHz low power oscillator requires very little bias current. External oscillator: Crystal, RC, C, or CMOS Clock SmaRTClock oscillator: 32 kHz Crystal or internal Can switch between clock sources on-the-fly; useful in implementing various power saving modes - On-Chip Debug - On-chip debug circuitry facilitates full-speed, non- proximity sensing Fast 40 µs per channel conversion time 16-bit resolution, up to 14 input channels Auto scan and wake-on-touch Auto-accumulate up to 64x samples intrusive in-system debug (no emulator required) Analog Comparator - Programmable hysteresis and response time - Configurable as wake-up or reset source 6-Bit Programmable Current Reference - Up to ±500 µA, can be used as a bias or for - Provides breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit Packages - 20-pin QFN (3 x 3 mm) - 24-pin QFN (4 x 4 mm) - 24-pin QSOP (easy to hand-solder) Temperature Range: –40 to +85 °C generating a custom reference voltage PWM enhanced resolution mode ANALOG PERIPHERALS A M U X 12/10-bit 75/300 ksps ADC TEM P SENSOR IREF VREF + VREG Capacitive Sense – VOLTAG E COM PAR ATO R DIGITAL I/O UART SM Bus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR - Digital Peripherals - Up to 17 port I/O; high sink current and Port 1 Port 2 24.5 M Hz PRECISION INTERNAL OSCILLATOR 20 MHz LOW POW ER INTERNAL OSCILLATOR External Oscillator HARDW ARE sm aRTClock HIGH-SPEED CONTROLLER CORE 8/4/2 kB ISP FLASH FLEXIBLE INTERRUPTS Rev. 1.3 6/17 8051 CPU (25 M IPS) DEBUG CIRCUITRY 512B SRAM POR W DT Copyright © 2017 by Silicon Laboratories C8051F99x-C8051F98x C8051F99x-C8051F98x Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 25 1.2. Port Input/Output............................................................................................... 26 1.3. Serial Ports ....................................................................................................... 27 1.4. Programmable Counter Array ........................................................................... 27 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode28 1.6. Programmable Current Reference (IREF0) ...................................................... 29 1.7. Comparator ....................................................................................................... 29 2. Ordering Information.............................................................................................. 31 3. Pinout and Package Definitions............................................................................ 32 4. Electrical Characteristics....................................................................................... 48 4.1. Absolute Maximum Specifications .................................................................... 48 4.2. Electrical Characteristics................................................................................... 49 5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode66 5.1. Output Code Formatting ................................................................................... 67 5.2. Modes of Operation .......................................................................................... 68 5.2.1. Starting a Conversion............................................................................... 68 5.2.2. Tracking Modes........................................................................................ 69 5.2.3. Burst Mode ............................................................................................... 70 5.2.4. Settling Time Requirements ..................................................................... 71 5.2.5. Gain Setting.............................................................................................. 72 5.3. 8-Bit Mode......................................................................................................... 72 5.4. 12-Bit Mode (C8051F980/6 and C8051F990/6 devices only)........................... 72 5.5. Low Power Mode .............................................................................................. 72 5.6. Programmable Window Detector ...................................................................... 80 5.6.1. Window Detector In Single-Ended Mode ................................................. 82 5.6.2. ADC0 Specifications................................................................................. 82 5.7. ADC0 Analog Multiplexer.................................................................................. 83 5.8. Temperature Sensor ......................................................................................... 85 5.8.1. Calibration ................................................................................................ 86 5.9. Voltage and Ground Reference Options........................................................... 88 5.10.External Voltage Reference.............................................................................. 89 5.11.Internal Voltage Reference............................................................................... 89 5.12.Analog Ground Reference................................................................................ 89 5.13.Temperature Sensor Enable ............................................................................ 89 5.14.Voltage Reference Electrical Specifications ..................................................... 90 6. Programmable Current Reference (IREF0) .......................................................... 91 6.1. PWM Enhanced Mode ...................................................................................... 91 2 Rev. 1.3 C8051F99x-C8051F98x 6.2. IREF0 Specifications......................................................................................... 92 7. Comparator ............................................................................................................. 93 7.1. Comparator Inputs ............................................................................................ 93 7.2. Comparator Outputs ......................................................................................... 94 7.3. Comparator Response Time............................................................................. 94 7.4. Comparator Hysteresis ..................................................................................... 94 7.5. Comparator Register Descriptions.................................................................... 95 7.6. Comparator0 Analog Multiplexer ...................................................................... 98 8. Capacitive Sense (CS0)........................................................................................ 100 8.1. Configuring Port Pins as Capacitive Sense Inputs ......................................... 101 8.2. Initializing the Capacitive Sensing Peripheral ................................................. 101 8.3. Capacitive Sense Start-Of-Conversion Sources............................................. 101 8.4. CS0 Multiple Channel Enable ......................................................................... 102 8.5. CS0 Gain Adjustment ..................................................................................... 102 8.6. Wake from Suspend ....................................................................................... 102 8.7. Using CS0 in Applications that Utilize Sleep Mode......................................... 102 8.8. Automatic Scanning (Method 1—CS0SMEN = 0) .......................................... 103 8.9. Automatic Scanning (Method 2—CS0SMEN = 1) .......................................... 104 8.10.CS0 Comparator............................................................................................. 104 8.11.CS0 Conversion Accumulator ........................................................................ 105 8.12.CS0 Pin Monitor ............................................................................................. 106 8.13.Adjusting CS0 For Special Situations............................................................. 106 8.14.Capacitive Sense Multiplexer ......................................................................... 117 9. CIP-51 Microcontroller ......................................................................................... 119 9.1. Performance ................................................................................................... 119 9.2. Programming and Debugging Support ........................................................... 120 9.3. Instruction Set ................................................................................................. 120 9.3.1. Instruction and CPU Timing ................................................................... 120 9.4. CIP-51 Register Descriptions.......................................................................... 125 10. Memory Organization........................................................................................... 128 10.1.Program Memory............................................................................................ 129 10.1.1.MOVX Instruction and Program Memory ............................................... 129 10.2.Data Memory .................................................................................................. 129 10.2.1.Internal RAM .......................................................................................... 129 10.2.2.External RAM ......................................................................................... 130 11. On-Chip XRAM...................................................................................................... 131 11.1.Accessing XRAM............................................................................................ 131 11.1.1.16-Bit MOVX Example ........................................................................... 131 11.1.2.8-Bit MOVX Example ............................................................................. 131 12. Special Function Registers ................................................................................. 132 12.1.SFR Paging .................................................................................................... 133 13. Interrupt Handler .................................................................................................. 138 13.1.Enabling Interrupt Sources ............................................................................. 138 13.2.MCU Interrupt Sources and Vectors............................................................... 138 13.3.Interrupt Priorities ........................................................................................... 139 Rev. 1.3 3 C8051F99x-C8051F98x 13.4.Interrupt Latency............................................................................................. 139 13.5.Interrupt Register Descriptions ....................................................................... 141 13.6.External Interrupts INT0 and INT1.................................................................. 148 14. Flash Memory ....................................................................................................... 150 14.1.Programming the Flash Memory .................................................................... 150 14.1.1.Flash Lock and Key Functions ............................................................... 150 14.1.2.Flash Erase Procedure .......................................................................... 151 14.1.3.Flash Write Procedure ........................................................................... 151 14.2.Non-volatile Data Storage .............................................................................. 151 14.3.Security Options ............................................................................................. 152 14.4.Determining the Device Part Number at Run Time ........................................ 154 14.5.Flash Write and Erase Guidelines .................................................................. 156 14.5.1.VDD Maintenance and the VDD Monitor ................................................. 156 14.5.2.PSWE Maintenance ............................................................................... 157 14.5.3.System Clock ......................................................................................... 157 14.6.Minimizing Flash Read Current ...................................................................... 158 15. Power Management.............................................................................................. 162 15.1.Normal Mode .................................................................................................. 163 15.2.Idle Mode........................................................................................................ 164 15.3.Stop Mode ...................................................................................................... 164 15.4.Suspend Mode ............................................................................................... 165 15.5.Sleep Mode .................................................................................................... 165 15.6.Configuring Wakeup Sources......................................................................... 166 15.7.Determining the Event that Caused the Last Wakeup.................................... 167 15.8.Power Management Specifications ................................................................ 171 16. Cyclic Redundancy Check Unit (CRC0) ............................................................. 172 16.1.CRC Algorithm................................................................................................ 172 16.2.Preparing for a CRC Calculation .................................................................... 174 16.3.Performing a CRC Calculation ....................................................................... 174 16.4.Accessing the CRC0 Result ........................................................................... 174 16.5.CRC0 Bit Reverse Feature............................................................................. 179 17. Voltage Regulator (VREG0) ................................................................................. 180 17.1.Voltage Regulator Electrical Specifications .................................................... 180 18. Reset Sources....................................................................................................... 181 18.1.Power-On Reset ............................................................................................. 182 18.2.Power-Fail Reset ............................................................................................ 183 18.3.External Reset ................................................................................................ 184 18.4.Missing Clock Detector Reset ........................................................................ 185 18.5.Comparator0 Reset ........................................................................................ 185 18.6.PCA Watchdog Timer Reset .......................................................................... 185 18.7.Flash Error Reset ........................................................................................... 185 18.8.SmaRTClock (Real Time Clock) Reset .......................................................... 186 18.9.Software Reset ............................................................................................... 186 19. Clocking Sources ................................................................................................. 188 19.1.Programmable Precision Internal Oscillator ................................................... 189 4 Rev. 1.3 C8051F99x-C8051F98x 19.2.Low Power Internal Oscillator......................................................................... 189 19.3.External Oscillator Drive Circuit...................................................................... 189 19.3.1.External Crystal Mode............................................................................ 189 19.3.2.External RC Mode.................................................................................. 191 19.3.3.External Capacitor Mode........................................................................ 192 19.3.4.External CMOS Clock Mode .................................................................. 192 19.4.Special Function Registers for Selecting and Configuring the System Clock 193 20. SmaRTClock (Real Time Clock) .......................................................................... 197 20.1.SmaRTClock Interface ................................................................................... 198 20.1.1.SmaRTClock Lock and Key Functions................................................... 198 20.1.2.Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers 199 20.1.3.RTC0ADR Short Strobe Feature............................................................ 199 20.1.4.SmaRTClock Interface Autoread Feature .............................................. 199 20.1.5.RTC0ADR Autoincrement Feature......................................................... 200 20.2.SmaRTClock Clocking Sources ..................................................................... 203 20.2.1.Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock . 203 20.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode...................... 204 20.2.3.Using the Low Frequency Oscillator (LFO) ............................................ 204 20.2.4.Programmable Load Capacitance.......................................................... 205 20.2.5.Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling ..................................................................................................... 206 20.2.6.Missing SmaRTClock Detector .............................................................. 208 20.2.7.SmaRTClock Oscillator Crystal Valid Detector ...................................... 208 20.3.SmaRTClock Timer and Alarm Function ........................................................ 208 20.3.1.Setting and Reading the SmaRTClock Timer Value .............................. 208 20.3.2.Setting a SmaRTClock Alarm ................................................................ 209 20.3.3.Software Considerations for using the SmaRTClock Timer and Alarm . 210 21. Port Input/Output.................................................................................................. 215 21.1.Port I/O Modes of Operation........................................................................... 216 21.1.1.Port Pins Configured for Analog I/O....................................................... 216 21.1.2.Port Pins Configured For Digital I/O....................................................... 216 21.1.3.Interfacing Port I/O to 5 V Logic ............................................................. 217 21.1.4.Increasing Port I/O Drive Strength ......................................................... 217 21.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 217 21.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 217 21.2.2.Assigning Port I/O Pins to Digital Functions........................................... 218 21.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 218 21.3.Priority Crossbar Decoder .............................................................................. 219 21.4.Port Match ...................................................................................................... 225 21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 227 22. SMBus ................................................................................................................... 235 22.1.Supporting Documents ................................................................................... 236 22.2.SMBus Configuration...................................................................................... 236 Rev. 1.3 5 C8051F99x-C8051F98x 22.3.SMBus Operation ........................................................................................... 237 22.3.1.Transmitter vs. Receiver ........................................................................ 237 22.3.2.Arbitration............................................................................................... 238 22.3.3.Clock Low Extension.............................................................................. 238 22.3.4.SCL Low Timeout................................................................................... 238 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 238 22.4.Using the SMBus............................................................................................ 239 22.4.1.SMBus Configuration Register............................................................... 240 22.4.2.SMB0CN Control Register ..................................................................... 243 22.4.3.Hardware Slave Address Recognition ................................................... 246 22.4.4.Data Register ......................................................................................... 248 22.5.SMBus Transfer Modes.................................................................................. 249 22.5.1.Write Sequence (Master) ....................................................................... 249 22.5.2.Read Sequence (Master) ....................................................................... 250 22.5.3.Write Sequence (Slave) ......................................................................... 251 22.5.4.Read Sequence (Slave) ......................................................................... 252 22.6.SMBus Status Decoding................................................................................. 252 23. UART0.................................................................................................................... 257 23.1.Enhanced Baud Rate Generation................................................................... 258 23.2.Operational Modes ......................................................................................... 259 23.2.1.8-Bit UART ............................................................................................. 259 23.2.2.9-Bit UART ............................................................................................. 260 23.3.Multiprocessor Communications .................................................................... 260 24. Enhanced Serial Peripheral Interface (SPI0)...................................................... 265 24.1.Signal Descriptions......................................................................................... 266 24.1.1.Master Out, Slave In (MOSI).................................................................. 266 24.1.2.Master In, Slave Out (MISO).................................................................. 266 24.1.3.Serial Clock (SCK) ................................................................................. 266 24.1.4.Slave Select (NSS) ................................................................................ 266 24.2.SPI0 Master Mode Operation ......................................................................... 266 24.3.SPI0 Slave Mode Operation ........................................................................... 268 24.4.SPI0 Interrupt Sources ................................................................................... 269 24.5.Serial Clock Phase and Polarity ..................................................................... 269 24.6.SPI Special Function Registers ...................................................................... 271 25. Timers.................................................................................................................... 278 25.1.Timer 0 and Timer 1 ....................................................................................... 280 25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 280 25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 281 25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 282 25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 283 25.2.Timer 2 .......................................................................................................... 288 25.2.1.16-bit Timer with Auto-Reload................................................................ 288 25.2.2.8-bit Timers with Auto-Reload................................................................ 289 25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 290 25.3.Timer 3 .......................................................................................................... 294 6 Rev. 1.3 C8051F99x-C8051F98x 25.3.1.16-bit Timer with Auto-Reload................................................................ 294 25.3.2.8-Bit Timers with Auto-Reload ............................................................... 295 25.3.3.SmaRTClock/External Oscillator Capture Mode .................................... 296 26. Programmable Counter Array ............................................................................. 300 26.1.PCA Counter/Timer ........................................................................................ 301 26.2.PCA0 Interrupt Sources.................................................................................. 302 26.3.Capture/Compare Modules ............................................................................ 303 26.3.1.Edge-triggered Capture Mode................................................................ 304 26.3.2.Software Timer (Compare) Mode........................................................... 305 26.3.3.High-Speed Output Mode ...................................................................... 306 26.3.4.Frequency Output Mode ........................................................................ 306 26.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................. 307 26.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 310 26.4.Watchdog Timer Mode ................................................................................... 311 26.4.1.Watchdog Timer Operation .................................................................... 311 26.4.2.Watchdog Timer Usage ......................................................................... 312 26.5.Register Descriptions for PCA0...................................................................... 313 27. C2 Interface ........................................................................................................... 319 27.1.C2 Interface Registers.................................................................................... 319 27.2.C2 Pin Sharing ............................................................................................... 322 Document Change List............................................................................................. 323 Contact Information.................................................................................................. 325 Rev. 1.3 7 C8051F99x-C8051F98x List of Figures Figure 1.1. C8051F980 Block Diagram .................................................................... 18 Figure 1.2. C8051F981 Block Diagram .................................................................... 18 Figure 1.3. C8051F982 Block Diagram .................................................................... 19 Figure 1.4. C8051F983 Block Diagram .................................................................... 19 Figure 1.5. C8051F985 Block Diagram .................................................................... 20 Figure 1.6. C8051F986 Block Diagram .................................................................... 20 Figure 1.7. C8051F987 Block Diagram .................................................................... 21 Figure 1.8. C8051F988 Block Diagram .................................................................... 21 Figure 1.9. C8051F989 Block Diagram .................................................................... 22 Figure 1.10. C8051F990 Block Diagram .................................................................. 22 Figure 1.11. C8051F991 Block Diagram .................................................................. 23 Figure 1.12. C8051F996 Block Diagram .................................................................. 23 Figure 1.13. C8051F997 Block Diagram .................................................................. 24 Figure 1.14. Port I/O Functional Block Diagram ....................................................... 26 Figure 1.15. PCA Block Diagram.............................................................................. 27 Figure 1.16. ADC0 Functional Block Diagram.......................................................... 28 Figure 1.17. ADC0 Multiplexer Block Diagram ......................................................... 29 Figure 1.18. Comparator 0 Functional Block Diagram ............................................. 30 Figure 3.1. QFN-20 Pinout Diagram (Top View) ...................................................... 35 Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 36 Figure 3.3. QSOP-24 Pinout Diagram (Top View).................................................... 37 Figure 3.4. QFN-20 Package Marking Diagram ....................................................... 38 Figure 3.5. QFN-24 Package Marking Diagram ....................................................... 38 Figure 3.6. QSOP-24 Package Marking Diagram .................................................... 39 Figure 3.7. QFN-20 Package Drawing ..................................................................... 40 Figure 3.8. Typical QFN-20 Landing Diagram.......................................................... 41 Figure 3.9. QFN-24 Package Drawing ..................................................................... 43 Figure 3.10. Typical QFN-24 Landing Diagram........................................................ 44 Figure 3.11. QSOP-24 Package Diagram ................................................................ 46 Figure 3.12. QSOP-24 Landing Diagram ................................................................. 47 Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 52 Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 53 Figure 4.3. Typical VOH Curves, 1.8–3.6 V ............................................................. 55 Figure 4.4. Typical VOL Curves, 1.8–3.6 V .............................................................. 56 Figure 5.1. ADC0 Functional Block Diagram............................................................ 66 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 69 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 70 Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 71 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 82 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 82 Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 83 Figure 5.8. Temperature Sensor Transfer Function ................................................. 85 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.65 V) ..... 86 8 Rev. 1.3 C8051F99x-C8051F98x Figure 5.10. Voltage Reference Functional Block Diagram...................................... 88 Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 93 Figure 7.2. Comparator Hysteresis Plot ................................................................... 95 Figure 7.3. CP0 Multiplexer Block Diagram.............................................................. 98 Figure 8.1. CS0 Block Diagram .............................................................................. 100 Figure 8.2. Auto-Scan Example.............................................................................. 103 Figure 8.3. CS0 Multiplexer Block Diagram............................................................ 117 Figure 9.1. CIP-51 Block Diagram.......................................................................... 119 Figure 10.1. C8051F99x-C8051F98x Memory Map ............................................... 128 Figure 10.2. Flash Program Memory Map.............................................................. 129 Figure 14.1. Flash Program Memory Map (8 kB and smaller devices) .................. 152 Figure 15.1. C8051F99x-C8051F98x Power Distribution....................................... 163 Figure 16.1. CRC0 Block Diagram ......................................................................... 172 Figure 16.2. Bit Reverse Register .......................................................................... 179 Figure 18.1. Reset Sources.................................................................................... 181 Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 182 Figure 19.1. Clocking Sources Block Diagram ....................................................... 188 Figure 19.2. 25 MHz External Crystal Example...................................................... 190 Figure 20.1. SmaRTClock Block Diagram.............................................................. 197 Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 206 Figure 21.1. Port I/O Functional Block Diagram ..................................................... 215 Figure 21.2. Port I/O Cell Block Diagram ............................................................... 216 Figure 21.3. Peripheral Availability on Port I/O Pins............................................... 219 Figure 21.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped). 220 Figure 21.5. Crossbar Priority Decoder in Example Configuration (4 Pins Skipped) ... 220 Figure 22.1. SMBus Block Diagram ....................................................................... 235 Figure 22.2. Typical SMBus Configuration ............................................................. 236 Figure 22.3. SMBus Transaction ............................................................................ 237 Figure 22.4. Typical SMBus SCL Generation......................................................... 240 Figure 22.5. Typical Master Write Sequence ......................................................... 249 Figure 22.6. Typical Master Read Sequence ......................................................... 250 Figure 22.7. Typical Slave Write Sequence ........................................................... 251 Figure 22.8. Typical Slave Read Sequence ........................................................... 252 Figure 23.1. UART0 Block Diagram ....................................................................... 257 Figure 23.2. UART0 Baud Rate Logic .................................................................... 258 Figure 23.3. UART Interconnect Diagram .............................................................. 259 Figure 23.4. 8-Bit UART Timing Diagram............................................................... 259 Figure 23.5. 9-Bit UART Timing Diagram............................................................... 260 Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 261 Figure 24.1. SPI Block Diagram ............................................................................. 265 Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 267 Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram 267 Rev. 1.3 9 C8051F99x-C8051F98x Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 268 Figure 24.5. Master Mode Data/Clock Timing ........................................................ 270 Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 270 Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 271 Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 275 Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 275 Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 276 Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 276 Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 281 Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 282 Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 283 Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 288 Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 289 Figure 25.6. Timer 2 Capture Mode Block Diagram ............................................... 290 Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 294 Figure 25.8. Timer 3 8-Bit Mode Block Diagram .................................................... 295 Figure 25.9. Timer 3 Capture Mode Block Diagram ............................................... 296 Figure 26.1. PCA Block Diagram............................................................................ 300 Figure 26.2. PCA Counter/Timer Block Diagram.................................................... 301 Figure 26.3. PCA Interrupt Block Diagram ............................................................. 302 Figure 26.4. PCA Capture Mode Diagram.............................................................. 304 Figure 26.5. PCA Software Timer Mode Diagram .................................................. 305 Figure 26.6. PCA High-Speed Output Mode Diagram............................................ 306 Figure 26.7. PCA Frequency Output Mode ............................................................ 307 Figure 26.8. PCA 8-Bit PWM Mode Diagram ......................................................... 308 Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ....................................... 309 Figure 26.10. PCA 16-Bit PWM Mode.................................................................... 310 Figure 26.11. PCA Module 2 with Watchdog Timer Enabled ................................. 311 Figure 27.1. Typical C2 Pin Sharing....................................................................... 322 10 Rev. 1.3 C8051F99x-C8051F98x List of Tables Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 3.1. Pin Definitions for the C8051F99x-C8051F98x . . . . . . . . . . . . . . . . . . . 32 Table 3.2. QFN-20 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.3. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 3.4. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 3.5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 3.6. QSOP-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 3.7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 4.1. Absolute Maximum Ratings .................................................................... 48 Table 4.2. Global Electrical Characteristics ............................................................. 49 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 54 Table 4.4. Reset Electrical Characteristics .............................................................. 57 Table 4.5. Power Management Electrical Specifications ......................................... 58 Table 4.6. Flash Electrical Characteristics .............................................................. 58 Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 58 Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 58 Table 4.9. SmaRTClock Characteristics .................................................................. 59 Table 4.10. ADC0 Electrical Characteristics ............................................................ 59 Table 4.11. Temperature Sensor Electrical Characteristics .................................... 60 Table 4.12. Voltage Reference Electrical Characteristics ....................................... 61 Table 4.13. IREF0 Electrical Characteristics ........................................................... 62 Table 4.14. Comparator Electrical Characteristics .................................................. 63 Table 4.15. VREG0 Electrical Characteristics ......................................................... 64 Table 4.16. Capacitive Sense Electrical Characteristics ......................................... 65 Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65 V High-Speed VREF . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 8.1. Operation with Auto-scan and Accumulate . . . . . . . . . . . . . . . . . . . . . 105 Table 9.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 12.1. Special Function Register (SFR) Memory Map (Page 0x0) . . . . . . . . 132 Table 12.2. Special Function Register (SFR) Memory Map (Page 0xF) . . . . . . . . 133 Table 12.3. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 13.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 14.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 15.1. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 16.1. Example 16-bit CRC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 19.1. Recommended XFCN Settings for Crystal Mode . . . . . . . . . . . . . . . . 190 Table 19.2. Recommended XFCN Settings for RC and C modes . . . . . . . . . . . . . 191 Table 20.1. SmaRTClock Internal Registers ......................................................... 198 Table 20.2. SmaRTClock Load Capacitance Settings . . . . . . . . . . . . . . . . . . . . . 205 Table 20.3. SmaRTClock Bias Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 21.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 217 Table 21.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . . 218 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions . . 218 Rev. 1.3 11 C8051F99x-C8051F98x Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 241 Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 245 Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 246 Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled  (EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Table 23.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 264 Table 23.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 264 Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Table 26.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . . 312 12 Rev. 1.3 C8051F99x-C8051F98x List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration . . . . . . . . . . . . . . . . . 76 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time . . . . . . . . . . . . . . 77 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time . . . . . . . . . . . . . . . . . . . . 78 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte . . . . . . . . . . . . . . . . . . 80 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte . . . . . . . . . . . . . . . . . . 80 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte . . . . . . . . . . . . . . . . . . . 81 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte . . . . . . . . . . . . . . . . . . . . 81 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select . . . . . . . . . . . . . . . . . . . . 84 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . 87 SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . 87 SFR Definition 5.15. REF0CN: Voltage Reference Control . . . . . . . . . . . . . . . . . . . . . 90 SFR Definition 6.1. IREF0CN: Current Reference Control . . . . . . . . . . . . . . . . . . . . . . 91 SFR Definition 6.2. IREF0CF: Current Reference Configuration . . . . . . . . . . . . . . . . . 92 SFR Definition 7.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection . . . . . . . . . . . . . . . . . . . 97 SFR Definition 7.3. CPT0MX: Comparator0 Input Channel Select . . . . . . . . . . . . . . . . 99 SFR Definition 8.1. CS0CN: Capacitive Sense Control . . . . . . . . . . . . . . . . . . . . . . . 107 SFR Definition 8.2. CS0CF: Capacitive Sense Configuration . . . . . . . . . . . . . . . . . . . 108 SFR Definition 8.3. CS0DH: Capacitive Sense Data High Byte . . . . . . . . . . . . . . . . . 109 SFR Definition 8.4. CS0DL: Capacitive Sense Data Low Byte . . . . . . . . . . . . . . . . . . 109 SFR Definition 8.5. CS0SCAN0: Capacitive Sense Channel Scan Mask 0 . . . . . . . . 110 SFR Definition 8.6. CS0SCAN1: Capacitive Sense Channel Scan Mask 1 . . . . . . . . 110 SFR Definition 8.7. CS0SS: Capacitive Sense Auto-Scan Start Channel . . . . . . . . . 111 SFR Definition 8.8. CS0SE: Capacitive Sense Auto-Scan End Channel . . . . . . . . . . 111 SFR Definition 8.9. CS0THH: Capacitive Sense Comparator Threshold High Byte . . 112 SFR Definition 8.10. CS0THL: Capacitive Sense Comparator Threshold Low Byte . 112 SFR Definition 8.11. CS0MD1: Capacitive Sense Mode 1 . . . . . . . . . . . . . . . . . . . . . 113 SFR Definition 8.12. CS0MD2: Capacitive Sense Mode 2 . . . . . . . . . . . . . . . . . . . . . 114 SFR Definition 8.13. CS0MD3: Capacitive Sense Mode 3 . . . . . . . . . . . . . . . . . . . . . 115 SFR Definition 8.14. CS0PM: Capacitive Sense Pin Monitor . . . . . . . . . . . . . . . . . . . 116 SFR Definition 8.15. CS0MX: Capacitive Sense Mux Channel Select . . . . . . . . . . . . 118 SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 9.4. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 9.5. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 9.6. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SFR Definition 12.1. SFR Page: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SFR Definition 13.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Rev. 1.3 13 C8051F99x-C8051F98x SFR Definition 13.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 144 SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 145 SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 146 SFR Definition 13.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 147 SFR Definition 13.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 149 SFR Definition 14.1. DEVICEID: Device Identification . . . . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 14.2. REVID: Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SFR Definition 14.3. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 159 SFR Definition 14.4. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SFR Definition 14.5. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SFR Definition 14.6. FLWR: Flash Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 SFR Definition 15.1. PMU0CF: Power Management Unit Configuration1,2,3 . . . . . . . . . . 168 SFR Definition 15.2. PMU0FL: Power Management Unit Flag1,2 . . . . . . . . . . . . . . . . . . . . 169 SFR Definition 15.3. PMU0MD: Power Management Unit Mode . . . . . . . . . . . . . . . . 170 SFR Definition 15.4. PCON: Power Management Control Register . . . . . . . . . . . . . . 171 SFR Definition 16.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 SFR Definition 16.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SFR Definition 16.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 176 SFR Definition 16.4. CRC0AUTO: CRC0 Automatic Control . . . . . . . . . . . . . . . . . . . 177 SFR Definition 16.5. CRC0CNT: CRC0 Automatic Flash Sector Count . . . . . . . . . . . 178 SFR Definition 16.6. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SFR Definition 17.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . 180 SFR Definition 18.1. VDM0CN: VDD Supply Monitor Control . . . . . . . . . . . . . . . . . . 184 SFR Definition 18.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 SFR Definition 19.1. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 19.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 19.3. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 195 SFR Definition 19.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key . . . . . . . . . . . . . . . . . . 201 SFR Definition 20.2. RTC0ADR: SmaRTClock Address . . . . . . . . . . . . . . . . . . . . . . 202 SFR Definition 20.3. RTC0DAT: SmaRTClock Data . . . . . . . . . . . . . . . . . . . . . . . . . 202 Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 211 Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 212 Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 213 Internal Register Definition 20.7. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 214 Internal Register Definition 20.8. ALARMn: SmaRTClock Alarm Programmed Value 214 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 222 SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 224 SFR Definition 21.4. P0MASK: Port0 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 21.5. P0MAT: Port0 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 21.6. P1MASK: Port1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 226 SFR Definition 21.7. P1MAT: Port1 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SFR Definition 21.8. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14 Rev. 1.3 C8051F99x-C8051F98x SFR Definition 21.9. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SFR Definition 21.10. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 21.11. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 21.12. P0DRV: Port0 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 230 SFR Definition 21.13. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 21.14. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 21.15. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 SFR Definition 21.16. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 232 SFR Definition 21.17. P1DRV: Port1 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 233 SFR Definition 21.18. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 SFR Definition 21.19. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 234 SFR Definition 21.20. P2DRV: Port2 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 234 SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 242 SFR Definition 22.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SFR Definition 22.3. SMB0ADR: SMBus Slave Address . . . . . . . . . . . . . . . . . . . . . . 247 SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask . . . . . . . . . . . . . . . . . 247 SFR Definition 22.5. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SFR Definition 23.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 262 SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 263 SFR Definition 24.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 272 SFR Definition 24.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 SFR Definition 24.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 SFR Definition 25.1. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 SFR Definition 25.2. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 SFR Definition 25.3. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SFR Definition 25.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 SFR Definition 25.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 SFR Definition 25.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SFR Definition 25.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SFR Definition 25.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 292 SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 292 SFR Definition 25.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SFR Definition 25.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SFR Definition 25.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 298 SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 298 SFR Definition 25.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 SFR Definition 25.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 SFR Definition 26.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 SFR Definition 26.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 SFR Definition 26.3. PCA0PWM: PCA PWM Configuration . . . . . . . . . . . . . . . . . . . . 315 SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 316 SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 317 Rev. 1.3 15 C8051F99x-C8051F98x SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 317 SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 318 SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 318 C2 Register Definition 27.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 C2 Register Definition 27.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 320 C2 Register Definition 27.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 320 C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 321 C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 321 16 Rev. 1.3 C8051F99x-C8051F98x 1. System Overview C8051F99x-C8051F98x devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.         Ultra low power consumption in active and sleep modes. High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) 10-bit 300 ksps or 12-bit 75 ksps single-ended ADC with analog multiplexer 6-bit programmable current reference (resolution can be increased with PWM) Precision programmable 24.5 MHz internal oscillator with spread spectrum technology. 8 kB, 4 kB, or 2 kB of on-chip Flash memory 512 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware  Four general-purpose 16-bit timers  Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer function  On-chip power-on reset, VDD monitor, and temperature sensor   One on-chip voltage comparator  Up to 14 Capacitive Touch Inputs  Up to 17 Port I/O With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the C8051F99xC8051F98x devices are truly stand-alone system-on-a-chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are powered from the supply voltage. The C8051F99x-C8051F98x devices are available in 20-pin or 24-pin QFN or 24-pin QSOP packages. All package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.9. Rev. 1.3 17 C8051F99x-C8051F98x Wake Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM C2D VREG Digital Power SPI Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND GND XTAL2 XTAL3 IREF0 Internal External VREF VREF A M U X 12-bit ADC SmaRTClock Oscillator XTAL4 P2.7/C2D Analog Peripherals 6-bit IREF External Oscillator Circuit XTAL1 Port 2 Drivers SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine VDD Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory VDD VREF Temp Sensor GND CP0 System Clock Configuration P1.0 P1.1 + - Comparator Figure 1.1. C8051F980 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM Digital Power GND XTAL1 XTAL2 XTAL3 XTAL4 Port 2 Drivers P2.7/C2D SMBus SPI Low Power 20 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder SYSCLK Precision 24.5 MHz Oscillator GND PCA/ WDT CRC Engine VREG Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 External Oscillator Circuit SmaRTClock Oscillator CP0 System Clock Configuration + - Comparator Figure 1.2. C8051F981 Block Diagram 18 Rev. 1.3 P1.0 P1.1 C8051F99x-C8051F98x Wake Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM C2D VREG Digital Power SPI Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND GND XTAL2 External Oscillator Circuit XTAL3 SmaRTClock XTAL4 Oscillator XTAL1 Port 2 Drivers P2.7/C2D SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine VDD Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 4 kB ISP Flash Program Memory Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF A M U X 10-bit ADC VDD VREF Temp Sensor GND CP0 System Clock Configuration P1.0 P1.1 + - Comparator Figure 1.3. C8051F982 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM Digital Power GND XTAL1 XTAL2 XTAL3 XTAL4 Port 2 Drivers P2.7/C2D SMBus SPI Low Power 20 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder SYSCLK Precision 24.5 MHz Oscillator GND PCA/ WDT CRC Engine VREG Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 Digital Peripherals 4 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 External Oscillator Circuit SmaRTClock Oscillator CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.4. C8051F983 Block Diagram Rev. 1.3 19 C8051F99x-C8051F98x Wake Reset C2CK/RST Debug / Programming Hardware Digital Peripherals 2 kB ISP Flash Program Memory UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM C2D VREG Digital Power SMBus SPI Crossbar Control SFR Bus Low Power 20 MHz Oscillator XTAL3 Port 1 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers P2.7/C2D GND External Oscillator Circuit XTAL2 Priority Crossbar Decoder SYSCLK Precision 24.5 MHz Oscillator XTAL1 Port 0 Drivers PCA/ WDT CRC Engine VDD GND GND Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU CP0 P1.0 P1.1 + - Comparator SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.5. C8051F985 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM Digital Power SPI Low Power 20 MHz Oscillator GND XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator Port 2 Drivers P2.7/C2D SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine VREG Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF A M U X 12-bit ADC VDD VREF Temp Sensor GND CP0 System Clock Configuration + - Comparator Figure 1.6. C8051F986 Block Diagram 20 Rev. 1.3 P1.0 P1.1 C8051F99x-C8051F98x Wake Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM C2D VREG Digital Power SPI Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND XTAL2 XTAL3 P2.7/C2D Analog Peripherals 6-bit IREF IREF0 GND External Oscillator Circuit XTAL1 Port 2 Drivers SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine VDD Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory CP0 P1.0 P1.1 + - Comparator SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.7. C8051F987 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 CRC Engine Digital Power SPI Low Power 20 MHz Oscillator GND XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator Port 2 Drivers P2.7/C2D SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT VREG Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 4 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF A M U X 10-bit ADC VDD VREF Temp Sensor GND CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.8. C8051F988 Block Diagram Rev. 1.3 21 C8051F99x-C8051F98x Wake Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 CRC Engine VDD VREG Digital Power SPI Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND XTAL2 XTAL3 P2.7/C2D Analog Peripherals 6-bit IREF IREF0 GND External Oscillator Circuit XTAL1 Port 2 Drivers SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT C2D Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 Digital Peripherals 4 kB ISP Flash Program Memory CP0 P1.0 P1.1 + - Comparator SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.9. C8051F989 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM VREG Low Power 20 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator Port 2 Drivers P2.7/C2D SMBus SPI SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine Digital Power Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF A M U X 12-bit ADC VDD VREF Temp Sensor 13-Channel Capacitance To Digital Converter GND CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.10. C8051F990 Block Diagram 22 Rev. 1.3 C8051F99x-C8051F98x Wake Reset C2CK/RST Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM C2D VREG Digital Power SPI Crossbar Control SFR Bus Low Power 20 MHz Oscillator GND GND XTAL2 XTAL3 P2.7/C2D Analog Peripherals 6-bit IREF IREF0 13-Channel Capacitance To Digital Converter External Oscillator Circuit XTAL1 Port 2 Drivers SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine VDD Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory SmaRTClock Oscillator XTAL4 CP0 System Clock Configuration P1.0 P1.1 + - Comparator Figure 1.11. C8051F991 Block Diagram Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM Digital Power SPI Low Power 20 MHz Oscillator GND XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator Port 2 Drivers P2.7/C2D SMBus SYSCLK Precision 24.5 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder PCA/ WDT CRC Engine VREG Port 0 Drivers P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 Internal External VREF VREF A M U X 12-bit ADC VDD VREF Temp Sensor 14-Channel Capacitance To Digital Converter GND CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.12. C8051F996 Block Diagram Rev. 1.3 23 C8051F99x-C8051F98x Wake Reset C2CK/RST Debug / Programming Hardware UART 256 Byte SRAM Timers 0, 1, 2, 3 256 Byte XRAM Digital Power XTAL1 XTAL2 XTAL3 XTAL4 Port 2 Drivers P2.7/C2D SMBus SPI Low Power 20 MHz Oscillator Port 1 Drivers P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 Priority Crossbar Decoder SYSCLK Precision 24.5 MHz Oscillator GND PCA/ WDT CRC Engine VREG Port 0 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 Digital Peripherals 8 kB ISP Flash Program Memory C2D VDD Port I/O Configuration CIP-51 8051 Controller Core Power On Reset/PMU Crossbar Control SFR Bus Analog Peripherals 6-bit IREF IREF0 14-Channel Capacitance To Digital Converter External Oscillator Circuit SmaRTClock Oscillator CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.13. C8051F997 Block Diagram 24 Rev. 1.3 C8051F99x-C8051F98x 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F99x-C8051F98x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.1.3. Additional Features The C8051F99x-C8051F98x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Rev. 1.3 25 C8051F99x-C8051F98x 1.2. Port Input/Output Digital and analog resources are available through 16 or 17 I/O pins. Port pins are organized as three bytewide ports. Port pins P0.0–P1.7 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on page 319 for more details. The designer has complete control over which digital and analog functions are assigned to individual Port pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on page 219 for more information on the Crossbar. All Port I/Os can tolerate voltages up to the supply rail when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD supply. Port I/Os used for analog functions can operate up to the VDD supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 216 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. XBR0, XBR1, XBR2, PnSKIP Registers Port Match P0MASK, P0MAT P1MASK, P1MAT External Interrupts EX0 and EX1 Priority Decoder Highest Priority UART 4 (Internal Digital Signals) SPI0 P0.0 2 SMBus Digital Crossbar 8 4 CP0 Output P0 I/O Cells P0.7 SYSCLK P1.0 8 P1 I/O Cells 4 PCA Lowest Priority PnMDOUT, PnMDIN Registers 2 2 T0, T1 P1.7* *P1.4 is not available on 20-pin devices. 8 (Port Latches) P0 1 (P0.0-P0.7) P2 I/O Cell 8 P1 (P1.0-P1.7) P2 (P2.7) P2.7 1 To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) Figure 1.14. Port I/O Functional Block Diagram 26 Rev. 1.3 C8051F99x-C8051F98x 1.3. Serial Ports The C8051F99x-C8051F98x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.4. Programmable Counter Array An on-chip programmable counter/timer array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of seven sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, the external oscillator clock source divided by 8, or the SmaRTClock divided by 8. Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SY S C LK /12 S Y S C L K /4 T im e r 0 O v e rflo w ECI PCA CLO CK MUX 1 6 -B it C o u n te r/ T im e r SYSC LK E x te r n a l C lo c k / 8 S m a R T C lo c k /8 C a p tu r e /C o m p a r e M o d u le0 C a p tu re /C o m p a re M o d u le1 C a p tu re / C o m p a re M o d u le 2 / W D T CEX2 CEX1 CEX0 ECI C ro s s b a r P o r t I/ O Figure 1.15. PCA Block Diagram Rev. 1.3 27 C8051F99x-C8051F98x 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode C8051F99x-C8051F98x devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximationregister (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without any additional CPU intervention. The ADC can sample the voltage at select GPIO pins (see Figure 1.17) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs include an on-chip temperature sensor, the VDD supply voltage, and the internal digital supply voltage. AD0CM0 AD0CM1 AD0CM2 AD0WINT AD0INT AD0BUSY BURSTEN AD0EN ADC0CN VDD Start Conversion ADC0TK Burst Mode Logic ADC0PWR ADC Timer 2 Overflow Timer 3 Overflow CNVSTR Input REF 16-Bit Accumulator SYSCLK AD0TM AMP0GN AD08BE AD0SC0 AD0SC1 AD0SC2 AD0SC3 AD0SC4 ADC0CF 010 011 100 ADC0L AIN+ AD0BUSY (W) Timer 0 Overflow ADC0H From AMUX0 10/12-Bit SAR 000 001 AD0WINT 32 ADC0LTH ADC0LTL ADC0GTH ADC0GTL Figure 1.16. ADC0 Functional Block Diagram 28 Rev. 1.3 Window Compare Logic C8051F99x-C8051F98x AD0MX4 AD0MX3 AD0MX2 AD0MX1 AM0MX0 ADC0MX P0.1 P0.2 P0.3 P0.4 Programmable Attenuator P0.5 P0.6 P0.7 P1.2 AIN+ AMUX ADC0 P1.3 *P1.4 Temp Sensor Gain = 0.5 or 1 Digital Supply VDD *Only available on 24-pin devices. Figure 1.17. ADC0 Multiplexer Block Diagram 1.6. Programmable Current Reference (IREF0) C8051F99x-C8051F98x devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.7. Comparator C8051F99x-C8051F98x devices include an on-chip programmable voltage comparator: Comparator 0 (CPT0) which is shown in Figure 1.18. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be used to directly sense capacitive touch switches. Rev. 1.3 29 CPT0CN C8051F99x-C8051F98x CP0EN CP0OUT CP0RIF CP0FIF VDD CP0HYP1 CP0HYP0 CP0HYN1 CP0 Interrupt CP0HYN0 CPT0MD Analog Input Multiplexer CP0FIE CP0RIE CP0MD1 CP0MD0 Px.x CP0 Rising-edge CP0 + CP0 Falling-edge Interrupt Logic Px.x CP0 + D - SET CLR Q Q D SET CLR Q Q Px.x Crossbar (SYNCHRONIZER) CP0 - GND (ASYNCHRONOUS) Px.x Reset Decision Tree Figure 1.18. Comparator 0 Functional Block Diagram 30 Rev. 1.3 CP0A C8051F99x-C8051F98x 2. Ordering Information Programmable Current Reference Analog Comparators Lead-free (RoHS Compliant) Package 1  QFN-20 10-bit —  1  QFN-20 —  1  QFN-20 —  1  QFN-20 4  17 10 12-bit —  1  QFN-24  4  17 10 12-bit —  1  QSOP-24   4  17 — — —  1  512   4  17 — — —  1  QSOP-24 4 512   4  17 10 10-bit —  1  25 4 512   4  17 10 10-bit —  1  QSOP-24 C8051F989-C-GM 25 4 512   4  17 — — —  1  C8051F989-C-GU 25 4 512   4  17 — — —  1  QSOP-24 C8051F990-C-GM 25 8 512   4  16 9 12-bit 13  1  QFN-20 C8051F991-C-GM 25 8 512   4  16 — 13  1  QFN-20 C8051F996-C-GM 25 8 512   4  17 10 12-bit 14  1  QFN-24 C8051F996-C-GU 25 8 512   4  17 10 12-bit 14  1  QSOP-24 C8051F997-C-GM 25 8 512   4  17 — — 14  1  C8051F997-C-GU 25 8 512   4  17 — — 14  1  QSOP-24 25 8 512   4  16 9 C8051F981-C-GM 25 8 512   4  16 — C8051F982-C-GM 25 4 512   4  16 9 C8051F983-C-GM 25 4 512   4  16 — — C8051F985-C-GM 25 2 512   4  16 — — C8051F986-C-GM 25 8 512   C8051F986-C-GU 25 8 512  C8051F987-C-GM 25 8 512 C8051F987-C-GU 25 8 C8051F988-C-GM 25 C8051F988-C-GU Analog to Digital Converter Inputs C8051F980-C-GM Digital Port I/Os Programmable Counter Array  Timers (16-bit) — SMBus/I2C, UART, Enhanced SPI QFN-20 SmaRTClock Real Time Clock  RAM (bytes) 1 Flash Memory (kB)  MIPS (Peak) 12-bit — Ordering Part Number Capacitive Touch Inputs ADC with internal voltage reference and temperature sensor Table 2.1. Product Selection Guide — — QFN-24 QFN-24 QFN-24 QFN-24 Note: Starting with silicon revision C, the ordering part numbers have been updated to include the silicon revision and use this format: "C8051F990-C-GM". Package marking diagrams are included as Figure 3.4, Figure 3.5, and Figure 3.6 to identify the silicon revision. Rev. 1.3 31 C8051F99x-C8051F98x 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F99x-C8051F98x Pin Numbers Name ‘F980/1/2 ‘F986/7 ‘F986/7 ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU Type Description Power Supply Voltage. Must be 1.8 to 3.6 V. VDD 4 3 6 P In GND 3, 12 2 5 G RST/ 5 6 9 D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1 k to 5 k pullup to VDD is recommended. See Section “18. Reset Sources” on page 181 Section for a complete description. D I/O Clock signal for the C2 Debug Interface. D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O Section for a complete description. D I/O Bi-directional data signal for the C2 Debug Interface. D I/O Port 1.6. See Port I/O Section for a complete description. A In SmaRTClock Oscillator Crystal Input. See Section 20 for a complete description. D I/O Port 1.7. See Port I/O Section for a complete description. A Out SmaRTClock Oscillator Crystal Output. See Section 20 for a complete description. C2CK P2.7/ 6 7 10 C2D P1.6/ 8 9 12 XTAL3 P1.7/ 7 8 11 XTAL4 P0.0/ VREF* 2 24 3 Required Ground. D I/O or Port 0.0. See Port I/O Section for a complete description. A In A In External VREF Input. See Section “5.9. Voltage and Ground Reference Options” on page 88. *Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices. 32 Rev. 1.3 C8051F99x-C8051F98x Table 3.1. Pin Definitions for the C8051F99x-C8051F98x (Continued) Pin Numbers Name P0.1/ ‘F980/1/2 ‘F986/7 ‘F986/7 ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU 1 23 2 20 22 1 XTAL1/ P0.3/ 19 21 24 D In A In D Out WAKEOUT P0.4/ 18 20 23 P0.5/ RX 17 19 22 External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Section “19. Clocking Sources” on page 188 for complete details. Wake-up request signal to wake up external devices. D I/O or Port 0.4. See Section “21. Port Input/Output” on A In page 215 for a complete description. D Out TX Buffered SmaRTClock oscillator output. D I/O or Port 0.3. See Section “21. Port Input/Output” on A In page 215 for a complete description. A Out XTAL2/ Optional Analog Ground. See Section “5.9. Voltage and Ground Reference Options” on page 88. D I/O or Port 0.2. See Port I/O Section for a complete description. A In External Clock Input. This pin is the external oscillator A In return for a crystal or resonator. See Section “19. Clocking Sources” on page 188. D Out RTCOUT Description D I/O or Port 0.1. See Port I/O Section for a complete description. A In G AGND* P0.2/ Type UART TX Pin. See Section “21. Port Input/Output” on page 215. D I/O or Port 0.5. See Section “21. Port Input/Output” on A In page 215 for a complete description. D In UART RX Pin. See Section “21. Port Input/Output” on page 215. *Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices. Rev. 1.3 33 C8051F99x-C8051F98x Table 3.1. Pin Definitions for the C8051F99x-C8051F98x (Continued) Pin Numbers Name P0.6/ ‘F980/1/2 ‘F986/7 ‘F986/7 ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU 16 18 21 17 20 D I/O or Port 0.7. See Section “21. Port Input/Output” on A In page 215 for a complete description. A Out IREF0 Output. See IREF Section for complete description. 14 16 19 D I/O or Port 1.0. See Section “21. Port Input/Output” on A In page 215 for a complete description. May also be used as SCK for SPI1. CP0+ P1.1 External Convert Start Input for ADC0. See Section “5.7. ADC0 Analog Multiplexer” on page 83 for a complete description. 15 IREF0 P1.0 Description D I/O or Port 0.6. See Section “21. Port Input/Output” on A In page 215 for a complete description. D In CNVSTR* P0.7/ Type A In 13 15 18 CP0- Comparator0 positive input. See Comparator Section for complete description. D I/O or Port 1.1. See Section “21. Port Input/Output” on A In page 215 for a complete description. A In Comparator0 negative input. See Comparator Section for complete description. P1.2 11 14 17 D I/O or Port 1.2. See Section “21. Port Input/Output” on A In page 215 for a complete description. P1.3 10 13 16 D I/O or Port 1.3. See Section “21. Port Input/Output” on A In page 215 for a complete description. P1.4 — 12 15 D I/O or Port 1.4. See Section “21. Port Input/Output” on A In page 215 for a complete description. P1.5 9 11 14 D I/O or Port 1.5. See Section “21. Port Input/Output” on A In page 215 for a complete description. *Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices. 34 Rev. 1.3 VS TR * P0.5/RX 17 P 0. 6/ C N P0.4/TX 18 D P0.3/XTAL2/WAKEOUT N 19 G A 1/ P0.2/XTAL1/RTCOUT . P0 20 C8051F99x-C8051F98x * 5 7/ C P 2. 16 15 P0.7/IREF0 14 P1.0/CP0+ 13 P1.1/CP0- 12 GND 11 .2 P1 2D 6 GND (Optional Connection) 10 RST/C2CK Top View P1.3 4 9 VDD P1.5 3 8 GND C8051F980/1/2/3/5 C8051F990/1 -GM P1.6/XTAL3 2 7 P0.0/VREF* P1.7/XTAL4 1 *Note: Signal only available on ‘F980, ‘F982 and ‘F990 devices. Figure 3.1. QFN-20 Pinout Diagram (Top View) Rev. 1.3 35 P0.0/VREF* P0.1/AGND* P0.2/XTAL1/RTCOUT P0.3/XTAL2/WAKEOUT P0.4/TX P0.5/RX 23 22 21 20 19 12 6 P1.4 RST/C2CK GND (optional connection) 11 5 P1.5 N.C. Top View 10 4 N.C. N.C. 9 3 P1.6/XTAL3 VDD C8051F986/7/8/9 C8051F996/7 -GM 8 2 P1.7/XTAL4 GND 7 1 P2.7/C2D N.C. 24 C8051F99x-C8051F98x 18 P0.6/CNVSTR* 17 P0.7/IREF0 16 P1.0/CP0+ 15 P1.1/CP0- 14 P1.2 13 P1.3 *Note: Signal only available on ‘F986, ‘F988, and ‘F996 devices. Figure 3.2. QFN-24 Pinout Diagram (Top View) 36 Rev. 1.3 C8051F99x-C8051F98x 1 24 P0.3/XTAL2/WAKEOUT P0.1/AGND* 2 23 P0.4/TX P0.0/VREF* 3 22 P0.5/RX 21 P0.6/CNVSTR * 20 P0.7/IREF0 19 P1.0/CP0+ 18 P1.1/CP0- 17 P1.2 16 P1.3 15 P1.4 N.C. 4 GND 5 VDD 6 N.C. 7 N.C. 8 RST/C2CK 9 C8051F986/7/8/9, C8051F996/7 - GU P0.2/XTAL1/RTCOUT P2.7/C2D 10 P1.7/XTAL4 11 14 P1.5 P1.6/XTAL3 12 13 N.C. *Note: Signal only available on ‘F986, ‘F988, and ‘F996 devices. Figure 3.3. QSOP-24 Pinout Diagram (Top View) Rev. 1.3 37 C8051F99x-C8051F98x First character of the trace code identifies the silicon revision Figure 3.4. QFN-20 Package Marking Diagram First character of the trace code identifies the silicon revision Figure 3.5. QFN-24 Package Marking Diagram 38 Rev. 1.3 C8051F99x-C8051F98x First character of the trace code identifies the silicon revision Figure 3.6. QSOP-24 Package Marking Diagram Rev. 1.3 39 C8051F99x-C8051F98x   Figure 3.7. QFN-20 Package Drawing Table 3.2. QFN-20 Package Dimensions Dimension Min A A1 b c D D2 e E E2 0.50 0.00 0.20 0.27 1.6 1.6 Typ Max Dimension 0.55 0.60 0.02 0.05 0.25 0.30 0.32 0.375 3.00 BSC 1.70 1.8 0.50 BSC 3.00 BSC 1.70 1.8 f L L1 aaa bbb ccc ddd eee Min 0.35 0.00 — — — — Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 40 Rev. 1.3 Typ Max 2.53 BSC 0.40 — — — — — — 0.45 0.10 0.05 0.05 0.08 0.10 0.10 C8051F99x-C8051F98x   Figure 3.8. Typical QFN-20 Landing Diagram Rev. 1.3 41 C8051F99x-C8051F98x Table 3.3. PCB Land Pattern Dimension Min D D2 Max 2.71 REF 1.60 1.80 e 0.50 BSC E 2.71 REF E2 1.60 f 1.80 2.53 REF GD 2.10 — GE 2.10 — W — 0.34 X — 0.28 Y 0.61 REF ZE — 3.31 ZD — 3.31 Notes: General 1. 2. 3. 4. All dimensions shown are in millimeters (mm) unless otherwise noted. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. This Land Pattern Design is based on IPC-SM-782 guidelines. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 42 Rev. 1.3 C8051F99x-C8051F98x Figure 3.9. QFN-24 Package Drawing Table 3.4. QFN-24 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0.70 0.75 0.80 L 0.30 0.40 0.50 A1 0.00 0.02 0.05 L1 0.00 — 0.15 b 0.18 0.25 0.30 aaa — — 0.15 bbb — — 0.10 ddd — — 0.05 D D2 4.00 BSC 2.55 2.70 2.80 e 0.50 BSC eee — — 0.08 E 4.00 BSC Z — 0.24 — Y — 0.18 — E2 2.55 2.70 2.80 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.3 43 C8051F99x-C8051F98x   Figure 3.10. Typical QFN-24 Landing Diagram 44 Rev. 1.3 C8051F99x-C8051F98x Table 3.5. PCB Land Pattern Dimension MIN MAX C1 3.90 4.00 C2 3.90 4.00 E 0.50 BSC X1 0.20 0.30 X2 2.70 2.80 Y1 0.65 0.75 Y2 2.70 2.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x2 array of 1.10 mm x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.3 45 C8051F99x-C8051F98x Figure 3.11. QSOP-24 Package Diagram Table 3.6. QSOP-24 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A — — 1.75 L 0.40 — 1.27 A1 0.10 — 0.25 L2 b 0.20 — 0.30  c 0.10 — 0.25 aaa 0.20 0.25 BSC 0º — D 8.65 BSC. bbb 0.18 E 6.00 BSC ccc 0.10 E1 3.90 BSC ddd 0.10 e 0.635 BSC 8º Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-147, variation AE. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 46 Rev. 1.3 C8051F99x-C8051F98x   Figure 3.12. QSOP-24 Landing Diagram Table 3.7. PCB Land Pattern Dimension MIN C 5.20 E MAX 5.30 0.635 BSC X 0.30 0.40 Y 1.50 1.60 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.3 47 C8051F99x-C8051F98x 4. Electrical Characteristics Throughout the Electrical Characteristics chapter, “VDD” refers to the Supply Voltage. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Conditions Min Typ Max Units Ambient Temperature under Bias –55 — 125 °C Storage Temperature –65 — 150 °C Voltage on any Port I/O Pin or RST with Respect to GND –0.3 — VDD + 0.3 V Voltage on VDD with Respect to GND –0.3 — 4.0 V Maximum Total Current through VDD or GND — — 500 mA Maximum Current through RST or any Port Pin — — 100 mA Maximum Total Current through all Port Pins — — 200 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 48 Rev. 1.3 C8051F99x-C8051F98x 4.2. Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Supply Voltage (VDD) Conditions Min 1.8 Typ 2.4 Max 3.6 Units V Minimum RAM Data  Retention Voltage1 not in sleep mode in sleep mode — — 1.4 0.3 — 0.45 V SYSCLK (System Clock)2 TSYSH (SYSCLK High Time) 0 — 25 MHz 18 — — ns TSYSL (SYSCLK Low Time) 18 — — ns Specified Operating  Temperature Range –40 — +85 °C Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) IDD 3, 4, 5 IDD Frequency  Sensitivity 1, 3, 5 VDD = 1.8–3.6 V, F = 24.5 MHz (includes precision oscillator current) — 3.6 4.5 mA VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) — 3.1 — mA VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) — — 225 290 — — µA µA VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) — 84 — µA VDD = 1.8–3.6 V, T = 25 °C, F < 14 MHz (Flash oneshot active, see Section 14.6) — 174 — µA/MHz VDD = 1.8–3.6 V, T = 25 °C, F > 14 MHz (Flash oneshot bypassed, see Section 14.6) — 88 — µA/MHz Rev. 1.3 49 C8051F99x-C8051F98x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) — 1.8 3.0 VDD = 1.8–3.6 V, F = 24.5 MHz IDD4, 6 (includes precision oscillator current) IDD Frequency Sensitivity1,6 Digital Supply Current (Sleep Mode, VDD Supply Monitor Disabled) 50 mA VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) — 1.4 — mA VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) — — 145 180 — — µA µA VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) — 82 — µA VDD = 1.8–3.6 V, T = 25 °C — 67 — µA/MHz — 77 — µA — — — — — — 0.60 0.70 0.80 0.80 0.90 1.00 — — — — — — µA — — — — — — 0.30 0.40 0.50 0.50 0.70 0.80 — — — — — — µA — — — — — — 0.05 0.07 0.08 0.20 0.24 0.28 — — — — — — µA — — — — — — 0.005 0.01 0.02 0.15 0.19 0.23 — — — — — — µA Digital Supply Current—Suspend and Sleep Mode Digital Supply Current  VDD = 1.8–3.6 V (Suspend Mode) Digital Supply Current 1.8 V, T = 25 °C 3.0 V, T = 25 °C (Sleep Mode, SmaRTClock 3.6 V, T = 25 °C running, 32.768 kHz crystal) 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and VDD Supply Monitor) Digital Supply Current 1.8 V, T = 25 °C (Sleep Mode, SmaRTClock 3.0 V, T = 25 °C running, internal LFO) 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and VDD Supply Monitor) Digital Supply Current (Sleep Mode) Units 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes VDD supply monitor) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C Rev. 1.3 C8051F99x-C8051F98x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Units Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. Includes oscillator and regulator supply current. 5. IDD can be estimated for frequencies < 14 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 84 µA. When using these numbers to estimate IDD for > 14 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 3.6 mA – (25 MHz – 20 MHz) x 0.088 mA/MHz = 3.16 mA assuming the same oscillator setting. 6. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 1.75 mA – (25 MHz – 5 MHz) x 0.067 mA/MHz = 0.41 mA. Rev. 1.3 51 C8051F99x-C8051F98x 4200 F < 14 MHz Oneshot Enabled 4100 4000 F > 14 MHz Oneshot Bypassed 3900 3800 3700 3600 < 150uA/MHz 3500 3400 3300 3200 152 uA/MHz 3100 3000 2900 2800 2700 Supply Current (uA) 2600 168 uA/MHz 2500 2400 180 uA/MHz 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 184 uA/MHz 1100 1000 900 800 700 600 500 400 300 250 uA/MHz 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Frequency (MHz) 15 16 17 18 19 20 Figure 4.1. Active Mode Current (External CMOS Clock) 52 Rev. 1.3 21 22 23 24 25 C8051F99x-C8051F98x 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 Supply Current (uA) 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Frequency (MHz) 15 16 17 18 19 20 21 22 23 24 25 Figure 4.2. Idle Mode Current (External CMOS Clock) Rev. 1.3 53 C8051F99x-C8051F98x Table 4.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions Min Typ Max Output High Voltage High Drive Strength, PnDRV.n = 1 Units V IOH = –3 mA, Port I/O push-pull VDD – 0.7 — — IOH = –10 µA, Port I/O push-pull VDD – 0.1 — — IOH = –10 mA, Port I/O push-pull See Chart Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull VDD – 0.7 — — VDD – 0.1 — — — See Chart — Output Low Voltage High Drive Strength, PnDRV.n = 1 V IOL = 8.5 mA — — 0.6 IOL = 10 µA — — 0.1 IOL = 25 mA — See Chart — IOL = 1.4 mA — — 0.6 IOL = 10 µA — — 0.1 IOL = 4 mA — See Chart — VDD = 2.0 to 3.6 V VDD – 0.6 — — V VDD = 0.9 to 2.0 V 0.7 x VDD — — V VDD = 2.0 to 3.6 V — — 0.6 V VDD = 0.9 to 2.0 V — — 0.3 x VDD V Weak Pullup Off — — ±1 µA Weak Pullup On, VIN = 0 V, VDD = 1.8 V — 4 — Weak Pullup On, Vin = 0 V, VDD = 3.6 V — 20 35 Low Drive Strength, PnDRV.n = 0 Input High Voltage Input Low Voltage Input Leakage  Current 54 Rev. 1.3 C8051F99x-C8051F98x Typical VOH (High Drive Mode) Voltage 3.6 3.3 VDD = 3.6V 3 VDD = 3.0V 2.7 VDD = 2.4V 2.4 VDD = 1.8V 2.1 1.8 1.5 1.2 0.9 0 5 10 15 20 25 30 35 40 45 50 Load Current (mA) Typical VOH (Low Drive Mode) Voltage 3.6 3.3 VDD = 3.6V 3 VDD = 3.0V 2.7 VDD = 2.4V 2.4 VDD = 1.8V 2.1 1.8 1.5 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) Figure 4.3. Typical VOH Curves, 1.8–3.6 V Rev. 1.3 55 C8051F99x-C8051F98x Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V Voltage 1.2 VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V Voltage 1.2 VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.4. Typical VOL Curves, 1.8–3.6 V 56 Rev. 1.3 C8051F99x-C8051F98x Table 4.4. Reset Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units RST Output Low Voltage IOL = 1.4 mA, — — 0.6 V RST Input High Voltage VDD = 12.0 to 3.6 V VDD – 0.6 — — V VDD = 10.9 to 2.0 V 0.7 x VDD — — V VDD = 12.0 to 3.6 V — — 0.6 V VDD = 10.9 to 2.0 V — — 0.3 x VDD V RST = 10.0 V, VDD = 1.8 V RST = 10.0 V, VDD = 13.6 V — 4 — — 20 30 Early Warning Reset Trigger (all power modes except Sleep) 1.8 1.85 1.9 1.7 1.75 1.8 VDD Ramp from 0–1.8 V — — 3 RST Input Low Voltage RST Input Pullup Current VDD Monitor Threshold (VRST) VDD Ramp Time for Power On µA V ms POR Monitor Threshold (VPOR) Brownout Condition (VDD Falling) 0.75 1.0 1.4 Recovery from Brownout (VDD Rising) — 1.75 — Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation 100 650 1000 µs Minimum System Clock w/ Missing Clock Detector Enabled System clock frequency which triggers a missing clock detector timeout — 7 10 kHz — 10 — µs Minimum RST Low Time to Generate a System Reset 15 — — µs VDD Monitor Turn-on Time — 300 — ns VDD Monitor Supply  Current — 7 — µA Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 Rev. 1.3 V 57 C8051F99x-C8051F98x Table 4.5. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Conditions Min Typ Max Units 2 — 3 SYSCLKs — 400 — ns — 2 — µs Idle Mode Wake-up Time Suspend Mode Wake-up Time CLKDIV = 0x00 Low Power or Precision Osc. Sleep Mode Wake-up Time Table 4.6. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Flash Size Conditions Min Typ Max Units C8051F980/1/6/7, C8051F990/1/6/7 8192 — — bytes C8051F982/3/8/9 4096 — — bytes C8051F985 2048 — — bytes 20 k 100k — Erase/Write Cycles Erase Cycle Time 28 32 36 ms Write Cycle Time 57 64 71 µs Endurance Table 4.7. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions Min Typ Max Units –40 to +85 °C, VDD = 1.8–3.6 V 24 24.5 25 MHz 25 °C; includes bias current of 90–100 µA — 300* — µA *Note: Does not include clock divider or clock tree supply current. Table 4.8. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions Min Typ Max Units –40 to +85 °C, VDD = 1.8–3.6 V 18 20 22 MHz 25 °C No separate bias current required — 100* — µA *Note: Does not include clock divider or clock tree supply current. 58 Rev. 1.3 C8051F99x-C8051F98x Table 4.9. SmaRTClock Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency (LFO) Conditions Min 13.1 Typ 16.4 Max 19.7 Units kHz Table 4.10. ADC0 Electrical Characteristics VDD = 1.8 to 3.6 V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Parameter Conditions DC Accuracy Min Typ Max 12 10 Units Resolution 12-bit mode 10-bit mode bits Integral Nonlinearity 12-bit mode1 10-bit mode — — ±1 ±0.5 ±1.5 ±1 LSB Differential Nonlinearity (Guaranteed Monotonic) 12-bit mode1 10-bit mode — — ±0.8 ±0.5 ±1 ±1 LSB Offset Error 12-bit mode 10-bit mode — — ±