C8051F99X_10

C8051F99x-C8051F98x Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU Ultra Low Power Consumption - 150 µA/MHz in active mode (24.5 MHz clock) - 2 µs wakeup time - 10 nA sleep mode with memory retention - 50 nA sleep mode with brownout detector - 300 nA sleep mode with LFO - 600 nA sleep mode with external crystal Supply Voltage 1.8 to 3.6 V - Built-in LDO regulator allows a high analog supply voltage and low digital core voltage - 2 built-in supply monitors (brownout detector) for sleep mode and active modes 12-Bit or 10-Bit Analog to Digital Converter - ±1 LSB INL (10-bit mode); ±1.5 LSB INL  (12-bit mode) no missing codes - Programmable throughput up to 300 ksps  (10-bit mode) or 75 ksps (12-bit mode) - Up to 10 external inputs - On-chip voltage reference; 0.5x gain allows measuring voltages up to twice the reference voltage - 16-bit auto-averaging accumulator with burst mode provides increased ADC resolution - Data dependent windowed interrupt generator - Built-in temperature sensor High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 512 bytes RAM - 8 kB (F990/1/6/7, F980/1/6/7), 4 kB (F982/3/8/9), or 2 kB (F985) Flash; in-system programmable Digital Peripherals - Up to 17 port I/O; high sink current and - programmable drive strength Hardware SMBus™/I2C™, SPI™, and UART serial ports available concurrently Four general purpose 16-bit counter/timers Programmable 16-bit counter/timer array with three capture/compare modules and watchdog timer Clock Sources - Internal oscillators: 24.5 MHz, 2% accuracy supports UART operation; 20 MHz low power oscillator requires very little bias current. External oscillator: Crystal, RC, C, or CMOS Clock SmaRTClock oscillator: 32 kHz Crystal or internal Can switch between clock sources on-the-fly; useful in implementing various power saving modes Capacitive Sense Interface (F99x) - Supports buttons, sliders, wheels, and capacitive Analog Comparator - Programmable hysteresis and response time - Configurable as wake-up or reset source 6-Bit Programmable Current Reference - Up to ±500 µA, can be used as a bias or for generating a custom reference voltage PWM enhanced resolution mode proximity sensing Fast 40 µs per channel conversion time 16-bit resolution, up to 14 input channels Auto scan and wake-on-touch Auto-accumulate up to 64x samples On-Chip Debug - On-chip debug circuitry facilitates full-speed, nonintrusive in-system debug (no emulator required) - Provides breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit Packages - 20-pin QFN (3 x 3 mm) - 24-pin QFN (4 x 4 mm) - 24-pin QSOP (easy to hand-solder) Temperature Range: –40 to +85 °C ANALOG PERIPHERALS A M U X DIGITAL I/O UART SM Bus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR 12/10-bit 75/300 ksps ADC VREF + I REF Port 1 TEM P SENSOR Capacitive Sense VREG – VOLTAG E COM PAR ATO R Port 2 24.5 M Hz PRECISION INTERNAL OSCILLATOR External Oscillator 20 MHz LOW POW ER INTERNAL OSCILLATOR HARDW ARE sm aRTClock HIGH-SPEED CONTROLLER CORE 8/4/2 kB ISP FLASH FLEXIBLE INTERRUPTS 8051 CPU (25 M IPS) D EBUG CIRCUITRY 512B SRAM POR W DT Rev. 1.0 11/10 Copyright © 2010 by Silicon Laboratories C8051F99x-C8051F98x C8051F99x-C8051F98x Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 25 1.2. Port Input/Output............................................................................................... 26 1.3. Serial Ports ....................................................................................................... 27 1.4. Programmable Counter Array ........................................................................... 27 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous  Low Power Burst Mode..................................................................................... 28 1.6. Programmable Current Reference (IREF0) ...................................................... 29 1.7. Comparator ....................................................................................................... 29 2. Ordering Information.............................................................................................. 31 3. Pinout and Package Definitions............................................................................ 32 4. Electrical Characteristics....................................................................................... 46 4.1. Absolute Maximum Specifications .................................................................... 46 4.2. Electrical Characteristics................................................................................... 47 5. SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode................................................................... 64 5.1. Output Code Formatting ................................................................................... 65 5.2. Modes of Operation .......................................................................................... 66 5.2.1. Starting a Conversion............................................................................... 66 5.2.2. Tracking Modes........................................................................................ 67 5.2.3. Burst Mode ............................................................................................... 68 5.2.4. Settling Time Requirements ..................................................................... 69 5.2.5. Gain Setting.............................................................................................. 70 5.3. 8-Bit Mode......................................................................................................... 70 5.4. 12-Bit Mode (C8051F980/6 and C8051F990/6 devices only)........................... 70 5.5. Low Power Mode .............................................................................................. 70 5.6. Programmable Window Detector ...................................................................... 78 5.6.1. Window Detector In Single-Ended Mode ................................................. 80 5.6.2. ADC0 Specifications................................................................................. 80 5.7. ADC0 Analog Multiplexer.................................................................................. 81 5.8. Temperature Sensor ......................................................................................... 83 5.8.1. Calibration ................................................................................................ 84 5.9. Voltage and Ground Reference Options........................................................... 86 5.10.External Voltage Reference.............................................................................. 87 5.11.Internal Voltage Reference............................................................................... 87 5.12.Analog Ground Reference................................................................................ 87 5.13.Temperature Sensor Enable ............................................................................ 87 5.14.Voltage Reference Electrical Specifications ..................................................... 88 6. Programmable Current Reference (IREF0) .......................................................... 89 6.1. PWM Enhanced Mode ...................................................................................... 89 2 Rev. 1.0 C8051F99x-C8051F98x 6.2. IREF0 Specifications......................................................................................... 90 7. Comparator ............................................................................................................. 91 7.1. Comparator Inputs ............................................................................................ 91 7.2. Comparator Outputs ......................................................................................... 92 7.3. Comparator Response Time............................................................................. 92 7.4. Comparator Hysteresis ..................................................................................... 92 7.5. Comparator Register Descriptions.................................................................... 93 7.6. Comparator0 Analog Multiplexer ...................................................................... 96 8. Capacitive Sense (CS0).......................................................................................... 98 8.1. Configuring Port Pins as Capacitive Sense Inputs ........................................... 99 8.2. Initializing the Capacitive Sensing Peripheral ................................................... 99 8.3. Capacitive Sense Start-Of-Conversion Sources............................................... 99 8.4. CS0 Multiple Channel Enable ......................................................................... 100 8.5. CS0 Gain Adjustment ..................................................................................... 100 8.6. Wake from Suspend ....................................................................................... 100 8.7. Using CS0 in Applications that Utilize Sleep Mode......................................... 100 8.8. Automatic Scanning (Method 1—CS0SMEN = 0) .......................................... 101 8.9. Automatic Scanning (Method 2—CS0SMEN = 1) .......................................... 102 8.10.CS0 Comparator............................................................................................. 102 8.11.CS0 Conversion Accumulator ........................................................................ 103 8.12.CS0 Pin Monitor ............................................................................................. 104 8.13.Adjusting CS0 For Special Situations............................................................. 105 8.14.Capacitive Sense Multiplexer ......................................................................... 116 9. CIP-51 Microcontroller ......................................................................................... 118 9.1. Performance ................................................................................................... 118 9.2. Programming and Debugging Support ........................................................... 119 9.3. Instruction Set ................................................................................................. 119 9.3.1. Instruction and CPU Timing ................................................................... 119 9.4. CIP-51 Register Descriptions.......................................................................... 124 10. Memory Organization........................................................................................... 127 10.1.Program Memory............................................................................................ 128 10.1.1.MOVX Instruction and Program Memory ............................................... 128 10.2.Data Memory .................................................................................................. 128 10.2.1.Internal RAM .......................................................................................... 128 10.2.2.External RAM ......................................................................................... 129 11. On-Chip XRAM...................................................................................................... 130 11.1.Accessing XRAM............................................................................................ 130 11.1.1.16-Bit MOVX Example ........................................................................... 130 11.1.2.8-Bit MOVX Example ............................................................................. 130 12. Special Function Registers ................................................................................. 131 12.1.SFR Paging .................................................................................................... 132 13. Interrupt Handler .................................................................................................. 137 13.1.Enabling Interrupt Sources ............................................................................. 137 13.2.MCU Interrupt Sources and Vectors............................................................... 137 13.3.Interrupt Priorities ........................................................................................... 138 Rev. 1.0 3 C8051F99x-C8051F98x 13.4.Interrupt Latency............................................................................................. 138 13.5.Interrupt Register Descriptions ....................................................................... 140 13.6.External Interrupts INT0 and INT1.................................................................. 147 14. Flash Memory ....................................................................................................... 149 14.1.Programming the Flash Memory .................................................................... 149 14.1.1.Flash Lock and Key Functions ............................................................... 149 14.1.2.Flash Erase Procedure .......................................................................... 150 14.1.3.Flash Write Procedure ........................................................................... 150 14.2.Non-volatile Data Storage .............................................................................. 150 14.3.Security Options ............................................................................................. 151 14.4.Determining the Device Part Number at Run Time ........................................ 153 14.5.Flash Write and Erase Guidelines .................................................................. 155 14.5.1.VDD Maintenance and the VDD Monitor ................................................. 155 14.5.2.PSWE Maintenance ............................................................................... 156 14.5.3.System Clock ......................................................................................... 156 14.6.Minimizing Flash Read Current ...................................................................... 157 15. Power Management.............................................................................................. 161 15.1.Normal Mode .................................................................................................. 162 15.2.Idle Mode........................................................................................................ 163 15.3.Stop Mode ...................................................................................................... 163 15.4.Suspend Mode ............................................................................................... 164 15.5.Sleep Mode .................................................................................................... 164 15.6.Configuring Wakeup Sources......................................................................... 165 15.7.Determining the Event that Caused the Last Wakeup.................................... 165 15.8.Power Management Specifications ................................................................ 169 16. Cyclic Redundancy Check Unit (CRC0) ............................................................. 170 16.1.CRC Algorithm................................................................................................ 170 16.2.Preparing for a CRC Calculation .................................................................... 172 16.3.Performing a CRC Calculation ....................................................................... 172 16.4.Accessing the CRC0 Result ........................................................................... 172 16.5.CRC0 Bit Reverse Feature............................................................................. 177 17. Voltage Regulator (VREG0) ................................................................................. 178 17.1.Voltage Regulator Electrical Specifications .................................................... 178 18. Reset Sources....................................................................................................... 179 18.1.Power-On Reset ............................................................................................. 180 18.2.Power-Fail Reset ............................................................................................ 180 18.3.External Reset ................................................................................................ 182 18.4.Missing Clock Detector Reset ........................................................................ 182 18.5.Comparator0 Reset ........................................................................................ 183 18.6.PCA Watchdog Timer Reset .......................................................................... 183 18.7.Flash Error Reset ........................................................................................... 183 18.8.SmaRTClock (Real Time Clock) Reset .......................................................... 183 18.9.Software Reset ............................................................................................... 184 19. Clocking Sources ................................................................................................. 186 19.1.Programmable Precision Internal Oscillator ................................................... 187 4 Rev. 1.0 C8051F99x-C8051F98x 19.2.Low Power Internal Oscillator......................................................................... 187 19.3.External Oscillator Drive Circuit...................................................................... 187 19.3.1.External Crystal Mode............................................................................ 187 19.3.2.External RC Mode.................................................................................. 189 19.3.3.External Capacitor Mode........................................................................ 190 19.3.4.External CMOS Clock Mode .................................................................. 190 19.4.Special Function Registers for Selecting and Configuring the System Clock 191 20. SmaRTClock (Real Time Clock) .......................................................................... 195 20.1.SmaRTClock Interface ................................................................................... 196 20.1.1.SmaRTClock Lock and Key Functions................................................... 196 20.1.2.Using RTC0ADR and RTC0DAT to Access SmaRTClock  Internal Registers ................................................................................... 197 20.1.3.RTC0ADR Short Strobe Feature............................................................ 197 20.1.4.SmaRTClock Interface Autoread Feature .............................................. 197 20.1.5.RTC0ADR Autoincrement Feature......................................................... 198 20.2.SmaRTClock Clocking Sources ..................................................................... 201 20.2.1.Using the SmaRTClock Oscillator with a Crystal or  External CMOS Clock ............................................................................ 201 20.2.2.Using the SmaRTClock Oscillator in Self-Oscillate Mode...................... 202 20.2.3.Using the Low Frequency Oscillator (LFO) ............................................ 202 20.2.4.Programmable Load Capacitance.......................................................... 203 20.2.5.Automatic Gain Control (Crystal Mode Only) and SmaRTClock  Bias Doubling ......................................................................................... 204 20.2.6.Missing SmaRTClock Detector .............................................................. 206 20.2.7.SmaRTClock Oscillator Crystal Valid Detector ...................................... 206 20.3.SmaRTClock Timer and Alarm Function ........................................................ 206 20.3.1.Setting and Reading the SmaRTClock Timer Value .............................. 206 20.3.2.Setting a SmaRTClock Alarm ................................................................ 207 20.3.3.Software Considerations for using the SmaRTClock Timer and Alarm . 208 21. Port Input/Output.................................................................................................. 213 21.1.Port I/O Modes of Operation........................................................................... 214 21.1.1.Port Pins Configured for Analog I/O....................................................... 214 21.1.2.Port Pins Configured For Digital I/O....................................................... 214 21.1.3.Interfacing Port I/O to 5 V Logic ............................................................. 215 21.1.4.Increasing Port I/O Drive Strength ......................................................... 215 21.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 215 21.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 215 21.2.2.Assigning Port I/O Pins to Digital Functions........................................... 216 21.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 216 21.3.Priority Crossbar Decoder .............................................................................. 217 21.4.Port Match ...................................................................................................... 223 21.5.Special Function Registers for Accessing and Configuring Port I/O .............. 225 22. SMBus ................................................................................................................... 233 22.1.Supporting Documents ................................................................................... 234 22.2.SMBus Configuration...................................................................................... 234 Rev. 1.0 5 C8051F99x-C8051F98x 22.3.SMBus Operation ........................................................................................... 235 22.3.1.Transmitter vs. Receiver ........................................................................ 235 22.3.2.Arbitration............................................................................................... 235 22.3.3.Clock Low Extension.............................................................................. 236 22.3.4.SCL Low Timeout................................................................................... 236 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 236 22.4.Using the SMBus............................................................................................ 237 22.4.1.SMBus Configuration Register............................................................... 238 22.4.2.SMB0CN Control Register ..................................................................... 241 22.4.3.Hardware Slave Address Recognition ................................................... 244 22.4.4.Data Register ......................................................................................... 246 22.5.SMBus Transfer Modes.................................................................................. 247 22.5.1.Write Sequence (Master) ....................................................................... 247 22.5.2.Read Sequence (Master) ....................................................................... 248 22.5.3.Write Sequence (Slave) ......................................................................... 249 22.5.4.Read Sequence (Slave) ......................................................................... 250 22.6.SMBus Status Decoding................................................................................. 250 23. UART0.................................................................................................................... 255 23.1.Enhanced Baud Rate Generation................................................................... 256 23.2.Operational Modes ......................................................................................... 257 23.2.1.8-Bit UART ............................................................................................. 257 23.2.2.9-Bit UART ............................................................................................. 258 23.3.Multiprocessor Communications .................................................................... 258 24. Enhanced Serial Peripheral Interface (SPI0)...................................................... 263 24.1.Signal Descriptions......................................................................................... 264 24.1.1.Master Out, Slave In (MOSI).................................................................. 264 24.1.2.Master In, Slave Out (MISO).................................................................. 264 24.1.3.Serial Clock (SCK) ................................................................................. 264 24.1.4.Slave Select (NSS) ................................................................................ 264 24.2.SPI0 Master Mode Operation ......................................................................... 264 24.3.SPI0 Slave Mode Operation ........................................................................... 266 24.4.SPI0 Interrupt Sources ................................................................................... 267 24.5.Serial Clock Phase and Polarity ..................................................................... 267 24.6.SPI Special Function Registers ...................................................................... 269 25. Timers.................................................................................................................... 276 25.1.Timer 0 and Timer 1 ....................................................................................... 278 25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 278 25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 279 25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 280 25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 281 25.2.Timer 2 .......................................................................................................... 286 25.2.1.16-bit Timer with Auto-Reload................................................................ 286 25.2.2.8-bit Timers with Auto-Reload................................................................ 287 25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 288 25.3.Timer 3 .......................................................................................................... 292 6 Rev. 1.0 C8051F99x-C8051F98x 25.3.1.16-bit Timer with Auto-Reload................................................................ 292 25.3.2.8-Bit Timers with Auto-Reload ............................................................... 293 25.3.3.SmaRTClock/External Oscillator Capture Mode .................................... 294 26. Programmable Counter Array ............................................................................. 298 26.1.PCA Counter/Timer ........................................................................................ 299 26.2.PCA0 Interrupt Sources.................................................................................. 300 26.3.Capture/Compare Modules ............................................................................ 301 26.3.1.Edge-triggered Capture Mode................................................................ 302 26.3.2.Software Timer (Compare) Mode........................................................... 303 26.3.3.High-Speed Output Mode ...................................................................... 304 26.3.4.Frequency Output Mode ........................................................................ 304 26.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................. 305 26.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 308 26.4.Watchdog Timer Mode ................................................................................... 309 26.4.1.Watchdog Timer Operation .................................................................... 309 26.4.2.Watchdog Timer Usage ......................................................................... 310 26.5.Register Descriptions for PCA0...................................................................... 311 27. C2 Interface ........................................................................................................... 317 27.1.C2 Interface Registers.................................................................................... 317 27.2.C2 Pin Sharing ............................................................................................... 320 Document Change List............................................................................................. 321 Contact Information.................................................................................................. 322 Rev. 1.0 7 C8051F99x-C8051F98x List of Figures Figure 1.1. C8051F980 Block Diagram .................................................................... 18 Figure 1.2. C8051F981 Block Diagram .................................................................... 18 Figure 1.3. C8051F982 Block Diagram .................................................................... 19 Figure 1.4. C8051F983 Block Diagram .................................................................... 19 Figure 1.5. C8051F985 Block Diagram .................................................................... 20 Figure 1.6. C8051F986 Block Diagram .................................................................... 20 Figure 1.7. C8051F987 Block Diagram .................................................................... 21 Figure 1.8. C8051F988 Block Diagram .................................................................... 21 Figure 1.9. C8051F989 Block Diagram .................................................................... 22 Figure 1.10. C8051F990 Block Diagram .................................................................. 22 Figure 1.11. C8051F991 Block Diagram .................................................................. 23 Figure 1.12. C8051F996 Block Diagram .................................................................. 23 Figure 1.13. C8051F997 Block Diagram .................................................................. 24 Figure 1.14. Port I/O Functional Block Diagram ....................................................... 26 Figure 1.15. PCA Block Diagram.............................................................................. 27 Figure 1.16. ADC0 Functional Block Diagram.......................................................... 28 Figure 1.17. ADC0 Multiplexer Block Diagram ......................................................... 29 Figure 1.18. Comparator 0 Functional Block Diagram ............................................. 30 Figure 3.1. QFN-20 Pinout Diagram (Top View) ...................................................... 35 Figure 3.2. QFN-24 Pinout Diagram (Top View) ...................................................... 36 Figure 3.3. QSOP-24 Pinout Diagram (Top View).................................................... 37 Figure 3.4. QFN-20 Package Drawing ..................................................................... 38 Figure 3.5. Typical QFN-20 Landing Diagram.......................................................... 39 Figure 3.6. QFN-24 Package Drawing ..................................................................... 41 Figure 3.7. Typical QFN-24 Landing Diagram.......................................................... 42 Figure 3.8. QSOP-24 Package Diagram .................................................................. 44 Figure 3.9. QSOP-24 Landing Diagram ................................................................... 45 Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 50 Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 51 Figure 4.3. Typical VOH Curves, 1.8–3.6 V ............................................................. 53 Figure 4.4. Typical VOL Curves, 1.8–3.6 V .............................................................. 54 Figure 5.1. ADC0 Functional Block Diagram............................................................ 64 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 67 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 68 Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 69 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 80 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 80 Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 81 Figure 5.8. Temperature Sensor Transfer Function ................................................. 83 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.65 V) ..... 84 Figure 5.10. Voltage Reference Functional Block Diagram...................................... 86 Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 91 Figure 7.2. Comparator Hysteresis Plot ................................................................... 93 8 Rev. 1.0 C8051F99x-C8051F98x Figure 7.3. CP0 Multiplexer Block Diagram.............................................................. 96 Figure 8.1. CS0 Block Diagram ................................................................................ 98 Figure 8.2. Auto-Scan Example.............................................................................. 101 Figure 8.3. CS0 Multiplexer Block Diagram............................................................ 116 Figure 9.1. CIP-51 Block Diagram.......................................................................... 118 Figure 10.1. C8051F99x-C8051F98x Memory Map ............................................... 127 Figure 10.2. Flash Program Memory Map.............................................................. 128 Figure 14.1. Flash Program Memory Map (8 kB and smaller devices) .................. 151 Figure 15.1. C8051F99x-C8051F98x Power Distribution....................................... 162 Figure 16.1. CRC0 Block Diagram ......................................................................... 170 Figure 16.2. Bit Reverse Register .......................................................................... 177 Figure 18.1. Reset Sources.................................................................................... 179 Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 180 Figure 19.1. Clocking Sources Block Diagram ....................................................... 186 Figure 19.2. 25 MHz External Crystal Example...................................................... 188 Figure 20.1. SmaRTClock Block Diagram.............................................................. 195 Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 204 Figure 21.1. Port I/O Functional Block Diagram ..................................................... 213 Figure 21.2. Port I/O Cell Block Diagram ............................................................... 214 Figure 21.3. Peripheral Availability on Port I/O Pins............................................... 217 Figure 21.4. Crossbar Priority Decoder in Example Configuration  (No Pins Skipped) .............................................................................. 218 Figure 21.5. Crossbar Priority Decoder in Example Configuration  (4 Pins Skipped) ................................................................................ 218 Figure 22.1. SMBus Block Diagram ....................................................................... 233 Figure 22.2. Typical SMBus Configuration ............................................................. 234 Figure 22.3. SMBus Transaction ............................................................................ 235 Figure 22.4. Typical SMBus SCL Generation......................................................... 238 Figure 22.5. Typical Master Write Sequence ......................................................... 247 Figure 22.6. Typical Master Read Sequence ......................................................... 248 Figure 22.7. Typical Slave Write Sequence ........................................................... 249 Figure 22.8. Typical Slave Read Sequence ........................................................... 250 Figure 23.1. UART0 Block Diagram ....................................................................... 255 Figure 23.2. UART0 Baud Rate Logic .................................................................... 256 Figure 23.3. UART Interconnect Diagram .............................................................. 257 Figure 23.4. 8-Bit UART Timing Diagram............................................................... 257 Figure 23.5. 9-Bit UART Timing Diagram............................................................... 258 Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................... 259 Figure 24.1. SPI Block Diagram ............................................................................. 263 Figure 24.2. Multiple-Master Mode Connection Diagram ....................................... 265 Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram .......................................................................... 265 Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode  Connection Diagram .......................................................................... 266 Figure 24.5. Master Mode Data/Clock Timing ........................................................ 268 Rev. 1.0 9 C8051F99x-C8051F98x Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 268 Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 269 Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 273 Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 273 Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 274 Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 274 Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 279 Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 280 Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 281 Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 286 Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 287 Figure 25.6. Timer 2 Capture Mode Block Diagram ............................................... 288 Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 292 Figure 25.8. Timer 3 8-Bit Mode Block Diagram .................................................... 293 Figure 25.9. Timer 3 Capture Mode Block Diagram ............................................... 294 Figure 26.1. PCA Block Diagram............................................................................ 298 Figure 26.2. PCA Counter/Timer Block Diagram.................................................... 299 Figure 26.3. PCA Interrupt Block Diagram ............................................................. 300 Figure 26.4. PCA Capture Mode Diagram.............................................................. 302 Figure 26.5. PCA Software Timer Mode Diagram .................................................. 303 Figure 26.6. PCA High-Speed Output Mode Diagram............................................ 304 Figure 26.7. PCA Frequency Output Mode ............................................................ 305 Figure 26.8. PCA 8-Bit PWM Mode Diagram ......................................................... 306 Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ....................................... 307 Figure 26.10. PCA 16-Bit PWM Mode.................................................................... 308 Figure 26.11. PCA Module 2 with Watchdog Timer Enabled ................................. 309 Figure 27.1. Typical C2 Pin Sharing....................................................................... 320 10 Rev. 1.0 C8051F99x-C8051F98x List of Tables Table 2.1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 3.1. Pin Definitions for the C8051F99x-C8051F98x . . . . . . . . . . . . . . . . . . . 32 Table 3.2. QFN-20 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 3.3. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.4. QFN-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 3.5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 3.6. QSOP-24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 3.7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 4.1. Absolute Maximum Ratings .................................................................... 46 Table 4.2. Global Electrical Characteristics ............................................................. 47 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 52 Table 4.4. Reset Electrical Characteristics .............................................................. 55 Table 4.5. Power Management Electrical Specifications ......................................... 56 Table 4.6. Flash Electrical Characteristics .............................................................. 56 Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 56 Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 56 Table 4.9. SmaRTClock Characteristics .................................................................. 57 Table 4.10. ADC0 Electrical Characteristics ............................................................ 57 Table 4.11. Temperature Sensor Electrical Characteristics .................................... 58 Table 4.12. Voltage Reference Electrical Characteristics ....................................... 59 Table 4.13. IREF0 Electrical Characteristics ........................................................... 60 Table 4.14. Comparator Electrical Characteristics .................................................. 61 Table 4.15. VREG0 Electrical Characteristics ......................................................... 62 Table 4.16. Capacitive Sense Electrical Characteristics ......................................... 63 Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65 V High-Speed VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 8.1. Operation with Auto-scan and Accumulate . . . . . . . . . . . . . . . . . . . . . 103 Table 9.1. CIP-51 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 12.1. Special Function Register (SFR) Memory Map (Page 0x0) . . . . . . . . 131 Table 12.2. Special Function Register (SFR) Memory Map (Page 0xF) . . . . . . . . 132 Table 12.3. Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 13.1. Interrupt Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 14.1. Flash Security Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 15.1. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 16.1. Example 16-bit CRC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 19.1. Recommended XFCN Settings for Crystal Mode . . . . . . . . . . . . . . . . 188 Table 19.2. Recommended XFCN Settings for RC and C modes . . . . . . . . . . . . . 189 Table 20.1. SmaRTClock Internal Registers ......................................................... 196 Table 20.2. SmaRTClock Load Capacitance Settings . . . . . . . . . . . . . . . . . . . . . 203 Table 20.3. SmaRTClock Bias Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 21.1. Port I/O Assignment for Analog Functions . . . . . . . . . . . . . . . . . . . . . 215 Table 21.2. Port I/O Assignment for Digital Functions . . . . . . . . . . . . . . . . . . . . . . 216 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions . . 216 Rev. 1.0 11 C8051F99x-C8051F98x Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 243 Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 244 Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled  (EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Table 23.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 262 Table 23.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 262 Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA  Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Table 26.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . . 310 12 Rev. 1.0 C8051F99x-C8051F98x List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration . . . . . . . . . . . . . . . . . 74 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time . . . . . . . . . . . . . . 75 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time . . . . . . . . . . . . . . . . . . . . 76 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . . 77 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . . 77 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte . . . . . . . . . . . . . . . . . . 78 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte . . . . . . . . . . . . . . . . . . 78 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte . . . . . . . . . . . . . . . . . . . 79 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte . . . . . . . . . . . . . . . . . . . . 79 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select . . . . . . . . . . . . . . . . . . . . 82 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte . . . . . . . . . . . . . . . . . . . . . 85 SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte . . . . . . . . . . . . . . . . . . . . . . 85 SFR Definition 5.15. REF0CN: Voltage Reference Control . . . . . . . . . . . . . . . . . . . . . 88 SFR Definition 6.1. IREF0CN: Current Reference Control . . . . . . . . . . . . . . . . . . . . . . 89 SFR Definition 6.2. IREF0CF: Current Reference Configuration . . . . . . . . . . . . . . . . . 90 SFR Definition 7.1. CPT0CN: Comparator 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection . . . . . . . . . . . . . . . . . . . 95 SFR Definition 7.3. CPT0MX: Comparator0 Input Channel Select . . . . . . . . . . . . . . . . 97 SFR Definition 8.1. CS0CN: Capacitive Sense Control . . . . . . . . . . . . . . . . . . . . . . . 106 SFR Definition 8.2. CS0CF: Capacitive Sense Configuration . . . . . . . . . . . . . . . . . . . 107 SFR Definition 8.3. CS0DH: Capacitive Sense Data High Byte . . . . . . . . . . . . . . . . . 108 SFR Definition 8.4. CS0DL: Capacitive Sense Data Low Byte . . . . . . . . . . . . . . . . . . 108 SFR Definition 8.5. CS0SCAN0: Capacitive Sense Channel Scan Mask 0 . . . . . . . . 109 SFR Definition 8.6. CS0SCAN1: Capacitive Sense Channel Scan Mask 1 . . . . . . . . 109 SFR Definition 8.7. CS0SS: Capacitive Sense Auto-Scan Start Channel . . . . . . . . . 110 SFR Definition 8.8. CS0SE: Capacitive Sense Auto-Scan End Channel . . . . . . . . . . 110 SFR Definition 8.9. CS0THH: Capacitive Sense Comparator Threshold High Byte . . 111 SFR Definition 8.10. CS0THL: Capacitive Sense Comparator Threshold Low Byte . 111 SFR Definition 8.11. CS0MD1: Capacitive Sense Mode 1 . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 8.12. CS0MD2: Capacitive Sense Mode 2 . . . . . . . . . . . . . . . . . . . . . 113 SFR Definition 8.13. CS0MD3: Capacitive Sense Mode 3 . . . . . . . . . . . . . . . . . . . . . 114 SFR Definition 8.14. CS0PM: Capacitive Sense Pin Monitor . . . . . . . . . . . . . . . . . . . 115 SFR Definition 8.15. CS0MX: Capacitive Sense Mux Channel Select . . . . . . . . . . . . 117 SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 9.4. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 9.5. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 9.6. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 12.1. SFR Page: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SFR Definition 13.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Rev. 1.0 13 C8051F99x-C8051F98x SFR Definition 13.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 144 SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 145 SFR Definition 13.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 146 SFR Definition 13.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 148 SFR Definition 14.1. DEVICEID: Device Identification . . . . . . . . . . . . . . . . . . . . . . . . 153 SFR Definition 14.2. REVID: Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 14.3. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 158 SFR Definition 14.4. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 SFR Definition 14.5. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SFR Definition 14.6. FLWR: Flash Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SFR Definition 15.1. PMU0CF: Power Management Unit Configuration1,2,3 . . . . . . . . . . 166 SFR Definition 15.2. PMU0FL: Power Management Unit Flag1,2 . . . . . . . . . . . . . . . . . . . . 167 SFR Definition 15.3. PMU0MD: Power Management Unit Mode . . . . . . . . . . . . . . . . 168 SFR Definition 15.4. PCON: Power Management Control Register . . . . . . . . . . . . . . 169 SFR Definition 16.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 SFR Definition 16.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 SFR Definition 16.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 174 SFR Definition 16.4. CRC0AUTO: CRC0 Automatic Control . . . . . . . . . . . . . . . . . . . 175 SFR Definition 16.5. CRC0CNT: CRC0 Automatic Flash Sector Count . . . . . . . . . . . 176 SFR Definition 16.6. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SFR Definition 17.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . 178 SFR Definition 18.1. VDM0CN: VDD Supply Monitor Control . . . . . . . . . . . . . . . . . . 182 SFR Definition 18.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 SFR Definition 19.1. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SFR Definition 19.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 192 SFR Definition 19.3. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 193 SFR Definition 19.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key . . . . . . . . . . . . . . . . . . 199 SFR Definition 20.2. RTC0ADR: SmaRTClock Address . . . . . . . . . . . . . . . . . . . . . . 200 SFR Definition 20.3. RTC0DAT: SmaRTClock Data . . . . . . . . . . . . . . . . . . . . . . . . . 200 Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 209 Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 210 Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 211 Internal Register Definition 20.7. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 212 Internal Register Definition 20.8. ALARMn: SmaRTClock Alarm Programmed Value 212 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 220 SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 221 SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 222 SFR Definition 21.4. P0MASK: Port0 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 21.5. P0MAT: Port0 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SFR Definition 21.6. P1MASK: Port1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 224 SFR Definition 21.7. P1MAT: Port1 Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SFR Definition 21.8. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 14 Rev. 1.0 C8051F99x-C8051F98x SFR Definition 21.9. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SFR Definition 21.10. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 SFR Definition 21.11. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 227 SFR Definition 21.12. P0DRV: Port0 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 228 SFR Definition 21.13. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 21.14. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SFR Definition 21.15. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 SFR Definition 21.16. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 230 SFR Definition 21.17. P1DRV: Port1 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 21.18. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SFR Definition 21.19. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 232 SFR Definition 21.20. P2DRV: Port2 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . 232 SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 240 SFR Definition 22.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 22.3. SMB0ADR: SMBus Slave Address . . . . . . . . . . . . . . . . . . . . . . 245 SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask . . . . . . . . . . . . . . . . . 245 SFR Definition 22.5. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 SFR Definition 23.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 260 SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 261 SFR Definition 24.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 270 SFR Definition 24.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 SFR Definition 24.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 SFR Definition 25.1. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 SFR Definition 25.2. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 SFR Definition 25.3. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 SFR Definition 25.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 SFR Definition 25.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 SFR Definition 25.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SFR Definition 25.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 SFR Definition 25.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 290 SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 290 SFR Definition 25.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 SFR Definition 25.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 SFR Definition 25.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 296 SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 296 SFR Definition 25.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 SFR Definition 25.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 SFR Definition 26.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 SFR Definition 26.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 SFR Definition 26.3. PCA0PWM: PCA PWM Configuration . . . . . . . . . . . . . . . . . . . . 313 SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 314 SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 315 Rev. 1.0 15 C8051F99x-C8051F98x SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 315 SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 316 SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 316 C2 Register Definition 27.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 C2 Register Definition 27.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 318 C2 Register Definition 27.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 318 C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 319 C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 319 16 Rev. 1.0 C8051F99x-C8051F98x 1. System Overview C8051F99x-C8051F98x devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.          Ultra low power consumption in active and sleep modes. High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) 10-bit 300 ksps or 12-bit 75 ksps single-ended ADC with analog multiplexer 6-bit programmable current reference (resolution can be increased with PWM) Precision programmable 24.5 MHz internal oscillator with spread spectrum technology. 8 kB , 4 kB, or 2 kB of on-chip Flash memory 512 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware  Four general-purpose 16-bit timers  Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer function  On-chip power-on reset, VDD monitor, and temperature sensor  One on-chip voltage comparator  Up to 14 Capacitive Touch (QuickSense™) Inputs  Up to 17 Port I/O With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the C8051F99xC8051F98x devices are truly stand-alone system-on-a-chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are powered from the supply voltage. The C8051F99x-C8051F98x devices are available in 20-pin or 24-pin QFN or 24-pin QSOP packages. All package options are lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.9. Rev. 1.0 17 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X CP0 VDD VREF Temp Sensor GND + - IREF0 Port 2 Drivers 12-bit ADC System Clock Configuration P1.0 P1.1 Comparator Figure 1.1. C8051F980 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.2. C8051F981 Block Diagram 18 Rev. 1.0 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 4 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock SFR Bus Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X CP0 VDD VREF Temp Sensor GND + - IREF0 Port 2 Drivers 10-bit ADC Oscillator System Clock Configuration P1.0 P1.1 Comparator Figure 1.3. C8051F982 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 4 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.4. C8051F983 Block Diagram Rev. 1.0 19 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 2 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM CRC Engine VREG Digital Power SYSCLK Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Crossbar Control Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 VDD Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers P2.7/C2D GND GND GND CP0 + - P1.0 P1.1 Comparator System Clock Configuration Figure 1.5. C8051F985 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X CP0 VDD VREF Temp Sensor GND + - IREF0 Port 2 Drivers GND 12-bit ADC System Clock Configuration P1.0 P1.1 Comparator Figure 1.6. C8051F986 Block Diagram 20 Rev. 1.0 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers GND GND CP0 + - P1.0 P1.1 Comparator System Clock Configuration Figure 1.7. C8051F987 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 4 kB ISP Flash Program Memory 256 Byte SRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK SMBus SPI Crossbar Control Port 1 Drivers VDD Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X CP0 VDD VREF Temp Sensor GND + - IREF0 Port 2 Drivers GND 10-bit ADC System Clock Configuration P1.0 P1.1 Comparator Figure 1.8. C8051F988 Block Diagram Rev. 1.0 21 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 4 kB ISP Flash Program Memory 256 Byte SRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK SMBus SPI Crossbar Control Port 1 Drivers VDD Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers GND GND CP0 + - P1.0 P1.1 Comparator System Clock Configuration Figure 1.9. C8051F989 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Crossbar Control Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D VDD VREG CRC Engine Digital Power SYSCLK Precision 24.5 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X CP0 VDD VREF Temp Sensor GND + - IREF0 Port 2 Drivers 12-bit ADC 13-Channel Capacitance To Digital Converter System Clock Configuration P1.0 P1.1 Comparator Figure 1.10. C8051F990 Block Diagram 22 Rev. 1.0 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator GND GND XTAL1 XTAL2 XTAL3 XTAL4 Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers 13-Channel Capacitance To Digital Converter CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.11. C8051F991 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X CP0 VDD VREF Temp Sensor GND + - IREF0 Port 2 Drivers GND 12-bit ADC 14-Channel Capacitance To Digital Converter System Clock Configuration P1.0 P1.1 Comparator Figure 1.12. C8051F996 Block Diagram Rev. 1.0 23 C8051F99x-C8051F98x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8 kB ISP Flash Program Memory 256 Byte SRAM 256 Byte XRAM Port I/O Configuration Digital Peripherals UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI Port 1 Drivers Priority Crossbar Decoder Port 0 Drivers C2CK/RST Debug / Programming Hardware C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6 P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 P1.4 P1.5 P1.6/XTAL3 P1.7/XTAL4 P2.7/C2D CRC Engine VREG Digital Power SYSCLK VDD Crossbar Control Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 XTAL3 XTAL4 External Oscillator Circuit SmaRTClock Oscillator SFR Bus Analog Peripherals 6-bit IREF IREF0 Port 2 Drivers GND 14-Channel Capacitance To Digital Converter CP0 System Clock Configuration + - P1.0 P1.1 Comparator Figure 1.13. C8051F997 Block Diagram 24 Rev. 1.0 C8051F99x-C8051F98x 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F99x-C8051F98x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.1.3. Additional Features The C8051F99x-C8051F98x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Rev. 1.0 25 C8051F99x-C8051F98x 1.2. Port Input/Output Digital and analog resources are available through 16 or 17 I/O pins. Port pins are organized as three bytewide ports. Port pins P0.0–P1.7 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “27. C2 Interface” on page 317 for more details. The designer has complete control over which digital and analog functions are assigned to individual Port pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on page 217 for more information on the Crossbar. All Port I/Os can tolerate voltages up to the supply rail when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD supply. Port I/Os used for analog functions can operate up to the VDD supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 214 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. XBR0, XBR1, XBR2, PnSKIP Registers Port Match P0MASK, P0MAT P1MASK, P1MAT Priority Decoder 2 4 2 SMBus 4 External Interrupts EX0 and EX1 PnMDOUT, PnMDIN Registers Highest Priority UART SPI0 (Internal Digital Signals) P0.0 Digital Crossbar 8 P0 I/O Cells P0.7 P1.0 P1 I/O Cells P1.7* *P1.5 is not available on 20-pin devices. P2 I/O Cell P2.7 CP0 Output SYSCLK PCA 8 4 2 8 Lowest Priority T0, T1 P0 (Port Latches) 1 (P0.0-P0.7) 8 P1 (P1.0-P1.7) 1 P2 (P2.7) To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) Figure 1.14. Port I/O Functional Block Diagram 26 Rev. 1.0 C8051F99x-C8051F98x 1.3. Serial Ports The C8051F99x-C8051F98x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.4. Programmable Counter Array An on-chip programmable counter/timer array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of seven sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, the external oscillator clock source divided by 8, or the SmaRTClock divided by 8. Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SY S C LK /12 S Y S C L K /4 T im e r 0 O v e rflo w ECI SYSC LK E x te r n a l C lo c k / 8 S m a R T C lo c k /8 PCA CLO CK MUX 1 6 -B it C o u n te r/ T im e r C a p tu r e /C o m p a r e M o d u le0 C a p tu re /C o m p a re M o d u le1 C a p tu re / C o m p a re M o d u le 2 / W D T CEX0 CEX1 CEX2 ECI C ro s s b a r P o r t I/ O Figure 1.15. PCA Block Diagram Rev. 1.0 27 C8051F99x-C8051F98x 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode C8051F99x-C8051F98x devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximationregister (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without any additional CPU intervention. The ADC can sample the voltage at select GPIO pins (see Figure 1.17) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs include an on-chip temperature sensor, the VDD supply voltage, and the internal digital supply voltage. ADC0CN BURSTEN AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 AD0INT AD0EN VDD ADC0TK Burst Mode Logic Start Conversion AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 3 Overflow CNVSTR Input ADC0PWR From AMUX0 AIN+ SYSCLK REF ADC0H ADC ADC0L 10/12-Bit SAR 16-Bit Accumulator AD0WINT Window Compare Logic AMP0GN AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD08BE AD0TM 32 ADC0LTH ADC0LTL ADC0CF ADC0GTH ADC0GTL Figure 1.16. ADC0 Functional Block Diagram 28 Rev. 1.0 C8051F99x-C8051F98x ADC0MX AD0MX4 AD0MX3 AD0MX2 AD0MX1 AM0MX0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.2 P1.3 *P1.4 Temp Sensor Gain = 0.5 or 1 AIN+ Programmable Attenuator AMUX ADC0 Digital Supply VDD *Only available on 24-pin devices. Figure 1.17. ADC0 Multiplexer Block Diagram 1.6. Programmable Current Reference (IREF0) C8051F99x-C8051F98x devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.7. Comparator C8051F99x-C8051F98x devices include an on-chip programmable voltage comparator: Comparator 0 (CPT0) which is shown in Figure 1.18. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be used to directly sense capacitive touch switches. See Application Note AN338 for details on Capacitive Touch Switch sensing. Rev. 1.0 29 C8051F99x-C8051F98x CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer CP0MD0 CP0MD1 CP0RIE CP0FIE Px.x CP0 Rising-edge CP0 Falling-edge CPT0CN VDD CP0 Interrupt CPT0MD CP0 + Px.x Interrupt Logic + D SET CP0 Q D SET Q Px.x GND CLR Q CLR Q Crossbar (SYNCHRONIZER) CP0 - (ASYNCHRONOUS) CP0A Px.x Reset Decision Tree Figure 1.18. Comparator 0 Functional Block Diagram 30 Rev. 1.0 C8051F99x-C8051F98x 2. Ordering Information Table 2.1. Product Selection Guide Capacitive Touch (QuickSense™) Inputs ADC with internal voltage reference and temperature sensor Programmable Current Reference SMBus/I2C, UART, Enhanced SPI Analog to Digital Converter Inputs SmaRTClock Real Time Clock Programmable Counter Array Lead-free (RoHS Compliant) Ordering Part Number Analog Comparators Flash Memory (kB) Digital Port I/Os Timers (16-bit) MIPS (Peak) RAM (bytes) C8051F980-GM 25 C8051F981-GM 25 C8051F982-GM 25 C8051F983-GM 25 C8051F985-GM 25 C8051F986-GM 25 C8051F986-GU 25 8 8 4 4 2 8 8 8 8 4 4 4 4 8 8 8 8 8 8 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512                                       4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4  16 9  16 —  16 9  16 —  16 — 12-bit — — —      1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1       QFN-20 QFN-20 QFN-20 QFN-20 QFN-20 QFN-24 10-bit — — — — —  17 10 12-bit —   17 10 12-bit —   17 —  17 — — — — —  QSOP-24  QFN-24 C8051F987-GM 25 C8051F987-GU 25    QSOP-24  QFN-24 C8051F988-GM 25 C8051F988-GU 25  17 10 10-bit —   17 10 10-bit —   17 —  17 —  16 9  16 — — — — —  QSOP-24  QFN-24 C8051F989-GM 25 C8051F989-GU 25    QSOP-24    QFN-20 QFN-20 QFN-24 C8051F990-GM 25 C8051F991-GM 25 C8051F996-GM 25 C8051F996-GU 25 12-bit 13  — 13   17 10 12-bit 14   17 10 12-bit 14   17 —  17 — — — 14  14   QSOP-24  QFN-24 C8051F997-GM 25 C8051F997-GU 25  QSOP-24 Rev. 1.0 Package 31 C8051F99x-C8051F98x 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the C8051F99x-C8051F98x Pin Numbers Name ‘F980/1/2 ‘F986/7 ‘F986/7 ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU Type Description VDD GND RST/ 4 3, 12 5 3 2 6 6 5 9 P In G D I/O Power Supply Voltage. Must be 1.8 to 3.6 V. Required Ground. Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1 k to 5 k pullup to VDD is recommended. See Section “18. Reset Sources” on page 179 Section for a complete description. Clock signal for the C2 Debug Interface. Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O Section for a complete description. Bi-directional data signal for the C2 Debug Interface. Port 1.6. See Port I/O Section for a complete description. SmaRTClock Oscillator Crystal Input. See Section 20 for a complete description. Port 1.7. See Port I/O Section for a complete description. SmaRTClock Oscillator Crystal Output. See Section 20 for a complete description. C2CK P2.7/ 6 7 10 D I/O D I/O C2D P1.6/ XTAL3 P1.7/ XTAL4 P0.0/ 2 24 3 7 8 11 8 9 12 D I/O D I/O A In D I/O A Out D I/O or Port 0.0. See Port I/O Section for a complete description. A In A In External VREF Input. See Section “5.9. Voltage and Ground Reference Options” on page 86. VREF* *Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices. 32 Rev. 1.0 C8051F99x-C8051F98x Table 3.1. Pin Definitions for the C8051F99x-C8051F98x (Continued) Pin Numbers Name ‘F980/1/2 ‘F986/7 ‘F986/7 ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU Type Description P0.1/ 1 23 2 D I/O or Port 0.1. See Port I/O Section for a complete description. A In G Optional Analog Ground. See Section “5.9. Voltage and Ground Reference Options” on page 86. AGND* P0.2/ 20 22 1 XTAL1/ D I/O or Port 0.2. See Port I/O Section for a complete description. A In External Clock Input. This pin is the external oscillator A In return for a crystal or resonator. See Section “19. Clocking Sources” on page 186. D Out Buffered SmaRTClock oscillator output. RTCOUT P0.3/ 19 21 24 D I/O or Port 0.3. See Section “21. Port Input/Output” on A In page 213 for a complete description. A Out D In A In External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Section “19. Clocking Sources” on page 186 for complete details. Wake-up request signal to wake up external devices. XTAL2/ WAKEOUT P0.4/ 18 20 23 D Out D I/O or Port 0.4. See Section “21. Port Input/Output” on A In page 213 for a complete description. D Out UART TX Pin. See Section “21. Port Input/Output” on page 213. TX P0.5/ 17 19 22 D I/O or Port 0.5. See Section “21. Port Input/Output” on A In page 213 for a complete description. D In UART RX Pin. See Section “21. Port Input/Output” on page 213. RX *Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices. Rev. 1.0 33 C8051F99x-C8051F98x Table 3.1. Pin Definitions for the C8051F99x-C8051F98x (Continued) Pin Numbers Name ‘F980/1/2 ‘F986/7 ‘F986/7 ‘F983/5 ‘F988/9 ‘F988/9 ‘F990/1 ‘F996/7 ‘F996/7 -GM -GM -GU Type Description P0.6/ 16 18 21 D I/O or Port 0.6. See Section “21. Port Input/Output” on A In page 213 for a complete description. D In External Convert Start Input for ADC0. See Section “5.7. ADC0 Analog Multiplexer” on page 81 for a complete description. CNVSTR* P0.7/ IREF0 15 17 20 D I/O or Port 0.7. See Section “21. Port Input/Output” on A In page 213 for a complete description. A Out IREF0 Output. See IREF Section for complete description. D I/O or Port 1.0. See Section “21. Port Input/Output” on A In page 213 for a complete description. May also be used as SCK for SPI1. A In Comparator0 positive input. See Comparator Section for complete description. P1.0 14 16 19 CP0+ P1.1 13 15 18 D I/O or Port 1.1. See Section “21. Port Input/Output” on A In page 213 for a complete description. A In Comparator0 negative input. See Comparator Section for complete description. CP0P1.2 P1.3 P1.4 P1.5 11 10 — 9 14 13 12 11 17 16 15 14 D I/O or Port 1.2. See Section “21. Port Input/Output” on A In page 213 for a complete description. D I/O or Port 1.3. See Section “21. Port Input/Output” on A In page 213 for a complete description. D I/O or Port 1.4. See Section “21. Port Input/Output” on A In page 213 for a complete description. D I/O or Port 1.5. See Section “21. Port Input/Output” on A In page 213 for a complete description. *Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices. 34 Rev. 1.0 C8051F99x-C8051F98x P0.3/XTAL2/WAKEOUT P0.2/XTAL1/RTCOUT P0.5/RX P0.4/TX 20 19 18 1 P0.0/VREF* GND VDD RST/C2CK 2 3 4 5 6 17 16 15 14 13 12 11 P0.7/IREF0 P1.0/CP0+ P1.1/CP0GND C8051F980/1/2/3/5 C8051F990/1 -GM Top View GND (Optional Connection) P1.7/XTAL4 P1.6/XTAL3 2D 10 7 8 9 P1.5 P 2. *Note: S ignal only available on ‘F980, ‘F982 and ‘F990 devices. Figure 3.1. QFN-20 Pinout Diagram (Top View) Rev. 1.0 P1.3 7/ C P 0. 6/ C N .2 P1 VS TR * . P0 G A 1/ N D * 35 C8051F99x-C8051F98x P0.3/XTAL2/WAKEOUT P0.2/XTAL1/RTCOUT P0.1/AGND* P0.0/VREF* 24 23 22 21 20 N.C. GND VDD N.C. N.C. RST/C2CK 1 2 3 4 5 6 19 P0.5/RX P0.4/TX 18 P0.6/CNVSTR* P0.7/IREF0 P1.0/CP0+ P1.1/CP0P1.2 P1.3 C8051F986/7/8/9 C8051F996/7 -GM Top View GND (optional connection) 17 16 15 14 13 10 11 P1.5 P2.7/C2D P1.7/XTAL4 P1.6/XTAL3 N.C. * Note: S ignal only available on ‘F986, ‘F988, and ‘F996 devices. Figure 3.2. QFN-24 Pinout Diagram (Top View) 36 Rev. 1.0 P1.4 12 7 8 9 C8051F99x-C8051F98x P0.2/XTAL1/RTCOUT 1 24 P0.3/XTAL2/WAKEOUT P0.1/AGND* 2 23 P0.4/TX P0.0/VREF* 3 22 P0.5/RX C8051F986/7/8/9, C8051F996/7 - GU N.C. 4 21 P0.6/CNVSTR * GND 5 20 P0.7/IREF0 VDD 6 19 P1.0/CP0+ N.C. 7 18 P1.1/CP0- N.C. 8 17 P1.2 RST/C2CK P2.7/C2D P1.7/XTAL4 9 16 P1.3 10 11 15 14 P1.4 P1.5 P1.6/XTAL3 12 13 N.C. * Note: S ignal only available on ‘F986, ‘F988, and ‘F996 devices. Figure 3.3. QSOP-24 Pinout Diagram (Top View) Rev. 1.0 37 C8051F99x-C8051F98x   Figure 3.4. QFN-20 Package Drawing Table 3.2. QFN-20 Package Dimensions Dimension A A1 b c D D2 e E E2 Min 0.50 0.00 0.20 0.27 1.65 Typ 0.55 0.02 0.25 0.32 3.00 BSC 1.70 0.50 BSC 3.00 BSC 1.70 Max 0.60 0.05 0.30 0.37 1.75 Dimension f L L1 aaa bbb ccc ddd eee Min 0.35 0.00 — — — — Typ 2.53 BSC 0.40 — — — — — — Max 0.45 0.10 0.05 0.05 0.08 0.10 0.10 1.65 1.75 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 38 Rev. 1.0 C8051F99x-C8051F98x   Figure 3.5. Typical QFN-20 Landing Diagram Rev. 1.0 39 C8051F99x-C8051F98x Table 3.3. PCB Land Pattern Dimension D D2 e E E2 f GD GE W X Y ZE ZD Notes: Min 2.71 REF 1.60 0.50 BSC 2.71 REF 1.60 2.53 REF 2.10 2.10 — — 0.61 REF — — Max 1.80 1.80 — — 0.34 0.28 3.31 3.31 General 1. 2. 3. 4. All dimensions shown are in millimeters (mm) unless otherwise noted. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. This Land Pattern Design is based on IPC-SM-782 guidelines. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 40 Rev. 1.0 C8051F99x-C8051F98x Figure 3.6. QFN-24 Package Drawing Table 3.4. QFN-24 Package Dimensions Dimension A A1 b D D2 e E E2 2.55 2.55 Min 0.70 0.00 0.18 Typ 0.75 0.02 0.25 4.00 BSC 2.70 0.50 BSC 4.00 BSC 2.70 2.80 2.80 Max 0.80 0.05 0.30 Dimension L L1 aaa bbb ddd eee Z Y Min 0.30 0.00 — — — — — — Typ 0.40 — — — — — 0.24 0.18 Max 0.50 0.15 0.15 0.10 0.05 0.08 — — Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 41 C8051F99x-C8051F98x   Figure 3.7. Typical QFN-24 Landing Diagram 42 Rev. 1.0 C8051F99x-C8051F98x Table 3.5. PCB Land Pattern Dimension MIN MAX C1 C2 E X1 X2 Y1 Y2 Notes: 3.90 3.90 0.50 BSC 0.20 2.70 0.65 2.70 4.00 4.00 0.30 2.80 0.75 2.80 General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x2 array of 1.10 mm x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 1. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 43 C8051F99x-C8051F98x Figure 3.8. QSOP-24 Package Diagram Table 3.6. QSOP-24 Package Dimensions Dimension A A1 b c D E E1 e Min — 0.10 0.20 0.10 Typ — — — — 8.65 BSC. 6.00 BSC 3.90 BSC 0.635 BSC Max 1.75 0.25 0.30 0.25 Dimension L L2  aaa bbb ccc ddd 0º Min 0.40 Typ — 0.25 BSC — 0.20 0.18 0.10 0.10 8º Max 1.27 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-147, variation AE. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 44 Rev. 1.0 C8051F99x-C8051F98x   Figure 3.9. QSOP-24 Landing Diagram Table 3.7. PCB Land Pattern Dimension C E X Y Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. MIN 5.20 0.635 BSC 0.30 1.50 MAX 5.30 0.40 1.60 Rev. 1.0 45 C8051F99x-C8051F98x 4. 4.1. Electrical Characteristics Absolute Maximum Specifications Throughout the Electrical Characteristics chapter, “VDD” refers to the Supply Voltage. Table 4.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Port I/O Pin or RST with Respect to GND Voltage on VDD with Respect to GND Maximum Total Current through VDD or GND Maximum Current through RST or any Port Pin Maximum Total Current through all Port Pins Conditions Min –55 –65 –0.3 –0.3 — — — Typ — — — — — — — Max 125 150 VDD + 0.3 4.0 500 100 200 Units °C °C V V mA mA mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 46 Rev. 1.0 C8051F99x-C8051F98x 4.2. Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Supply Voltage (VDD) Minimum RAM Data  Retention Voltage1 SYSCLK (System Clock)2 TSYSH (SYSCLK High Time) TSYSL (SYSCLK Low Time) Specified Operating  Temperature Range IDD 3, 4, 5 Conditions not in sleep mode in sleep mode Min 1.8 — — 0 18 18 –40 Typ 2.4 1.4 0.3 — — — — Max 3.6 — 0.45 25 — — +85 Units V V MHz ns ns °C Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) VDD = 1.8–3.6 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency  Sensitivity 1, 3, 5 — — — — — — — 3.6 3.1 225 290 84 174 88 4.5 — — — — — — mA mA µA µA µA µA/MHz µA/MHz VDD = 1.8–3.6 V, T = 25 °C, F < 14 MHz (Flash oneshot active, see Section 14.6) VDD = 1.8–3.6 V, T = 25 °C, F > 14 MHz (Flash oneshot bypassed, see Section 14.6) Rev. 1.0 47 C8051F99x-C8051F98x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) — 1.8 3.0 VDD = 1.8–3.6 V, F = 24.5 MHz IDD4, 6 (includes precision oscillator current) VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency Sensitivity1,6 VDD = 1.8–3.6 V, T = 25 °C — — — — — — — — — — — — 1.4 145 180 82 67 77 0.60 0.70 0.80 0.80 0.90 1.00 — — — — — — — — — — — — Units mA mA µA µA µA µA/MHz µA µA Digital Supply Current—Suspend and Sleep Mode Digital Supply Current  VDD = 1.8–3.6 V (Suspend Mode) Digital Supply Current 1.8 V, T = 25 °C 3.0 V, T = 25 °C (Sleep Mode, SmaRTClock 3.6 V, T = 25 °C running, 32.768 kHz crystal) 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) Digital Supply Current 1.8 V, T = 25 °C (Sleep Mode, SmaRTClock 3.0 V, T = 25 °C running, internal LFO) 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) Digital Supply Current (Sleep Mode) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes VBAT supply monitor) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C — — — — — — 0.30 0.40 0.50 0.50 0.70 0.80 — — — — — — µA — — — — — — — — — — — — 0.05 0.07 0.08 0.20 0.24 0.28 0.005 0.01 0.02 0.15 0.19 0.23 — — — — — — — — — — — — µA Digital Supply Current (Sleep Mode, VBAT Supply Monitor Disabled) µA 48 Rev. 1.0 C8051F99x-C8051F98x Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Units Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. Includes oscillator and regulator supply current. 5. IDD can be estimated for frequencies < 14 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 84 µA. When using these numbers to estimate IDD for > 14 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 3.6 mA – (25 MHz – 20 MHz) x 0.088 mA/MHz = 3.16 mA assuming the same oscillator setting. 6. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 1.75 mA – (25 MHz – 5 MHz) x 0.067 mA/MHz = 0.41 mA. Rev. 1.0 49 C8051F99x-C8051F98x 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 Supply Current (uA) F < 14 MHz Oneshot Enabled F > 14 MHz Oneshot Bypassed < 150uA/MHz 152 uA/MHz 168 uA/MHz 180 uA/MHz 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Frequency (MHz) 15 16 17 18 19 20 21 22 23 24 25 184 uA/MHz 250 uA/MHz Figure 4.1. Active Mode Current (External CMOS Clock) 50 Rev. 1.0 C8051F99x-C8051F98x 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 Supply Current (uA) 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Frequency (MHz) 15 16 17 18 19 20 21 22 23 24 25 Figure 4.2. Idle Mode Current (External CMOS Clock) Rev. 1.0 51 C8051F99x-C8051F98x Table 4.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull Min VDD – 0.7 VDD – 0.1 Typ Max Units V Output High Voltage High Drive Strength, PnDRV.n = 1 — — See Chart — — VDD – 0.7 VDD – 0.1 — — — See Chart — — — V Output Low Voltage High Drive Strength, PnDRV.n = 1 IOL = 8.5 mA IOL = 10 µA IOL = 25 mA Low Drive Strength, PnDRV.n = 0 IOL = 1.4 mA IOL = 10 µA IOL = 4 mA Input High Voltage VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V Input Low Voltage VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V Input Leakage  Current Weak Pullup Off Weak Pullup On, VIN = 0 V, VDD = 1.8 V Weak Pullup On, Vin = 0 V, VDD = 3.6 V — — — VDD – 0.6 0.7 x VDD — — — — — — — See Chart — — — — — 4 20 0.6 0.1 — — — 0.6 0.3 x VDD ±1 — 35 — — — — — See Chart 0.6 0.1 — V V V V µA 52 Rev. 1.0 C8051F99x-C8051F98x Typical VOH (High Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 5 10 15 20 25 30 35 40 45 50 Load Current (mA) Typical VOH (Low Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V Figure 4.3. Typical VOH Curves, 1.8–3.6 V Rev. 1.0 53 C8051F99x-C8051F98x Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.4. Typical VOL Curves, 1.8–3.6 V 54 Rev. 1.0 C8051F99x-C8051F98x Table 4.4. Reset Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage Conditions IOL = 1.4 mA, VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V Min — VDD – 0.6 0.7 x VDD — — — — 1.8 1.7 — 0.45 — 100 Typ — — — — — 4 20 1.85 1.75 — 0.7 1.75 650 Max 0.6 — — 0.6 0.3 x VDD — 30 1.9 1.8 3 1.0 — 1000 Units V V V V V µA V RST Input Low Voltage VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V RST Input Pullup Current VDD Monitor Threshold (VRST) VDD Ramp Time for Power On POR Monitor Threshold (VPOR) Missing Clock Detector Timeout Minimum System Clock w/ Missing Clock Detector Enabled Reset Time Delay Minimum RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply  Current RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.6 V Early Warning Reset Trigger (all power modes except Sleep) VBAT Ramp from 0–1.8 V Brownout Condition (VDD Falling) Recovery from Brownout (VDD Rising) Time from last system clock rising edge to reset initiation System clock frequency which triggers a missing clock detector timeout Delay between release of any reset source and code execution at location 0x0000 ms V µs — 7 10 kHz — 10 — µs 15 — — — 300 7 — — — µs ns µA Rev. 1.0 55 C8051F99x-C8051F98x Table 4.5. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Conditions Min 2 Typ — 400 Max 3 — Units SYSCLKs ns CLKDIV = 0x00 Low Power or Precision Osc. — Sleep Mode Wake-up Time — 2 — µs Table 4.6. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Flash Size Conditions C8051F980/1/6/7, C8051F990/1/6/7 C8051F982/3/8/9 C8051F985 Min 8192 4096 2048 20 k 28 57 Typ — — — 100k 32 64 Max — — — — 36 71 Units bytes bytes bytes Erase/Write Cycles ms µs Endurance Erase Cycle Time Write Cycle Time Table 4.7. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C, VDD = 1.8–3.6 V 25 °C; includes bias current of 90–100 µA Min 24 — Typ 24.5 300* Max 25 — Units MHz µA *Note: Does not include clock divider or clock tree supply current. Table 4.8. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C, VDD = 1.8–3.6 V 25 °C No separate bias current required Min 18 Typ 20 Max 22 Units MHz — 100* — µA *Note: Does not include clock divider or clock tree supply current. 56 Rev. 1.0 C8051F99x-C8051F98x Table 4.9. SmaRTClock Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency (LFO) Conditions Min 13.1 Typ 16.4 Max 19.7 Units kHz Table 4.10. ADC0 Electrical Characteristics VDD = 1.8 to 3.6 V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Parameter Conditions DC Accuracy 12-bit mode 10-bit mode 12-bit mode1 10-bit mode 12-bit mode1 10-bit mode 12-bit mode 10-bit mode 12-bit mode2 10-bit mode — — — — — — — — Min Typ 12 10 ±1 ±0.5 ±0.8 ±0.5 ±