CY2SSTV857ZXI-32

CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Features Description • Operating frequency: 60 MHz to 230 MHz The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV857-32 to be used as a zero delay buffer. • Supports 400 MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs. • Power management control input • High-impedance outputs when input clock < 20 MHz • 2.6V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP and 40 QFN package • Industrial temperature of –40°C to 85°C • Conforms to JEDEC DDR specification Block Diagram Pin Configuration 3 2 Test and Powerdown Logic PD 37 AVDD 16 5 6 10 9 22 23 CLK CLK# 13 14 FBIN FBIN# 36 35 Y3 Y3# Y4 Y4# 1 48 VS S Y0 # 2 47 Y5 # Y5 Y0 3 46 VD D Q 4 45 VD D Q Y1 5 44 Y6 Y1 # 6 43 Y6 # VS S 7 42 VS S VS S 8 Y2 # 9 Y2 10 VD D Q 11 41 VS S 40 Y7 # 39 Y7 38 VD D Q 37 PD# 36 FB IN 46 47 Y5 Y5# VD D Q 12 CLK 13 44 43 Y6 Y6# C LK# 14 35 FB IN # VD D Q 15 34 VD D Q 39 Y7 Y7# Y8 Y8# AVD D 16 33 FB O U T # AVS S 17 32 FB O U T VS S 18 31 VS S Y3 # 19 30 Y8 # 40 PLL Y2 Y2# VS S CY2SSTV857-32 20 19 Y0 Y0# Y1 Y1# 29 30 27 26 32 33 Y9 Y9# FBOUT FBOUT# .......................... Document #: 38-07557 Rev. *E Page 1 of 8 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 Y3 20 29 Y8 VD D Q 21 28 VD D Q Y4 22 27 Y9 Y4 # 23 26 Y9 # VS S 24 25 VS S 1+(512) 416-9669 www.silabs.com CY2SSTV857 Y6# Y6 VDDQ Y5 Y5# Y0# Y0 VDDQ Y1 Y1# 40 QFN Package 40 39 38 37 36 35 34 33 32 31 30 Y7# 29 28 Y7 27 PD# 26 FBIN 6 25 FBIN# VDDQ 7 24 VDDQ AVDD 8 23 VDDQ AVSS VSS 9 22 FBOUT# VSS 1 Y2# Y2 2 3 VDDQ 4 CLK 5 CLK# 40 QFN CY2SSTV857-32 FBOUT Y8# Y8 VDDQ Y9 Y9# Y4# Y4 VDDQ y3 Y3# 10 11 12 13 14 15 16 17 18 19 20 21 VDDQ Pin Description Pin # 48 TSSOP Pin # 40 QFN Pin Name I/O[1] Pin Description Electrical Characteristics 13, 14 5,6 CLK, CLK# I Differential Clock Input. LV Differential Input 35 25 FBIN# I Feedback Clock Input. Connect to FBOUT# for Differential Input accessing the PLL. 36 26 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. 3, 5, 10, 20, 22 37,39,3,12,14 Y(0:4) O Clock Outputs. 2, 6, 9, 19, 23 36,40,2,11,15 Y#(0:4) O Clock Outputs. 27, 29, 39, 44, 46 17,19,29,32,34 Y(9:5) O Clock Outputs. 26, 30, 40, 43, 47 16,20,30,31,35 Y#(9:5) O Clock Outputs. 32 21 FBOUT O Feedback Clock Output. Connect to FBIN for Differential Outputs normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 33 22 FBOUT# O Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 37 27 PD# I Power Down Input. When PD# is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled Hi-Z and the PLL is powered down. 4, 11,12,15, 21, 28, 34, 38, 45 4,7,13,18,23,24, 28,33,38 VDDQ 2.6V Power Supply for Output Clock Buffers. 2.6V Nominal 16 8 AVDD 2.6V Power Supply for PLL. When VDDA is at 2.6V Nominal GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. Differential Outputs Differential Outputs 1, 7, 8, 18, 24, 25, 1,10 31, 41, 42, 48 VSS Common Ground. 0.0V Ground 17 AVSS Analog Ground. 0.0V Analog Ground 9 Note: 1. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin ( 66 MHz –75 – 75 ps f > 66 MHz –100 – 100 ps 1.5 3.5 7.5 ns 1.5 3.5 7.5 ns – – 100 ps –50 – 50 ps Test Mode only Error[14] Ordering Information Part Number Package Type Product Flow CY2SSTV857ZC–32 48-pin TSSOP Commercial, 0 to 70C CY2SSTV857ZC–32T 48-pin TSSOP–Tape and Reel Commercial, 0 to 70C 40-pin QFN Commercial, 0 to 70C 40-pin QFN–Tape and Reel Commercial, 0 to 70C CY2SSTV857ZI–32 48-pin TSSOP Industrial, –40 to 85C CY2SSTV857ZI–32T 48-pin TSSOP–Tape and Reel Industrial, –40 to 85C 40-pin QFN Industrial, –40 to 85C 40-pin QFN–Tape and Reel Industrial, –40 to 85C 48-pin TSSOP Commercial, 0 to 70C 48-pin TSSOP–Tape and Reel Commercial, 0 to 70C 40-pin QFN Commercial, 0 to 70C CY2SSTV857LFC–32[15] CY2SSTV857LFC–32T [15] [15] CY2SSTV857LFI–32 [15] CY2SSTV857LFI–32T Lead-Free CY2SSTV857ZXC–32 CY2SSTV857ZXC–32T [15] CY2SSTV857LFXC–32 [15] 40-pin QFN–Tape and Reel Commercial, 0 to 70C CY2SSTV857ZXI–32 48-pin TSSOP Industrial, –40 to 85C CY2SSTV857ZXI–32T 48-pin TSSOP–Tape and Reel Industrial, –40 to 85C CY2SSTV857LFXC–32T 857-32 0327L11 *SWR# Marketing Part Number Date Code and Fab Location Lot Code Figure 7. Actual Marking on the Device Notes: 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120/16 pF, as shown in Figure 5. 15. The ordering part number differs from the marking on the actual device. See Figure 7 for the actual marking on the device. ..........................Document #: 38-07557 Rev. *E Page 7 of 8 CY2SSTV85 Package Drawing and Dimension 48-lead (240-mil) TSSOP II Z4824 0.500[0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.33gms 5.994[0.236] 6.198[0.244] PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 25 48 12.395[0.488] 12.598[0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.500[0.020] BSC 0.851[0.033] 0.950[0.037] 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0.508[0.020] 0.762[0.030] 0°-8° 0.100[0.003] 0.200[0.008] SEATING PLANE 40-lead QFN 6 x 6 MM LF40A BOTTOM VIEW SIDE VIEW TOP VIEW 0.08[0.003] C 1.00[0.039] MAX. 5.90[0.232] 6.10[0.240] A 0.05[0.002] MAX. 0.80[0.031] MAX. 5.70[0.224] 5.80[0.228] 0.18[0.007] 0.28[0.011] 0.20[0.008] REF. 0.60[0.024] DIA. PIN1 ID 0.20[0.008] R. N N 1 1 2 2 0.45[0.018] 0.30[0.012] 0.50[0.020] 4.45[0.175] 4.55[0.179] 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0°-12° 0.50[0.020] C SEATING PLANE 0.24[0.009] 0.60[0.024] (4X) 4.45[0.175] 4.55[0.179] The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. ..........................Document #: 38-07557 Rev. *E Page 8 of 8