SI1001-C-GM

Si1000/1/2/3/4/5 Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver Ultra Low Power: 0.9 to 3.6 V Operation - Typical sleep mode current < 0.1 µA; retains state and Digital Peripherals - 19 or 16 port I/O plus 3 GPIO pins; Hardware enhanced D required) Built-in temperature sensor External conversion start input option Autonomous burst mode with 16-bit automatic averaging accumulator Dual Comparators - Programmable hysteresis and response time - Configurable as interrupt or reset source - Low current (< 0.5 µA) On-Chip Debug - On-chip debug circuitry facilitates full-speed, non-intrusive UART, SPI, and I2C serial ports available concurrently Low power 32-bit SmaRTClock Four general purpose 16-bit counter/timers; six channel programmable counter array (PCA) - fo r in-system debug (No emulator required) es ig ns - 10-Bit Analog to Digital Converter - Up to 300 ksps - Up to 18 external inputs - External pin or internal VREF (no external capacitor - Frequency range = 240–960 MHz Sensitivity = –121 dBm FSK, GFSK, and OOK modulation Max output power = +20 dBm (Si1000/1), +13 dBm (Si1002/3/4/5) RF power consumption - 18.5 mA receive - 18 mA @ +1 dBm transmit - 30 mA @ +13 dBm transmit - 85 mA @ +20 dBm transmit Data rate = 0.123 to 256 kbps Auto-frequency calibration (AFC) Antenna diversity and transmit/receive switch control Programmable packet handler TX and RX 64 byte FIFOs Frequency hopping capability On-chip crystal tuning - RAM contents over full supply range; fast wakeup of < 2 µs Less than 600 nA with RTC running Less than 1 µA with RTC running and radio state retained On-chip dc-dc converter allows operation down to 0.9 V. Two built-in brown-out detectors cover sleep and active modes N ew - EZRadioPRO® Transceiver - Provides breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instruc- m en de d Clock Sources - Precision internal oscillators: 24.5 MHz with ±2% accuracy tions in 1 or 2 system clocks - - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 4352 bytes internal data RAM (256 + 4096) - 64 kB (Si1000/2/4) or 32 kB (Si1001/3/5) flash; In-system Package - 42-pin LGA (5 x 7 mm) Temperature Range: –40 to +85 °C programmable in 1024-byte sectors—1024 bytes are reserved in the 64 kB devices N ot R ec A M U X Rev. 1.3 2/13 10-bit 300 ksps ADC TEMP SENSOR VREF VREG IREF + + – – VOLTAGE COMPARATORS DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR om ANALOG PERIPHERALS supports UART operation; spread-spectrum mode for reduced EMI; Low power 20 MHz internal oscillator External oscillator: Crystal, RC, C, CMOS clock SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate Can switch between clock sources on-the-fly; useful in implementing various power saving modes EZRadio PRO Serial Interface Port 1 LNA PA Mixer Port 2 PGA ADC 24.5 MHz PRECISION INTERNAL OSCILLATOR 20 MHz LOW POWER INTERNAL OSCILLATOR External Oscillator HARDWARE smaRTClock HIGH-SPEED CONTROLLER CORE 64/32 kB ISP FLASH FLEXIBLE INTERRUPTS EZRadioPRO (240–960 MHz) 8051 CPU (25 MIPS) DEBUG CIRCUITRY 4352 B SRAM POR Digital Modem PLL Delta Sigma Modulator Digital Logic OSC WDT Copyright © 2013 by Silicon Laboratories Si1000/1/2/3/4/5 N ot m en de d om ec R fo r N ew es ig ns D Si1000/1/2/3/4/5 2 Rev. 1.3 Si1000/1/2/3/4/5 Table of Contents N ot R ec om m en de d fo r N ew D es ig ns 1. System Overview ..................................................................................................... 17 1.1. Typical Connection Diagram ............................................................................. 21 1.2. CIP-51™ Microcontroller Core .......................................................................... 22 1.3. Port Input/Output ............................................................................................... 23 1.4. Serial Ports ........................................................................................................ 24 1.5. Programmable Counter Array............................................................................ 24 1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode................................................................ 25 1.7. Programmable Current Reference (IREF0)....................................................... 26 1.8. Comparators...................................................................................................... 26 2. Ordering Information ............................................................................................... 28 3. Pinout and Package Definitions ............................................................................. 29 4. Electrical Characteristics ........................................................................................ 40 4.1. Absolute Maximum Specifications..................................................................... 40 4.2. MCU Electrical Characteristics .......................................................................... 41 4.3. EZRadioPRO® Electrical Characteristics .......................................................... 66 4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 73 5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode ................................................................... 74 5.1. Output Code Formatting .................................................................................... 74 5.2. Modes of Operation ........................................................................................... 76 5.3. 8-Bit Mode ......................................................................................................... 81 5.4. Programmable Window Detector....................................................................... 88 5.5. ADC0 Analog Multiplexer .................................................................................. 91 5.6. Temperature Sensor.......................................................................................... 93 5.7. Voltage and Ground Reference Options ........................................................... 96 5.8. External Voltage References............................................................................. 97 5.9. Internal Voltage References .............................................................................. 97 5.10. Analog Ground Reference............................................................................... 97 5.11. Temperature Sensor Enable ........................................................................... 97 5.12. Voltage Reference Electrical Specifications .................................................... 98 6. Programmable Current Reference (IREF0)............................................................ 99 6.1. IREF0 Specifications ......................................................................................... 99 7. Comparators........................................................................................................... 100 7.1. Comparator Inputs........................................................................................... 100 7.2. Comparator Outputs ........................................................................................ 101 7.3. Comparator Response Time ........................................................................... 102 7.4. Comparator Hysteresis.................................................................................... 102 7.5. Comparator Register Descriptions .................................................................. 103 7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 107 8. CIP-51 Microcontroller........................................................................................... 110 8.1. Performance .................................................................................................... 110 8.2. Programming and Debugging Support ............................................................ 111 Rev. 1.3 3 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns 8.3. Instruction Set.................................................................................................. 111 8.4. CIP-51 Register Descriptions .......................................................................... 116 9. Memory Organization ............................................................................................ 119 9.1. Program Memory............................................................................................. 120 9.2. Data Memory ................................................................................................... 120 10. On-Chip XRAM ..................................................................................................... 122 10.1. Accessing XRAM........................................................................................... 122 10.2. Special Function Registers............................................................................ 123 11. Special Function Registers................................................................................. 124 11.1. SFR Paging ................................................................................................... 125 12. Interrupt Handler.................................................................................................. 130 12.1. Enabling Interrupt Sources ............................................................................ 130 12.2. MCU Interrupt Sources and Vectors.............................................................. 130 12.3. Interrupt Priorities .......................................................................................... 131 12.4. Interrupt Latency............................................................................................ 131 12.5. Interrupt Register Descriptions ...................................................................... 133 12.6. External Interrupts INT0 and INT1................................................................. 140 13. Flash Memory....................................................................................................... 142 13.1. Programming the Flash Memory ................................................................... 142 13.2. Non-volatile Data Storage ............................................................................. 144 13.3. Security Options ............................................................................................ 144 13.4. Determining the Device Part Number at Run Time ....................................... 146 13.5. Flash Write and Erase Guidelines ................................................................. 146 13.6. Minimizing Flash Read Current ..................................................................... 148 14. Power Management ............................................................................................. 152 14.1. Normal Mode ................................................................................................. 153 14.2. Idle Mode....................................................................................................... 154 14.3. Stop Mode ..................................................................................................... 154 14.4. Suspend Mode .............................................................................................. 155 14.5. Sleep Mode ................................................................................................... 155 14.6. Configuring Wakeup Sources........................................................................ 156 14.7. Determining the Event that Caused the Last Wakeup................................... 156 14.8. Power Management Specifications ............................................................... 158 15. Cyclic Redundancy Check Unit (CRC0)............................................................. 159 15.1. 16-bit CRC Algorithm..................................................................................... 159 15.2. 32-bit CRC Algorithm..................................................................................... 161 15.3. Preparing for a CRC Calculation ................................................................... 163 15.4. Performing a CRC Calculation ...................................................................... 163 15.5. Accessing the CRC0 Result .......................................................................... 163 15.6. CRC0 Bit Reverse Feature............................................................................ 167 16. On-Chip DC-DC Converter (DC0)........................................................................ 168 16.1. Startup Behavior............................................................................................ 169 16.2. High Power Applications ............................................................................ 170 16.3. Pulse Skipping Mode..................................................................................... 170 16.4. Enabling the DC-DC Converter ..................................................................... 170 4 Rev. 1.3 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns 16.5. Minimizing Power Supply Noise .................................................................... 172 16.6. Selecting the Optimum Switch Size............................................................... 172 16.7. DC-DC Converter Clocking Options .............................................................. 172 16.8. DC-DC Converter Behavior in Sleep Mode ................................................... 173 16.9. DC-DC Converter Register Descriptions ....................................................... 174 16.10. DC-DC Converter Specifications ................................................................. 176 17. Voltage Regulator (VREG0)................................................................................. 177 17.1. Voltage Regulator Electrical Specifications ................................................... 177 18. Reset Sources ...................................................................................................... 178 18.1. Power-On (VBAT Supply Monitor) Reset ...................................................... 179 18.2. Power-Fail (VDD_MCU Supply Monitor) Reset............................................. 180 18.3. External Reset ............................................................................................... 182 18.4. Missing Clock Detector Reset ....................................................................... 182 18.5. Comparator0 Reset ....................................................................................... 183 18.6. PCA Watchdog Timer Reset ......................................................................... 183 18.7. Flash Error Reset .......................................................................................... 183 18.8. SmaRTClock (Real Time Clock) Reset ......................................................... 183 18.9. Software Reset .............................................................................................. 183 19. Clocking Sources................................................................................................. 185 19.1. Programmable Precision Internal Oscillator .................................................. 186 19.2. Low Power Internal Oscillator........................................................................ 186 19.3. External Oscillator Drive Circuit..................................................................... 186 19.4. Special Function Registers for Selecting and Configuring the  System Clock................................................................................................. 190 20. SmaRTClock (Real Time Clock).......................................................................... 193 20.1. SmaRTClock Interface .................................................................................. 193 20.2. SmaRTClock Clocking Sources .................................................................... 200 20.3. SmaRTClock Timer and Alarm Function ....................................................... 204 21. Port Input/Output ................................................................................................. 210 21.1. Port I/O Modes of Operation.......................................................................... 211 21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 212 21.3. Priority Crossbar Decoder ............................................................................. 214 21.4. Port Match ..................................................................................................... 219 21.5. Special Function Registers for Accessing and Configuring Port I/O ............. 222 22. EZRadioPRO® Serial Interface (SPI1) ................................................................ 231 22.1. Signal Descriptions........................................................................................ 232 22.2. SPI Master Operation on the MCU Core Side............................................... 232 22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 232 22.4. EZRadioPRO Serial Interface Interrupt Sources ........................................... 235 22.5. Serial Clock Phase and Polarity .................................................................... 235 22.6. SPI Special Function Registers ..................................................................... 236 23. EZRadioPRO® 240–960 MHz Transceiver.......................................................... 242 23.1. EZRadioPRO Operating Modes .................................................................... 243 23.2. Interrupts ...................................................................................................... 246 23.3. System Timing............................................................................................... 247 Rev. 1.3 5 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns 23.4. Modulation Options........................................................................................ 254 23.5. Internal Functional Blocks ............................................................................. 259 23.6. Data Handling and Packet Handler ............................................................... 264 23.7. RX Modem Configuration .............................................................................. 272 23.8. Auxiliary Functions ........................................................................................ 272 23.9. Reference Design.......................................................................................... 285 23.10. Application Notes and Reference Designs .................................................. 287 23.11. Customer Support ....................................................................................... 287 23.12. Register Table and Descriptions ................................................................. 288 23.13. Required Changes to Default Register Values............................................ 290 24. SMBus................................................................................................................... 291 24.1. Supporting Documents .................................................................................. 292 24.2. SMBus Configuration..................................................................................... 292 24.3. SMBus Operation .......................................................................................... 292 24.4. Using the SMBus........................................................................................... 294 24.5. SMBus Transfer Modes................................................................................. 306 24.6. SMBus Status Decoding................................................................................ 309 25. UART0 ................................................................................................................... 314 25.1. Enhanced Baud Rate Generation.................................................................. 315 25.2. Operational Modes ........................................................................................ 316 25.3. Multiprocessor Communications ................................................................... 317 26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 322 26.1. Signal Descriptions........................................................................................ 323 26.2. SPI0 Master Mode Operation ........................................................................ 323 26.3. SPI0 Slave Mode Operation .......................................................................... 325 26.4. SPI0 Interrupt Sources .................................................................................. 326 26.5. Serial Clock Phase and Polarity .................................................................... 327 26.6. SPI Special Function Registers ..................................................................... 328 27. Timers ................................................................................................................... 335 27.1. Timer 0 and Timer 1 ...................................................................................... 337 27.2. Timer 2 .......................................................................................................... 345 27.3. Timer 3 .......................................................................................................... 351 28. Programmable Counter Array............................................................................. 357 28.1. PCA Counter/Timer ....................................................................................... 358 28.2. PCA0 Interrupt Sources................................................................................. 359 28.3. Capture/Compare Modules ........................................................................... 360 28.4. Watchdog Timer Mode .................................................................................. 368 28.5. Register Descriptions for PCA0..................................................................... 370 29. Device Specific Behavior .................................................................................... 376 29.1. Device Identification ...................................................................................... 376 30. C2 Interface .......................................................................................................... 377 30.1. C2 Interface Registers................................................................................... 377 30.2. C2 Pin Sharing .............................................................................................. 380 Document Change List.............................................................................................. 381 Contact Information................................................................................................... 382 6 Rev. 1.3 Si1000/1/2/3/4/5 List of Figures N ot R ec om m en de d fo r N ew D es ig ns Figure 1.1. Si1000 Block Diagram ........................................................................... 18 Figure 1.2. Si1001 Block Diagram ........................................................................... 18 Figure 1.3. Si1002 Block Diagram ........................................................................... 19 Figure 1.4. Si1003 Block Diagram ........................................................................... 19 Figure 1.5. Si1004 Block Diagram ........................................................................... 20 Figure 1.6. Si1005 Block Diagram ........................................................................... 20 Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example .................................... 21 Figure 1.8. Si1000/1 Antenna Diversity Application Example ................................. 21 Figure 1.9. Port I/O Functional Block Diagram ........................................................ 23 Figure 1.10. PCA Block Diagram ............................................................................. 24 Figure 1.11. ADC0 Functional Block Diagram ......................................................... 25 Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 26 Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 27 Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 27 Figure 3.1. Si100/1/2/3-E-GM2 Pinout Diagram (Top View) ................................... 33 Figure 3.2. Si1004/5-E-GM2 Pinout Diagram (Top View) ....................................... 34 Figure 3.3. LGA-42 Package Drawing (Si1000/1/2/3/4/5-E-GM2) ........................... 35 Figure 3.4. LGA-42 PCB Land Pattern Dimensions (Si1000/1/2/3/4/5-E-GM2) ...... 37 Figure 3.5. LGA-42 PCB Stencil and Via Placement ............................................... 39 Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 44 Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 45 Figure 4.3. Typical DC-DC Converter Efficiency  (High Current, VDD/DC+ = 2 V ............................................................. 46 Figure 4.4. Typical DC-DC Converter Efficiency  (High Current, VDD/DC+ = 3 V) ............................................................ 47 Figure 4.5. Typical DC-DC Converter Efficiency  (Low Current, VDD/DC+ = 2 V) ............................................................. 48 Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 49 Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 51 Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 52 Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 53 Figure 4.10. Typical VOL Curves, 1.8–3.6 V ........................................................... 54 Figure 4.11. Typical VOL Curves, 0.9–1.8 V ........................................................... 55 Figure 5.1. ADC0 Functional Block Diagram ........................................................... 74 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing  (BURSTEN = 0) ..................................................................................... 77 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 79 Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 80 Figure 5.5. ADC Window Compare Example: Right-Justified  Single-Ended Data ................................................................................ 90 Figure 5.6. ADC Window Compare Example: Left-Justified  Single-Ended Data ................................................................................ 90 Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 91 Rev. 1.3 7 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns Figure 5.8. Temperature Sensor Transfer Function ................................................ 93 Figure 5.9. Temperature Sensor Error with 1-Point Calibration  (VREF = 1.68 V) ..................................................................................... 94 Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 96 Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 100 Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 101 Figure 7.3. Comparator Hysteresis Plot ................................................................ 102 Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 107 Figure 8.1. CIP-51 Block Diagram ......................................................................... 110 Figure 9.1. Si1000/1/2/3/4/5 Memory Map ............................................................ 119 Figure 9.2. Flash Program Memory Map ............................................................... 120 Figure 13.1. Flash Program Memory Map ............................................................. 144 Figure 14.1. Si1000/1/2/3/4/5 Power Distribution .................................................. 153 Figure 15.1. CRC0 Block Diagram ........................................................................ 159 Figure 15.2. Bit Reverse Register ......................................................................... 167 Figure 16.1. DC-DC Converter Block Diagram ...................................................... 168 Figure 16.2. DC-DC Converter Configuration Options .......................................... 171 Figure 18.1. Reset Sources ................................................................................... 178 Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 179 Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 180 Figure 19.1. Clocking Sources Block Diagram ...................................................... 185 Figure 19.2. 25 MHz External Crystal Example ..................................................... 187 Figure 20.1. SmaRTClock Block Diagram ............................................................. 193 Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 202 Figure 21.1. Port I/O Functional Block Diagram .................................................... 210 Figure 21.2. Port I/O Cell Block Diagram .............................................................. 211 Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 215 Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 216 Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 231 Figure 22.2. SPI Timing ......................................................................................... 233 Figure 22.3. SPI Timing—READ Mode ................................................................. 233 Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 234 Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 234 Figure 22.6. Master Mode Data/Clock Timing ....................................................... 235 Figure 22.7. SPI Master Timing ............................................................................. 241 Figure 23.1. State Machine Diagram ..................................................................... 244 Figure 23.2. TX Timing .......................................................................................... 247 Figure 23.3. RX Timing .......................................................................................... 248 Figure 23.4. Frequency Deviation ......................................................................... 251 Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 253 Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 255 Figure 23.7. Direct Synchronous Mode Example .................................................. 258 Figure 23.8. Direct Asynchronous Mode Example ................................................ 258 Figure 23.9. Microcontroller Connections .............................................................. 259 Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 261 8 Rev. 1.3 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns Figure 23.11. FIFO Thresholds ............................................................................. 264 Figure 23.12. Packet Structure .............................................................................. 265 Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 266 Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 266 Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 267 Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 267 Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 269 Figure 23.18. Manchester Coding Example .......................................................... 269 Figure 23.19. Header ............................................................................................. 271 Figure 23.20. POR Glitch Parameters ................................................................... 272 Figure 23.21. General Purpose ADC Architecture ................................................ 275 Figure 23.22. Temperature Ranges using ADC8 .................................................. 277 Figure 23.23. WUT Interrupt and WUT Operation ................................................. 280 Figure 23.24. Low Duty Cycle Mode ..................................................................... 281 Figure 23.25. RSSI Value vs. Input Power ............................................................ 284 Figure 23.26. Si1002 Split RF TX/RX Direct-Tie  Reference Design—Schematic ....................................................... 285 Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 286 Figure 24.1. SMBus Block Diagram ...................................................................... 291 Figure 24.2. Typical SMBus Configuration ............................................................ 292 Figure 24.3. SMBus Transaction ........................................................................... 293 Figure 24.4. Typical SMBus SCL Generation ........................................................ 295 Figure 24.5. Typical Master Write Sequence ........................................................ 306 Figure 24.6. Typical Master Read Sequence ........................................................ 307 Figure 24.7. Typical Slave Write Sequence .......................................................... 308 Figure 24.8. Typical Slave Read Sequence .......................................................... 309 Figure 25.1. UART0 Block Diagram ...................................................................... 314 Figure 25.2. UART0 Baud Rate Logic ................................................................... 315 Figure 25.3. UART Interconnect Diagram ............................................................. 316 Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 316 Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 317 Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 318 Figure 26.1. SPI Block Diagram ............................................................................ 322 Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 324 Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode  Connection Diagram ......................................................................... 324 Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode  Connection Diagram ......................................................................... 325 Figure 26.5. Master Mode Data/Clock Timing ....................................................... 327 Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 328 Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 328 Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 332 Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 332 Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 333 Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 333 Rev. 1.3 9 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 338 Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 339 Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 340 Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 345 Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 346 Figure 27.6. Timer 2 Capture Mode Block Diagram .............................................. 347 Figure 27.7. Timer 3 16-Bit Mode Block Diagram ................................................. 351 Figure 27.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 352 Figure 27.9. Timer 3 Capture Mode Block Diagram .............................................. 353 Figure 28.1. PCA Block Diagram ........................................................................... 357 Figure 28.2. PCA Counter/Timer Block Diagram ................................................... 358 Figure 28.3. PCA Interrupt Block Diagram ............................................................ 359 Figure 28.4. PCA Capture Mode Diagram ............................................................. 361 Figure 28.5. PCA Software Timer Mode Diagram ................................................. 362 Figure 28.6. PCA High-Speed Output Mode Diagram ........................................... 363 Figure 28.7. PCA Frequency Output Mode ........................................................... 364 Figure 28.8. PCA 8-Bit PWM Mode Diagram ........................................................ 365 Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 366 Figure 28.10. PCA 16-Bit PWM Mode ................................................................... 367 Figure 28.11. PCA Module 5 with Watchdog Timer Enabled ................................ 368 Figure 29.1. Si100x Revision Information .............................................................. 376 Figure 30.1. Typical C2 Pin Sharing ...................................................................... 380 10 Rev. 1.3 Si1000/1/2/3/4/5 List of Tables N ot R ec om m en de d fo r N ew D es ig ns Table 2.1. Product Selection Guide ......................................................................... 28 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 .................................................. 29 Table 3.2. LGA-42 Package Dimensions (Si1000/1/2/3/4/5-E-GM2) ...................... 36 Table 3.3. LGA-42 PCB Land Pattern Dimensions (Si1000/1/2/3/4/5-E-GM2) ....... 38 Table 4.1. Absolute Maximum Ratings .................................................................... 40 Table 4.2. Global Electrical Characteristics ............................................................. 41 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 50 Table 4.4. Reset Electrical Characteristics .............................................................. 56 Table 4.5. Power Management Electrical Specifications ......................................... 57 Table 4.6. Flash Electrical Characteristics .............................................................. 57 Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 58 Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 58 Table 4.9. ADC0 Electrical Characteristics .............................................................. 59 Table 4.10. Temperature Sensor Electrical Characteristics .................................... 60 Table 4.11. Voltage Reference Electrical Characteristics ....................................... 60 Table 4.12. IREF0 Electrical Characteristics ........................................................... 61 Table 4.13. Comparator Electrical Characteristics .................................................. 62 Table 4.14. DC-DC Converter (DC0) Electrical Characteristics .............................. 64 Table 4.15. VREG0 Electrical Characteristics ......................................................... 65 Table 4.16. DC Characteristics ................................................................................ 66 Table 4.17. Synthesizer AC Electrical Characteristics ............................................ 67 Table 4.18. Receiver AC Electrical Characteristics ................................................. 68 Table 4.19. Transmitter AC Electrical Characteristics ............................................. 69 Table 4.20. Auxiliary Block Specifications ................................................................ 70 Table 4.21. Digital IO Specifications (nIRQ) ............................................................ 71 Table 4.22. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ........................ 71 Table 4.23. Absolute Maximum Ratings .................................................................. 72 Table 8.1. CIP-51 Instruction Set Summary .......................................................... 112 Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 124 Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 125 Table 11.3. Special Function Registers ................................................................. 126 Table 12.1. Interrupt Summary .............................................................................. 132 Table 13.1. Flash Security Summary .................................................................... 145 Table 14.1. Power Modes ...................................................................................... 152 Table 15.1. Example 16-bit CRC Outputs ............................................................. 160 Table 15.2. Example 32-bit CRC Outputs ............................................................. 162 Table 16.1. IPeak Inductor Current Limit Settings ................................................. 169 Table 19.1. Recommended XFCN Settings for Crystal Mode ............................... 187 Table 19.2. Recommended XFCN Settings for RC and C modes ......................... 188 Table 20.1. SmaRTClock Internal Registers ......................................................... 194 Table 20.2. SmaRTClock Load Capacitance Settings .......................................... 201 Table 20.3. SmaRTClock Bias Settings ................................................................ 203 Table 21.1. Port I/O Assignment for Analog Functions ......................................... 213 Rev. 1.3 11 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns Table 21.2. Port I/O Assignment for Digital Functions ........................................... 213 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 214 Table 22.1. Serial Interface Timing Parameters .................................................... 233 Table 22.2. SPI Timing Parameters ...................................................................... 241 Table 23.1. EZRadioPRO Operating Modes ......................................................... 243 Table 23.2. EZRadioPRO Operating Modes Response Time ............................... 244 Table 23.3. Frequency Band Selection ................................................................. 249 Table 23.4. Packet Handler Registers ................................................................... 268 Table 23.5. Minimum Receiver Settling Time ........................................................ 270 Table 23.6. POR Parameters ................................................................................ 273 Table 23.7. Temperature Sensor Range ............................................................... 276 Table 23.8. Antenna Diversity Control ................................................................... 283 Table 23.9. EZRadioPRO Internal Register Descriptions ...................................... 288 Table 24.1. SMBus Clock Source Selection .......................................................... 295 Table 24.2. Minimum SDA Setup and Hold Times ................................................ 296 Table 24.3. Sources for Hardware Changes to SMB0CN ..................................... 300 Table 24.4. Hardware Address Recognition Examples (EHACK = 1) ................... 301 Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) ....................................................................................... 310 Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) ....................................................................................... 312 Table 25.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator .............................................. 321 Table 25.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator ......................................... 321 Table 26.1. SPI Slave Timing Parameters ............................................................ 334 Table 27.1. Timer 0 Running Modes ..................................................................... 337 Table 28.1. PCA Timebase Input Options ............................................................. 358 Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA  Capture/Compare Modules ................................................................ 360 Table 28.3. Watchdog Timer Timeout Intervals1 ................................................... 369 12 Rev. 1.3 Si1000/1/2/3/4/5 List of Registers N ot R ec om m en de d fo r N ew D es ig ns SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 82 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 83 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 84 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 85 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 86 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 87 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 87 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 88 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 88 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 89 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 89 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 92 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 95 SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 95 SFR Definition 5.15. REF0CN: Voltage Reference Control .......................................... 98 SFR Definition 6.1. IREF0CN: Current Reference Control ........................................... 99 SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 103 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 104 SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 105 SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 106 SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 108 SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 109 SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 116 SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 116 SFR Definition 8.3. SP: Stack Pointer ......................................................................... 117 SFR Definition 8.4. ACC: Accumulator ....................................................................... 117 SFR Definition 8.5. B: B Register ................................................................................ 117 SFR Definition 8.6. PSW: Program Status Word ........................................................ 118 SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 123 SFR Definition 11.1. SFRPage: SFR Page ................................................................. 126 SFR Definition 12.1. IE: Interrupt Enable .................................................................... 134 SFR Definition 12.2. IP: Interrupt Priority .................................................................... 135 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 ............................................ 136 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 ............................................ 137 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 ............................................ 138 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 ............................................ 139 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration .............................................. 141 SFR Definition 13.1. PSCTL: Program Store R/W Control ......................................... 149 SFR Definition 13.2. FLKEY: Flash Lock and Key ...................................................... 150 SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 151 SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 151 SFR Definition 14.1. PMU0CF: Power Management Unit Configuration .................... 157 SFR Definition 14.2. PCON: Power Management Control Register ........................... 158 SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 164 Rev. 1.3 13 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 165 SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 165 SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 166 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 166 SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 167 SFR Definition 16.1. DC0CN: DC-DC Converter Control ........................................... 174 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration .................................. 175 SFR Definition 17.1. REG0CN: Voltage Regulator Control ........................................ 177 SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control .......................... 182 SFR Definition 18.2. RSTSRC: Reset Source ............................................................ 184 SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 190 SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 191 SFR Definition 19.3. OSCICL: Internal Oscillator Calibration ..................................... 191 SFR Definition 19.4. OSCXCN: External Oscillator Control ........................................ 192 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key .................................... 197 SFR Definition 20.2. RTC0ADR: SmaRTClock Address ............................................ 198 SFR Definition 20.3. RTC0DAT: SmaRTClock Data .................................................. 199 Internal Register Definition 20.4. RTC0CN: SmaRTClock Control ............................. 206 Internal Register Definition 20.5. RTC0XCN:  SmaRTClock Oscillator Control ...................................... 207 Internal Register Definition 20.6. RTC0XCF:  SmaRTClock Oscillator Configuration ............................ 208 Internal Register Definition 20.7. RTC0PIN:  SmaRTClock Pin Configuration ...................................... 208 Internal Register Definition 20.8. CAPTUREn:  SmaRTClock Timer Capture ........................................... 209 Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm  Programmed Value ......................................................... 209 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 .......................................... 217 SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 .......................................... 218 SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 .......................................... 219 SFR Definition 21.4. P0MASK: Port0 Mask Register .................................................. 220 SFR Definition 21.5. P0MAT: Port0 Match Register ................................................... 220 SFR Definition 21.6. P1MASK: Port1 Mask Register .................................................. 221 SFR Definition 21.7. P1MAT: Port1 Match Register ................................................... 221 SFR Definition 21.8. P0: Port0 .................................................................................... 223 SFR Definition 21.9. P0SKIP: Port0 Skip .................................................................... 223 SFR Definition 21.10. P0MDIN: Port0 Input Mode ...................................................... 224 SFR Definition 21.11. P0MDOUT: Port0 Output Mode ............................................... 224 SFR Definition 21.12. P0DRV: Port0 Drive Strength .................................................. 225 SFR Definition 21.13. P1: Port1 .................................................................................. 226 SFR Definition 21.14. P1SKIP: Port1 Skip .................................................................. 226 SFR Definition 21.15. P1MDIN: Port1 Input Mode ...................................................... 227 SFR Definition 21.16. P1MDOUT: Port1 Output Mode ............................................... 227 SFR Definition 21.17. P1DRV: Port1 Drive Strength .................................................. 228 14 Rev. 1.3 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns SFR Definition 21.18. P2: Port2 .................................................................................. 228 SFR Definition 21.19. P2SKIP: Port2 Skip .................................................................. 229 SFR Definition 21.20. P2MDIN: Port2 Input Mode ...................................................... 229 SFR Definition 21.21. P2MDOUT: Port2 Output Mode ............................................... 230 SFR Definition 21.22. P2DRV: Port2 Drive Strength .................................................. 230 SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 237 SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 238 SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 239 SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 240 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ...................................... 297 SFR Definition 24.2. SMB0CN: SMBus Control .......................................................... 299 SFR Definition 24.3. SMB0ADR: SMBus Slave Address ............................................ 302 SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask .................................. 302 SFR Definition 24.5. SMB0DAT: SMBus Data ............................................................ 305 SFR Definition 25.1. SCON0: Serial Port 0 Control .................................................... 319 SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 320 SFR Definition 26.7. SPI0CFG: SPI0 Configuration ................................................... 329 SFR Definition 26.8. SPI0CN: SPI0 Control ............................................................... 330 SFR Definition 26.9. SPI0CKR: SPI0 Clock Rate ....................................................... 331 SFR Definition 26.10. SPI0DAT: SPI0 Data ............................................................... 331 SFR Definition 27.1. CKCON: Clock Control .............................................................. 336 SFR Definition 27.2. TCON: Timer Control ................................................................. 341 SFR Definition 27.3. TMOD: Timer Mode ................................................................... 342 SFR Definition 27.4. TL0: Timer 0 Low Byte ............................................................... 343 SFR Definition 27.5. TL1: Timer 1 Low Byte ............................................................... 343 SFR Definition 27.6. TH0: Timer 0 High Byte ............................................................. 344 SFR Definition 27.7. TH1: Timer 1 High Byte ............................................................. 344 SFR Definition 27.8. TMR2CN: Timer 2 Control ......................................................... 348 SFR Definition 27.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 349 SFR Definition 27.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 349 SFR Definition 27.11. TMR2L: Timer 2 Low Byte ....................................................... 350 SFR Definition 27.12. TMR2H Timer 2 High Byte ....................................................... 350 SFR Definition 27.13. TMR3CN: Timer 3 Control ....................................................... 354 SFR Definition 27.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 355 SFR Definition 27.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 355 SFR Definition 27.16. TMR3L: Timer 3 Low Byte ....................................................... 356 SFR Definition 27.17. TMR3H Timer 3 High Byte ....................................................... 356 SFR Definition 28.1. PCA0CN: PCA Control .............................................................. 370 SFR Definition 28.2. PCA0MD: PCA Mode ................................................................ 371 SFR Definition 28.3. PCA0PWM: PCA PWM Configuration ....................................... 372 SFR Definition 28.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 373 SFR Definition 28.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 374 SFR Definition 28.6. PCA0H: PCA Counter/Timer High Byte ..................................... 374 SFR Definition 28.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 375 SFR Definition 28.8. PCA0CPHn: PCA Capture Module High Byte ........................... 375 Rev. 1.3 15 Si1000/1/2/3/4/5 N ot R ec om m en de d fo r N ew D es ig ns C2 Register Definition 30.1. C2ADD: C2 Address ...................................................... 377 C2 Register Definition 30.2. DEVICEID: C2 Device ID ............................................... 378 C2 Register Definition 30.3. REVID: C2 Revision ID .................................................. 378 C2 Register Definition 30.4. FPCTL: C2 Flash Programming Control ........................ 379 C2 Register Definition 30.5. FPDAT: C2 Flash Programming Data ............................ 379 16 Rev. 1.3 Si1000/1/2/3/4/5 1. System Overview         240–960 MHz EZRadioPRO® transceiver Single/Dual battery operation with on-chip dc-dc boost converter High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 300 ksps 23-channel single-ended ADC with analog multiplexer 6-bit programmable current reference Precision programmable 24.5 MHz internal oscillator with spread spectrum technology 64 kB or 32 kB of on-chip flash memory 4352 bytes of on-chip RAM D  es ig ns Si1000/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. N ew SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware  (SPI1 is dedicated for communication with the EZRadioPRO peripheral)  Four general-purpose 16-bit timers  Programmable counter/timer array (PCA) with six capture/compare modules and watchdog timer (WDT) function  On-chip power-on reset, VDD monitor, and temperature sensor fo r  Two on-chip voltage comparators with 18 touch sense inputs  19 or 22 port I/O (5 V tolerant except for GPIO_0, GPIO_1, and GPIO_2) With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the Si1000/1/2/3/4/5 devices are truly standalone system-on-a-chip solutions. The flash memory can be reprogrammed even incircuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. m en de d  The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. om Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The Si1000/1/2/3/4/5 are available in a 42-pin LGA package (lead-free and RoHS compliant). See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.6. N ot R ec The transceiver's extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. The advanced radio features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption. The transceivers digital receive architecture features a high-performance ADC and DSP-based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading, ensuring compliance with global regulations including FCC, ETSI, ARIB, and 802.15.4d regulations. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. Rev. 1.3 17 Si1000/1/2/3/4/5 64k Byte ISP Flash Program Memory 6-bit IREF 256 Byte SRAM C2D VDD VREF VREF CP0, CP0A CP1, CP1A XTAL3 XTAL4 RXp RXn LNA PGA ADC + - + - Comparators Transceiver Control Interface Digital Modem Delta Sigma Modulator Digital Logic UART External Oscillator Circuit Timers 0, 1, 2, 3 SmaRTClock Oscillator PCA/ WDT System Clock Configuration SMBus OSC Priority Crossbar Decoder SPI 0 fo r P0.3/XTAL2 AGC Mixer Digital Peripherals Low Power 20 MHz Oscillator P0.2/XTAL1 VDD VREF Temp Sensor GND SFR Bus Precision 24.5 MHz Oscillator TX A M U X 10-bit 300ksps ADC SYSCLK GND PA External CRC Engine VREG IREF0 Internal 4096 Byte XRAM RF XCVR (240-960 MHz, +20 dBm) es ig ns Debug / Programming Hardware C2CK/RST Analog Peripherals D Wake Reset CIP-51 8051 Controller Core N ew Power On Reset/PMU Port I/O Config 22 XIN XOUT ANALOG & DIGITAL I/O m en de d Figure 1.1. Si1000 Block Diagram Power On Reset/PMU Wake Reset C2CK/RST Debug / Programming Hardware CIP-51 8051 Controller Core Analog Peripherals 32k Byte ISP Flash Program Memory 6-bit IREF 256 Byte SRAM om C2D VDD N ot R ec GND XTAL4 VREF CP1, CP1A SFR Bus P0.2/XTAL1 VDD VREF Temp Sensor + - RXp RXn LNA PGA ADC + - Digital Peripherals Transceiver Control Interface Digital Modem Delta Sigma Modulator Digital Logic UART Timers 0, 1, 2, 3 SmaRTClock Oscillator PCA/ WDT SMBus SPI 0 Rev. 1.3 XIN XOUT OSC Priority Crossbar Decoder Figure 1.2. Si1001 Block Diagram 18 AGC Mixer GND Comparators External Oscillator Circuit System Clock Configuration TX A M U X CP0, CP0A Low Power 20 MHz Oscillator P0.3/XTAL2 XTAL3 VREF 10-bit 300ksps ADC SYSCLK Precision 24.5 MHz Oscillator PA External CRC Engine VREG IREF0 Internal 4096 Byte XRAM RF XCVR (240-960 MHz, +20 dBm) Port I/O Config 22 ANALOG & DIGITAL I/O Si1000/1/2/3/4/5 C2CK/RST 64k Byte ISP Flash Program Memory 6-bit IREF 256 Byte SRAM C2D VREF VREF CP0, CP0A CP1, CP1A XTAL3 XTAL4 RXp RXn LNA PGA ADC + - + - Comparators Transceiver Control Interface Digital Modem Delta Sigma Modulator Digital Logic UART External Oscillator Circuit Timers 0, 1, 2, 3 SmaRTClock Oscillator PCA/ WDT System Clock Configuration SMBus OSC Priority Crossbar Decoder SPI 0 fo r P0.3/XTAL2 AGC Mixer Digital Peripherals Low Power 20 MHz Oscillator P0.2/XTAL1 VDD VREF Temp Sensor GND SFR Bus Precision 24.5 MHz Oscillator TX A M U X 10-bit 300ksps ADC SYSCLK GND PA External CRC Engine VREG VDD IREF0 Internal 4096 Byte XRAM RF XCVR (240-960 MHz, +13 dBm) es ig ns Debug / Programming Hardware Analog Peripherals D Wake Reset CIP-51 8051 Controller Core N ew Power On Reset/PMU Port I/O Config 22 XIN XOUT ANALOG & DIGITAL I/O m en de d Figure 1.3. Si1002 Block Diagram Power On Reset/PMU Wake Reset C2CK/RST Debug / Programming Hardware CIP-51 8051 Controller Core Analog Peripherals 32k Byte ISP Flash Program Memory 6-bit IREF 256 Byte SRAM om C2D VDD N ot R ec GND XTAL4 VREF CP1, CP1A SFR Bus P0.2/XTAL1 VDD VREF Temp Sensor AGC RXp RXn LNA Mixer GND + - PGA ADC + - Comparators Digital Peripherals Transceiver Control Interface Digital Modem Delta Sigma Modulator Digital Logic UART External Oscillator Circuit Timers 0, 1, 2, 3 SmaRTClock Oscillator PCA/ WDT System Clock Configuration TX A M U X CP0, CP0A Low Power 20 MHz Oscillator P0.3/XTAL2 XTAL3 VREF 10-bit 300ksps ADC SYSCLK Precision 24.5 MHz Oscillator PA External CRC Engine VREG IREF0 Internal 4096 Byte XRAM RF XCVR (240-960 MHz, +13 dBm) XIN XOUT OSC Priority Crossbar Decoder SMBus SPI 0 Port I/O Config 22 ANALOG & DIGITAL I/O Figure 1.4. Si1003 Block Diagram Rev. 1.3 19 Si1000/1/2/3/4/5 6-bit IREF VREG Analog Power GND/DC- DC/DC Converter VREF VREF Digital Power CP0, CP0A SYSCLK CP1, CP1A SFR Bus XTAL3 XTAL4 AGC RXp RXn LNA Mixer PGA ADC + - + - Comparators Digital Peripherals Transceiver Control Interface Digital Modem Delta Sigma Modulator Digital Logic UART External Oscillator Circuit Timers 0, 1, 2, 3 SmaRTClock Oscillator PCA/ WDT XTAL1 XTAL2 VDD VREF Temp Sensor GND Low Power 20 MHz Oscillator GND TX A M U X 10-bit 300ksps ADC CRC Engine Precision 24.5 MHz Oscillator VBAT External System Clock Configuration SMBus OSC Priority Crossbar Decoder SPI 0 fo r VDD/DC+ PA Internal 4096 Byte XRAM C2D Power Net IREF0 es ig ns 64k Byte ISP Flash Program Memory RF XCVR (240-960 MHz) 256 Byte SRAM Debug / Programming Hardware C2CK/RST Analog Peripherals D Wake Reset CIP-51 8051 Controller Core N ew Power On Reset/PMU Port I/O Config 19 XIN XOUT ANALOG & DIGITAL I/O m en de d Figure 1.5. Si1004 Block Diagram Power On Reset/PMU Wake Reset C2CK/RST CIP-51 8051 Controller Core Analog Peripherals 32k Byte ISP Flash Program Memory 6-bit IREF 256 Byte SRAM Debug / Programming Hardware C2D om Power Net VDD/DC+ Analog Power ec GND/DC- VBAT DC/DC Converter N ot R GND XTAL1 XTAL2 XTAL3 XTAL4 VREG VREF VREF SFR Bus VDD VREF Temp Sensor + - Comparators Transceiver Control Interface PGA ADC Digital Modem Delta Sigma Modulator Digital Logic UART External Oscillator Circuit Timers 0, 1, 2, 3 SmaRTClock Oscillator PCA/ WDT SMBus System Clock Configuration SPI 0 Rev. 1.3 XIN XOUT OSC Priority Crossbar Decoder Figure 1.6. Si1005 Block Diagram 20 RXp RXn LNA + - Digital Peripherals Low Power 20 MHz Oscillator AGC Mixer GND CP0, CP0A CP1, CP1A TX A M U X 10-bit 300ksps ADC SYSCLK Precision 24.5 MHz Oscillator PA External CRC Engine Digital Power IREF0 Internal 4096 Byte XRAM RF XCVR (240-960 MHz) Port I/O Config 19 ANALOG & DIGITAL I/O Si1000/1/2/3/4/5 1.1. Typical Connection Diagram es ig ns The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference design is available from Silicon Laboratories applications support. For applications seeking improved performance in the presence of multipath fading, antenna diversity can be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support. supply voltage 1u L1 L2 L4 C3 VDD_MCU VDD_DIG Px.x XIN VDD_RF TX L3 C1 RFp C2 D 100n N ew 100p X1 30MHz nIRQ C8 XOUT C7 SDN C6 Si100x RXn GPIO2 VR_DIG GPIO1 L5 L6 GPIO0 ANT_A fo r C4 0.1 uF 0.1 uF C9 1u m en de d C5 Programmable load capacitors for X1 are integrated. L1-L6 and C1-C5 values depend on frequency band, antenna impedance, output power and supply voltage range. Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example Supply Voltage C2 VDD_RF VDD_MCU VDD_DIG Px.x TX C1 RXp Si100x RXn L4 GPIO2 C4 0.1 uF VR_DIG 4 C3 L2 GPIO1 5 3 L1 L3 nIRQ 1u XOUT 100 n XIN 100 p X1 30 MHz SDN C8 GPIO0 ec 6 2 R N ot C7 om TR & ANT-DIV Switch 1 C6 0.1 uF C9 C5 1u Programmable load capacitors for X1 are integrated. L1–L4 and C1–C5 values depend on frequency band, antenna impedance, output power, and supply voltage range. Figure 1.8. Si1000/1 Antenna Diversity Application Example Rev. 1.3 21 Si1000/1/2/3/4/5 1.2. CIP-51™ Microcontroller Core 1.2.1. Fully 8051 Compatible es ig ns The Si1000/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.2.2. Improved Throughput D The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. Clocks to Execute 1 2 2/3 3 Number of Instructions 26 50 5 14 N ew The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. 3/4 4 4/5 5 8 7 3 1 2 1 1.2.3. Additional Features fo r With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. m en de d The Si1000/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51, allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. om Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a watchdog timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. N ot R ec The internal oscillator factory is calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. 22 Rev. 1.3 Si1000/1/2/3/4/5 1.3. Port Input/Output es ig ns Digital and analog resources are available through 19 (Si1000/1/2/3) or 16 (Si1004/5) I/O pins. Three additional GPIO pins are available through the EZRadioPRO peripheral. Port pins are organized as three bytewide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P1.0, P1.1, P1.2, and P1.4 are dedicated for communication with the EZRadioPRO peripheral. P1.3 is not available. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “29. Device Specific Behavior” on page 376 for more details. D The designer has complete control over which digital and analog functions are assigned to individual port pins and is limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on page 214 for more information on the crossbar. Port Match P0MASK, P0MAT P1MASK, P1MAT fo r XBR0, XBR1, XBR2, PnSKIP Registers N ew All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog functions can operate up to the VDD_MCU supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 211 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. External Interrupts EX0 and EX1 Highest Priority m en de d Priority Decoder 4 Digital Crossbar CP0 CP1 Outputs ec 7 P0 (P0.0-P0.7) (Port Latches) R N ot 8 (P1.0-P1.7) 8 P2 P1.5 P1 I/O Cells (P2.0-P2.7) P1.6 P1.7 8 8 P1 P0 I/O Cells P0.7 8 2 T0, T1 8 4 SYSCLK PCA P0.0 2 SMBus om (Internal Digital Signals) SPI0 SPI1 Lowest Priority PnMDOUT, PnMDIN Registers 2 UART P2.0 P2 I/O Cell P2.6 P2.7 To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) No analog functionality available on P2.7 Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not internally or externally connected. P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3 Figure 1.9. Port I/O Functional Block Diagram Rev. 1.3 23 Si1000/1/2/3/4/5 1.4. Serial Ports es ig ns The Si1000/1/2/3/4/5 family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There is also a dedicated EZRadioPRO Serial Interface (SPI1) to allow communication with the EZRadioPRO peripheral. 1.5. Programmable Counter Array D An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. SYSCLK /12 SYSCLK /4 PCA CLOCK MUX 16 -Bit Counter/Timer m en de d Timer 0 Overflow ECI fo r N ew Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK External Clock /8 Capture/ Compare Module 1 Capture/ Compare Module 3 R N ot 24 Port I/O Figure 1.10. PCA Block Diagram Rev. 1.3 Capture/ Compare Module5 / WDT CEX5 Crossbar Capture/ Compare Module 4 CEX4 CEX3 ec Capture/ Compare Module 2 CEX2 CEX1 CEX0 ECI om Capture/ Compare Module 0 Si1000/1/2/3/4/5 1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode es ig ns Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically average the ADC results, providing an effective 11, 12, or 13-bit ADC result without any additional CPU intervention. D The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs include an on-chip temperature sensor, the VDD_MCU supply voltage, the VBAT supply voltage, and the internal digital supply voltage. AIN+ N ot AD0TM AMP0GN AD08BE AD0SC0 AD0SC1 AD0SC2 AD0SC3 AD0SC4 R ec AD0CM0 AD0CM1 AD0CM2 N ew 010 011 100 Timer 2 Overflow Timer 3 Overflow CNVSTR Input 16-Bit Accumulator REF om SYSCLK ADC ADC0CF AD0WINT AD0INT AD0BUSY 10-bit SAR AD0BUSY (W) Timer 0 Overflow ADC0L From AMUX0 Burst Mode Logic 000 001 ADC0LTH ADC0H ADC0PWR Start Conversion m en de d ADC0TK fo r VDD BURSTEN AD0EN ADC0CN AD0WINT ADC0LTL 32 Window Compare Logic ADC0GTH ADC0GTL Figure 1.11. ADC0 Functional Block Diagram Rev. 1.3 25 Si1000/1/2/3/4/5 es ig ns AD0MX4 AD0MX3 AD0MX2 AD0MX1 AM0MX0 ADC0MX P0.0 N ew D Programmable Attenuator AIN+ P2.6* AMUX Temp Sensor ADC0 Digital Supply m en de d VDD_MCU fo r Gain = 0. 5 or 1 *P1.0 – P1.4 are not available as device pins Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) om Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.8. Comparators R ec Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0), which is shown in Figure 1.13, and Comparator 1 (CPT1), which is shown in Figure 1.14. The two comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section “18. Reset Sources” on page 178 and Section “14. Power Management” on page 152 for details on reset sources and low power mode wake-up sources, respectively. N ot The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be used to directly sense capacitive touch switches. See Application Note “AN338: Capacitive Touch Sense Solution” for details on Capacitive Touch Switch sensing. 26 Rev. 1.3 CP0EN CP0OUT CP0RIF CP0FIF VDD es ig ns CPT0CN Si1000/1/2/3/4/5 CP0HYP1 CP0HYP0 CP0HYN1 CP0 Interrupt CP0HYN0 CPT0MD Analog Input Multiplexer CP0 Rising-edge CP0 Falling-edge D CP0FIE CP0RIE CP0MD1 CP0MD0 Px.x CP0 + Interrupt Logic CP0 N ew Px.x + SET D - CLR Px.x D Q Q SET CLR Q Q Crossbar (SYNCHRONIZER) GND CP0 - CP0A (ASYNCHRONOUS) fo r Reset Decision Tree Px.x m en de d Figure 1.13. Comparator 0 Functional Block Diagram CPT0CN CP1EN CP1OUT CP1RIF VDD CP1FIF CP1HYP1 CP1HYN0 CPT0MD CP1FIE CP1RIE Px.x CP1MD1 CP1MD0 om Analog Input Multiplexer ec CP1 Interrupt CP1HYP0 CP1HYN1 CP1 Rising-edge CP1 + Interrupt Logic Px.x CP1 + R N ot CP1 Falling-edge D - SET CLR Q Q D SET CLR Q Q Px.x Crossbar (SYNCHRONIZER) CP1 - GND (ASYNCHRONOUS) CP1A Reset Decision Tree Px.x Figure 1.14. Comparator 1 Functional Block Diagram Rev. 1.3 27 N ot m en de d om ec R 28 Rev. 1.3 N ew es ig ns D Package Lead-free (RoHS Compliant) Minimum Operating Voltage (Volts) Maximum Transmit Power Temperature Sensor Internal Voltage Reference 10-bit 300ksps ADC Digital Port I/Os (includes EZRadioPRO GPIOs) Programmable Counter Array Timers (16-bit) fo r Enhanced SPI (available for external communication) UART SMBus/I2C SmaRTClock Real Time Clock RAM (bytes) Flash Memory (kB) MIPS (Peak) Ordering Part Number Si1000/1/2/3/4/5 2. Ordering Information Table 2.1. Product Selection Guide Si1000-E-GM2 25 64 4352 P 1 1 1 4 P 22 P P P +20 dBm 1.8 P LGA-42 Si1001-E-GM2 25 32 4352 P 1 1 1 4 P 22 P P P +20 dBm 1.8 P LGA-42 Si1002-E-GM2 25 64 4352 P 1 1 1 4 P 22 P P P +13 dBm 1.8 P LGA-42 Si1003-E-GM2 25 32 4352 P 1 1 1 4 P 22 P P P +13 dBm 1.8 P LGA-42 Si1004-E-GM2 25 64 4352 P 1 1 1 4 P 19 P P P +13 dBm 0.9 P LGA-42 Si1005-E-GM2 25 32 4352 P 1 1 1 4 P 19 P P P +13 dBm 0.9 P LGA-42 Si1000/1/2/3/4/5 3. Pinout and Package Definitions Name Pin Number Type Description Si1000/1 Si1004/5 Si1002/3 es ig ns Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 VDD_MCU 38 — P In GND_MCU 37 — G VBAT — 41 P In Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in dual-cell battery mode. GND — 38 P In In dual-cell battery mode, this pin must be connected directly to ground. In one-cell applications, this pin should be connected directly to the negative battery terminal, which is not connected to the ground plane. DCEN — 40 P In VDD_MCU / DC+ — 39 P In P Out — om GND_MCU D DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to VBAT through a 0.68 µH inductor. In dual-cell battery mode, this pin must be connected directly to ground. m en de d G N ew G Required Ground for the entire MCU except for the  EZRadioPRO peripheral. fo r VBAT- Power Supply Voltage for the entire MCU except for the EZRadioPRO peripheral. Must be 1.8 to 3.6 V. 37 DC– G G Power Supply Voltage for the entire MCU except for the EZRadioPRO peripheral. Must be 1.8 to 3.6 V. This supply voltage is not required in low power sleep mode. This voltage must always be > VBAT. Positive output of the dc-dc converter. In single-cell battery mode, a 1uF ceramic capacitor is required between dc+ and dc–. This pin can supply power to external devices when operating in single-cell battery mode. In dual-cell battery mode, this pin must be connected directly to ground. DC-DC converter return current path. In one-cell mode, this pin must be connected to the ground plane. 16 16 P In Power Supply Voltage for the analog portion of the  EZRadioPRO peripheral. Must be 1.8 to 3.6 V. VDD_DIG 28 28 P In Power Supply Voltage for the digital portion of the  EZRadioPRO peripheral. Must be 1.8 to 3.6 V. 27 27 P Out 23 23 G R ec VDD_RF N ot VR_DIG GND_RF Regulated Output Voltage of the digital 1.7 V regulator for the EZRadioPRO peripheral. A 1 µF decoupling capacitor is required. Required Ground for the digital and analog portions of the EZRadioPRO peripheral. Rev. 1.3 29 Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Type Description 42 C2CK P2.7/ 40 1 C2D Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1–5 k pullup to VDD_MCU is recommended. See Reset Sources section for a complete description. D I/O Clock signal for the C2 Debug Interface. D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O section for a complete description. D I/O Bi-directional data signal for the C2 Debug Interface. 1 3 A In SmaRTClock Oscillator Crystal Input. See Section 20 for a complete description. XTAL4 42 2 A Out SmaRTClock Oscillator Crystal Output. See Section 20 for a complete description. P0.0 36 36 A In A Out 35 P0.2 35 34 34 ec R P0.3 N ot XTAL2 33 33 Optional Analog Ground. See VREF chapter. D I/O or Port 0.2. See Port I/O Section for a complete description. A In A In XTAL1 External VREF Input. Internal VREF Output. External VREF decoupling capacitors are recommended. See Voltage Reference section. D I/O or Port 0.1. See Port I/O Section for a complete description. A In G om AGND D I/O or Port 0.0. See Port I/O section for a complete description. A In m en de d P0.1 fo r XTAL3 VREF 30 D I/O D 39 N ew RST/ es ig ns Si1000/1 Si1004/5 Si1002/3 External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Oscillator section. D I/O or Port 0.3. See Port I/O Section for a complete description. A In A Out D In A In External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Oscillator section for complete details. Rev. 1.3 Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Pin Number Type Description Si1000/1 Si1004/5 Si1002/3 32 D I/O or Port 0.4. See Port I/O section for a complete description. A In D Out TX P0.5 31 31 D I/O or Port 0.5. See Port I/O section for a complete description. A In D In RX P0.6 30 30 UART RX Pin. See Port I/O section. D I/O or Port 0.6. See Port I/O section for a complete description. A In D In CNVSTR UART TX Pin. See Port I/O section. D 32 N ew P0.4 es ig ns Name External Convert Start Input for ADC0. See ADC0 section for a complete description. 29 D I/O or Port 0.7. See Port I/O section for a complete description. A In A Out IREF0 Output. See IREF section for complete description. P1.5 10 10 D I/O or Port 1.5. See Port I/O section for a complete description. A In P1.6 9 9 D I/O or Port 1.6. See Port I/O section for a complete description. A In P1.7 8 8 D I/O or Port 1.7. See Port I/O section for a complete description. A In P2.0 7 7 D I/O or Port 2.0. See Port I/O section for a complete description. A In P2.1 6 6 D I/O or Port 2.1. See Port I/O section for a complete description. A In om m en de d IREF0 fo r 29 P0.7 5 5 D I/O or Port 2.2. See Port I/O section for a complete description. A In P2.3 4 4 D I/O or Port 2.3. See Port I/O section for a complete description. A In P2.4 3 — D I/O or Port 2.4. See Port I/O section for a complete description. A In 2 — D I/O or Port 2.5. See Port I/O section for a complete description. A In 41 — D I/O or Port 2.6. See Port I/O section for a complete description. A In R ec P2.2 N ot P2.5 P2.6 Rev. 1.3 31 Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Type Description es ig ns Si1000/1 Si1004/5 Si1002/3 24 24 D I/O or General Purpose I/O controlled by the EZRadioPRO periphA I/O eral. May be configured through the EZRadioPRO registers to perform various functions including: Clock Output, FIFO D I/O or status, POR, Wake-Up Timer, Low Battery Detect, TRSW, A I/O AntDiversity control, etc. See the EZRadioPRO GPIO ConD I/O or figuration Registers for more information. A I/O GPIO_1 25 25 GPIO_2 26 26 nIRQ 11 11 DO EZRadioPRO peripheral interrupt status pin. Will be set low to indicate a pending EZRadioPRO interrupt event. See the EZRadioPRO Control Logic Registers for more details. This pin is an open-drain output with a 220 k internal pullup resistor. An external pull-up resistor is recommended. XOUT 12 12 AO EZRadioPRO peripheral crystal oscillator output. Connect to an external 30 MHz crystal or to an external clock source. If using an external clock source with no crystal, dc coupling with a nominal 0.8 VDC level is recommended with a minimum ac amplitude of 700 mVpp. Refer to AN417 for more details about using an external clock source. XIN 13 13 AI EZRadioPRO peripheral crystal oscillator input. Connect to an external 30 MHz crystal or leave floating if driving the XOUT pin with an external signal source. NC 14, 20, 22 14, 20, 22 SDN 15 15 DI EZRadioPRO peripheral shutdown pin. When driven to logic HIGH, the EZRadioPRO peripheral will be completely shut down and the contents of the EZRadioPRO registers will be lost. This pin should be driven to logic LOW during all other times; this pin should never be left floating. 17 17 AO EZRadioPRO peripheral transmit RF output pin. The PA output is an open-drain connection so the L-C match must supply (1.8 to 3.6 VDC) to this pin. RXp 18 18 AI RXn 19 19 AI EZRadioPRO peripheral differential RF input pins of the LNA. See application schematic for example matching network. ANT_A 21 21 DO EZRadioPRO peripheral TR switch control signal. om No Connect. May be left floating or tied to power or ground. N ot R ec TX m en de d fo r N ew D GPIO_0 32 Rev. 1.3 P2.6 P2.7/C2D RST/C2CK VDD_MCU GND_MCU P0.0/VREF 41 40 39 38 37 36 es ig ns XTAL4 42 Si1000/1/2/3/4/5 1 35 P0.1/AGND P2.5 2 34 P0.2/XTAL1 P2.4 3 33 P0.3/XTAL2 P2.3 4 32 P0.4/TX P2.2 5 P2.1 6 P2.0 7 P1.7 8 P1.6 9 P1.5 10 N ew P0.6/CNVSTR 29 P0.7/IREF0 28 VDD_DIG 27 VR_DIG 26 GPIO_2 25 GPIO_1 24 GPIO_0 13 23 GND_RF 14 22 N.C. fo r Si1000/1/2/3 Top View 11 12 16 17 18 19 20 21 VDD_RF TX RXp RXn N.C. ANT_A GND ec om N.C. 30 15 XIN P0.5/RX SDN XOUT 31 m en de d nIRQ D XTAL3 N ot R Figure 3.1. Si100/1/2/3-E-GM2 Pinout Diagram (Top View) Rev. 1.3 33 VBAT DCEN VDD_MCU/DC+ GND/VBAT- GND_MCU/DC- P0.0/VREF 41 40 39 38 37 36 1 35 P0.1/AGND XTAL4 2 34 P0.2/XTAL1 XTAL3 3 33 P2.3 4 P2.2 5 P2.1 6 P2.0 7 P1.7 8 P1.6 9 D P2.7/C2D P0.3/XTAL2 N ew m en de d fo r Si1004/5 Top View 32 P0.4/TX 31 P0.5/RX 30 P0.6/CNVSTR 29 P0.7/IREF0 28 VDD_DIG 27 VR_DIG 10 26 GPIO_2 nIRQ 11 25 GPIO_1 XOUT 12 24 GPIO_0 XIN 13 23 GND_RF N.C. 14 22 N.C. 15 16 17 18 19 20 21 SDN VDD_RF TX RXp RXn N.C. ANT_A GND Figure 3.2. Si1004/5-E-GM2 Pinout Diagram (Top View) R ec om P1.5 N ot 34 es ig ns RST/C2CK 42 Si1000/1/2/3/4/5 Rev. 1.3 m en de d fo r N ew D es ig ns Si1000/1/2/3/4/5 N ot R ec om Figure 3.3. LGA-42 Package Drawing (Si1000/1/2/3/4/5-E-GM2) Rev. 1.3 35 Si1000/1/2/3/4/5 Min Nom Max A 0.85 0.90 0.95 b 0.20 0.25 0.30 5.00 BSC. D1 3.15 D2 3.00 D3 4.40 e 0.50 BSC. E 7.00 BSC. E1 5.40 E2 6.40 E3 6.50 0.35 m en de d L fo r N ew D D Dimension es ig ns Table 3.2. LGA-42 Package Dimensions (Si1000/1/2/3/4/5-E-GM2) 0.40 0.45 L1 0.05 0.10 0.15 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 N ot R ec om Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 36 Rev. 1.3 Si1000/1/2/3/4/5 E1 X E2 fo r N ew E3 Y D (1.65) es ig ns D1 m en de d E D2 D3 N ot R ec om Figure 3.4. LGA-42 PCB Land Pattern Dimensions (Si1000/1/2/3/4/5-E-GM2) Rev. 1.3 37 Si1000/1/2/3/4/5 mm D1 3.15 D2 3.00 D3 4.40 E 0.50 E1 5.45 E2 6.40 E3 6.50 X 0.25 N ew D Dimension es ig ns Table 3.3. LGA-42 PCB Land Pattern Dimensions (Si1000/1/2/3/4/5-E-GM2) Y 0.50 N ot R ec om m en de d fo r Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. PCB Design 4. PCB design must ensure sufficient thermal relief for operation of the device. 5. Place vias in E-pad as shown in Figure 3.5. Solder Mask Design 6. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 7. Place ground pad openings as shown in Figure 3.5. 8. The stencil thickness should be 0.125 mm (5 mils). 9. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 10. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. Card Assembly 11. A No-Clean, Type-3 solder paste is recommended. 12. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 38 Rev. 1.3 N ew D es ig ns Si1000/1/2/3/4/5 2.420 Ø0.250 0.075 1.350 1.200 R ec om m en de d fo r 1.210 Center pad paste detail: R 0.25 N ot 1.11 1.11 Figure 3.5. LGA-42 PCB Stencil and Via Placement Rev. 1.3 39 Si1000/1/2/3/4/5 4. Electrical Characteristics es ig ns In sections 4.1 and 4.2, “VDD” refers to the VDD_MCU supply voltage on Si1000/1/2/3 devices and to the VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in these two sections do not apply to the EZRadioPRO peripheral. In sections 4.3 and 4.4, “VDD” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifications in these sections pertain to the EZRadioPRO peripheral. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Ambient Temperature under Bias Storage Temperature Min Typ –55 — Max Unit 125 °C D Test Condition N ew Parameter –65 — 150 °C –0.3 –0.3 — — 5.8 VDD + 3.6 V –0.3 –0.3 — — 2.0 4.0 V –0.3 — 4.0 V Maximum Total Current through VBAT, DCEN, VDD_MCU/DC+ or GND — — 500 mA Maximum Output Current Sunk by RST or any Px.x Pin — — 100 mA Maximum Total Current through all Px.x Pins — — 200 mA DC-DC Converter Output Power — — 110 mW All pins except TX, RXp, and RXn — — 2 kV TX, RXp, and RXn — — 1 kV All pins except TX, RXp, and RXn — — 150 V TX, RXp, and RXn — — 45 V Voltage on VBAT with respect to GND One-Cell Mode Two-Cell Mode om m en de d Voltage on VDD_MCU or VDD_MCU/DC+ with respect to GND VDD > 2.2 V VDD < 2.2 V fo r Voltage on any Px.x I/O Pin or RST with Respect to GND ec ESD (Human Body Model) N ot R ESD (Machine Model) Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 40 Rev. 1.3 Si1000/1/2/3/4/5 4.2. MCU Electrical Characteristics Table 4.2. Global Electrical Characteristics Parameter Test Condition es ig ns –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Min Typ Max Unit One-Cell Mode Two-Cell Mode 0.9 1.8 1.2 2.4 1.8 3.6 V Supply Voltage (VDD_MCU/DC+) One-Cell Mode Two-Cell Mode 1.8 1.8 1.9 2.4 3.6 3.6 V Minimum RAM Data  Retention Voltage1 VDD (not in Sleep Mode) VBAT (in Sleep Mode) — — 1.4 0.3 — 0.5 V 0 — 25 MHz 18 — — ns 18 — — ns –40 — +85 °C N ew SYSCLK (System Clock)2 D Battery Supply Voltage (VBAT) TSYSH (SYSCLK High Time) TSYSL (SYSCLK Low Time) fo r Specified Operating  Temperature Range Digital Supply Current—CPU Active (Normal Mode, fetching instructions from flash) IDD 3, 4, 5, 6, 7, 8 — 4.1 5.0 mA VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) — 3.5 — mA VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) — — 295 365 — — µA µA VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) — 90 — µA VDD = 1.8–3.6 V, T = 25 °C, F < 10 MHz (flash oneshot active, see 13.6) — 226 — µA/MHz VDD = 1.8–3.6 V, T = 25 °C, F > 10 MHz (flash oneshot bypassed, see 13.6) — 120 — µA/MHz Frequency Sensitivity3, 5, 6, N ot R ec IDD 7. 8 om m en de d VDD = 1.8–3.6 V, F = 24.5 MHz (includes precision oscillator current) Rev. 1.3 41 Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) Parameter Test Condition Min es ig ns –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Typ Max Unit Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from flash) 2.5 3.0 mA VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) — 1.8 — mA VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) — — VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) — VDD = 1.8–3.6 V, T = 25 °C D — 165 235 — — µA µA N ew IDD Frequency Sensitivity1,6,8 VDD = 1.8–3.6 V, F = 24.5 MHz (includes precision oscillator current) 84 — µA — 95 — µA/MHz — 77 — µA fo r IDD4, 6,7,8 Digital Supply Current—Suspend and Sleep Mode VDD = 1.8–3.6 V, two-cell mode m en de d Digital Supply Current6,7,8 (Suspend Mode) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and brownout detector) — — — — — — 0.61 0.76 0.87 1.32 1.62 1.93 — — — — — — µA Digital Supply Current8 (Sleep Mode) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes brownout detector) — — — — — — 0.06 0.09 0.14 0.77 0.92 1.23 — — — — — — µA N ot R ec om Digital Supply Current8 (Sleep Mode, SmaRTClock running) 42 Rev. 1.3 Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) Parameter Test Condition Min es ig ns –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Typ Max Unit m en de d fo r N ew D Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 128-byte flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 128-byte address boundaries. 4. Includes oscillator and regulator supply current. 5. IDD can be estimated for frequencies 10 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4.1 mA – (25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA. 6. The Supply Voltage is the voltage at the VDD_MCU pin, typically 1.8 to 3.6 V (default = 1.9 V). Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz – 5 MHz) x 0.095 mA/MHz = 0.6 mA. 7. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be estimated using the following equation: Supply Voltage  Supply Current (two-cell mode) VBAT Current (one-cell mode) = ----------------------------------------------------------------------------------------------------------------------------------DC-DC Converter Efficiency  VBAT Voltage N ot R ec om The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V. The Supply Current (two-cell mode) is the data sheet specification for supply current. The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V). The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5. 8. The EZRadioPRO peripheral is placed in Shutdown mode. Rev. 1.3 43 4200 F < 10 MHz Oneshot Enabled 4100 4000 F > 10 MHz Oneshot Bypassed 3900 3800 3700 3600 3500 3400 D < 170 µA/MHz 3300 3200 N ew 3100 3000 200 µA/MHz 2900 2800 2700 2600 215 µA/MHz fo r 2500 2400 2300 2200 2100 m en de d Supply Current (uA) es ig ns Si1000/1/2/3/4/5 2000 1900 1800 1700 1600 1500 1400 240 µA/MHz 1300 1200 1100 om 1000 900 250 µA/MHz 800 ec 700 600 500 R 400 300 300 µA/MHz 200 N ot 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (MHz) Figure 4.1. Active Mode Current (External CMOS Clock) 44 Rev. 1.3 21 22 23 24 25 Si1000/1/2/3/4/5 es ig ns Supply Current vs. Frequency 4200 4100 4000 3900 3800 3700 3600 D 3500 3400 3300 N ew 3200 3100 3000 2900 2800 2700 fo r 2600 2400 2300 2200 m en de d Supply Current (uA) 2500 2100 2000 1900 1800 1700 1600 1500 1400 1300 1100 1000 900 800 ec 700 om 1200 600 500 N ot R 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Frequency (MHz) Figure 4.2. Idle Mode Current (External CMOS Clock) Rev. 1.3 45 6:6(/  es ig ns Si1000/1/2/3/4/5 6:6(/      D   N ew      fo r    9%$7 9  m en de d Efficiency (%)        9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 X+,QGXFWRUSDFNDJH(65 2KPV 9'''& 90LQLPXP3XOVH:LGWK QV3XOVH6NLSSLQJ'LVDEOHG  om  1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ LQGXFWRUZLWKDORZHU(65   ec   R   N ot                           Load Current (mA) Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V 46 Rev. 1.3  Si1000/1/2/3/4/5 6:6(/  6:6(/  es ig ns       D   N ew     9%$7 9 fo r 9%$7 9 9%$7 9  9%$7 9  9%$7 9  9%$7 9 9%$7 9 m en de d Efficiency (%)     X+,QGXFWRUSDFNDJH(65 2KPV 9'''& 90LQLPXP3XOVH:LGWK QV 3XOVH6NLSSLQJ'LVDEOHG 1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\ FKRRVLQJDQLQGXFWRUZLWKDORZHU(65     om    ec   N ot R                        Load current (mA) Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) Rev. 1.3 47 es ig ns Si1000/1/2/3/4/5  D  N ew   fo r 9%$7 9    9%$7 9 9%$7 9 9%$7 9 9%$7 9 m en de d Efficiency (%)  9%$7 9 9%$7 9 om X+,QGXFWRUSDFNDJH(65 2KPV 6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV ec  N ot R                Load current (mA) Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) 48 Rev. 1.3  X+,QGXFWRUSDFNDJH(65 2KPV 6:6(/ 9'''& 9/RDG&XUUHQW X$   D  es ig ns Si1000/1/2/3/4/5 0LQ3XOVH:LGWKQV N ew  0LQ3XOVH:LGWKQV  0LQ3XOVH:LGWKQV 0LQ3XOVH:LGWKQV  fo r  m en de d 9%$7&XUUHQWX$      om   ec  N ot R             9%$79 Figure 4.6. Typical One-Cell Suspend Mode Current Rev. 1.3 49 Si1000/1/2/3/4/5 Table 4.3. Port I/O DC Electrical Characteristics Parameters Test Condition Typ VDD – 0.7 VDD – 0.1 — — See Chart — — — VDD – 0.7 — VDD – 0.1 See Chart — — — — — — See Chart 0.6 0.1 — — — — — — See Chart 0.6 0.1 — VDD = 2.0 to 3.6 V VDD – 0.6 — — V VDD = 0.9 to 2.0 V 0.7 x VDD — — V VDD = 2.0 to 3.6 V — — 0.6 V VDD = 0.9 to 2.0 V — — 0.3 x VDD V Weak Pullup On, VIN = 0 V, VDD = 1.8 V Weak Pullup On, Vin = 0 V, VDD = 3.6 V — — 4 20 — 30 µA D Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull — — — Input Low Voltage N ot R ec om Input Leakage  Current m en de d fo r Low Drive Strength, PnDRV.n = 0 IOL = 1.4 mA IOL = 10 µA IOL = 4 mA Input High Voltage 50 Rev. 1.3 Unit V Output High Voltage High Drive Strength, PnDRV.n = 1 IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Output Low Voltage High Drive Strength, PnDRV.n = 1 IOL = 8.5 mA IOL = 10 µA IOL = 25 mA Max es ig ns Min N ew VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. V Typical VOH (High Drive Mode) 3.6 VDD = 3.6V 3 VDD = 3.0V 2.7 VDD = 2.4V 2.4 VDD = 1.8V D Voltage 3.3 es ig ns Si1000/1/2/3/4/5 2.1 N ew 1.8 1.5 1.2 0.9 5 10 15 20 25 30 35 40 45 50 fo r 0 Load Current (mA) Typical VOH (Low Drive Mode) Voltage m en de d 3.6 3.3 VDD = 3.6V 3 VDD = 3.0V 2.7 VDD = 2.4V 2.4 VDD = 1.8V 2.1 om 1.8 1.5 N ot R ec 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) Figure 4.7. Typical VOH Curves, 1.8–3.6 V Rev. 1.3 51 Typical VOH (High Drive Mode) 1.8 1.7 VDD = 1.8V 1.6 VDD = 1.5V 1.5 1.4 VDD = 1.2V VDD = 0.9V 1.2 D Voltage 1.3 1.1 0.9 0.8 0.7 0.6 0.5 1 2 3 4 5 6 7 8 9 10 11 12 fo r 0 N ew 1 Load Current (mA) Typical VOH (Low Drive Mode) m en de d 1.8 1.7 VDD = 1.8V 1.6 VDD = 1.5V 1.5 1.4 VDD = 1.2V Voltage 1.3 1.2 VDD = 0.9V 1.1 1 om 0.9 0.8 0.7 0.5 0 1 2 3 Load Current (mA) N ot R ec 0.6 52 es ig ns Si1000/1/2/3/4/5 Figure 4.8. Typical VOH Curves, 0.9–1.8 V Rev. 1.3 Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V VDD = 2.4V D Voltage 1.2 es ig ns Si1000/1/2/3/4/5 VDD = 1.8V 0.9 N ew 0.6 0.3 0 -70 -60 -50 -40 -30 -20 -10 0 fo r -80 Load Current (mA) Typical VOL (Low Drive Mode) m en de d 1.8 VDD = 3.6V 1.5 VDD = 3.0V Voltage 1.2 VDD = 2.4V VDD = 1.8V 0.9 om 0.6 N ot R ec 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.9. Typical VOL Curves, 1.8–3.6 V Rev. 1.3 53 Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V VDD = 2.4V D Voltage 1.2 VDD = 1.8V 0.9 N ew 0.6 0.3 0 -70 -60 -50 -40 -30 -20 -10 0 fo r -80 Load Current (mA) Typical VOL (Low Drive Mode) m en de d 1.8 VDD = 3.6V 1.5 VDD = 3.0V Voltage 1.2 VDD = 2.4V VDD = 1.8V 0.9 om 0.6 N ot R ec 0.3 54 es ig ns Si1000/1/2/3/4/5 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.10. Typical VOL Curves, 1.8–3.6 V Rev. 1.3 Si1000/1/2/3/4/5 es ig ns Typical VOL (High Drive Mode) 0.5 VDD = 1.8V VDD = 1.5V VDD = 1.2V 0.3 D Voltage 0.4 VDD = 0.9V N ew 0.2 0.1 0 -4 -3 -2 -1 0 fo r -5 Load Current (mA) Typical VOL (Low Drive Mode) m en de d 0.5 0.3 VDD = 1.8V 0.2 VDD = 1.5V om Voltage 0.4 VDD = 1.2V VDD = 0.9V 0 -3 -2 -1 0 Load Current (mA) N ot R ec 0.1 Figure 4.11. Typical VOL Curves, 0.9–1.8 V Rev. 1.3 55 Si1000/1/2/3/4/5 Table 4.4. Reset Electrical Characteristics Min Typ Max Unit RST Output Low Voltage IOL = 1.4 mA, — — 0.6 V RST Input High Voltage VDD = 2.0 to 3.6 V VDD – 0.6 — — V VDD = 0.9 to 2.0 V 0.7 x VDD — — V VDD = 2.0 to 3.6 V — — 0.6 V VDD = 0.9 to 2.0 V — — 0.3 x VDD V RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.6 V — — 4 20 — 30 µA Early Warning Reset Trigger (all power modes except Sleep) 1.8 1.7 1.85 1.75 1.9 1.8 V VDD Ramp Time for Power On One-cell Mode: VBAT Ramp 0–0.9 V Two-cell Mode: VBAT Ramp 0–1.8 V — — 3 ms VDD Monitor Threshold (VPOR) Initial Power-On (VDD Rising) Brownout Condition (VDD Falling) Recovery from Brownout (VDD Rising) — 0.7 — 0.75 0.8 0.95 — 0.9 — V Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation 100 650 1000 µs Minimum System Clock w/ Missing Clock Detector Enabled System clock frequency which triggers a missing clock detector timeout — 7 10 kHz Delay between release of any reset source and code execution at location 0x0000 — 10 — µs Minimum RST Low Time to Generate a System Reset 15 — — µs VDD Monitor Turn-on Time — 300 — ns — 7 — µA RST Input Pullup Current ec om Reset Time Delay m en de d VDD_MCU Monitor Threshold (VRST) N ew RST Input Low Voltage N ot R VDD Monitor Supply  Current 56 D Test Condition fo r Parameter es ig ns VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Rev. 1.3 Si1000/1/2/3/4/5 Table 4.5. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Min Typ 2 — Low power oscillator — 400 Precision oscillator — 1.3 Two-cell mode — 2 One-cell mode — 10 Suspend Mode Wake-up Time Sleep Mode Wake-up Time Table 4.6. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Flash Size Test Condition Si1000/2/4 Scratchpad Size Erase Cycle Time Write Cycle Time m en de d Endurance Unit 3 SYSCLKs — ns — µs — µs — µs Min Typ Max Unit 65536* — — bytes 32768 — — bytes 1024 — 1024 bytes 1k 30k — Erase/Write Cycles 28 32 36 ms 57 64 71 µs fo r Si1001/3/5 N ew Idle Mode Wake-up Time Max es ig ns Test Condition D Parameter N ot R ec om Note: 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved. Rev. 1.3 57 Si1000/1/2/3/4/5 Table 4.7. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Oscillator Frequency Oscillator Supply Current  (from VDD) Test Condition Min Typ –40 to +85 °C, VDD = 1.8–3.6 V 25 °C; includes bias current of 90–100 µA 24 24.5 — 300* Table 4.8. Internal Low-Power Oscillator Electrical Characteristics Unit 25 MHz — µA D *Note: Does not include clock divider or clock tree supply current. Max es ig ns Parameter VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Oscillator Frequency Oscillator Supply Current  (from VDD) Test Condition –40 to +85 °C, VDD = 1.8–3.6 V 25 °C No separate bias current required. Typ Max Unit 18 20 22 MHz — 100* — µA N ot R ec om m en de d fo r *Note: Does not include clock divider or clock tree supply current. Min N ew Parameter 58 Rev. 1.3 Si1000/1/2/3/4/5 Table 4.9. ADC0 Electrical Characteristics VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Test Condition Min Typ DC Accuracy Resolution 10 — ±0.5 — ±0.5 Offset Error — ±