SI1003-C-GM

Si1000/1/2/3/4/5 Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver Ultra Low Power: 0.9 to 3.6 V Operation - Typical sleep mode current < 0.1 µA; retains state and - EZRadioPRO® Transceiver Frequency range = 240–960 MHz Sensitivity = –121 dBm FSK, GFSK, and OOK modulation Max output power = +20 dBm (Si1000/1), +13 dBm (Si1002/3/4/5) RF power consumption - 18.5 mA receive - 18 mA @ +1 dBm transmit - 30 mA @ +13 dBm transmit - 85 mA @ +20 dBm transmit Data rate = 0.123 to 256 kbps Auto-frequency calibration (AFC) Antenna diversity and transmit/receive switch control Programmable packet handler TX and RX 64 byte FIFOs Frequency hopping capability On-chip crystal tuning RAM contents over full supply range; fast wakeup of < 2 µs Less than 600 nA with RTC running Less than 1 µA with RTC running and radio state retained On-chip dc-dc converter allows operation down to 0.9 V. Two built-in brown-out detectors cover sleep and active modes 10-Bit Analog to Digital Converter - Up to 300 ksps - Up to 18 external inputs - External pin or internal VREF (no external capacitor - required) Built-in temperature sensor External conversion start input option Autonomous burst mode with 16-bit automatic averaging accumulator Dual Comparators - Programmable hysteresis and response time - Configurable as interrupt or reset source - Low current (< 0.5 µA) On-Chip Debug - On-chip debug circuitry facilitates full-speed, non-intrusive in-system debug (No emulator required) Digital Peripherals - 19 or 16 port I/O plus 3 GPIO pins; Hardware enhanced UART, SPI, and I2C serial ports available concurrently Low power 32-bit SmaRTClock Four general purpose 16-bit counter/timers; six channel programmable counter array (PCA) - Provides breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Clock Sources - Precision internal oscillators: 24.5 MHz with ±2% accuracy - - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 4352 bytes internal data RAM (256 + 4096) - 64 kB (Si1000/2/4) or 32 kB (Si1001/3/5) Flash; In-system programmable in 1024-byte sectors—1024 bytes are reserved in the 64 kB devices supports UART operation; spread-spectrum mode for reduced EMI; Low power 20 MHz internal oscillator External oscillator: Crystal, RC, C, CMOS clock SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate Can switch between clock sources on-the-fly; useful in implementing various power saving modes Package - 42-pin QFN (5 x 7 mm) Temperature Range: –40 to +85 °C ANALOG PERIPHERALS A M U X DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR EZRadio PRO Serial Interface Port 1 Port 2 EZRadioPRO (240–960 MHz) LNA 10-bit 300 ksps ADC + IREF + – PA TEMP SENSOR VREF VREG – Mixer PGA ADC VOLTAGE COMPARATORS 24.5 MHz PRECISION INTERNAL OSCILLATOR External Oscillator 20 MHz LOW POWER INTERNAL OSCILLATOR HARDWARE smaRTClock Digital Modem Delta Sigma Modulator Digital Logic PLL HIGH-SPEED CONTROLLER CORE 64/32 kB ISP FLASH FLEXIBLE INTERRUPTS 8051 CPU (25 MIPS) D EBUG CIRCUITRY 4352 B SRAM POR W DT OSC Rev. 1.0 9/10 Copyright © 2010 by Silicon Laboratories Si1000/1/2/3/4/5 Si1000/1/2/3/4/5 2 Rev. 1.0 Si1000/1/2/3/4/5 Table of Contents 1. System Overview ..................................................................................................... 16 1.1. Typical Connection Diagram ............................................................................. 20 1.2. CIP-51™ Microcontroller Core .......................................................................... 21 1.3. Port Input/Output ............................................................................................... 22 1.4. Serial Ports ........................................................................................................ 23 1.5. Programmable Counter Array............................................................................ 23 1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode ................................................................ 24 1.7. Programmable Current Reference (IREF0)....................................................... 25 1.8. Comparators...................................................................................................... 25 2. Ordering Information ............................................................................................... 27 3. Pinout and Package Definitions ............................................................................. 28 4. Electrical Characteristics ........................................................................................ 40 4.1. Absolute Maximum Specifications..................................................................... 40 4.2. MCU Electrical Characteristics .......................................................................... 41 4.3. EZRadioPRO® Electrical Characteristics .......................................................... 66 4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 73 5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode ................................................................... 74 5.1. Output Code Formatting .................................................................................... 74 5.2. Modes of Operation ........................................................................................... 76 5.3. 8-Bit Mode ......................................................................................................... 80 5.4. Programmable Window Detector....................................................................... 87 5.5. ADC0 Analog Multiplexer .................................................................................. 90 5.6. Temperature Sensor.......................................................................................... 92 5.7. Voltage and Ground Reference Options ........................................................... 95 5.8. External Voltage References............................................................................. 95 5.9. Internal Voltage References .............................................................................. 96 5.10. Analog Ground Reference............................................................................... 96 5.11. Temperature Sensor Enable ........................................................................... 96 5.12. Voltage Reference Electrical Specifications .................................................... 97 6. Programmable Current Reference (IREF0)............................................................ 98 6.1. IREF0 Specifications ......................................................................................... 98 7. Comparators............................................................................................................. 99 7.1. Comparator Inputs............................................................................................. 99 7.2. Comparator Outputs ........................................................................................ 100 7.3. Comparator Response Time ........................................................................... 101 7.4. Comparator Hysteresis.................................................................................... 101 7.5. Comparator Register Descriptions .................................................................. 102 7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 106 8. CIP-51 Microcontroller........................................................................................... 109 8.1. Performance .................................................................................................... 109 8.2. Programming and Debugging Support ............................................................ 110 Rev. 1.0 3 Si1000/1/2/3/4/5 8.3. Instruction Set.................................................................................................. 110 8.4. CIP-51 Register Descriptions .......................................................................... 115 9. Memory Organization ............................................................................................ 118 9.1. Program Memory............................................................................................. 119 9.2. Data Memory ................................................................................................... 119 10. On-Chip XRAM ..................................................................................................... 121 10.1. Accessing XRAM........................................................................................... 121 10.2. Special Function Registers............................................................................ 122 11. Special Function Registers................................................................................. 123 11.1. SFR Paging ................................................................................................... 124 12. Interrupt Handler.................................................................................................. 129 12.1. Enabling Interrupt Sources ............................................................................ 129 12.2. MCU Interrupt Sources and Vectors.............................................................. 129 12.3. Interrupt Priorities .......................................................................................... 130 12.4. Interrupt Latency............................................................................................ 130 12.5. Interrupt Register Descriptions ...................................................................... 132 12.6. External Interrupts INT0 and INT1................................................................. 139 13. Flash Memory....................................................................................................... 141 13.1. Programming The Flash Memory .................................................................. 141 13.2. Non-volatile Data Storage ............................................................................. 143 13.3. Security Options ............................................................................................ 143 13.4. Determining the Device Part Number at Run Time ....................................... 145 13.5. Flash Write and Erase Guidelines ................................................................. 145 13.6. Minimizing Flash Read Current ..................................................................... 147 14. Power Management ............................................................................................. 151 14.1. Normal Mode ................................................................................................. 152 14.2. Idle Mode....................................................................................................... 153 14.3. Stop Mode ..................................................................................................... 153 14.4. Suspend Mode .............................................................................................. 154 14.5. Sleep Mode ................................................................................................... 154 14.6. Configuring Wakeup Sources........................................................................ 155 14.7. Determining the Event that Caused the Last Wakeup................................... 155 14.8. Power Management Specifications ............................................................... 157 15. Cyclic Redundancy Check Unit (CRC0)............................................................. 158 15.1. CRC Algorithm............................................................................................... 158 15.2. Preparing for a CRC Calculation ................................................................... 160 15.3. Performing a CRC Calculation ...................................................................... 160 15.4. Accessing the CRC0 Result .......................................................................... 160 15.5. CRC0 Bit Reverse Feature............................................................................ 164 16. On-Chip DC-DC Converter (DC0)........................................................................ 165 16.1. Startup Behavior............................................................................................ 166 16.2. High Power Applications ............................................................................ 167 16.3. Pulse Skipping Mode..................................................................................... 167 16.4. Enabling the DC-DC Converter ..................................................................... 167 16.5. Minimizing Power Supply Noise .................................................................... 168 4 Rev. 1.0 Si1000/1/2/3/4/5 16.6. Selecting the Optimum Switch Size............................................................... 169 16.7. DC-DC Converter Clocking Options .............................................................. 169 16.8. DC-DC Converter Behavior in Sleep Mode ................................................... 169 16.9. DC-DC Converter Register Descriptions ....................................................... 171 16.10. DC-DC Converter Specifications ................................................................. 173 17. Voltage Regulator (VREG0)................................................................................. 174 17.1. Voltage Regulator Electrical Specifications ................................................... 174 18. Reset Sources ...................................................................................................... 175 18.1. Power-On (VBAT Supply Monitor) Reset ...................................................... 176 18.2. Power-Fail (VDD_MCU Supply Monitor) Reset............................................. 177 18.3. External Reset ............................................................................................... 179 18.4. Missing Clock Detector Reset ....................................................................... 179 18.5. Comparator0 Reset ....................................................................................... 180 18.6. PCA Watchdog Timer Reset ......................................................................... 180 18.7. Flash Error Reset .......................................................................................... 180 18.8. SmaRTClock (Real Time Clock) Reset ......................................................... 180 18.9. Software Reset .............................................................................................. 180 19. Clocking Sources................................................................................................. 182 19.1. Programmable Precision Internal Oscillator .................................................. 183 19.2. Low Power Internal Oscillator........................................................................ 183 19.3. External Oscillator Drive Circuit..................................................................... 183 19.4. Special Function Registers for Selecting and Configuring the System Clock 187 20. SmaRTClock (Real Time Clock).......................................................................... 190 20.1. SmaRTClock Interface .................................................................................. 190 20.2. SmaRTClock Clocking Sources .................................................................... 197 20.3. SmaRTClock Timer and Alarm Function ....................................................... 201 21. Port Input/Output ................................................................................................. 207 21.1. Port I/O Modes of Operation.......................................................................... 208 21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 209 21.3. Priority Crossbar Decoder ............................................................................. 211 21.4. Port Match ..................................................................................................... 216 21.5. Special Function Registers for Accessing and Configuring Port I/O ............. 219 22. EZRadioPRO® Serial Interface (SPI1) ................................................................ 228 22.1. Signal Descriptions........................................................................................ 229 22.2. SPI Master Operation on the MCU Core Side.............................................. 229 22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 229 22.4. EZRadioPRO Serial Interface Interrupt Sources ........................................... 232 22.5. Serial Clock Phase and Polarity .................................................................... 232 22.6. SPI Special Function Registers ..................................................................... 233 23. EZRadioPRO® 240–960 MHz Transceiver.......................................................... 239 23.1. EZRadioPRO Operating Modes .................................................................... 240 23.2. Interrupts ...................................................................................................... 243 23.3. System Timing............................................................................................... 244 23.4. Modulation Options........................................................................................ 251 23.5. Internal Functional Blocks ............................................................................. 256 Rev. 1.0 5 Si1000/1/2/3/4/5 23.6. Data Handling and Packet Handler ............................................................... 261 23.7. RX Modem Configuration .............................................................................. 269 23.8. Auxiliary Functions ........................................................................................ 269 23.9. Reference Design.......................................................................................... 280 23.10. Application Notes and Reference Designs .................................................. 283 23.11. Customer Support ....................................................................................... 283 23.12. Register Table and Descriptions ................................................................. 284 23.13. Required Changes to Default Register Values............................................ 286 24. SMBus................................................................................................................... 287 24.1. Supporting Documents .................................................................................. 288 24.2. SMBus Configuration..................................................................................... 288 24.3. SMBus Operation .......................................................................................... 288 24.4. Using the SMBus........................................................................................... 290 24.5. SMBus Transfer Modes................................................................................. 302 24.6. SMBus Status Decoding................................................................................ 305 25. UART0 ................................................................................................................... 310 25.1. Enhanced Baud Rate Generation.................................................................. 311 25.2. Operational Modes ........................................................................................ 311 25.3. Multiprocessor Communications ................................................................... 313 26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 317 26.1. Signal Descriptions........................................................................................ 318 26.2. SPI0 Master Mode Operation ........................................................................ 318 26.3. SPI0 Slave Mode Operation .......................................................................... 320 26.4. SPI0 Interrupt Sources .................................................................................. 321 26.5. Serial Clock Phase and Polarity .................................................................... 322 26.6. SPI Special Function Registers ..................................................................... 323 27. Timers ................................................................................................................... 330 27.1. Timer 0 and Timer 1 ...................................................................................... 332 27.2. Timer 2 .......................................................................................................... 340 27.3. Timer 3 .......................................................................................................... 346 28. Programmable Counter Array............................................................................. 352 28.1. PCA Counter/Timer ....................................................................................... 353 28.2. PCA0 Interrupt Sources................................................................................. 354 28.3. Capture/Compare Modules ........................................................................... 355 28.4. Watchdog Timer Mode .................................................................................. 363 28.5. Register Descriptions for PCA0..................................................................... 365 29. C2 Interface .......................................................................................................... 371 29.1. C2 Interface Registers................................................................................... 371 29.2. C2 Pin Sharing .............................................................................................. 374 Document Change List.............................................................................................. 375 Contact Information................................................................................................... 376 6 Rev. 1.0 Si1000/1/2/3/4/5 List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 81 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 82 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 83 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 84 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 85 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 86 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 86 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 87 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 87 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 88 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 88 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 91 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 94 SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 94 SFR Definition 5.15. REF0CN: Voltage Reference Control .......................................... 97 SFR Definition 6.1. IREF0CN: Current Reference Control ........................................... 98 SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 102 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 103 SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 104 SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 105 SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 107 SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 108 SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 115 SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 115 SFR Definition 8.3. SP: Stack Pointer ......................................................................... 116 SFR Definition 8.4. ACC: Accumulator ....................................................................... 116 SFR Definition 8.5. B: B Register ................................................................................ 116 SFR Definition 8.6. PSW: Program Status Word ........................................................ 117 SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 122 SFR Definition 11.1. SFRPage: SFR Page ................................................................. 125 SFR Definition 12.1. IE: Interrupt Enable .................................................................... 133 SFR Definition 12.2. IP: Interrupt Priority .................................................................... 134 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 ............................................ 135 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 ............................................ 136 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 ............................................ 137 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 ............................................ 138 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration .............................................. 140 SFR Definition 13.1. PSCTL: Program Store R/W Control ......................................... 148 SFR Definition 13.2. FLKEY: Flash Lock and Key ...................................................... 149 SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 150 SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 150 SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2 ................ 156 SFR Definition 14.2. PCON: Power Management Control Register ........................... 157 SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 161 Rev. 1.0 7 Si1000/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 162 SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 162 SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 163 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 163 SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 164 SFR Definition 16.1. DC0CN: DC-DC Converter Control ........................................... 171 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration .................................. 172 SFR Definition 17.1. REG0CN: Voltage Regulator Control ........................................ 174 SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control .......................... 179 SFR Definition 18.2. RSTSRC: Reset Source ............................................................ 181 SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 187 SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 188 SFR Definition 19.3. OSCICL: Internal Oscillator Calibration ..................................... 188 SFR Definition 19.4. OSCXCN: External Oscillator Control ........................................ 189 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key .................................... 194 SFR Definition 20.2. RTC0ADR: SmaRTClock Address ............................................ 195 SFR Definition 20.3. RTC0DAT: SmaRTClock Data .................................................. 196 Internal Register Definition 20.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 203 Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 204 Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 205 Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration . . . . . . 205 Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 206 Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value 206 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 .......................................... 214 SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 .......................................... 215 SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 .......................................... 216 SFR Definition 21.4. P0MASK: Port0 Mask Register .................................................. 217 SFR Definition 21.5. P0MAT: Port0 Match Register ................................................... 217 SFR Definition 21.6. P1MASK: Port1 Mask Register .................................................. 218 SFR Definition 21.7. P1MAT: Port1 Match Register ................................................... 218 SFR Definition 21.8. P0: Port0 .................................................................................... 220 SFR Definition 21.9. P0SKIP: Port0 Skip .................................................................... 220 SFR Definition 21.10. P0MDIN: Port0 Input Mode ...................................................... 221 SFR Definition 21.11. P0MDOUT: Port0 Output Mode ............................................... 221 SFR Definition 21.12. P0DRV: Port0 Drive Strength .................................................. 222 SFR Definition 21.13. P1: Port1 .................................................................................. 223 SFR Definition 21.14. P1SKIP: Port1 Skip .................................................................. 223 SFR Definition 21.15. P1MDIN: Port1 Input Mode ...................................................... 224 SFR Definition 21.16. P1MDOUT: Port1 Output Mode ............................................... 224 SFR Definition 21.17. P1DRV: Port1 Drive Strength .................................................. 225 SFR Definition 21.18. P2: Port2 .................................................................................. 225 SFR Definition 21.19. P2SKIP: Port2 Skip .................................................................. 226 SFR Definition 21.20. P2MDIN: Port2 Input Mode ...................................................... 226 SFR Definition 21.21. P2MDOUT: Port2 Output Mode ............................................... 227 SFR Definition 21.22. P2DRV: Port2 Drive Strength .................................................. 227 8 Rev. 1.0 Si1000/1/2/3/4/5 SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 234 SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 235 SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 236 SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 237 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ...................................... 293 SFR Definition 24.2. SMB0CN: SMBus Control .......................................................... 295 SFR Definition 24.3. SMB0ADR: SMBus Slave Address ............................................ 298 SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask .................................. 298 SFR Definition 24.5. SMB0DAT: SMBus Data ............................................................ 301 SFR Definition 25.1. SCON0: Serial Port 0 Control .................................................... 314 SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 315 SFR Definition 26.7. SPI0CFG: SPI0 Configuration ................................................... 324 SFR Definition 26.8. SPI0CN: SPI0 Control ............................................................... 325 SFR Definition 26.9. SPI0CKR: SPI0 Clock Rate ....................................................... 326 SFR Definition 26.10. SPI0DAT: SPI0 Data ............................................................... 326 SFR Definition 27.1. CKCON: Clock Control .............................................................. 331 SFR Definition 27.2. TCON: Timer Control ................................................................. 336 SFR Definition 27.3. TMOD: Timer Mode ................................................................... 337 SFR Definition 27.4. TL0: Timer 0 Low Byte ............................................................... 338 SFR Definition 27.5. TL1: Timer 1 Low Byte ............................................................... 338 SFR Definition 27.6. TH0: Timer 0 High Byte ............................................................. 339 SFR Definition 27.7. TH1: Timer 1 High Byte ............................................................. 339 SFR Definition 27.8. TMR2CN: Timer 2 Control ......................................................... 343 SFR Definition 27.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 344 SFR Definition 27.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 344 SFR Definition 27.11. TMR2L: Timer 2 Low Byte ....................................................... 345 SFR Definition 27.12. TMR2H Timer 2 High Byte ....................................................... 345 SFR Definition 27.13. TMR3CN: Timer 3 Control ....................................................... 349 SFR Definition 27.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 350 SFR Definition 27.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 350 SFR Definition 27.16. TMR3L: Timer 3 Low Byte ....................................................... 351 SFR Definition 27.17. TMR3H Timer 3 High Byte ....................................................... 351 SFR Definition 28.1. PCA0CN: PCA Control .............................................................. 365 SFR Definition 28.2. PCA0MD: PCA Mode ................................................................ 366 SFR Definition 28.3. PCA0PWM: PCA PWM Configuration ....................................... 367 SFR Definition 28.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 368 SFR Definition 28.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 369 SFR Definition 28.6. PCA0H: PCA Counter/Timer High Byte ..................................... 369 SFR Definition 28.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 370 SFR Definition 28.8. PCA0CPHn: PCA Capture Module High Byte ........................... 370 C2 Register Definition 29.1. C2ADD: C2 Address ...................................................... 371 C2 Register Definition 29.2. DEVICEID: C2 Device ID ............................................... 372 C2 Register Definition 29.3. REVID: C2 Revision ID .................................................. 372 C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control ........................ 373 C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data ............................ 373 Rev. 1.0 9 Si1000/1/2/3/4/5 List of Figures Figure 1.1. Si1000 Block Diagram ........................................................................... 17 Figure 1.2. Si1001 Block Diagram ........................................................................... 17 Figure 1.3. Si1002 Block Diagram ........................................................................... 18 Figure 1.4. Si1003 Block Diagram ........................................................................... 18 Figure 1.5. Si1004 Block Diagram ........................................................................... 19 Figure 1.6. Si1005 Block Diagram ........................................................................... 19 Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example .................................... 20 Figure 1.8. Si1000/1 Antenna Diversity Application Example ................................. 20 Figure 1.9. Port I/O Functional Block Diagram ........................................................ 22 Figure 1.10. PCA Block Diagram ............................................................................. 23 Figure 1.11. ADC0 Functional Block Diagram ......................................................... 24 Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 25 Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 26 Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 26 Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) .............................................. 32 Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 33 Figure 3.3. QFN-42 Package Drawing .................................................................... 34 Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 36 Figure 3.5. VIA Placement and Keepout Region ..................................................... 37 Figure 3.6. Typical PCB Stencil Diagram ................................................................ 38 Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 45 Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 46 Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V ... 47 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) .. 48 Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ... 49 Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 50 Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 52 Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 53 Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 54 Figure 4.10. Typical VOL Curves, 1.8–3.6 V ........................................................... 55 Figure 4.11. Typical VOL Curves, 0.9–1.8 V ........................................................... 56 Figure 5.1. ADC0 Functional Block Diagram ........................................................... 74 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ... 77 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 78 Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 79 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data .. 89 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 89 Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 90 Figure 5.8. Temperature Sensor Transfer Function ................................................ 92 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 93 Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 95 Figure 7.1. Comparator 0 Functional Block Diagram .............................................. 99 Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 100 10 Rev. 1.0 Si1000/1/2/3/4/5 Figure 7.3. Comparator Hysteresis Plot ................................................................ 101 Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 106 Figure 8.1. CIP-51 Block Diagram ......................................................................... 109 Figure 9.1. Si1000/1/2/3/4/5 Memory Map ............................................................ 118 Figure 9.2. Flash Program Memory Map ............................................................... 119 Figure 13.1. Flash Program Memory Map ............................................................. 143 Figure 14.1. Si1000/1/2/3/4/5 Power Distribution .................................................. 152 Figure 15.1. CRC0 Block Diagram ........................................................................ 158 Figure 15.2. Bit Reverse Register ......................................................................... 164 Figure 16.1. DC-DC Converter Block Diagram ...................................................... 165 Figure 16.2. DC-DC Converter Configuration Options .......................................... 168 Figure 18.1. Reset Sources ................................................................................... 175 Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 176 Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 177 Figure 19.1. Clocking Sources Block Diagram ...................................................... 182 Figure 19.2. 25 MHz External Crystal Example ..................................................... 184 Figure 20.1. SmaRTClock Block Diagram ............................................................. 190 Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 199 Figure 21.1. Port I/O Functional Block Diagram .................................................... 207 Figure 21.2. Port I/O Cell Block Diagram .............................................................. 208 Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 212 Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 213 Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 228 Figure 22.2. SPI Timing ......................................................................................... 230 Figure 22.3. SPI Timing—READ Mode ................................................................. 230 Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 231 Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 231 Figure 22.6. Master Mode Data/Clock Timing ....................................................... 232 Figure 22.7. SPI Master Timing ............................................................................. 238 Figure 23.1. State Machine Diagram ..................................................................... 241 Figure 23.2. TX Timing .......................................................................................... 244 Figure 23.3. RX Timing .......................................................................................... 245 Figure 23.4. Frequency Deviation ......................................................................... 248 Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 250 Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 252 Figure 23.7. Direct Synchronous Mode Example .................................................. 255 Figure 23.8. Direct Asynchronous Mode Example ................................................ 255 Figure 23.9. Microcontroller Connections .............................................................. 256 Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 258 Figure 23.11. FIFO Thresholds ............................................................................. 261 Figure 23.12. Packet Structure .............................................................................. 262 Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 263 Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 263 Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 264 Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 264 Rev. 1.0 11 Si1000/1/2/3/4/5 Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 266 Figure 23.18. Manchester Coding Example .......................................................... 266 Figure 23.19. Header ............................................................................................. 268 Figure 23.20. POR Glitch Parameters ................................................................... 269 Figure 23.21. General Purpose ADC Architecture ................................................ 272 Figure 23.22. Temperature Ranges using ADC8 .................................................. 274 Figure 23.23. WUT Interrupt and WUT Operation ................................................. 277 Figure 23.24. Low Duty Cycle Mode ..................................................................... 278 Figure 23.25. RSSI Value vs. Input Power ............................................................ 280 Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design—Schematic . 281 Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 282 Figure 24.1. SMBus Block Diagram ...................................................................... 287 Figure 24.2. Typical SMBus Configuration ............................................................ 288 Figure 24.3. SMBus Transaction ........................................................................... 289 Figure 24.4. Typical SMBus SCL Generation ........................................................ 291 Figure 24.5. Typical Master Write Sequence ........................................................ 302 Figure 24.6. Typical Master Read Sequence ........................................................ 303 Figure 24.7. Typical Slave Write Sequence .......................................................... 304 Figure 24.8. Typical Slave Read Sequence .......................................................... 305 Figure 25.1. UART0 Block Diagram ...................................................................... 310 Figure 25.2. UART0 Baud Rate Logic ................................................................... 311 Figure 25.3. UART Interconnect Diagram ............................................................. 312 Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 312 Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 313 Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 313 Figure 26.1. SPI Block Diagram ............................................................................ 317 Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 319 Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram .......................................................................... 319 Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram .......................................................................... 320 Figure 26.5. Master Mode Data/Clock Timing ....................................................... 322 Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 323 Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 323 Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 327 Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 327 Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 328 Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 328 Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 333 Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 334 Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 335 Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 340 Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 341 Figure 27.6. Timer 2 Capture Mode Block Diagram .............................................. 342 Figure 27.7. Timer 3 16-Bit Mode Block Diagram ................................................. 346 12 Rev. 1.0 Si1000/1/2/3/4/5 Figure 27.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 347 Figure 27.9. Timer 3 Capture Mode Block Diagram .............................................. 348 Figure 28.1. PCA Block Diagram ........................................................................... 352 Figure 28.2. PCA Counter/Timer Block Diagram ................................................... 353 Figure 28.3. PCA Interrupt Block Diagram ............................................................ 354 Figure 28.4. PCA Capture Mode Diagram ............................................................. 356 Figure 28.5. PCA Software Timer Mode Diagram ................................................. 357 Figure 28.6. PCA High-Speed Output Mode Diagram ........................................... 358 Figure 28.7. PCA Frequency Output Mode ........................................................... 359 Figure 28.8. PCA 8-Bit PWM Mode Diagram ........................................................ 360 Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 361 Figure 28.10. PCA 16-Bit PWM Mode ................................................................... 362 Figure 28.11. PCA Module 5 with Watchdog Timer Enabled ................................ 363 Figure 29.1. Typical C2 Pin Sharing ...................................................................... 374 Rev. 1.0 13 Si1000/1/2/3/4/5 List of Tables Table 2.1. Product Selection Guide ......................................................................... 27 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 .................................................. 28 Table 3.2. QFN-42 Package Dimensions ................................................................ 35 Table 3.3. PCB Land Pattern ................................................................................... 39 Table 4.1. Absolute Maximum Ratings .................................................................... 40 Table 4.2. Global Electrical Characteristics ............................................................. 41 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 51 Table 4.4. Reset Electrical Characteristics .............................................................. 57 Table 4.5. Power Management Electrical Specifications ......................................... 58 Table 4.6. Flash Electrical Characteristics .............................................................. 58 Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 59 Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 59 Table 4.9. ADC0 Electrical Characteristics .............................................................. 60 Table 4.10. Temperature Sensor Electrical Characteristics .................................... 61 Table 4.11. Voltage Reference Electrical Characteristics ....................................... 61 Table 4.12. IREF0 Electrical Characteristics ........................................................... 62 Table 4.13. Comparator Electrical Characteristics .................................................. 63 Table 4.14. DC-DC Converter (DC0) Electrical Characteristics .............................. 65 Table 4.15. VREG0 Electrical Characteristics ......................................................... 65 Table 4.16. DC Characteristics1 .............................................................................. 66 Table 4.17. Synthesizer AC Electrical Characteristics1 ........................................... 67 Table 4.18. Receiver AC Electrical Characteristics1 ............................................... 68 Table 4.19. Transmitter AC Electrical Characteristics1 ............................................ 69 Table 4.20. Auxiliary Block Specifications1 .............................................................. 70 Table 4.21. Digital IO Specifications (nIRQ) ............................................................ 71 Table 4.22. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ........................ 71 Table 4.23. Absolute Maximum Ratings .................................................................. 72 Table 8.1. CIP-51 Instruction Set Summary .......................................................... 111 Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 123 Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 124 Table 11.3. Special Function Registers ................................................................. 125 Table 12.1. Interrupt Summary .............................................................................. 131 Table 13.1. Flash Security Summary .................................................................... 144 Table 14.1. Power Modes ...................................................................................... 151 Table 15.1. Example 16-bit CRC Outputs ............................................................. 159 Table 16.1. IPeak Inductor Current Limit Settings ................................................. 166 Table 19.1. Recommended XFCN Settings for Crystal Mode ............................... 184 Table 19.2. Recommended XFCN Settings for RC and C modes ......................... 185 Table 20.1. SmaRTClock Internal Registers ......................................................... 191 Table 20.2. SmaRTClock Load Capacitance Settings .......................................... 198 Table 20.3. SmaRTClock Bias Settings ................................................................ 200 Table 21.1. Port I/O Assignment for Analog Functions ......................................... 210 Table 21.2. Port I/O Assignment for Digital Functions ........................................... 210 14 Rev. 1.0 Si1000/1/2/3/4/5 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 211 Table 22.1. Serial Interface Timing Parameters .................................................... 230 Table 22.2. SPI Timing Parameters ...................................................................... 238 Table 23.1. EZRadioPRO Operating Modes ......................................................... 240 Table 23.2. EZRadioPRO Operating Modes Response Time ............................... 241 Table 23.3. Frequency Band Selection ................................................................. 246 Table 23.4. Packet Handler Registers ................................................................... 265 Table 23.5. Minimum Receiver Settling Time ........................................................ 267 Table 23.6. POR Parameters ................................................................................ 270 Table 23.7. Temperature Sensor Range ............................................................... 273 Table 23.8. Antenna Diversity Control ................................................................... 279 Table 23.9. EZRadioPRO Internal Register Descriptions ...................................... 284 Table 24.1. SMBus Clock Source Selection .......................................................... 291 Table 24.2. Minimum SDA Setup and Hold Times ................................................ 292 Table 24.3. Sources for Hardware Changes to SMB0CN ..................................... 296 Table 24.4. Hardware Address Recognition Examples (EHACK = 1) ................... 297 Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) ....................................................................................... 306 Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) ....................................................................................... 308 Table 25.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator .............................................. 316 Table 25.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator ......................................... 316 Table 26.1. SPI Slave Timing Parameters ............................................................ 329 Table 27.1. Timer 0 Running Modes ..................................................................... 332 Table 28.1. PCA Timebase Input Options ............................................................. 353 Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA  Capture/Compare Modules ................................................................ 355 Table 28.3. Watchdog Timer Timeout Intervals1 ................................................... 364 Rev. 1.0 15 Si1000/1/2/3/4/5 1. System Overview Si1000/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.           240–960 MHz EZRadioPRO® transceiver Single/Dual battery operation with on-chip dc-dc boost converter High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 300 ksps 23-channel single-ended ADC with analog multiplexer 6-bit programmable current reference Precision programmable 24.5 MHz internal oscillator with spread spectrum technology 64 kB or 32 kB of on-chip flash memory 4352 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware  (SPI1 is dedicated for communication with the EZRadioPRO peripheral)  Four general-purpose 16-bit timers  Programmable counter/timer array (PCA) with six capture/compare modules and watchdog timer (WDT) function  On-chip power-on reset, VDD monitor, and temperature sensor Two on-chip voltage comparators with 18 touch sense inputs  19 or 22 port I/O (5 V tolerant except for GPIO_0, GPIO_1, and GPIO_2) With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the Si1000/1/2/3/4/5 devices are truly standalone system-on-a-chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings.  The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The Si1000/1/2/3/4/5 are available in a 42-pin QFN package (lead-free and RoHS compliant). See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.6. The transceiver's extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. The advanced radio features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption. The transceivers digital receive architecture features a high-performance ADC and DSP-based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading, ensuring compliance with global regulations including FCC, ETSI, ARIB, and 802.15.4d regulations. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. 16 Rev. 1.0 Si1000/1/2/3/4/5 Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 64k Byte ISP Flash Program Memory 256 Byte SRAM 4096 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz, +20 dBm) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 10-bit 300ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator P0.2/XTAL1 P0.3/XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 22 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.1. Si1000 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 32k Byte ISP Flash Program Memory 256 Byte SRAM 4096 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz, +20 dBm) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 10-bit 300ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator P0.2/XTAL1 P0.3/XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 22 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.2. Si1001 Block Diagram Rev. 1.0 17 Si1000/1/2/3/4/5 Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 64k Byte ISP Flash Program Memory 256 Byte SRAM 4096 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz, +13 dBm) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 10-bit 300ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator P0.2/XTAL1 P0.3/XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 22 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.3. Si1002 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 32k Byte ISP Flash Program Memory 256 Byte SRAM 4096 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz, +13 dBm) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 10-bit 300ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator P0.2/XTAL1 P0.3/XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 22 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.4. Si1003 Block Diagram 18 Rev. 1.0 Si1000/1/2/3/4/5 Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 64k Byte ISP Flash Program Memory 256 Byte SRAM 4096 Byte XRAM CRC Engine Digital Power SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 10-bit 300ksps ADC RXp RXn VDD/DC+ GND/DC- Power Net Analog Power VREG Precision 24.5 MHz Oscillator DC/DC Converter Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface VBAT GND UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL1 XTAL2 XTAL3 XTAL4 Priority Crossbar Decoder 19 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.5. Si1004 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 32k Byte ISP Flash Program Memory 256 Byte SRAM 4096 Byte XRAM CRC Engine Digital Power SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 10-bit 300ksps ADC RXp RXn VDD/DC+ GND/DC- Power Net Analog Power VREG Precision 24.5 MHz Oscillator DC/DC Converter Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface VBAT GND UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL1 XTAL2 XTAL3 XTAL4 Priority Crossbar Decoder 19 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.6. Si1005 Block Diagram Rev. 1.0 19 Si1000/1/2/3/4/5 1.1. Typical Connection Diagram The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference design is available from Silicon Laboratories applications support. For applications seeking improved performance in the presence of multipath fading, antenna diversity can be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support. supply voltage C6 100p C7 100n C8 1u SDN X1 30MHz XOUT L1 L2 L4 C3 L3 C2 C4 C1 TX RFp RXn nIRQ VDD_MCU VDD_DIG Px.x VDD_RF XIN Si100x ANT GPIO0 GPIO1 GPIO2 L6 L5 VR_DIG 0.1 uF 0.1 uF C9 C5 1u Programmable load capacitors for X1 are integrated. L1-L6 and C1-C5 values depend on frequency band, antenna impedance, output power and supply voltage range. Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example Supply Voltage C6 100 p C7 100 n C8 1u SDN X1 30 MHz XOUT TR & ANT-DIV Switch 1 2 3 6 5 4 L1 L3 C3 L2 C2 C1 TX RXp RXn C4 VDD_RF nIRQ VDD_MCU VDD_DIG Px.x XIN Si100x GPIO0 GPIO1 GPIO2 L4 VR_DIG 0.1 uF 0.1 uF C9 C5 1u Programmable load capacitors for X1 are integrated. L1–L4 and C1–C5 values depend on frequency band, antenna impedance, output power, and supply voltage range. Figure 1.8. Si1000/1 Antenna Diversity Application Example 20 Rev. 1.0 Si1000/1/2/3/4/5 1.2. CIP-51™ Microcontroller Core 1.2.1. Fully 8051 Compatible The Si1000/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.2.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.2.3. Additional Features The Si1000/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51, allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a watchdog timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. The internal oscillator factory is calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Rev. 1.0 21 Si1000/1/2/3/4/5 1.3. Port Input/Output Digital and analog resources are available through 19 (Si1000/1/2/3) or 16 (Si1004/5) I/O pins. Three additional GPIO pins are available through the EZRadioPRO peripheral. Port pins are organized as three bytewide ports. Port pins P0.0–P2.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P1.0, P1.1, P1.2, and P1.4 are dedicated for communication with the EZRadioPRO peripheral. P1.3 is not available. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “29. C2 Interface” on page 371 for more details. The designer has complete control over which digital and analog functions are assigned to individual port pins and is limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on page 211 for more information on the crossbar. All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog functions can operate up to the VDD_MCU supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 208 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. XBR0, XBR1, XBR2, PnSKIP Registers Port Match P0MASK, P0MAT P1MASK, P1MAT Priority Decoder Highest Priority UART SPI0 SPI1 (Internal Digital Signals) SMBus CP0 CP1 Outputs SYSCLK PCA Lowest Priority T0, T1 7 2 8 P0 (Port Latches) (P0.0-P0.7) 8 P1 (P1.0-P1.7) 8 P2 (P2.0-P2.7) To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) 8 P2 I/O Cell 2 4 2 External Interrupts EX0 and EX1 PnMDOUT, PnMDIN Registers P0.0 Digital Crossbar 4 8 P0 I/O Cells P0.7 P1.5 P1 I/O Cells P1.6 P1.7 8 P2.0 P2.6 P2.7 No analog functionality available on P2.7 Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the EZRadioPRO peripheral. P1.3 is not internally or externally connected. P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3 Figure 1.9. Port I/O Functional Block Diagram 22 Rev. 1.0 Si1000/1/2/3/4/5 1.4. Serial Ports The Si1000/1/2/3/4/5 family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There is also a dedicated EZRadioPRO Serial Interface (SPI1) to allow communication with the EZRadioPRO peripheral. 1.5. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK /12 SYSCLK /4 Timer 0 Overflow ECI SYSCLK External Clock /8 PCA CLOCK MUX 16 -Bit Counter/Timer Capture/ Compare Module 0 Capture/ Compare Module 1 Capture/ Compare Module 2 Capture/ Compare Module 3 Capture/ Compare Module 4 Capture/ Compare Module5 / WDT CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI Crossbar Port I/O Figure 1.10. PCA Block Diagram Rev. 1.0 23 Si1000/1/2/3/4/5 1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically average the ADC results, providing an effective 11, 12, or 13-bit ADC result without any additional CPU intervention. The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs include an on-chip temperature sensor, the VDD_MCU supply voltage, the VBAT supply voltage, and the internal digital supply voltage. ADC0CN BURSTEN AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 AD0INT AD0EN VDD ADC0TK ADC0PWR Burst Mode Logic Start Conversion AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 3 Overflow CNVSTR Input From AMUX0 AIN+ SYSCLK REF ADC0H ADC ADC0L 10-bit SAR 16-Bit Accumulator AD0WINT Window Compare Logic AMP0GN AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD08BE AD0TM ADC0LTH ADC0LTL 32 ADC0CF ADC0GTH ADC0GTL Figure 1.11. ADC0 Functional Block Diagram 24 Rev. 1.0 Si1000/1/2/3/4/5 ADC0MX AD0MX4 AD0MX3 AD0MX2 AD0MX1 AM0MX0 P0.0 Programmable Attenuator AIN+ P2.6* Temp Sensor AMUX ADC0 Gain = 0. 5 or 1 Digital Supply VDD_MCU *P1.0 – P1.4 are not available as device pins Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.8. Comparators Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0), which is shown in Figure 1.13, and Comparator 1 (CPT1), which is shown in Figure 1.14. The two comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section “18. Reset Sources” on page 175 and Section “14. Power Management” on page 151 for details on reset sources and low power mode wake-up sources, respectively. The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be used to directly sense capacitive touch switches. See Application Note “AN338: Capacitive Touch Sense Solution” for details on Capacitive Touch Switch sensing. Rev. 1.0 25 Si1000/1/2/3/4/5 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer CP0MD0 CP0MD1 Px.x CPT0CN VDD CP0 Interrupt CPT0MD CP0RIE CP0FIE CP0 Rising-edge CP0 Falling-edge CP0 + Px.x Interrupt Logic + D SET CP0 Q D SET Q Px.x CP0 GND CLR Q CLR Q Crossbar (SYNCHRONIZER) (ASYNCHRONOUS) CP0A Px.x Reset Decision Tree Figure 1.13. Comparator 0 Functional Block Diagram CP1EN CPT0CN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 VDD CP1 Interrupt Analog Input Multiplexer CP1MD0 CP1MD1 Px.x CPT0MD CP1RIE CP1FIE CP1 Rising-edge CP1 Falling-edge CP1 + Px.x Interrupt Logic + D SET CP1 Q D SET Q Px.x CP1 GND CLR Q CLR Q Crossbar (SYNCHRONIZER) (ASYNCHRONOUS) CP1A Px.x Reset Decision Tree Figure 1.14. Comparator 1 Functional Block Diagram 26 Rev. 1.0 Si1000/1/2/3/4/5 2. Ordering Information Table 2.1. Product Selection Guide Enhanced SPI (available for external communication) Digital Port I/Os (includes EZRadioPRO GPIOs) SmaRTClock Real Time Clock Minimum Operating Voltage (Volts) Programmable Counter Array Ordering Part Number Flash Memory (kB) RAM (bytes) MIPS (Peak) SMBus/I2C Lead-free (RoHS Compliant) Internal Voltage Reference Maximum Transmit Power Temperature Sensor 10-bit 300ksps ADC Timers (16-bit) Si1000-C-GM 25 64 4352 Si1001-C-GM 25 32 4352 Si1002-C-GM 25 64 4352 Si1003-C-GM 25 32 4352 Si1004-C-GM 25 64 4352 Si1005-C-GM 25 32 4352 P P P P P P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 4 4 P P P P P P 22 P 22 P 22 P 22 P 19 P 19 P P P P P P P P P P P P P +20 dBm 1.8 P +20 dBm 1.8 P +13 dBm 1.8 P +13 dBm 1.8 P +13 dBm 0.9 P +13 dBm 0.9 P QFN-42 QFN-42 QFN-42 QFN-42 QFN-42 QFN-42 Rev. 1.0 Package UART 27 Si1000/1/2/3/4/5 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 Name Pin Number Si1000/1 Si1004/5 Si1002/3 VDD_MCU GND_MCU VBAT GND VBAT38 37 — — — — 41 38 P In G P In P In G Power Supply Voltage for the entire MCU except for the EZRadioPRO peripheral. Must be 1.8 to 3.6 V. Required Ground for the entire MCU except for the  EZRadioPRO peripheral. Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in dual-cell battery mode. In dual-cell battery mode, this pin must be connected directly to ground. In one-cell applications, this pin should be connected directly to the negative battery terminal, which is not connected to the ground plane. DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to VBAT through a 0.68 µH inductor. In dual-cell battery mode, this pin must be connected directly to ground. Power Supply Voltage for the entire MCU except for the EZRadioPRO peripheral. Must be 1.8 to 3.6 V. This supply voltage is not required in low power sleep mode. This voltage must always be > VBAT. Positive output of the dc-dc converter. In single-cell battery mode, a 1uF ceramic capacitor is required between dc+ and dc–. This pin can supply power to external devices when operating in single-cell battery mode. In dual-cell battery mode, this pin must be connected directly to ground. DC-DC converter return current path. In one-cell mode, this pin must be connected to the ground plane. Power Supply Voltage for the analog portion of the  EZRadioPRO peripheral. Must be 1.8 to 3.6 V. Power Supply Voltage for the digital portion of the  EZRadioPRO peripheral. Must be 1.8 to 3.6 V. Regulated Output Voltage of the digital 1.7 V regulator for the EZRadioPRO peripheral. A 1 µF decoupling capacitor is required. Required Ground for the digital and analog portions of the EZRadioPRO peripheral. Type Description DCEN — 40 P In G VDD_MCU / — 39 P In DC+ P Out GND_MCU DC– VDD_RF VDD_DIG VR_DIG — 37 G G 16 28 27 16 28 27 P In P In P Out GND_RF 23 23 G 28 Rev. 1.0 Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Si1000/1 Si1004/5 Si1002/3 RST/ 39 42 D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1–5 k pullup to VDD_MCU is recommended. See Reset Sources section for a complete description. Clock signal for the C2 Debug Interface. Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O section for a complete description. Bi-directional data signal for the C2 Debug Interface. SmaRTClock Oscillator Crystal Input. See Section 20 for a complete description. SmaRTClock Oscillator Crystal Output. See Section 20 for a complete description. Type Description C2CK P2.7/ 40 1 D I/O D I/O C2D XTAL3 XTAL4 P0.0 1 42 36 3 2 36 D I/O A In A Out D I/O or Port 0.0. See Port I/O section for a complete description. A In A In A Out External VREF Input. Internal VREF Output. External VREF decoupling capacitors are recommended. See Voltage Reference section. VREF P0.1 35 35 D I/O or Port 0.1. See Port I/O Section for a complete description. A In G Optional Analog Ground. See VREF chapter. AGND P0.2 34 34 D I/O or Port 0.2. See Port I/O Section for a complete description. A In A In External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Oscillator section. XTAL1 P0.3 33 33 D I/O or Port 0.3. See Port I/O Section for a complete description. A In A Out D In A In External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Oscillator section for complete details. XTAL2 Rev. 1.0 29 Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Si1000/1 Si1004/5 Si1002/3 P0.4 32 32 D I/O or Port 0.4. See Port I/O section for a complete description. A In D Out 31 31 UART TX Pin. See Port I/O section. Type Description TX P0.5 D I/O or Port 0.5. See Port I/O section for a complete description. A In D In UART RX Pin. See Port I/O section. RX P0.6 30 30 D I/O or Port 0.6. See Port I/O section for a complete description. A In D In External Convert Start Input for ADC0. See ADC0 section for a complete description. CNVSTR P0.7 IREF0 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 10 9 8 7 6 5 4 3 2 41 10 9 8 7 6 5 4 — — — 29 29 D I/O or Port 0.7. See Port I/O section for a complete description. A In A Out IREF0 Output. See IREF section for complete description. D I/O or Port 1.5. See Port I/O section for a complete description. A In D I/O or Port 1.6. See Port I/O section for a complete description. A In D I/O or Port 1.7. See Port I/O section for a complete description. A In D I/O or Port 2.0. See Port I/O section for a complete description. A In D I/O or Port 2.1. See Port I/O section for a complete description. A In D I/O or Port 2.2. See Port I/O section for a complete description. A In D I/O or Port 2.3. See Port I/O section for a complete description. A In D I/O or Port 2.4. See Port I/O section for a complete description. A In D I/O or Port 2.5. See Port I/O section for a complete description. A In D I/O or Port 2.6. See Port I/O section for a complete description. A In 30 Rev. 1.0 Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Si1000/1 Si1004/5 Si1002/3 GPIO_0 GPIO_1 GPIO_2 nIRQ 24 25 26 11 24 25 26 11 D I/O or General Purpose I/O controlled by the EZRadioPRO periphA I/O eral. May be configured through the EZRadioPRO registers D I/O or to perform various functions including: Clock Output, FIFO status, POR, Wake-Up Timer, Low Battery Detect, TRSW, A I/O AntDiversity control, etc. See the EZRadioPRO GPIO ConD I/O or figuration Registers for more information. A I/O DO EZRadioPRO peripheral interrupt status pin. Will be set low to indicate a pending EZRadioPRO interrupt event. See the EZRadioPRO Control Logic Registers for more details. This pin is an open-drain output with a 220 k internal pullup resistor. An external pull-up resistor is recommended. EZRadioPRO peripheral crystal oscillator output. Connect to an external 30 MHz crystal or leave floating if driving the XIN pin with an external signal source. EZRadioPRO peripheral crystal oscillator input. Connect to an external 30 MHz crystal or to an external source. If using an external clock source with no crystal, dc coupling with a nominal 0.8 VDC level is recommended with a minimum ac amplitude of 700 mVpp. No Connect. May be left floating or tied to power or ground. DI EZRadioPRO peripheral shutdown pin. When driven to logic HIGH, the EZRadioPRO peripheral will be completely shut down and the contents of the EZRadioPRO registers will be lost. This pin should be driven to logic LOW during all other times; this pin should never be left floating. EZRadioPRO peripheral transmit RF output pin. The PA output is an open-drain connection so the L-C match must supply (1.8 to 3.6 VDC) to this pin. EZRadioPRO peripheral differential RF input pins of the LNA. See application schematic for example matching network. EZRadioPRO peripheral TR switch control signal. Type Description XOUT 12 12 AO XIN 13 13 AI NC SDN 14, 20, 22 15 14, 20, 22 15 TX 17 17 AO RXp RXn ANT_A 18 19 21 18 19 21 AI AI DO Rev. 1.0 31 Si1000/1/2/3/4/5 GND_MCU 37 P0.0/VREF 36 VDD_MCU 38 RST/C2CK 39 42 41 XTAL3 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P1.7 P1.6 P1.5 nIRQ XOUT XIN N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 40 P2.7/C2D XTAL4 P2.6 35 34 33 32 31 P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 VDD_DIG VR_DIG GPIO_2 GPIO_1 GPIO_0 GND_RF N.C. GND_MCU Si1000/1/2/3 Top View 30 29 28 27 26 25 24 GND_RF 23 22 SDN RXp RXn N.C. TX Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) 32 VDD_RF Rev. 1.0 ANT_A Si1000/1/2/3/4/5 VDD_MCU/DC+ GND_MCU/DC37 GND/VBAT- 42 41 40 39 38 P2.7/C2D XTAL4 XTAL3 P2.3 P2.2 P2.1 P2.0 P1.7 P1.6 P1.5 nIRQ XOUT XIN N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 36 P0.0/VREF RST/C2CK DCEN VBAT 35 34 33 32 31 P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 VDD_DIG VR_DIG GPIO_2 GPIO_1 GPIO_0 GND_RF N.C. GND_M CU Si1004/5 Top View 30 29 28 27 26 25 24 GND_RF 23 22 N.C. TX VDD_RF Figure 3.2. Si1004/5 Pinout Diagram (Top View) Rev. 1.0 ANT_A SDN RXp RXn 33 Si1000/1/2/3/4/5   Figure 3.3. QFN-42 Package Drawing 34 Rev. 1.0 Si1000/1/2/3/4/5 Table 3.2. QFN-42 Package Dimensions Dimension A b D D1 D2 D3 D4 e E E1 E2 E3 E4 Min 0.60 0.20 Typ 0.65 0.25 5.00 BSC 3.00 BSC 4.25 BSC 3.16 2.73 0.50 BSC 7.00 BSC 6.50 BSC 3.00 BSC 2.97 2.63 Max 0.70 0.30 Dimension F G L L1 L2 L3 P14 P24 aaa bbb ccc ddd fff Min Typ Max 0.07 REF 1.42 BSC 0.25 0.30 0.35 0.50 0.55 0.60 0.10 REF 0.125 REF 0.525 BSC 0.475 BSC — — — — — — — — — — 0.15 0.10 0.10 0.05 0.10 3.11 2.68 3.21 2.78 2.92 2.58 3.02 2.68 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. All pitches other than P1, P2 are represented by e. Rev. 1.0 35 Si1000/1/2/3/4/5   Figure 3.4. Typical QFN-42 Landing Diagram 36 Rev. 1.0 Si1000/1/2/3/4/5   Figure 3.5. VIA Placement and Keepout Region Rev. 1.0 37 Si1000/1/2/3/4/5   Figure 3.6. Typical PCB Stencil Diagram 38 Rev. 1.0 Si1000/1/2/3/4/5 Table 3.3. PCB Land Pattern Dimension C1 X1 (27x) Y1 (27x) C2 X2 (15x) Y2 (15x) E K X3 X4 Y4 Y5 X6 Y6 X7 Y7 General 1. 2. All dimensions shown are in millimeters (mm) unless otherwise noted. This land pattern design is based on the IPC-7351 guidelines. High-Tg PCB materials (Glass Transition Temperature > 170° C are recommended for Pb-free reflow profiles per standard industry practice. PCB design must ensure sufficient thermal relief for operation of the device. Via placement must minimize mechanical stress due to CTE mismatch between PCB material and the package while maintaining electrical or thermal performance as required for the particular application. a. A minimum of four vias are required under each E-pad; eight or more vias are recommended for designs that require increased thermal conductivity. b. Via diameters should be between 0.20 and 0.31 mm (8 to 12 mil). c. Metal-to-metal distance between outer edge of via diameter and closest edge of device perimeter pad must be > 1.00 mm (dimension "K"). d. Vias may be placed as desired within the non-hatched area of the E-pads. Final via size and quantity is dependent on choice of PCB materials and total thermal relief provided by internal Cu plane in the PCB. e. Vias should either be filled or tented on the top-side of the board to prevent solder from migrating away from the E-pads during reflow. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad should be 60 µm minimum around the pad. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. The stencil thickness should be 0.125 mm (5 mils). The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. A 3x3 array of 0.7 mm square openings on 0.9 mm pitch should be used for the upper center ground pad. A 3x3 array of 0.8 mm square openings on 1.0 mm pitch should be used for the lower center ground pad. A No-Clean, Type-3 solder paste is recommended. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Value 4.75 0.95 0.30 7.00 0.30 0.70 0.50 >1.00 0.125 2.73 2.63 1.59 3.16 2.97 0.07 1.42 PCB Design 1. 2. 3. Solder Mask Design 1. Stencil Design 1. 2. 3. 4. 5. 1. 2. Card Assembly Rev. 1.0 39 Si1000/1/2/3/4/5 4. Electrical Characteristics In sections 4.1 and 4.2, , “VDD” refers to the VDD_MCU supply voltage on Si1000/1/2/3 devices and to the VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in these two sections do not apply to the EZRadioPRO peripheral. In sections 4.3 and 4.4, “VDD” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifications in these sections pertain to the EZRadioPRO peripheral. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Px.x I/O Pin or RST with Respect to GND Voltage on VBAT with respect to GND Voltage on VDD_MCU or VDD_MCU/DC+ with respect to GND Maximum Total Current through VBAT, DCEN, VDD_MCU/DC+ or GND Maximum Output Current Sunk by RST or any Px.x Pin Maximum Total Current through all Px.x Pins DC-DC Converter Output Power ESD (Human Body Model) All pins except TX, RXp, and RXn TX, RXp, and RXn ESD (Machine Model) All pins except TX, RXp, and RXn TX, RXp, and RXn VDD > 2.2 V VDD < 2.2 V One-Cell Mode Two-Cell Mode Conditions Min –55 –65 –0.3 –0.3 –0.3 –0.3 –0.3 Typ — — — — — — — Max 125 150 5.8 VDD + 3.6 2.0 4.0 4.0 Units °C °C V V V — — 500 mA — — — — — — — — — — — — — — 100 200 110 2 1 150 45 mA mA mW kV kV V V Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 40 Rev. 1.0 Si1000/1/2/3/4/5 4.2. MCU Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Battery Supply Voltage (VBAT) Supply Voltage (VDD_MCU/DC+) Minimum RAM Data  Retention Voltage1 SYSCLK (System Clock)2 TSYSH (SYSCLK High Time) TSYSL (SYSCLK Low Time) Specified Operating  Temperature Range Conditions One-Cell Mode Two-Cell Mode One-Cell Mode Two-Cell Mode VDD (not in Sleep Mode) VBAT (in Sleep Mode) Min 0.9 1.8 1.8 1.8 — — 0 18 18 –40 Typ 1.2 2.4 1.9 2.4 1.4 0.3 — — — — Max 1.8 3.6 3.6 3.6 — 0.5 25 — — +85 Units V V V MHz ns ns °C Rev. 1.0 41 Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter IDD 3, 4, 5, 6, 7, 8 Conditions Min Typ Max Units Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) VDD = 1.8–3.6 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD 7. 8 Frequency Sensitivity3, 5, 6, VDD = 1.8–3.6 V, T = 25 °C, F < 10 MHz (Flash oneshot active, see 13.6) VDD = 1.8–3.6 V, T = 25 °C, F > 10 MHz (Flash oneshot bypassed, see 13.6) IDD4, 6,7,8 — — — — 4.1 3.5 295 365 5.0 — — — mA mA µA µA — 90 — µA — 226 — µA/MHz — 120 — µA/MHz Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) VDD = 1.8–3.6 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency Sensitivity1,6,8 VDD = 1.8–3.6 V, T = 25 °C — — — — 2.5 1.8 165 235 3.0 — — — mA mA µA µA — 84 — µA — 95 — µA/MHz 42 Rev. 1.0 Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Digital Supply Current6,7,8 (Suspend Mode) Digital Supply Current8 (Sleep Mode, SmaRTClock running) Conditions Min Typ Max Units Digital Supply Current—Suspend and Sleep Mode VDD = 1.8–3.6 V, two-cell mode 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and brownout detector) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes brownout detector) — — — — — — — — — — — — — 77 0.61 0.76 0.87 1.32 1.62 1.93 0.06 0.09 0.14 0.77 0.92 1.23 — — — — — — — — — — — — — µA µA Digital Supply Current8 (Sleep Mode) µA Rev. 1.0 43 Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. Parameter Conditions Min Typ Max Units Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 128-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 128-byte address boundaries. 4. Includes oscillator and regulator supply current. 5. IDD can be estimated for frequencies 10 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4.1 mA – (25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA. 6. The Supply Voltage is the voltage at the VDD_MCU pin, typically 1.8 to 3.6 V (default = 1.9 V). Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz – 5 MHz) x 0.095 mA/MHz = 0.6 mA. 7. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be estimated using the following equation: Supply Voltage  Supply Current (two-cell mode) VBAT Current (one-cell mode) = ---------------------------------------------------------------------------------------------------------------------------------DC-DC Converter Efficiency  VBAT Voltage The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V. The Supply Current (two-cell mode) is the data sheet specification for supply current. The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V). The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5. 8. The EZRadioPRO peripheral is placed in Shutdown mode. 44 Rev. 1.0 Si1000/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 Supply Current (uA) 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Frequency (MHz) F < 10 MHz Oneshot Enabled F > 10 MHz Oneshot Bypassed < 170 µA/MHz 200 µA/MHz 215 µA/MHz 240 µA/MHz 250 µA/MHz 300 µA/MHz Figure 4.1. Active Mode Current (External CMOS Clock) Rev. 1.0 45 Si1000/1/2/3/4/5 Supply Current vs. Frequency 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 Supply Current (uA) 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Frequency (MHz) Figure 4.2. Idle Mode Current (External CMOS Clock) 46 Rev. 1.0 Si1000/1/2/3/4/5               6:6(/  6:6(/  Efficiency (%)                                  9%$7 9%$7 9%$7 9%$7 9%$7 9%$7 9%$7  9  9  9  9  9  9  9  X+ ,QGXFWRU  SDFNDJH (65  2KPV 9'''&  9 0LQLPXP 3XOVH :LGWK QV 3XOVH 6NLSSLQJ 'LVDEOHG 1RWH (IILFLHQF\ DW KLJK FXUUHQWV PD\ EH LPSURYHG E\ FKRRVLQJ DQ LQGXFWRU ZLWK D ORZHU (65           Load Current (mA) Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V Rev. 1.0 47 Si1000/1/2/3/4/5 6:6(/  6:6(/               9%$7 9%$7 9%$7 9%$7 9%$7 9%$7 9%$7  9  9  9  9  9  9  9 Efficiency (%)                                 X+ ,QGXFWRU  SDFNDJH (65  2KPV 9'''&  9 0LQLPXP 3XOVH :LGWK  QV 3XOVH 6NLSSLQJ 'LVDEOHG 1RWH (IILFLHQF\ DW KLJK FXUUHQWV PD\ EH LPSURYHG E\ FKRRVLQJ DQ LQGXFWRU ZLWK D ORZHU (65        Load current (mA) Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) 48 Rev. 1.0 Si1000/1/2/3/4/5     9%$7  Efficiency (%)  9  9  9  9  9  9  9 9%$7 9%$7 9%$7 9%$7 9%$7 9%$7     X+ ,QGXFWRU  SDFNDJH (65  2KPV 6:6(/  9'''&  9 0LQLPXP 3XOVH :LGWK   QV                Load current (mA) Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) Rev. 1.0 49 Si1000/1/2/3/4/5         9%$7 &XUUHQW X$                     9%$7 9  X+ ,QGXFWRU  SDFNDJH (65  2KPV 6:6(/  9'''&  9 /RDG &XUUHQW  X$ 0LQ 3XOVH :LGWK  QV 0LQ 3XOVH :LGWK  QV 0LQ 3XOVH :LGWK  QV 0LQ 3XOVH :LGWK  QV Figure 4.6. Typical One-Cell Suspend Mode Current 50 Rev. 1.0 Si1000/1/2/3/4/5 Table 4.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions Min VDD – 0.7 VDD – 0.1 Typ — — See Chart Max — — Units V Output High Voltage High Drive Strength, PnDRV.n = 1 IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull Output Low Voltage High Drive Strength, PnDRV.n = 1 IOL = 8.5 mA IOL = 10 µA IOL = 25 mA Low Drive Strength, PnDRV.n = 0 IOL = 1.4 mA IOL = 10 µA IOL = 4 mA Input High Voltage VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V Input Low Voltage VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V Input Leakage  Current Weak Pullup On, VIN = 0 V, VDD = 1.8 V Weak Pullup On, Vin = 0 V, VDD = 3.6 V — VDD – 0.7 — VDD – 0.1 See Chart — — — — — — See Chart — — — V 0.6 0.1 — — — — VDD – 0.6 0.7 x VDD — — — — — — See Chart — — — — 4 20 0.6 0.1 — — — 0.6 0.3 x VDD — 30 V V V V µA Rev. 1.0 51 Si1000/1/2/3/4/5 Typical VOH (High Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 5 10 15 20 25 30 35 40 45 50 Load Current (mA) Typical VOH (Low Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V Figure 4.7. Typical VOH Curves, 1.8–3.6 V 52 Rev. 1.0 Si1000/1/2/3/4/5 Typical VOH (High Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 Voltage 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 Load Current (mA) Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 Voltage 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 1 2 Load Current (mA) 3 VDD = 1.5V VDD = 1.2V VDD = 0.9V VDD = 1.8V VDD = 0.9V VDD = 1.5V VDD = 1.2V VDD = 1.8V Figure 4.8. Typical VOH Curves, 0.9–1.8 V Rev. 1.0 53 Si1000/1/2/3/4/5 Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.9. Typical VOL Curves, 1.8–3.6 V 54 Rev. 1.0 Si1000/1/2/3/4/5 Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.10. Typical VOL Curves, 1.8–3.6 V Rev. 1.0 55 Si1000/1/2/3/4/5 Typical VOL (High Drive Mode) 0.5 VDD = 1.8V 0.4 VDD = 1.5V VDD = 1.2V VDD = 0.9V 0.2 Voltage 0.3 0.1 0 -5 -4 -3 -2 -1 0 Load Current (mA) Typical VOL (Low Drive Mode) 0.5 0.4 Voltage 0.3 VDD = 1.8V 0.2 VDD = 1.5V VDD = 1.2V 0.1 VDD = 0.9V 0 -3 -2 Load Current (mA) -1 0 Figure 4.11. Typical VOL Curves, 0.9–1.8 V 56 Rev. 1.0 Si1000/1/2/3/4/5 Table 4.4. Reset Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage Conditions IOL = 1.4 mA, VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.6 V Early Warning Reset Trigger (all power modes except Sleep) VDD Ramp from 0–0.9 V Initial Power-On (VDD Rising) Brownout Condition (VDD Falling) Recovery from Brownout (VDD Rising) Time from last system clock rising edge to reset initiation System clock frequency which triggers a missing clock detector timeout Delay between release of any reset source and code execution at location 0x0000 Min — VDD – 0.6 0.7 x VDD — — — — 1.8 1.7 — — 0.7 — 100 — Typ — — — — — 4 20 1.85 1.75 — 0.75 0.8 0.95 650 7 Max 0.6 — — 0.6 0.3 x VDD — 30 1.9 1.8 3 — 0.9 — 1000 10 Units V V V V V µA V RST Input Low Voltage RST Input Pullup Current VDD_MCU Monitor Threshold (VRST) VDD Ramp Time for Power On VDD Monitor Threshold (VPOR) Missing Clock Detector Timeout Minimum System Clock w/ Missing Clock Detector Enabled Reset Time Delay ms V µs kHz — 10 — µs Minimum RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply  Current 15 — — — 300 7 — — — µs ns µA Rev. 1.0 57 Si1000/1/2/3/4/5 Table 4.5. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Conditions Min 2 Typ — 400 1.3 2 10 Max 3 — — — — Units SYSCLKs ns µs µs µs Low power oscillator Precision oscillator — — — — Sleep Mode Wake-up Time Two-cell mode One-cell mode Table 4.6. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Flash Size Scratchpad Size Endurance Erase Cycle Time Write Cycle Time Conditions Si1000/2/4 Si1001/3/5 Min 65536* 32768 1024 1k 28 57 Typ — — — 30k 32 64 Max — — 1024 — 36 71 Units bytes bytes bytes Erase/Write Cycles ms µs Note: 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved. 58 Rev. 1.0 Si1000/1/2/3/4/5 Table 4.7. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C, VDD = 1.8–3.6 V 25 °C; includes bias current of 90–100 µA Min 24 — Typ 24.5 300* Max 25 — Units MHz µA *Note: Does not include clock divider or clock tree supply current. Table 4.8. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C, VDD = 1.8–3.6 V 25 °C No separate bias current required. Min 18 — Typ 20 100* Max 22 — Units MHz µA *Note: Does not include clock divider or clock tree supply current. Rev. 1.0 59 Si1000/1/2/3/4/5 Table 4.9. ADC0 Electrical Characteristics VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Signal-to-Noise Plus Distortion Signal-to-Distortion Spurious-Free Dynamic Range Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks Track/Hold Acquisition Time Throughput Rate Analog Inputs ADC Input Voltage Range Absolute Pin Voltage with respect to GND Sampling Capacitance Input Multiplexer Impedance Power Specifications Power Supply Current  (VDD supplied to ADC0) Power Supply Rejection Conversion Mode (300 ksps) Tracking Mode (0 ksps) Internal High Speed VREF External VREF — — — — 800 680 67 74 — — — — µA dB Single Ended (AIN+ – GND) Single Ended 1x Gain 0.5x Gain 0 0 — — — — 30 28 5 VREF VDD — — V V pF k 10-bit Mode 8-bit Mode — 13 11 1.5 — — — — — — 7.33 — — — 300 MHz clocks us ksps Guaranteed Monotonic — — — — 54 — — 10 ±0.5 ±0.5 ±