SI1012-A-GM

Si1010/1/2/3/4/5 Ultra Low Power, 16/8 kB, 12/10-Bit ADC MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver Ultra Low Power: 0.9 to 3.6 V Operation - Typical sleep mode current < 0.1 µA; retains state and - EZRadioPRO® Transceiver Frequency range = 240–960 MHz Sensitivity = –121 dBm FSK, GFSK, and OOK modulation Max output power = +20 dBm (Si1010/1), +13 dBm (Si1012/3/4/5) RF power consumption - 18.5 mA receive - 18 mA @ +1 dBm transmit - 30 mA @ +13 dBm transmit - 85 mA @ +20 dBm transmit (Si1010/1) Data rate = 0.123 to 256 kbps Auto-frequency calibration (AFC) Antenna diversity and transmit/receive switch control Programmable packet handler TX and RX 64 byte FIFOs Frequency hopping capability On-chip crystal tuning RAM contents over full supply range; fast wakeup of < 2 µs Less than 600 nA with RTC running Less than 1 µA with RTC running and radio state retained On-chip dc-dc converter allows operation down to 0.9 V. Two built-in brown-out detectors cover sleep and active modes 10-Bit or 12-Bit Analog to Digital Converter - Up to 300 ksps - Up to 18 external inputs - External pin or internal VREF (no external capacitor - required) Built-in temperature sensor External conversion start input option Autonomous burst mode with 16-bit automatic averaging accumulator Dual Comparators - Programmable hysteresis and response time - Configurable as interrupt or reset source - Low current (< 0.5 µA) On-Chip Debug - On-chip debug circuitry facilitates full-speed, non-intrusive in-system debug (No emulator required) Digital Peripherals - 12 port I/O plus 3 GPIO pins; Hardware enhanced UART, SPI, and I2C serial ports available concurrently Low power 32-bit SmaRTClock Four general purpose 16-bit counter/timers; six channel programmable counter array (PCA) - Provides breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instrucMemory - 768 bytes RAM 16 kB (Si1010/2/4) or 8 kB (Si1011/3/5) Flash; In-system programmable tions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz clock Expanded interrupt handler Clock Sources - Precision internal oscillators: 24.5 MHz with ±2% accuracy - supports UART operation; spread-spectrum mode for reduced EMI; Low power 20 MHz internal oscillator External oscillator: Crystal, RC, C, CMOS clock SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate Can switch between clock sources on-the-fly; useful in power saving modes and in implementing various power saving modes Package - 42-pin QFN (5 x 7 mm) Temperature Range: –40 to +85 °C ANALOG PERIPHERALS A M U X DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR EZRadio PRO Serial Interface Port 1 Port 2 EZRadioPRO (240–960 MHz) LNA 12/10-bit 75/300 ksps ADC + IREF + – PA TEMP SENSOR VREF VREG – VOLTAGE COMPARATORS Mixer PGA ADC 24.5 MHz PRECISION INTERNAL OSCILLATOR External Oscillator 20 MHz LOW POWER INTERNAL OSCILLATOR HARDWARE smaRTClock Digital Modem Delta Sigma Modulator Digital Logic HIGH-SPEED CONTROLLER CORE 16/8 kB ISP FLASH FLEXIBLE INTERRUPTS 8051 CPU (25 MIPS) DEBUG CIRCUITRY 768 B SRAM POR WDT PLL OSC Rev. 1.0 9/10 Copyright © 2010 by Silicon Laboratories Si1010/1/2/3/4/5 Si1010/1/2/3/4/5 Table of Contents 1. System Overview ..................................................................................................... 20 1.1. Typical Connection Diagram ............................................................................. 24 1.2. CIP-51™ Microcontroller Core .......................................................................... 25 1.2.1. Fully 8051 Compatible .............................................................................. 25 1.2.2. Improved Throughput................................................................................ 25 1.2.3. Additional Features ................................................................................... 25 1.3. Port Input/Output ............................................................................................... 26 1.4. Serial Ports ........................................................................................................ 27 1.5. Programmable Counter Array............................................................................ 27 1.6. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode.......................................................................................................... 28 1.7. Programmable Current Reference (IREF0)....................................................... 29 1.8. Comparators...................................................................................................... 29 2. Ordering Information ............................................................................................... 31 3. Pinout and Package Definitions ............................................................................. 32 4. Electrical Characteristics ........................................................................................ 44 4.1. Absolute Maximum Specifications..................................................................... 44 4.2. Electrical Characteristics ................................................................................... 45 4.3. EZRadioPRO® Electrical Characteristics .......................................................... 69 4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 76 5. SAR ADC with 16-Bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode .................................................................... 77 5.1. Output Code Formatting .................................................................................... 78 5.2. Modes of Operation ........................................................................................... 79 5.2.1. Starting a Conversion................................................................................ 79 5.2.2. Tracking Modes......................................................................................... 80 5.2.3. Burst Mode................................................................................................ 81 5.2.4. Settling Time Requirements...................................................................... 82 5.2.5. Gain Setting .............................................................................................. 82 5.3. 8-Bit Mode ......................................................................................................... 83 5.4. 12-Bit Mode ....................................................................................................... 83 5.5. Low Power Mode............................................................................................... 83 5.6. Programmable Window Detector....................................................................... 91 5.6.1. Window Detector In Single-Ended Mode .................................................. 93 5.6.2. ADC0 Specifications ................................................................................. 93 5.7. ADC0 Analog Multiplexer .................................................................................. 94 5.8. Temperature Sensor.......................................................................................... 96 5.8.1. Calibration ................................................................................................. 96 5.9. Voltage and Ground Reference Options ........................................................... 99 5.10. External Voltage References......................................................................... 100 5.11. Internal Voltage References .......................................................................... 100 5.12. Analog Ground Reference............................................................................. 100 5.13. Temperature Sensor Enable ......................................................................... 100 2 Rev. 1.0 Si1010/1/2/3/4/5 5.14. Voltage Reference Electrical Specifications .................................................. 101 6. Programmable Current Reference (IREF0).......................................................... 102 6.1. PWM Enhanced Mode..................................................................................... 102 6.2. IREF0 Specifications ....................................................................................... 103 7. Comparators........................................................................................................... 104 7.1. Comparator Inputs........................................................................................... 104 7.2. Comparator Outputs ........................................................................................ 105 7.3. Comparator Response Time ........................................................................... 106 7.4. Comparator Hysteresis.................................................................................... 106 7.5. Comparator Register Descriptions .................................................................. 107 7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 111 8. CIP-51 Microcontroller........................................................................................... 114 8.1. Performance .................................................................................................... 114 8.2. Programming and Debugging Support ............................................................ 115 8.3. Instruction Set.................................................................................................. 115 8.3.1. Instruction and CPU Timing .................................................................... 115 8.4. CIP-51 Register Descriptions .......................................................................... 119 9. Memory Organization ............................................................................................ 123 9.1. Program Memory............................................................................................. 123 9.1.1. MOVX Instruction and Program Memory ................................................ 124 9.2. Data Memory ................................................................................................... 124 9.2.1. Internal RAM ........................................................................................... 124 9.2.2. External RAM .......................................................................................... 125 10. On-Chip XRAM ..................................................................................................... 126 10.1. Accessing XRAM........................................................................................... 126 10.1.1. 16-Bit MOVX Example .......................................................................... 126 10.1.2. 8-Bit MOVX Example ............................................................................ 126 10.2. Special Function Registers............................................................................ 126 11. Special Function Registers................................................................................. 128 11.1. SFR Paging ................................................................................................... 129 12. Interrupt Handler.................................................................................................. 134 12.1. Enabling Interrupt Sources ............................................................................ 134 12.2. MCU Interrupt Sources and Vectors.............................................................. 134 12.3. Interrupt Priorities .......................................................................................... 135 12.4. Interrupt Latency............................................................................................ 135 12.5. Interrupt Register Descriptions ...................................................................... 137 12.6. External Interrupts INT0 and INT1................................................................. 144 13. Flash Memory....................................................................................................... 146 13.1. Programming the Flash Memory ................................................................... 146 13.1.1. Flash Lock and Key Functions .............................................................. 146 13.1.2. Flash Erase Procedure ......................................................................... 147 13.1.3. Flash Write Procedure .......................................................................... 147 13.2. Non-Volatile Data Storage............................................................................. 147 13.3. Security Options ............................................................................................ 148 13.4. Determining the Device Part Number at Run Time ....................................... 150 Rev. 1.0 3 Si1010/1/2/3/4/5 13.5. Flash Write and Erase Guidelines ................................................................. 151 13.5.1. VDD Maintenance and the VDD Monitor .............................................. 151 13.5.2. PSWE Maintenance .............................................................................. 151 13.5.3. System Clock ........................................................................................ 152 13.6. Minimizing Flash Read Current ..................................................................... 153 14. Power Management ............................................................................................. 157 14.1. Normal Mode ................................................................................................. 158 14.2. Idle Mode....................................................................................................... 158 14.3. Stop Mode ..................................................................................................... 159 14.4. Suspend Mode .............................................................................................. 160 14.5. Sleep Mode ................................................................................................... 161 14.6. Configuring Wakeup Sources........................................................................ 162 14.7. Determining the Event that Caused the Last Wakeup................................... 162 14.8. Power Management Specifications ............................................................... 165 15. Cyclic Redundancy Check Unit (CRC0)............................................................. 166 15.1. CRC Algorithm............................................................................................... 166 15.2. Preparing for a CRC Calculation ................................................................... 168 15.3. Performing a CRC Calculation ...................................................................... 168 15.4. Accessing the CRC0 Result .......................................................................... 168 15.5. CRC0 Bit Reverse Feature............................................................................ 173 16. On-Chip DC-DC Converter (DC0)........................................................................ 174 16.1. Startup Behavior............................................................................................ 175 16.2. High Power Applications ............................................................................ 176 16.3. Pulse Skipping Mode..................................................................................... 176 16.4. Enabling the DC-DC Converter ..................................................................... 176 16.5. Minimizing Power Supply Noise .................................................................... 178 16.6. Selecting the Optimum Switch Size............................................................... 178 16.7. DC-DC Converter Clocking Options .............................................................. 178 16.8. DC-DC Converter Behavior in Sleep Mode ................................................... 179 16.9. Bypass Mode................................................................................................. 179 16.10. Low Power Mode......................................................................................... 180 16.11. Passive Diode Mode.................................................................................... 180 16.12. DC-DC Converter Register Descriptions ..................................................... 181 16.13. DC-DC Converter Specifications ................................................................. 183 17. Voltage Regulator (VREG0)................................................................................. 184 17.1. Voltage Regulator Electrical Specifications ................................................... 184 18. Reset Sources ...................................................................................................... 185 18.1. Power-On (VBAT Supply Monitor) Reset ...................................................... 186 18.2. Power-Fail (VDD_MCU/DC+ Supply Monitor) Reset .................................... 188 18.3. External Reset ............................................................................................... 191 18.4. Missing Clock Detector Reset ....................................................................... 191 18.5. Comparator0 Reset ....................................................................................... 191 18.6. PCA Watchdog Timer Reset ......................................................................... 191 18.7. Flash Error Reset .......................................................................................... 191 18.8. SmaRTClock (Real Time Clock) Reset ......................................................... 192 4 Rev. 1.0 Si1010/1/2/3/4/5 18.9. Software Reset .............................................................................................. 192 19. Clocking Sources................................................................................................. 194 19.1. Programmable Precision Internal Oscillator .................................................. 195 19.2. Low Power Internal Oscillator........................................................................ 195 19.3. External Oscillator Drive Circuit..................................................................... 195 19.3.1. External Crystal Mode........................................................................... 195 19.3.2. External RC Mode................................................................................. 197 19.3.3. External Capacitor Mode....................................................................... 198 19.3.4. External CMOS Clock Mode ................................................................. 198 19.4. Special Function Registers for Selecting and Configuring the System Clock 199 20. SmaRTClock (Real Time Clock).......................................................................... 203 20.1. SmaRTClock Interface .................................................................................. 203 20.1.1. SmaRTClock Lock and Key Functions.................................................. 204 20.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock  Internal Registers .................................................................................. 204 20.1.3. RTC0ADR Short Strobe Feature........................................................... 205 20.1.4. SmaRTClock Interface Autoread Feature ............................................. 205 20.1.5. RTC0ADR Autoincrement Feature........................................................ 206 20.2. SmaRTClock Clocking Sources .................................................................... 209 20.2.1. Using the SmaRTClock Oscillator with a Crystal or  External CMOS Clock ........................................................................... 209 20.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 210 20.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 210 20.2.4. Programmable Load Capacitance......................................................... 210 20.2.5. Automatic Gain Control (Crystal Mode Only) and  SmaRTClock Bias Doubling.................................................................. 211 20.2.6. Missing SmaRTClock Detector ............................................................. 212 20.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 213 20.3. SmaRTClock Timer and Alarm Function ....................................................... 213 20.3.1. Setting and Reading the SmaRTClock Timer Value ............................. 213 20.3.2. Setting a SmaRTClock Alarm ............................................................... 213 20.3.3. Software Considerations for using the SmaRTClock Timer and Alarm 214 21. Port Input/Output ................................................................................................. 219 21.1. Port I/O Modes of Operation.......................................................................... 220 21.1.1. Port Pins Configured for Analog I/O...................................................... 220 21.1.2. Port Pins Configured For Digital I/O...................................................... 220 21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic............................................ 221 21.1.4. Increasing Port I/O Drive Strength ........................................................ 221 21.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 221 21.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 221 21.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 222 21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 222 21.3. Priority Crossbar Decoder ............................................................................. 223 21.4. Port Match ..................................................................................................... 228 21.5. Special Function Registers for Accessing and Configuring Port I/O ............. 231 Rev. 1.0 5 Si1010/1/2/3/4/5 22. EZRadioPRO Serial Interface (SPI1)................................................................... 239 22.1. Signal Descriptions........................................................................................ 240 22.1.1. Master Out, Slave In (MOSI)................................................................. 240 22.1.2. Master In, Slave Out (MISO)................................................................. 240 22.1.3. Serial Clock (SCK) ................................................................................ 240 22.1.4. Slave Select (NSS) ............................................................................... 240 22.2. SPI Master Operation on the MCU Core Side............................................... 240 22.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 240 22.4. EZRadioPRO Serial Interface Interrupt Sources ........................................... 243 22.5. Serial Clock Phase and Polarity .................................................................... 243 22.6. SPI Special Function Registers ..................................................................... 244 23. EZRadioPRO® 240–960 MHz Transceiver.......................................................... 249 23.1. EZRadioPRO Operating Modes .................................................................... 250 23.1.1. Operating Mode Control ....................................................................... 251 23.2. Interrupts ...................................................................................................... 253 23.3. System Timing............................................................................................... 254 23.3.1. Frequency Control................................................................................. 255 23.3.2. Frequency Programming....................................................................... 255 23.3.3. Easy Frequency Programming for FHSS.............................................. 257 23.3.4. Automatic State Transition for Frequency Change ............................... 258 23.3.5. Frequency Deviation ............................................................................. 258 23.3.6. Frequency Offset Adjustment................................................................ 259 23.3.7. Automatic Frequency Control (AFC) ..................................................... 259 23.3.8. TX Data Rate Generator ....................................................................... 261 23.4. Modulation Options........................................................................................ 261 23.4.1. Modulation Type.................................................................................... 261 23.4.2. Modulation Data Source........................................................................ 262 23.4.3. PN9 Mode ............................................................................................. 266 23.5. Internal Functional Blocks ............................................................................. 266 23.5.1. RX LNA ................................................................................................. 266 23.5.2. RX I-Q Mixer ......................................................................................... 266 23.5.3. Programmable Gain Amplifier ............................................................... 266 23.5.4. ADC ..................................................................................................... 267 23.5.5. Digital Modem ....................................................................................... 267 23.5.6. Synthesizer ........................................................................................... 268 23.5.7. Power Amplifier ..................................................................................... 269 23.5.8. Crystal Oscillator ................................................................................... 269 23.5.9. Regulators............................................................................................. 270 23.6. Data Handling and Packet Handler ............................................................... 271 23.6.1. RX and TX FIFOs.................................................................................. 271 23.6.2. Packet Configuration............................................................................. 272 23.6.3. Packet Handler TX Mode ...................................................................... 273 23.6.4. Packet Handler RX Mode...................................................................... 273 23.6.5. Data Whitening, Manchester Encoding, and CRC ................................ 275 6 Rev. 1.0 Si1010/1/2/3/4/5 23.6.6. Preamble Detector ................................................................................ 276 23.6.7. Preamble Length................................................................................... 276 23.6.8. Invalid Preamble Detector..................................................................... 277 23.6.9. Synchronization Word Configuration..................................................... 277 23.6.10. Receive Header Check ....................................................................... 278 23.6.11. TX Retransmission and Auto TX......................................................... 278 23.7. RX Modem Configuration .............................................................................. 279 23.7.1. Modem Settings for FSK and GFSK ..................................................... 279 23.8. Auxiliary Functions ........................................................................................ 279 23.8.1. Smart Reset .......................................................................................... 279 23.8.2. Output Clock ......................................................................................... 280 23.8.3. General Purpose ADC .......................................................................... 281 23.8.4. Temperature Sensor ............................................................................. 282 23.8.5. Low Battery Detector............................................................................. 284 23.8.6. Wake-Up Timer and 32 kHz Clock Source ........................................... 285 23.8.7. Low Duty Cycle Mode ........................................................................... 287 23.8.8. GPIO Configuration............................................................................... 288 23.8.9. Antenna Diversity .................................................................................. 289 23.8.10. RSSI and Clear Channel Assessment ................................................ 289 23.9. Reference Design.......................................................................................... 290 23.10. Application Notes and Reference Designs .................................................. 293 23.11. Customer Support ....................................................................................... 293 23.12. Register Table and Descriptions ................................................................. 294 23.13. Required Changes to Default Register Values............................................ 296 24. SMBus................................................................................................................... 297 24.1. Supporting Documents .................................................................................. 298 24.2. SMBus Configuration..................................................................................... 298 24.3. SMBus Operation .......................................................................................... 298 24.3.1. Transmitter vs. Receiver ....................................................................... 299 24.3.2. Arbitration.............................................................................................. 299 24.3.3. Clock Low Extension............................................................................. 299 24.3.4. SCL Low Timeout.................................................................................. 299 24.3.5. SCL High (SMBus Free) Timeout ......................................................... 300 24.4. Using the SMBus........................................................................................... 300 24.4.1. SMBus Configuration Register.............................................................. 300 24.4.2. SMB0CN Control Register .................................................................... 304 24.4.3. Hardware Slave Address Recognition .................................................. 306 24.4.4. Data Register ........................................................................................ 309 24.5. SMBus Transfer Modes................................................................................. 309 24.5.1. Write Sequence (Master) ...................................................................... 309 24.5.2. Read Sequence (Master) ...................................................................... 310 24.5.3. Write Sequence (Slave) ........................................................................ 311 24.5.4. Read Sequence (Slave) ........................................................................ 312 24.6. SMBus Status Decoding................................................................................ 313 Rev. 1.0 7 Si1010/1/2/3/4/5 25. UART0 ................................................................................................................... 318 25.1. Enhanced Baud Rate Generation.................................................................. 319 25.2. Operational Modes ........................................................................................ 319 25.2.1. 8-Bit UART ............................................................................................ 320 25.2.2. 9-Bit UART ............................................................................................ 320 25.3. Multiprocessor Communications ................................................................... 321 26. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 325 26.1. Signal Descriptions........................................................................................ 326 26.1.1. Master Out, Slave In (MOSI)................................................................. 326 26.1.2. Master In, Slave Out (MISO)................................................................. 326 26.1.3. Serial Clock (SCK) ................................................................................ 326 26.1.4. Slave Select (NSS) ............................................................................... 326 26.2. SPI0 Master Mode Operation ........................................................................ 326 26.3. SPI0 Slave Mode Operation .......................................................................... 328 26.4. SPI0 Interrupt Sources .................................................................................. 329 26.5. Serial Clock Phase and Polarity .................................................................... 329 26.6. SPI Special Function Registers ..................................................................... 331 27. Timers ................................................................................................................... 338 27.1. Timer 0 and Timer 1 ...................................................................................... 340 27.1.1. Mode 0: 13-Bit Counter/Timer............................................................... 340 27.1.2. Mode 1: 16-Bit Counter/Timer............................................................... 341 27.1.3. Mode 2: 8-Bit Counter/Timer with Auto-Reload .................................... 341 27.1.4. Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only) ............................... 342 27.2. Timer 2 .......................................................................................................... 348 27.2.1. 16-Bit Timer with Auto-Reload .............................................................. 348 27.2.2. 8-Bit Timers with Auto-Reload .............................................................. 349 27.2.3. Comparator 0/SmaRTClock Capture Mode .......................................... 350 27.3. Timer 3 .......................................................................................................... 354 27.3.1. 16-Bit Timer with Auto-Reload .............................................................. 354 27.3.2. 8-Bit Timers with Auto-Reload .............................................................. 355 27.3.3. Comparator 1/External Oscillator Capture Mode .................................. 356 28. Programmable Counter Array............................................................................. 360 28.1. PCA Counter/Timer ....................................................................................... 361 28.2. PCA0 Interrupt Sources................................................................................. 362 28.3. Capture/Compare Modules ........................................................................... 363 28.3.1. Edge-triggered Capture Mode............................................................... 364 28.3.2. Software Timer (Compare) Mode.......................................................... 365 28.3.3. High-Speed Output Mode ..................................................................... 366 28.3.4. Frequency Output Mode ....................................................................... 366 28.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes.............. 367 28.3.6. 16-Bit Pulse Width Modulator Mode.................................................... 369 28.4. Watchdog Timer Mode .................................................................................. 370 28.4.1. Watchdog Timer Operation ................................................................... 370 28.4.2. Watchdog Timer Usage ........................................................................ 371 8 Rev. 1.0 Si1010/1/2/3/4/5 28.5. Register Descriptions for PCA0..................................................................... 373 29. C2 Interface .......................................................................................................... 379 29.1. C2 Interface Registers................................................................................... 379 29.2. C2 Pin Sharing .............................................................................................. 382 Document Change List.............................................................................................. 383 Contact Information................................................................................................... 384 Rev. 1.0 9 Si1010/1/2/3/4/5 List of Figures Figure 1.1. Si1010 Block Diagram ........................................................................... 21 Figure 1.2. Si1011 Block Diagram ........................................................................... 21 Figure 1.3. Si1012 Block Diagram ........................................................................... 22 Figure 1.4. Si1013 Block Diagram ........................................................................... 22 Figure 1.5. Si1014 Block Diagram ........................................................................... 23 Figure 1.6. Si1015 Block Diagram ........................................................................... 23 Figure 1.7. Si1012/3 RX/TX Direct-tie Application Example .................................... 24 Figure 1.8. Si1010/1 Antenna Diversity Application Example ................................. 24 Figure 1.9. Port I/O Functional Block Diagram ........................................................ 26 Figure 1.10. PCA Block Diagram ............................................................................. 27 Figure 1.11. ADC0 Functional Block Diagram ......................................................... 28 Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 29 Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 30 Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 30 Figure 3.1. Si1010/1/2/3 Pinout Diagram (Top View) .............................................. 36 Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 37 Figure 3.3. QFN-42 Package Drawing .................................................................... 38 Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 40 Figure 3.5. VIA Placement and Keepout Region ..................................................... 41 Figure 3.6. Typical PCB Stencil Diagram ................................................................ 42 Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 49 Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 50 Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) .. 51 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) .. 52 Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ... 53 Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 54 Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 56 Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 57 Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 58 Figure 4.10. Typical VOL Curves, 0.9–1.8 V ........................................................... 59 Figure 5.1. ADC0 Functional Block Diagram ........................................................... 77 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ... 80 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 81 Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 82 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data .. 93 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 93 Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 94 Figure 5.8. Temperature Sensor Transfer Function ................................................ 96 Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 97 Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 99 Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 104 Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 105 Figure 7.3. Comparator Hysteresis Plot ................................................................ 106 10 Rev. 1.0 Si1010/1/2/3/4/5 Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 111 Figure 8.1. CIP-51 Block Diagram ......................................................................... 114 Figure 9.1. Si1010/1/2/3/4/5 Memory Map ............................................................ 123 Figure 9.2. Flash Program Memory Map ............................................................... 124 Figure 13.1. Flash Program Memory Map (16 kB and 8 kB devices) .................... 148 Figure 14.1. Si1010/1/2/3/4/5 Power Distribution .................................................. 158 Figure 15.1. CRC0 Block Diagram ........................................................................ 166 Figure 15.2. Bit Reverse Register ......................................................................... 173 Figure 16.1. DC-DC Converter Block Diagram ...................................................... 174 Figure 16.2. DC-DC Converter Configuration Options .......................................... 177 Figure 18.1. Reset Sources ................................................................................... 186 Figure 18.2. Power-Fail Reset Timing Diagram .................................................... 187 Figure 18.3. Power-Fail Reset Timing Diagram .................................................... 188 Figure 19.1. Clocking Sources Block Diagram ...................................................... 194 Figure 19.2. 25 MHz External Crystal Example ..................................................... 196 Figure 20.1. SmaRTClock Block Diagram ............................................................. 203 Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 212 Figure 21.1. Port I/O Functional Block Diagram .................................................... 219 Figure 21.2. Port I/O Cell Block Diagram .............................................................. 220 Figure 21.3. Crossbar Priority Decoder with No Pins Skipped .............................. 224 Figure 21.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 225 Figure 22.1. EZRadioPRO Serial Interface Block Diagram ................................... 239 Figure 22.2. SPI Timing ......................................................................................... 241 Figure 22.3. SPI Timing—READ Mode ................................................................. 241 Figure 22.4. SPI Timing—Burst Write Mode ......................................................... 242 Figure 22.5. SPI Timing—Burst Read Mode ......................................................... 242 Figure 22.6. Master Mode Data/Clock Timing ....................................................... 243 Figure 22.7. SPI Master Timing ............................................................................. 248 Figure 23.1. State Machine Diagram ..................................................................... 251 Figure 23.2. TX Timing .......................................................................................... 254 Figure 23.3. RX Timing .......................................................................................... 255 Figure 23.4. Frequency Deviation ......................................................................... 258 Figure 23.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 260 Figure 23.6. FSK vs. GFSK Spectrums ................................................................. 262 Figure 23.7. Direct Synchronous Mode Example .................................................. 265 Figure 23.8. Direct Asynchronous Mode Example ................................................ 265 Figure 23.9. Microcontroller Connections .............................................................. 266 Figure 23.10. PLL Synthesizer Block Diagram ...................................................... 268 Figure 23.11. FIFO Thresholds ............................................................................. 271 Figure 23.12. Packet Structure .............................................................................. 272 Figure 23.13. Multiple Packets in TX Packet Handler ........................................... 273 Figure 23.14. Required RX Packet Structure with Packet Handler Disabled ........ 273 Figure 23.15. Multiple Packets in RX Packet Handler ........................................... 274 Figure 23.16. Multiple Packets in RX with CRC or Header Error .......................... 274 Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 276 Rev. 1.0 11 Si1010/1/2/3/4/5 Figure 23.18. Manchester Coding Example .......................................................... 276 Figure 23.19. Header ............................................................................................. 278 Figure 23.20. POR Glitch Parameters ................................................................... 279 Figure 23.21. General Purpose ADC Architecture ................................................ 282 Figure 23.22. Temperature Ranges using ADC8 .................................................. 284 Figure 23.23. WUT Interrupt and WUT Operation ................................................. 287 Figure 23.24. Low Duty Cycle Mode ..................................................................... 288 Figure 23.25. RSSI Value vs. Input Power ............................................................ 290 Figure 23.26. Si1002 Split RF TX/RX Direct-Tie Reference Design—Schematic . 291 Figure 23.27. Si1000 Switch Matching Reference Design—Schematic ................ 292 Figure 24.1. SMBus Block Diagram ...................................................................... 297 Figure 24.2. Typical SMBus Configuration ............................................................ 298 Figure 24.3. SMBus Transaction ........................................................................... 299 Figure 24.4. Typical SMBus SCL Generation ........................................................ 301 Figure 24.5. Typical Master Write Sequence ........................................................ 310 Figure 24.6. Typical Master Read Sequence ........................................................ 311 Figure 24.7. Typical Slave Write Sequence .......................................................... 312 Figure 24.8. Typical Slave Read Sequence .......................................................... 313 Figure 25.1. UART0 Block Diagram ...................................................................... 318 Figure 25.2. UART0 Baud Rate Logic ................................................................... 319 Figure 25.3. UART Interconnect Diagram ............................................................. 320 Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 320 Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 321 Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 321 Figure 26.1. SPI Block Diagram ............................................................................ 325 Figure 26.2. Multiple-Master Mode Connection Diagram ...................................... 327 Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave  Mode Connection Diagram ................................................................ 327 Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave  Mode Connection Diagram ................................................................ 328 Figure 26.5. Master Mode Data/Clock Timing ....................................................... 330 Figure 26.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 330 Figure 26.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 331 Figure 26.8. SPI Master Timing (CKPHA = 0) ....................................................... 335 Figure 26.9. SPI Master Timing (CKPHA = 1) ....................................................... 335 Figure 26.10. SPI Slave Timing (CKPHA = 0) ....................................................... 336 Figure 26.11. SPI Slave Timing (CKPHA = 1) ....................................................... 336 Figure 27.1. T0 Mode 0 Block Diagram ................................................................. 341 Figure 27.2. T0 Mode 2 Block Diagram ................................................................. 342 Figure 27.3. T0 Mode 3 Block Diagram ................................................................. 343 Figure 27.4. Timer 2 16-Bit Mode Block Diagram ................................................. 348 Figure 27.5. Timer 2 8-Bit Mode Block Diagram ................................................... 349 Figure 27.6. Timer 2 Capture Mode Block Diagram .............................................. 350 Figure 27.7. Timer 3 16-Bit Mode Block Diagram ................................................. 354 Figure 27.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 355 12 Rev. 1.0 Si1010/1/2/3/4/5 Figure 27.9. Timer 3 Capture Mode Block Diagram .............................................. 356 Figure 28.1. PCA Block Diagram ........................................................................... 360 Figure 28.2. PCA Counter/Timer Block Diagram ................................................... 362 Figure 28.3. PCA Interrupt Block Diagram ............................................................ 363 Figure 28.4. PCA Capture Mode Diagram ............................................................. 365 Figure 28.5. PCA Software Timer Mode Diagram ................................................. 365 Figure 28.6. PCA High-Speed Output Mode Diagram ........................................... 366 Figure 28.7. PCA Frequency Output Mode ........................................................... 367 Figure 28.8. PCA 8-Bit PWM Mode Diagram ........................................................ 368 Figure 28.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 369 Figure 28.10. PCA 16-Bit PWM Mode ................................................................... 370 Figure 28.11. PCA Module 5 with Watchdog Timer Enabled ................................ 371 Figure 29.1. Typical C2 Pin Sharing ...................................................................... 382 Rev. 1.0 13 Si1010/1/2/3/4/5 List of Tables Table 2.1. Product Selection Guide ......................................................................... 31 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 .................................................. 32 Table 3.2. QFN-42 Package Dimensions ................................................................ 39 Table 3.3. PCB Land Pattern ................................................................................... 43 Table 4.1. Absolute Maximum Ratings .................................................................... 44 Table 4.2. Global Electrical Characteristics ............................................................. 45 Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 55 Table 4.4. Reset Electrical Characteristics .............................................................. 60 Table 4.5. Power Management Electrical Specifications ......................................... 61 Table 4.6. Flash Electrical Characteristics .............................................................. 61 Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 61 Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 61 Table 4.9. SmaRTClock Characteristics .................................................................. 62 Table 4.10. ADC0 Electrical Characteristics ............................................................ 62 Table 4.11. Temperature Sensor Electrical Characteristics .................................... 63 Table 4.12. Voltage Reference Electrical Characteristics ....................................... 64 Table 4.13. IREF0 Electrical Characteristics ........................................................... 65 Table 4.14. Comparator Electrical Characteristics .................................................. 66 Table 4.15. VREG0 Electrical Characteristics ......................................................... 67 Table 4.16. DC-DC Converter (DC0) Electrical Characteristics .............................. 68 Table 4.17. DC Characteristics1 .................................................................................................... 69 Table 4.18. Synthesizer AC Electrical Characteristics1 ........................................................ 70 Table 4.19. Receiver AC Electrical Characteristics1 ............................................... 71 Table 4.20. Transmitter AC Electrical Characteristics1 ........................................................ 72 Table 4.21. Auxiliary Block Specifications1 ............................................................................... 73 Table 4.22. Digital IO Specifications (nIRQ) ............................................................................. 74 Table 4.23. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ................................ 74 Table 4.24. Absolute Maximum Ratings .................................................................. 75 Table 5.1. Representative Conversion Times and Energy Consumption for the SAR ADC with 1.65V High-Speed VREF ........................................................ 84 Table 8.1. CIP-51 Instruction Set Summary .......................................................... 116 Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 128 Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 129 Table 11.3. Special Function Registers ................................................................. 130 Table 12.1. Interrupt Summary .............................................................................. 136 Table 13.1. Flash Security Summary .................................................................... 149 Table 14.1. Power Modes ...................................................................................... 157 Table 15.1. Example 16-Bit CRC Outputs ............................................................. 167 Table 16.1. IPeak Inductor Current Limit Settings ................................................. 175 Table 19.1. Recommended XFCN Settings for Crystal Mode ............................... 196 Table 19.2. Recommended XFCN Settings for RC and C modes ......................... 197 Table 20.1. SmaRTClock Internal Registers ......................................................... 204 Table 20.2. SmaRTClock Load Capacitance Settings .......................................... 211 14 Rev. 1.0 Si1010/1/2/3/4/5 Table 20.3. SmaRTClock Bias Settings ................................................................ 212 Table 21.1. Port I/O Assignment for Analog Functions ......................................... 221 Table 21.2. Port I/O Assignment for Digital Functions ........................................... 222 Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 222 Table 22.1. Serial Interface Timing Parameters .................................................... 241 Table 22.2. SPI Timing Parameters ...................................................................... 248 Table 23.1. EZRadioPRO Operating Modes ......................................................... 250 Table 23.2. EZRadioPRO Operating Modes Response Time ............................... 251 Table 23.3. Frequency Band Selection ................................................................. 256 Table 23.4. Packet Handler Registers ................................................................... 275 Table 23.5. Minimum Receiver Settling Time ........................................................ 277 Table 23.6. POR Parameters ................................................................................ 280 Table 23.7. Temperature Sensor Range ............................................................... 283 Table 23.8. Antenna Diversity Control ................................................................... 289 Table 23.9. EZRadioPRO Internal Register Descriptions ...................................... 294 Table 24.1. SMBus Clock Source Selection .......................................................... 301 Table 24.2. Minimum SDA Setup and Hold Times ................................................ 302 Table 24.3. Sources for Hardware Changes to SMB0CN ..................................... 306 Table 24.4. Hardware Address Recognition Examples (EHACK = 1) ................... 307 Table 24.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) ....................................................................................... 314 Table 24.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) ....................................................................................... 316 Table 25.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator .............................................. 324 Table 25.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator ......................................... 324 Table 26.1. SPI Slave Timing Parameters ............................................................ 337 Table 27.1. Timer 0 Running Modes ..................................................................... 340 Table 28.1. PCA Timebase Input Options ............................................................. 361 Table 28.2. PCA0CPM and PCA0PWM Bit Settings for PCA  Capture/Compare Modules ................................................................ 364 Table 28.3. Watchdog Timer Timeout Intervals1 ................................................... 372 Rev. 1.0 15 Si1010/1/2/3/4/5 List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 85 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 86 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 87 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 88 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 89 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 90 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 90 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 91 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 91 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 92 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 92 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 95 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 98 SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 98 SFR Definition 5.15. REF0CN: Voltage Reference Control ........................................ 101 SFR Definition 6.1. IREF0CN: Current Reference Control ......................................... 102 SFR Definition 6.2. IREF0CF: Current Reference Configuration ................................ 103 SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 107 SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 108 SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 109 SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 110 SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 112 SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 113 SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 120 SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 120 SFR Definition 8.3. SP: Stack Pointer ......................................................................... 121 SFR Definition 8.4. ACC: Accumulator ....................................................................... 121 SFR Definition 8.5. B: B Register ................................................................................ 121 SFR Definition 8.6. PSW: Program Status Word ........................................................ 122 SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 127 SFR Definition 11.1. SFR Page: SFR Page ................................................................ 130 SFR Definition 12.1. IE: Interrupt Enable .................................................................... 138 SFR Definition 12.2. IP: Interrupt Priority .................................................................... 139 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 ............................................ 140 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 ............................................ 141 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 ............................................ 142 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 ............................................ 143 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration .............................................. 145 SFR Definition 13.1. PSCTL: Program Store R/W Control ......................................... 154 SFR Definition 13.2. FLKEY: Flash Lock and Key ...................................................... 155 SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 156 SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 156 SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2 ................ 163 16 Rev. 1.0 Si1010/1/2/3/4/5 SFR Definition 14.2. PMU0MD: Power Management Unit Mode ................................ 164 SFR Definition 14.3. PCON: Power Management Control Register ........................... 165 SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 169 SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 170 SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 170 SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 171 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 172 SFR Definition 15.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 173 SFR Definition 16.1. DC0CN: DC-DC Converter Control ........................................... 181 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration .................................. 182 SFR Definition 16.3. DC0MD: DC-DC Mode .............................................................. 183 SFR Definition 17.1. REG0CN: Voltage Regulator Control ........................................ 184 SFR Definition 18.1. VDM0CN: VDD_MCU/DC+ Supply Monitor Control .................. 190 SFR Definition 18.2. RSTSRC: Reset Source ............................................................ 193 SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 200 SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 201 SFR Definition 19.3. OSCICL: Internal Oscillator Calibration ..................................... 201 SFR Definition 19.4. OSCXCN: External Oscillator Control ........................................ 202 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key .................................... 207 SFR Definition 20.2. RTC0ADR: SmaRTClock Address ............................................ 208 SFR Definition 20.3. RTC0DAT: SmaRTClock Data .................................................. 209 Internal Register Definition 20.4. RTC0CN: SmaRTClock Control ............................. 215 Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control ........... 216 Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration . 217 Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration ............ 217 Internal Register Definition 20.8. CAPTUREn: SmaRTClock Timer Capture ............. 218 Internal Register Definition 20.9. ALARMn: SmaRTClock Alarm Programmed Value 218 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 .......................................... 226 SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1 .......................................... 227 SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2 .......................................... 228 SFR Definition 21.4. P0MASK: Port0 Mask Register .................................................. 229 SFR Definition 21.5. P0MAT: Port0 Match Register ................................................... 229 SFR Definition 21.6. P1MASK: Port1 Mask Register .................................................. 230 SFR Definition 21.7. P1MAT: Port1 Match Register ................................................... 230 SFR Definition 21.8. P0: Port0 .................................................................................... 232 SFR Definition 21.9. P0SKIP: Port0 Skip .................................................................... 232 SFR Definition 21.10. P0MDIN: Port0 Input Mode ...................................................... 233 SFR Definition 21.11. P0MDOUT: Port0 Output Mode ............................................... 233 SFR Definition 21.12. P0DRV: Port0 Drive Strength .................................................. 234 SFR Definition 21.13. P1: Port1 .................................................................................. 235 SFR Definition 21.14. P1SKIP: Port1 Skip .................................................................. 235 SFR Definition 21.15. P1MDIN: Port1 Input Mode ...................................................... 236 SFR Definition 21.16. P1MDOUT: Port1 Output Mode ............................................... 236 SFR Definition 21.17. P1DRV: Port1 Drive Strength .................................................. 237 SFR Definition 21.18. P2: Port2 .................................................................................. 237 Rev. 1.0 17 Si1010/1/2/3/4/5 SFR Definition 21.19. P2MDOUT: Port2 Output Mode ............................................... 238 SFR Definition 21.20. P2DRV: Port2 Drive Strength .................................................. 238 SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 244 SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 245 SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 246 SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 247 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ...................................... 303 SFR Definition 24.2. SMB0CN: SMBus Control .......................................................... 305 SFR Definition 24.3. SMB0ADR: SMBus Slave Address ............................................ 308 SFR Definition 24.4. SMB0ADM: SMBus Slave Address Mask .................................. 308 SFR Definition 24.5. SMB0DAT: SMBus Data ............................................................ 309 SFR Definition 25.1. SCON0: Serial Port 0 Control .................................................... 322 SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 323 SFR Definition 26.7. SPI0CFG: SPI0 Configuration ................................................... 332 SFR Definition 26.8. SPI0CN: SPI0 Control ............................................................... 333 SFR Definition 26.9. SPI0CKR: SPI0 Clock Rate ....................................................... 334 SFR Definition 26.10. SPI0DAT: SPI0 Data ............................................................... 334 SFR Definition 27.1. CKCON: Clock Control .............................................................. 339 SFR Definition 27.2. TCON: Timer Control ................................................................. 344 SFR Definition 27.3. TMOD: Timer Mode ................................................................... 345 SFR Definition 27.4. TL0: Timer 0 Low Byte ............................................................... 346 SFR Definition 27.5. TL1: Timer 1 Low Byte ............................................................... 346 SFR Definition 27.6. TH0: Timer 0 High Byte ............................................................. 347 SFR Definition 27.7. TH1: Timer 1 High Byte ............................................................. 347 SFR Definition 27.8. TMR2CN: Timer 2 Control ......................................................... 351 SFR Definition 27.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 352 SFR Definition 27.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 352 SFR Definition 27.11. TMR2L: Timer 2 Low Byte ....................................................... 353 SFR Definition 27.12. TMR2H Timer 2 High Byte ....................................................... 353 SFR Definition 27.13. TMR3CN: Timer 3 Control ....................................................... 357 SFR Definition 27.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 358 SFR Definition 27.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 358 SFR Definition 27.16. TMR3L: Timer 3 Low Byte ....................................................... 359 SFR Definition 27.17. TMR3H Timer 3 High Byte ....................................................... 359 SFR Definition 28.1. PCA0CN: PCA Control .............................................................. 373 SFR Definition 28.2. PCA0MD: PCA Mode ................................................................ 374 SFR Definition 28.3. PCA0PWM: PCA PWM Configuration ....................................... 375 SFR Definition 28.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 376 SFR Definition 28.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 377 SFR Definition 28.6. PCA0H: PCA Counter/Timer High Byte ..................................... 377 SFR Definition 28.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 378 SFR Definition 28.8. PCA0CPHn: PCA Capture Module High Byte ........................... 378 C2 Register Definition 29.1. C2ADD: C2 Address ...................................................... 379 C2 Register Definition 29.2. DEVICEID: C2 Device ID ............................................... 380 C2 Register Definition 29.3. REVID: C2 Revision ID .................................................. 380 18 Rev. 1.0 Si1010/1/2/3/4/5 C2 Register Definition 29.4. FPCTL: C2 Flash Programming Control ........................ 381 C2 Register Definition 29.5. FPDAT: C2 Flash Programming Data ............................ 381 Rev. 1.0 19 Si1010/1/2/3/4/5 1. System Overview Si1010/1/2/3/4/5 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.           240–960 MHz EZRadioPRO® transceiver Single/Dual Battery operation with on-chip dc-dc boost converter. High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) 10-bit 300 ksps or 12-bit 75 ksps single-ended ADC with analog multiplexer 6-Bit Programmable Current Reference. Resolution can be increased with PWM. Precision programmable 24.5 MHz internal oscillator with spread spectrum technology. 16 kB or 8 kB of on-chip Flash memory 768 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and two Enhanced SPI serial interfaces implemented in hardware  Four general-purpose 16-bit timers  Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer function  On-chip Power-On Reset, VDD Monitor, and Temperature Sensor Two On-chip Voltage Comparators with 11 Capacitive Touch Sense inputs.  15 Port I/O (5 V tolerant except for GPIO_0, GPIO_1, and GPIO_2) With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the Si1010/1/2/3/4/5 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings.  The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 0.9 to 1.8 V, 0.9 to 3.6 V or 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The Si1010/1/2/3/4/5 devices are available in a 42-pin QFN package which is lead-free and RoHS compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 through Figure 1.4. The transceiver's extremely low receive sensitivity (–121 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. The advanced radio features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption. The transceivers digital receive architecture features a high-performance ADC and DSP-based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading, ensuring compliance with global regulations including FCC, ETSI, ARIB, and 802.15.4d regulations. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. 20 Rev. 1.0 Si1010/1/2/3/4/5 CIP-51 8051 Controller Core 16k Byte ISP Flash Program Memory 256 Byte SRAM 512 Byte XRAM CRC Engine SYSCLK Power On Reset/PMU Wake Reset Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 12/10-bit 75/300 ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 15 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.1. Si1010 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8k Byte ISP Flash Program Memory 256 Byte SRAM 512 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 12/10-bit 75/300 ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 15 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.2. Si1011 Block Diagram Rev. 1.0 21 Si1010/1/2/3/4/5 Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 16k Byte ISP Flash Program Memory 256 Byte SRAM 512 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 12/10-bit 75/300 ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 15 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.3. Si1012 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8k Byte ISP Flash Program Memory 256 Byte SRAM 512 Byte XRAM CRC Engine SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 12/10-bit 75/300 ksps ADC RXp RXn VDD GND VREG Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator XTAL1 XTAL2 External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL3 XTAL4 Priority Crossbar Decoder 15 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.4. Si1013 Block Diagram 22 Rev. 1.0 Si1010/1/2/3/4/5 Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 16k Byte ISP Flash Program Memory 256 Byte SRAM 512 Byte XRAM CRC Engine Digital Power SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 12/10-bit 75/300 ksps ADC RXp RXn VDD/DC+ GND/DC- Power Net Analog Power VREG VBAT GND DC/DC Converter Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL1 XTAL2 XTAL3 XTAL4 Priority Crossbar Decoder 15 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.5. Si1014 Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 8k Byte ISP Flash Program Memory 256 Byte SRAM 512 Byte XRAM CRC Engine Digital Power SYSCLK Analog Peripherals 6-bit IREF Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - RF XCVR (240-960 MHz) IREF0 PA TX AGC LNA Mixer PGA ADC C2CK/RST Debug / Programming Hardware C2D 12/10-bit 75/300 ksps ADC RXp RXn VDD/DC+ GND/DC- Power Net Analog Power VREG VBAT GND DC/DC Converter Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator External Oscillator Circuit SmaRTClock Oscillator SFR Bus + - Comparators Digital Modem Delta Sigma Modulator Digital Logic Digital Peripherals Transceiver Control Interface UART Timers 0, 1, 2, 3 PCA/ WDT SMBus SPI 0 Port I/O Config OSC XTAL1 XTAL2 XTAL3 XTAL4 Priority Crossbar Decoder 15 XIN XOUT System Clock Configuration ANALOG & DIGITAL I/O Figure 1.6. Si1015 Block Diagram Rev. 1.0 23 Si1010/1/2/3/4/5 1.1. Typical Connection Diagram The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference design is available from Silicon Laboratories applications support. For applications seeking improved performance in the presence of multipath fading, antenna diversity can be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support. supply voltage C6 100p C7 100n C8 1u SDN X1 30MHz XOUT L1 L2 L4 C3 L3 C2 C4 C1 TX RFp RXn nIRQ VDD_M CU VDD_DIG Px.x VDD_RF XIN Si101x GPIO0 GPIO1 GPIO2 L6 L5 VR_DIG 0.1 uF 0.1 uF ANT C9 C5 1u Programm able load capacitors for X1 are integrated. L1-L6 and C1-C5 values depend on frequency band , antenna im pedance, output power and supply voltage range. Figure 1.7. Si1012/3 RX/TX Direct-Tie Application Example Supply Voltage C6 100 p C7 100 n C8 1u SDN X1 30MHz XOUT TR & ANT-DIV Switch 1 2 3 6 5 4 L1 L3 C3 L2 C2 C1 TX RXp RXn C4 VDD_RF nIRQ VDD_MCU VDD_DIG Px.x XIN Si101x GPIO0 GPIO1 GPIO2 L4 VR_DIG 0.1 uF 0.1 uF C9 C5 1u Programmable load capacitors for X1 are integrated. L1–L4 and C1–C5 values depend on frequency band, antenna impedance, output power, and supply voltage range. Figure 1.8. Si1010/1 Antenna Diversity Application Example 24 Rev. 1.0 Si1010/1/2/3/4/5 1.2. CIP-51™ Microcontroller Core 1.2.1. Fully 8051 Compatible The Si1010/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.2.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.2.3. Additional Features The Si1010/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Rev. 1.0 25 Si1010/1/2/3/4/5 1.3. Port Input/Output Digital and analog resources are available through 12 I/O pins. Port pins are organized as three byte-wide ports. Port pins P0.0–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P1.0, P1.1, P1.2, and P1.3 are dedicated for communication with the EZRadioPRO peripheral. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “29. C2 Interface” on page 379 for more details. The designer has complete control over which digital and analog functions are assigned to individual Port pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on page 223 for more information on the Crossbar. All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os configured as push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog functions can operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on page 220 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. XBR0, XBR1, XBR2, PnSKIP Registers Port Match P0MASK, P0MAT P1MASK, P1MAT Priority Decoder Highest Priority UART SPI0 SPI1 (Internal Digital Signals) SMBus CP0 CP1 Outputs SYSCLK PCA Lowest Priority T0, T1 7 2 8 P0 (Port Latches) (P0.0-P0.7) 7 P1 (P1.0-P1.6) 1 P2 (P2.7) To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) 1 P2 I/O Cell 2 4 2 External Interrupts EX0 and EX1 PnMDOUT, PnMDIN Registers P0.0 Digital Crossbar 4 8 P0 I/O Cells P0.7 P1.4 P1 I/O Cells P1.5 P1.6 7 P2.7 No analog functionality available on P2.7 Note: P1.0, P1.1, P1.2, and P1.3 are internally connected to the EZRadioPRO peripheral. Figure 1.9. Port I/O Functional Block Diagram 26 Rev. 1.0 Si1010/1/2/3/4/5 1.4. Serial Ports The Si1010/1/2/3/4/5 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.5. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. ‘F912 and ‘F902 devices also support a SmaRTClock divided by 8 clock source. Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 SmaRTClock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 Capture/Compare Module 3 Capture/Compare Module 4 Capture/Compare Module 5 / WDT CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI Crossbar Port I/O Figure 1.10. PCA Block Diagram Rev. 1.0 27 Si1010/1/2/3/4/5 1.6. SAR ADC with 16-Bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Si1010/1/2/3/4/5 devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically average the ADC results, providing an effective 11, 12, or 13 bit ADC result without any additional CPU intervention. The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs include an on-chip temperature sensor, the VDD/DC+ supply voltage, the VBAT supply voltage, and the internal digital supply voltage. ADC0CN BURSTEN AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 AD0INT AD0EN VDD ADC0TK ADC0PWR Burst Mode Logic Start Conversion AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 3 Overflow CNVSTR Input From AMUX0 AIN+ SYSCLK REF ADC0H ADC ADC0L 10/12-Bit SAR 16-Bit Accumulator AD0WINT Window Compare Logic AMP0GN AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD08BE AD0TM ADC0LTH ADC0LTL 32 ADC0CF ADC0GTH ADC0GTL Figure 1.11. ADC0 Functional Block Diagram 28 Rev. 1.0 Si1010/1/2/3/4/5 ADC0MX AM0MX0 AD0MX4 AD0MX3 AD0MX2 AD0MX1 P0.0 Programmable Attenuator AIN+ P1.6* Temp Sensor AMUX ADC0 VBAT Digital Supply VDD_MCU/DC+ Gain = 0. 5 or 1 *P1.0 – P1.3 are not available as device pins Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si1010/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.8. Comparators Si1010/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) which is shown in Figure 1.13; Comparator 1 (CPT1) which is shown in Figure 1.14. The two comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section “18. Reset Sources” on page 185 and the Section “14. Power Management” on page 157 for details on reset sources and low power mode wake-up sources, respectively. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be used to directly sense capacitive touch switches. See Application Note AN338 for details on Capacitive Touch Switch sensing. Rev. 1.0 29 Si1010/1/2/3/4/5 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer CP0MD0 CP0MD1 Px.x CPT0CN VDD CP0 Interrupt CPT0MD CP0RIE CP0FIE CP0 Rising-edge CP0 Falling-edge CP0 + Px.x Interrupt Logic + D SET CP0 Q D SET Q Px.x CP0 GND CLR Q CLR Q Crossbar (SYNCHRONIZER) (ASYNCHRONOUS) CP0A Px.x Reset Decision Tree Figure 1.13. Comparator 0 Functional Block Diagram CP1EN CPT0CN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 VDD CP1 Interrupt Analog Input Multiplexer CP1MD0 CP1MD1 Px.x CPT0MD CP1RIE CP1FIE CP1 Rising-edge CP1 Falling-edge CP1 + Px.x Interrupt Logic + D SET CP1 Q D SET Q Px.x CP1 GND CLR Q CLR Q Crossbar (SYNCHRONIZER) (ASYNCHRONOUS) CP1A Px.x Reset Decision Tree Figure 1.14. Comparator 1 Functional Block Diagram 30 Rev. 1.0 Si1010/1/2/3/4/5 2. Ordering Information Table 2.1. Product Selection Guide Enhanced SPI (available for external communication) Digital Port I/Os (Includes EZRadioPRO GPIOs) SmaRTClock Real Time Clock Minimum Operating Voltage (Volts) Programmable Counter Array Ordering Part Number Lead-free (RoHS Compliant) Internal Voltage Reference Maximum Transmit Power Flash Memory (kB) RAM (bytes) MIPS (Peak) SMBus/I2C ‘F9xx Plus Features* P P P P P P Temperature Sensor 10-bit 300ksps ADC Timers (16-bit) Si1010-A-GM 25 16 768 Si1011-A-GM 25 8 768 P P P P P P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 4 4 P 15 P P 15 P P 15 P P 15 P P 15 P P 15 P P P P P P P P +20 dBm 1.8 P P +20 dBm 1.8 P P +13 dBm 1.8 P P +13 dBm 1.8 P P +13 dBm 0.9 P P +13 dBm 0.9 P QFN-42 QFN-42 QFN-42 QFN-42 QFN-42 QFN-42 Si1012-A-GM 25 16 768 Si1013-A-GM 25 8 768 Si1014-A-GM 25 16 768 Si1015-A-GM 25 8 768 *The ‘F9xx Plus features are a set of enhancements that allow greater power efficiency and increased functionality. They include 12-bit ADC mode, PWM Enhanced IREF, ultra-low power SmaRTClock LFO, VBAT input voltage from 0.9 to 3.6 V, and VBAT battery low indicator. The ‘F9xx Plus features are described in detail in “AN431: F93x-F90x Software Porting Guide.” Rev. 1.0 Package 31 UART Si1010/1/2/3/4/5 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 Name Pin Number Si1010/1 Si1014/5 Si1012/3 VDD_MCU GND_MCU VBAT GND VBAT38 37 — — — — 41 38 P In G P In P In G Power Supply Voltage for the entire MCU except for the EZRadioPRO peripheral. Must be 1.8 to 3.6 V. Required Ground for the entire MCU except for the  EZRadioPRO peripheral. Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in dual-cell battery mode. In dual-cell battery mode, this pin must be connected directly to ground. In one-cell applications, this pin should be connected directly to the negative battery terminal, which is not connected to the ground plane. DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to VBAT through a 0.68 µH inductor. In dual-cell battery mode, this pin must be connected directly to ground. Power Supply Voltage for the entire MCU except for the EZRadioPRO peripheral. Must be 1.8 to 3.6 V. This supply voltage is not required in low power sleep mode. This voltage must always be > VBAT. Positive output of the dc-dc converter. In single-cell battery mode, a 1uF ceramic capacitor is required between dc+ and dc–. This pin can supply power to external devices when operating in single-cell battery mode. In dual-cell battery mode, this pin must be connected directly to ground. DC-DC converter return current path. In one-cell mode, this pin must be connected to the ground plane. Power Supply Voltage for the analog portion of the  EZRadioPRO peripheral. Must be 1.8 to 3.6 V. Power Supply Voltage for the digital portion of the  EZRadioPRO peripheral. Must be 1.8 to 3.6 V. Regulated Output Voltage of the digital 1.7 V regulator for the EZRadioPRO peripheral. A 1 µF decoupling capacitor is required. Required Ground for the digital and analog portions of the EZRadioPRO peripheral. Type Description DCEN — 40 P In G VDD_MCU / — 39 P In DC+ P Out GND_MCU DC– VDD_RF VDD_DIG VR_DIG — 37 G G 16 28 27 16 28 27 P In P In P Out GND_RF 23 23 G 32 Rev. 1.0 Si1010/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Si1010/1 Si1014/5 Si1012/3 RST/ 39 42 D I/O Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1–5 k pullup to VDD_MCU is recommended. See Reset Sources section for a complete description. Clock signal for the C2 Debug Interface. Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O section for a complete description. Bi-directional data signal for the C2 Debug Interface. SmaRTClock Oscillator Crystal Input. See Section 20 for a complete description. SmaRTClock Oscillator Crystal Output. See Section 20 for a complete description. Type Description C2CK P2.7/ 40 1 D I/O D I/O C2D XTAL3 XTAL4 P0.0 1 42 36 3 2 36 D I/O A In A Out D I/O or Port 0.0. See Port I/O section for a complete description. A In A In A Out External VREF Input. Internal VREF Output. External VREF decoupling capacitors are recommended. See Voltage Reference section. VREF P0.1 35 35 D I/O or Port 0.1. See Port I/O Section for a complete description. A In G Optional Analog Ground. See VREF chapter. AGND P0.2 34 34 D I/O or Port 0.2. See Port I/O Section for a complete description. A In A In External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Oscillator section. XTAL1 P0.3 33 33 D I/O or Port 0.3. See Port I/O Section for a complete description. A In A Out D In A In External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Oscillator section for complete details. XTAL2 Rev. 1.0 33 Si1010/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Si1010/1 Si1014/5 Si1012/3 P0.4 32 32 D I/O or Port 0.4. See Port I/O section for a complete description. A In D Out 31 31 UART TX Pin. See Port I/O section. Type Description TX P0.5 D I/O or Port 0.5. See Port I/O section for a complete description. A In D In UART RX Pin. See Port I/O section. RX P0.6 30 30 D I/O or Port 0.6. See Port I/O section for a complete description. A In D In External Convert Start Input for ADC0. See ADC0 section for a complete description. CNVSTR P0.7 IREF0 P1.4 P1.5 P1.6 GPIO_0 GPIO_1 GPIO_2 nIRQ 6 5 4 24 25 26 11 6 5 4 24 25 26 11 29 29 D I/O or Port 0.7. See Port I/O section for a complete description. A In A Out IREF0 Output. See IREF section for complete description. D I/O or Port 1.4. See Port I/O section for a complete description. A In D I/O or Port 1.5. See Port I/O section for a complete description. A In D I/O or Port 1.6. See Port I/O section for a complete description. A In D I/O or General Purpose I/O controlled by the EZRadioPRO periphA I/O eral. May be configured through the EZRadioPRO registers to perform various functions including: Clock Output, FIFO D I/O or status, POR, Wake-Up Timer, Low Battery Detect, TRSW, A I/O AntDiversity control, etc. See the EZRadioPRO GPIO ConD I/O or figuration Registers for more information. A I/O DO EZRadioPRO peripheral interrupt status pin. Will be set low to indicate a pending EZRadioPRO interrupt event. See the EZRadioPRO Control Logic Registers for more details. This pin is an open-drain output with a 220 k internal pullup resistor. An external pull-up resistor is recommended. EZRadioPRO peripheral crystal oscillator output. Connect to an external 30 MHz crystal or leave floating if driving the XIN pin with an external signal source. EZRadioPRO peripheral crystal oscillator input. Connect to an external 30 MHz crystal or to an external source. If using an external clock source with no crystal, dc coupling with a nominal 0.8 VDC level is recommended with a minimum ac amplitude of 700 mVpp. XOUT 12 12 AO XIN 13 13 AI 34 Rev. 1.0 Si1010/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued) Name Pin Number Si1010/1 Si1014/5 Si1012/3 NC SDN 14, 20, 22 15 14, 20, 22 15 DI No Connect. May be left floating or tied to power or ground. EZRadioPRO peripheral shutdown pin. When driven to logic HIGH, the EZRadioPRO peripheral will be completely shut down and the contents of the EZRadioPRO registers will be lost. This pin should be driven to logic LOW during all other times; this pin should never be left floating. EZRadioPRO peripheral transmit RF output pin. The PA output is an open-drain connection so the L-C match must supply (1.8 to 3.6 VDC) to this pin. EZRadioPRO peripheral differential RF input pins of the LNA. See application schematic for example matching network. EZRadioPRO antenna diversity GPIO Ant1 signal direct digital output. Refer to the description of GPIO Ant1 in the Function and Control 2 register. A complete description may be found in “AN440: EZRadioPRO Detailed Transceiver Register Descriptions.” Type Description TX 17 17 AO RXp RXn ANT_A 18 19 21 18 19 21 AI AI DO Rev. 1.0 35 Si1010/1/2/3/4/5 GND_MCU 37 P0.0/VREF 36 RST/C2CK 39 VDD_MCU 38 42 41 XTAL3 N.C. N.C. P1.6 P1.5 P1.4 N.C. N.C. N.C. N.C. nIRQ XOUT XIN N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 40 P2.7/C2D XTAL4 N.C. 35 34 33 32 31 P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 VDD_DIG VR_DIG GPIO_2 GPIO_1 GPIO_0 GND_RF N.C. GND_M CU Si1010/1/2/3 Top View 30 29 28 27 26 25 24 GND_RF 23 22 TX VDD_RF Figure 3.1. Si1010/1/2/3 Pinout Diagram (Top View) 36 Rev. 1.0 ANT_A SDN N.C. RXp RXn Si1010/1/2/3/4/5 VDD_MCU/DC+ GND_MCU/DC37 GND/VBAT- 42 41 40 39 38 P2.7/C2D XTAL4 XTAL3 P1.6 P1.5 P1.4 N.C. N.C. N.C. N.C. nIRQ XOUT XIN N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 36 P0.0/VREF RST/C2CK DCEN VBAT 35 34 33 32 31 P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7/IREF0 VDD_DIG VR_DIG GPIO_2 GPIO_1 GPIO_0 GND_RF N.C. GND_M CU Si1014/5 Top View 30 29 28 27 26 25 24 GND_RF 23 22 VDD_RF SDN RXp RXn N.C. TX Figure 3.2. Si1004/5 Pinout Diagram (Top View) Rev. 1.0 ANT_A 37 Si1010/1/2/3/4/5   Figure 3.3. QFN-42 Package Drawing 38 Rev. 1.0 Si1010/1/2/3/4/5 Table 3.2. QFN-42 Package Dimensions Dimension A b D D1 D2 D3 D4 e E E1 E2 E3 E4 Min 0.60 0.20 Typ 0.65 0.25 5.00 BSC 3.00 BSC 4.25 BSC 3.16 2.73 0.50 BSC 7.00 BSC 6.50 BSC 3.00 BSC 2.97 2.63 Max 0.70 0.30 Dimension F G L L1 L2 L3 P14 P24 aaa bbb ccc ddd fff Min Typ Max 0.07 REF 1.42 BSC 0.25 0.30 0.35 0.50 0.55 0.60 0.10 REF 0.125 REF 0.525 BSC 0.475 BSC — — — — — — — — — — 0.15 0.10 0.10 0.05 0.10 3.11 2.68 3.21 2.78 2.92 2.58 3.02 2.68 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. All pitches other than P1, P2 are represented by e. Rev. 1.0 39 Si1010/1/2/3/4/5   Figure 3.4. Typical QFN-42 Landing Diagram 40 Rev. 1.0 Si1010/1/2/3/4/5   Figure 3.5. VIA Placement and Keepout Region Rev. 1.0 41 Si1010/1/2/3/4/5   Figure 3.6. Typical PCB Stencil Diagram 42 Rev. 1.0 Si1010/1/2/3/4/5 Table 3.3. PCB Land Pattern Dimension C1 X1 (27x) Y1 (27x) C2 X2 (15x) Y2 (15x) E K X3 X4 Y4 Y5 X6 Y6 X7 Y7 General 1. 2. All dimensions shown are in millimeters (mm) unless otherwise noted. This land pattern design is based on the IPC-7351 guidelines. High-Tg PCB materials (Glass Transition Temperature > 170° C are recommended for Pb-free reflow profiles per standard industry practice. PCB design must ensure sufficient thermal relief for operation of the device. Via placement must minimize mechanical stress due to CTE mismatch between PCB material and the package while maintaining electrical or thermal performance as required for the particular application. a. A minimum of four vias are required under each E-pad; eight or more vias are recommended for designs that require increased thermal conductivity. b. Via diameters should be between 0.20 and 0.31 mm (8 to 12 mil). c. Metal-to-metal distance between outer edge of via diameter and closest edge of device perimeter pad must be > 1.00 mm (dimension "K"). d. Vias may be placed as desired within the non-hatched area of the E-pads. Final via size and quantity is dependent on choice of PCB materials and total thermal relief provided by internal Cu plane in the PCB. e. Vias should either be filled or tented on the top-side of the board to prevent solder from migrating away from the E-pads during reflow. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad should be 60 µm minimum around the pad. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. The stencil thickness should be 0.125 mm (5 mils). The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. A 3x3 array of 0.7 mm square openings on 0.9 mm pitch should be used for the upper center ground pad. A 3x3 array of 0.8 mm square openings on 1.0 mm pitch should be used for the lower center ground pad. A No-Clean, Type-3 solder paste is recommended. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Value 4.75 0.95 0.30 7.00 0.30 0.70 0.50 >1.00 0.125 2.73 2.63 1.59 3.16 2.97 0.07 1.42 PCB Design 1. 2. 3. Solder Mask Design 1. Stencil Design 1. 2. 3. 4. 5. 1. 2. Card Assembly Rev. 1.0 43 Si1010/1/2/3/4/5 4. Electrical Characteristics In Section 4.1 and Section 4.2, “VDD” refers to the VDD_MCU supply voltage on Si1010/1/2/3 devices and to the VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in these two sections do not apply to the EZRadioPRO peripheral. In Section 4.3 and Section 4.4, “VDD” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifications in these sections pertain to the EZRadioPRO peripheral. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Px.x I/O Pin or RST with Respect to GND Voltage on VBAT with respect to GND Voltage on VDD_MCU or VDD_MCU/DC+ with respect to GND Maximum Total Current through VBAT, DCEN, VDD_MCU/DC+ or GND Maximum Output Current Sunk by RST or any Px.x Pin Maximum Total Current through all Px.x Pins DC-DC Converter Output Power ESD (Human Body Model) All pins except TX, RXp, and RXn TX, RXp, and RXn ESD (Machine Model) All pins except TX, RXp, and RXn TX, RXp, and RXn VDD > 2.2 V VDD < 2.2 V One-Cell Mode Two-Cell Mode Conditions Min –55 –65 –0.3 –0.3 –0.3 –0.3 –0.3 Typ — — — — — — — Max 125 150 5.8 VDD + 3.6 4.0 4.0 4.0 Units °C °C V V V — — 500 mA — — — — — — — — — — — — — — 100 200 110 2 1 150 45 mA mA mW kV kV V V Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 44 Rev. 1.0 Si1010/1/2/3/4/5 4.2. Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for the EZRadioPRO peripheral placed in shutdown mode. Parameter Battery Supply Voltage (VBAT) Supply Voltage (VDD_MCU/DC+) Minimum RAM Data  Retention Voltage1 SYSCLK (System Clock)2 TSYSH (SYSCLK High Time) TSYSL (SYSCLK Low Time) Specified Operating  Temperature Range Conditions One-Cell Mode Two-Cell Mode One-Cell Mode Two-Cell Mode VDD (not in Sleep Mode) VBAT (in Sleep Mode) Min 0.9 1.8 1.8 1.8 — — 0 18 18 –40 Typ 1.2 2.4 1.9 2.4 1.4 0.3 — — — — Max 3.6 3.6 3.6 3.6 — 0.5 25 — — +85 Units V V V MHz ns ns °C Rev. 1.0 45 Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for the EZRadioPRO peripheral placed in shutdown mode. Parameter IDD 3, 4, 5, 6 Conditions VDD = 1.8–3.6 V, F = 24.5 MHz  (includes precision oscillator current) VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.6 V, F = 32.768 kHz  (includes SmaRTClock oscillator current) Min Typ Max Units Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) — — — — — — — 4.0 3.4 265 305 84 191 102 5.0 — — — — — — mA mA µA µA µA µA/MHz µA/MHz IDD Frequency Sensitivity3, 5, 6 VDD = 1.8–3.6 V, T = 25 °C, F < 14 MHz (Flash oneshot active, see Section 13.6) VDD = 1.8–3.6 V, T = 25 °C, F > 14 MHz (Flash oneshot bypassed, see Section 13.6) Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) IDD4, 6, 7 VDD = 1.8–3.6 V, F = 24.5 MHz  (includes precision oscillator current) VDD = 1.8–3.6 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.6 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.6 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency Sensitivity1,6,7 VDD = 1.8–3.6 V, T = 25 °C — — — — — — 2.1 1.6 160 185 82 79 3.0 — — — — — mA mA µA µA µA µA/MHz 46 Rev. 1.0 Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for the EZRadioPRO peripheral placed in shutdown mode. Parameter Digital Supply Current6  (Suspend Mode) Conditions Min Typ Max Units Digital Supply Current—Suspend and Sleep Mode VDD = 1.8–3.6 V, two-cell mode — — — — — — — 77 0.61 0.76 0.87 1.32 1.62 1.93 — — — — — — — µA µA Digital Supply Current 1.8 V, T = 25 °C (Sleep Mode, SmaRTClock 3.0 V, T = 25 °C running, 32.768 kHz crystal) 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) Digital Supply Current (Sleep Mode, SmaRTClock running, internal LFO) Digital Supply Current (Sleep Mode) 1.8 V, T = 25 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.6 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.6 V, T = 85 °C (includes VBAT supply monitor) 1.8 V, T = 25 °C — 0.31 — µA — — — — — — — 0.06 0.09 0.14 0.77 0.92 1.23 0.02 — — — — — — — µA Digital Supply Current (Sleep Mode, VBAT Supply Monitor Disabled) µA Rev. 1.0 47 Si1010/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. All supply current specs are for the EZRadioPRO peripheral placed in shutdown mode. Parameter Conditions Min Typ Max Units Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte Flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. Includes oscillator and regulator supply current. 5. IDD can be estimated for frequencies 14 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4 mA – (25 MHz – 20 MHz) x 0.102 mA/MHz = 3.5 mA assuming the same oscillator setting. 6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be estimated using the following equation: Supply Voltage  Supply Current (two-cell mode) VBAT Current (one-cell mode) = ---------------------------------------------------------------------------------------------------------------------------------DC-DC Converter Efficiency  VBAT Voltage The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V. The Supply Current (two-cell mode) is the data sheet specification for supply current. The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V). The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5. 7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.1 mA – (25 MHz – 5 MHz) x 0.079 mA/MHz = 0.52 mA. 48 Rev. 1.0 Si1010/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 Supply Current (uA) 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Frequency (MHz) F < 14 MHz Oneshot Enabled F > 14 MHz Oneshot Bypassed < 160 uA/MHz 185 uA/MHz 200 uA/MHz 215 uA/MHz 300 uA/MHz Figure 4.1. Active Mode Current (External CMOS Clock) Rev. 1.0 49 Si1010/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 Supply Current (uA) 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Frequency (MHz) Figure 4.2. Idle Mode Current (External CMOS Clock) 50 Rev. 1.0 Si1010/1/2/3/4/5               6:6(/  6:6(/  Efficiency (%)                                  9%$7 9%$7 9%$7 9%$7 9%$7 9%$7 9%$7  9  9  9  9  9  9  9  X+ ,QGXFWRU  SDFNDJH (65  2KPV 9'''&  9 0LQLPXP 3XOVH :LGWK QV 3XOVH 6NLSSLQJ 'LVDEOHG 1RWH (IILFLHQF\ DW KLJK FXUUHQWV PD\ EH LPSURYHG E\ FKRRVLQJ DQ LQGXFWRU ZLWK D ORZHU (65           Load Current (mA) Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) Rev. 1.0 51 Si1010/1/2/3/4/5 6:6(/  6:6(/               9%$7 9%$7 9%$7 9%$7 9%$7 9%$7 9%$7  9  9  9  9  9  9  9 Efficiency (%)                                 X+ ,QGXFWRU  SDFNDJH (65  2KPV 9'''&  9 0LQLPXP 3XOVH :LGWK  QV 3XOVH 6NLSSLQJ 'LVDEOHG 1RWH (IILFLHQF\ DW KLJK FXUUHQWV PD\ EH LPSURYHG E\ FKRRVLQJ DQ LQGXFWRU ZLWK D ORZHU (65        Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) 52 Rev. 1.0 Si1010/1/2/3/4/5     9%$7   9  9  9  9  9  9  9 9%$7 9%$7 9%$7 9%$7 9%$7 9%$7 Efficiency (%)     X+ ,QGXFWRU  SDFNDJH (65  2KPV 6:6(/  9'''&  9 0LQLPXP 3XOVH :LGWK   QV                Load current (mA) Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) Rev. 1.0 53 Si1010/1/2/3/4/5          X+ ,QGXFWRU  SDFNDJH (65  2KPV 6:6(/  9'''&  9 /RDG &XUUHQW  X$ 0LQ 3XOVH :LGWK  QV 0LQ 3XOVH :LGWK  QV 0LQ 3XOVH :LGWK  QV 0LQ 3XOVH :LGWK  QV 9%$7 &XUUHQW X$                     9%$7 9 Figure 4.6. Typical One-Cell Suspend Mode Current 54 Rev. 1.0 Si1010/1/2/3/4/5 Table 4.3. Port I/O DC Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions Min VDD – 0.7 VDD – 0.1 Typ — — See Chart Max — — Units V Output High Voltage High Drive Strength, PnDRV.n = 1 IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull Output Low Voltage High Drive Strength, PnDRV.n = 1 IOL = 8.5 mA IOL = 10 µA IOL = 25 mA Low Drive Strength, PnDRV.n = 0 IOL = 1.4 mA IOL = 10 µA IOL = 4 mA Input High Voltage Input Low Voltage Input Leakage  Current VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V Weak Pullup Off Weak Pullup On, VIN = 0 V, VDD = 1.8 V Weak Pullup On, Vin = 0 V, VDD = 3.6 V — VDD – 0.7 VDD – 0.1 — — See Chart — — — — — See Chart — — — V 0.6 0.1 — — — — VDD – 0.6 0.7 x VDD — — — — — — — See Chart — — — — — 4 20 0.6 0.1 — — — 0.6 0.3 x VDD ±1 — 35 V V V V µA Rev. 1.0 55 Si1010/1/2/3/4/5 Typical VOH (High Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 5 10 15 20 25 30 35 40 45 50 Load Current (mA) Typical VOH (Low Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V Figure 4.7. Typical VOH Curves, 1.8–3.6 V 56 Rev. 1.0 Si1010/1/2/3/4/5 Typical VOH (High Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 Voltage 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 Load Current (mA) Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 Voltage 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0 1 2 Load Current (mA) 3 VDD = 1.5V VDD = 1.2V VDD = 0.9V VDD = 1.8V VDD = 0.9V VDD = 1.5V VDD = 1.2V VDD = 1.8V Figure 4.8. Typical VOH Curves, 0.9–1.8 V Rev. 1.0 57 Si1010/1/2/3/4/5 Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.9. Typical VOL Curves, 1.8–3.6 V 58 Rev. 1.0 Si1010/1/2/3/4/5 Typical VOL (High Drive Mode) 0.5 VDD = 1.8V 0.4 VDD = 1.5V VDD = 1.2V VDD = 0.9V 0.2 Voltage 0.3 0.1 0 -5 -4 -3 -2 -1 0 Load Current (mA) Typical VOL (Low Drive Mode) 0.5 0.4 Voltage 0.3 VDD = 1.8V 0.2 VDD = 1.5V VDD = 1.2V 0.1 VDD = 0.9V 0 -3 -2 Load Current (mA) -1 0 Figure 4.10. Typical VOL Curves, 0.9–1.8 V Rev. 1.0 59 Si1010/1/2/3/4/5 Table 4.4. Reset Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage Conditions IOL = 1.4 mA, VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V VDD = 2.0 to 3.6 V VDD = 0.9 to 2.0 V RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.6 V Early Warning Reset Trigger (all power modes except Sleep) VBAT Ramp from 0–0.9 V Initial Power-On (VBAT Rising) Early Warning Brownout Condition (VBAT Falling) Recovery from Brownout (VBAT Rising) Time from last system clock rising edge to reset initiation System clock frequency which triggers a missing clock detector timeout Delay between release of any reset source and code execution at location 0x0000 Min — VDD – 0.6 0.7 x VDD — — — — 1.8 1.7 — — 0.9 0.7 — 100 — Typ — — — — — 4 20 1.85 1.75 — 0.75 1.0 0.8 0.95 525 2 Max 0.6 — — 0.6 0.3 x VDD — 35 1.9 1.8 3 — 1.1 0.9 — 1000 10 Units V V V V V µA V RST Input Low Voltage RST Input Pullup Current VDD/DC+ Monitor Threshold (VRST) VBAT Ramp Time for Power On VBAT Monitor Threshold (VPOR) ms V Missing Clock Detector Timeout Minimum System Clock w/ Missing Clock Detector Enabled Reset Time Delay µs kHz — 10 — µs Minimum RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply  Current 15 — — — 300 10 — — — µs ns µA 60 Rev. 1.0 Si1010/1/2/3/4/5 Table 4.5. Power Management Electrical Specifications VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Sleep Mode Wake-up Time Conditions Min 2 Typ — 400 400 2 10 Max 3 — — — — Units SYSCLKs ns ns µs µs Low power oscillator Precision oscillator Two-cell mode One-cell mode — — — — Table 4.6. Flash Electrical Characteristics VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameter Flash Size Scratchpad Size Endurance Erase Cycle Time Write Cycle Time Conditions Si1010/2/4 Si1011/3/5 Min 16384* 8192 512 1k 28 57 Typ — — — 90 k 32 64 Max — — 512 — 36 71 Units bytes bytes bytes Erase/Write Cycles ms µs Note: On 16KB devices, 1024 bytes at addresses 0x3C00 to 0x3FFF are reserved. Table 4.7. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C,  VDD = 1.8–3.6 V 25 °C; includes bias current of 90–100 µA Min 24 — Typ 24.5 300* Max 25 — Units MHz µA Note: Does not include clock divider or clock tree supply current. Table 4.8. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C,  VDD = 1.8–3.6 V 25 °C No separate bias current required. Min 18 — Typ 20 100* Max 22 — Units MHz µA Note: Does not include clock divider or clock tree supply current. Rev. 1.0 61 Si1010/1/2/3/4/5 Table 4.9. SmaRTClock Characteristics VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency (LFO) Conditions Min 13.1 Typ 16.4 Max 19.7 Units kHz Table 4.10. ADC0 Electrical Characteristics VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity (Guaranteed Monotonic) Offset Error Full Scale Error 12-bit mode 10-bit mode 12-bit mode2 10-bit mode 12-bit mode2 10-bit mode 12-bit mode 10-bit mode 12-bit mode3 10-bit mode 12 10 ±1 ±0.5 ±0.8 ±0.5 ±