SI3016

Si3016 3.3 V ENHANCED GLOBAL DIRECT ACCESS ARRANGEMENT Features Complete DAA includes the following: Line voltage monitor Loop current monitor 3.2 dBm transmit/receive levels Parallel handset detection 7 µA on-hook line monitor current Overload protection Programmable line interface AC termination DC termination Ring detect threshold Ringer impedance 84 dB dynamic range TX/RX Integrated analog front end (AFE) and 2- to 4-wire hybrid Integrated ring detector Caller ID support Pulse dialing support Billing tone detection 3.3 V or 5 V power supply Direct interface to DSPs Up to 5000 V isolation Proprietary isolation technology Ordering Information See page 46. Pin Assignments Si3016 QE2 DCT IGND C1B RNG1 RNG2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FILT2 FILT RX REXT REXT2 REF VREG2 VREG Polarity reversal detection Applications V.90 modems Voice mail systems Set-top boxes Fax machines Internet appliances VOIP systems QB QE Description The Si3016 is an integrated direct access arrangement (DAA) line-side device with a programmable line interface to meet global telephone line interface requirements. Available in a 16-pin small outline package, it eliminates the need for an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3016 dramatically reduces the number of discrete components and cost required to achieve compliance with global regulatory requirements. The Si3016 interfaces directly to a Silicon Laboratories integrated DAA system-side interface. U.S. Patent #5,870,046 U.S. Patent #6,061,009 Other Patents Pending Functional Block Diagram Si3016 RX FILT FILT2 REF DCT VREG VREG 2 REXT REXT2 RNG 1 Ring Detect RNG 2 QB Off-Hook QE QE2 Silicon Laboratories Integrated DAA Interface Hybrid and DC Termination Isolation Interface Rev. 1.0 8/06 Copyright © 2006 by Silicon Laboratories Si3016 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i3016 2 Rev. 1.0 S i3016 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.2. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4. Transmit/Receive Full Scale Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.5. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9. DC Termination Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.10. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.12. Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13. DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14. Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.15. Billing Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.16. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.17. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.18. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.19. Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.20. Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.21. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.23. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.24. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.25. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.26. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.27. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Appendix A—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Appendix B—CISPR22 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6. Pin Descriptions: Si3016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8. Package Outline: SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Rev. 1.0 3 S i3016 1. Electrical Specifications All Si3016 electrical specifications are based on the assumption that all specifications listed in the data sheet of the host processor with the integrated system-side DAA module are met. Table 1. Recommended Operating Conditions Parameter1 Ambient Temperature Ambient Temperature Symbol TA TA Test Condition K-Grade B-Grade Min2 0 –40 Typ 25 25 Max2 70 85 Unit °C °C Notes: 1. The Si3016 specifications are guaranteed when the typical application circuit (including component tolerance) and any system-side module and any Si3016 are used. See Figure 6, “Si3016 Typical Application Circuit,” on page 9. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 4 Rev. 1.0 S i3016 Table 2. Loop Characteristics (TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade, See Figure 1) Parameter DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage On Hook Leakage Current1 Operating Loop Current Operating Loop Current DC Ring Current1 Ring Detect Voltage2 Ring Detect Voltage2 Ring Frequency Ringer Equivalence Number 3 Symbol VTR VTR VTR VTR VTR VTR VTR VTR VTR ILK ILP ILP Test Condition IL = 20 mA, ACT = 1 DCT = 11 (CTR21) IL = 42 mA, ACT = 1 DCT = 11 (CTR21) IL = 50 mA, ACT = 1 DCT = 11 (CTR21) IL = 60 mA, ACT = 1 DCT = 11 (CTR21) IL = 20 mA, ACT = 0 DCT = 01 (Japan) IL = 100 mA, ACT = 0 DCT = 01 (Japan) IL = 20 mA, ACT = 0 DCT = 10 (FCC) IL = 100 mA, ACT = 0 DCT = 10 (FCC) IL = 15 mA, ACT = 0 DCT = 00 (Low Voltage) VTR = –48 V FCC / Japan Modes CTR21 Mode dc flowing through ring detection circuitry Min — — — 40 — 9 — 9 — — 13 13 — 11 17 15 — Typ — — — — — — — — — — — — — — — — — Max 7.5 14.5 40 — 6.0 — 7.5 — 5.2 7 120 60 7 22 33 68 0.2 Unit V V V V V V V V V µA mA mA µA VRMS VRMS Hz VRD VRD FR REN RT = 0 RT = 1 Notes: 1. R25 and R26 installed. 2. The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above the maximum. 3. RZ = 0. See "4.12. Ringer Impedance" on page 18. TIP + 600 Ω Si3016 V TR 1 0 µF – IL RING Figure 1. Test Circuit for Loop Characteristics Rev. 1.0 5 S i3016 Table 3. DC Characteristics (TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade) Parameter Input Leakage Current Power Supply Current, Analog* Symbol IL IA Test Condition Min –10 — Typ — 0.3 Max 10 — Unit µA mA *Note: This current is required from the integrated system-side interface to communicate with the Si3016 through the isolation interface. Table 4. AC Characteristics (TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade; see Figure 6 on page 9) Parameter Sample Rate Transmit Frequency Response Receive Frequency Response Transmit Full Scale Level Receive Full Scale Level Dynamic Range4,5,6 1 Symbol Fs Test Condition Fs = FPLL2/5120 Low –3 dBFS Corner Low –3 dBFS Corner Min 7.2 — — — — — — — — — — — — — — Typ — 0 5 1 1.58 1 1.58 82 83 84 –85 –76 –74 –82 60 Max 11.025 — — — — — — — — — — — — — — Unit KHz Hz Hz VPEAK VPEAK VPEAK VPEAK dB dB dB dB dB dB dB dB VFS VFS DR DR DR THD THD THD THD DRCID FULL = 0 (–1 dBm) FULL = 1 (+3.2 dBm)2 FULL = 0 (–1 dBm) FULL = 1 (+3.2 dBm)3 ACT=0, DCT=10 (FCC) IL=100 mA ACT=0, DCT=01 (Japan) IL=20 mA ACT=1, DCT=11(CTR21) IL=60 mA ACT=0, DCT=10 (FCC) IL=100 mA ACT=0, DCT=01 (Japan) IL=20 mA ACT=0, DCT=01 (Japan) IL=20 mA ACT=1, DCT=11 (CTR21) IL=60 mA VIN = 1 kHz, –13 dBm 1,3 Dynamic Range4,5,7 Dynamic Range4,5,6 Transmit Total Harmonic Distortion6,8 Transmit Total Harmonic Distortion7,8 Receive Total Harmonic Distortion7,8 Receive Total Harmonic Distortion6,8 Dynamic Range (Caller ID mode) Notes: 1. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1. 2. R2 should be changed to a 243 Ω resistor when the FULLSCALE bit (FULL) is set to 1 (Register 18, bit 7). 3. Receive full scale level will produce –0.9 dBFS at SDO. 4. DR = 20 x log |Vin| + 20 x log (RMS signal/RMS noise). 5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. 6. Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz. 7. Vin = 1 KHz, –6 dBFS, Fs = 10300 Hz. 8. THD = 20 x log (RMS distortion/RMS signal). 9. The AOUT pin is an optional pin located on the integrated system-side module. VD refers to the digital power supply of the integrated system-side module. 6 Rev. 1.0 S i3016 Table 4. AC Characteristics (Continued) (TA = 0 to 70 °C for K-Grade and –40 to 85 °C for B-Grade; see Figure 6 on page 9) Parameter Caller ID Full Scale Level (0 dB gain) Caller ID Full Scale Level (ARX = 00) Gain Accuracy 5,6 Symbol VCID VCID Test Condition MODE = 0 MODE = 1 2-W to SDO, ATX and ARX = 000, 001, or 010 2-W to SDO, ATX and ARX = 011, 1xx Min — — –0.5 –1 Typ 0.8 1.4 0 0 Max — — 0.5 1 Unit VPP VPP dB dB Gain Accuracy5,6 Notes: 1. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1. 2. R2 should be changed to a 243 Ω resistor when the FULLSCALE bit (FULL) is set to 1 (Register 18, bit 7). 3. Receive full scale level will produce –0.9 dBFS at SDO. 4. DR = 20 x log |Vin| + 20 x log (RMS signal/RMS noise). 5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. 6. Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz. 7. Vin = 1 KHz, –6 dBFS, Fs = 10300 Hz. 8. THD = 20 x log (RMS distortion/RMS signal). 9. The AOUT pin is an optional pin located on the integrated system-side module. VD refers to the digital power supply of the integrated system-side module. Table 5. Absolute Maximum Ratings Parameter Operating Temperature Range Storage Temperature Range Symbol TA TSTG Value –40 to 100 –65 to 150 Unit °C °C Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Digital FIR Filter Characteristics—Transmit and Receive (Sample Rate = 8 kHz, TA = 70 °C for K-Grade and –40 to 85 °C for B-Grade) Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Symbol F(0.1 dB) F(3 dB) Min 0 0 –0.1 — –74 Typ — — — 4.4 — 12/Fs Max 3.3 3.6 0.1 — — — Unit kHz kHz dB kHz dB sec tgd — Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 2, 3, 4, and 5. Rev. 1.0 7 S i3016 Attenuation—dB Attenuation—dB Input Frequency—Hz Input Frequency—Hz Figure 2. FIR Receive Filter Response Figure 4. FIR Transmit Filter Response Attenuation—dB Input Frequency —Hz Attenuation—dB Input Frequency—Hz Figure 3. FIR Receive Filter Passband Ripple Figure 5. FIR Transmit Filter Passband Ripple For Figures 2–5, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows: F(0.1 dB) = 0.4125 Fs F(–3 dB) = 0.45 Fs where Fs is the sample frequency. 8 Rev. 1.0 Decoupling cap for VA No Ground Plane In DAA Section C3 Z4 D3 BAV99 Q1 R5 R8 R7 R15 Q4 Host Processor w/ Silicon Laboratories Integrated DAA System-Side Device C13 R24 C12 + U2 Si3016 Q2 + R27 R28 C5 R18 R6 R12 C30 Z1 R16 AOUT C1 C22 R2 R19 R17 9 AOUT VA GND C1A 13 12 11 1 2 3 4 5 6 7 8 QE2 DCT IGND C1B RNG1 RNG2 QB QE FILT2 FILT RX REXT REXT2 REF VREG2 VREG 16 15 14 13 12 11 10 9 R11 D4 BAV99 C6 C16 Z5 C14 + R13 C2 C20 Q3 C8 R10 L2 FB2 RING C19 D2 R26 C9 Rev. 1.0 C18 C7 C4 R9 C25 C32 RV1 RV2 R25 C24 D1 L1 C31 TIP FB1 Note 1: Please refer to Appendix B for information regarding the installation of L1 and L2. See Note 1 Note 2: R12, R13 and C14 are only required if complex AC termination is used (ACT bit = 1). Note 3: See "Billing Tone Detection" section for optional billing tone filter (Germany, Switzerland, South Africa). Note 4: See Appendix A for applications requiring UL 1950 3rd edition compliance. Figure 6. Si3016 Typical Application Circuit S i3016 9 S i3016 2. Bill of Materials Component C1,C4 1 Table 7. Si3016 Global Component Values Value 150 pF, 3 kV, X7R,±20% Not Installed 0.22 µF, 16 V, X7R, ±20% 0.1 µF, 50 V, Elec/Tant, ±20% 0.1 µF, 16 V, X7R, ±20% 560 pF, 250 V, X7R, ±20% 10 nF, 250 V, X7R, ±20% 1.0 µF, 16 V, Tant, ±20% 0.68 µF, 16 V, X7R/Elec/Tant, ±20% 3.9 nF, 16 V, X7R, ±20% 0.01 µF, 16 V, X7R, ±20% 1800 pF, 50 V, X7R, ±20% 1000 pF, 3 kV, X7R, ±10% Not Installed Dual Diode, 300 V, 225 mA BAV99 Dual Diode, 70 V, 350 mW Ferrite Bead 330 μH, DCR < 3 Ω, 120 mA, ±10% A42, NPN, 300 V A92, PNP, 300 V BCP56T1, NPN, 80 V, 1/2 W Sidactor, 275 V, 100 A Not Installed 402 Ω, 1/16 W, ±1% 100 kΩ, 1/16 W, ±1% 120 kΩ, 1/16 W, ±5% 5.36 kΩ, 1/4 W, ±1% 56 kΩ, 1/10 W, ±5% 9.31 kΩ, 1/16 W, ±1% 78.7 Ω, 1/16 W, ±1% 215 Ω, 1/16 W, ±1% 2.2 kΩ, 1/10 W, ±5% 150 Ω, 1/16 W, ±5% 10 MΩ, 1/16 W, ±5% 10 Ω, 1/10 W, ±5% Si3021 Silicon Labs System-Side Device Zener Diode, 43 V, 1/2 W Zener Diode, 5.6 V, 1/2 W Silicon Labs Silicon Labs Vishay, Motorola, Rohm Vishay, Motorola, Rohm Central Semiconductor Diodes Inc., OnSemiconductor, Fairchild Murata Taiyo-Yuden, ACT, Transtek Magnetics, Cooper Electronics OnSemiconductor, Fairchild OnSemiconductor, Fairchild OnSemiconductor, Fairchild Teccor, ST Microelectronics, Microsemi, TI Panasonic Novacap, Johanson, Murata, Panasonic Supplier(s) Novacap, Venkel, Johanson, Murata, Panasonic C2, C31, C32 C3, C132 C5 C6,C16 C7,C8 C9 C12 C14 C18,C19 C20 C22 C24,C251 C303 D1,D24 D3,D4 FB1,FB2 L1, L25 Q1,Q3 Q2 Q46 RV1 RV27 R28 R5 R6 R7,R8,R15,R16,R17,R199 R9,R10 R11 R12 R13 R18 R24 R25,R26 R27,R28 U1 U2 Z1 Z4,Z5 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Y2 class capacitors are needed for the Nordic requirements of EN60950 and may also be used to achieve surge performance of 5 kV or better. C13 is used to ensure compliance with on-hook pulse dialing and spark quenching requirements in countries, such as Australia and South Africa. If this is not a concern, a 0.1 µF cap may be used. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%). Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.). See Appendix B for additional requirements. Q4 may require copper on board to meet 1/2 W power requirement. (Contact manufacturer for details.) RV2 can be installed to improve performance from 2500 V to 3500 V for multiple longitudinal surges (270 V, MOV). If supporting +3.2 dBFS voice applications, R2 should be 243 Ω and set the FULLSCALE bit (Reg 18[7]). The R7, R8, R15, and R16, R17, and R19 resistors may each be replaced with a single resistor of 1.62 kΩ, 3/4 W, ±1%. 10 Rev. 1.0 S i3016 3. Analog Output Figure 7 illustrates an optional application circuit to support the analog output capability of the DAA system-side module for call progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated by 0, –6, or –12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by –20, –26, or –32 dB. Both the transmit and receive paths can also be independently muted. +5 V C2 AOUT C1 C6 R1 R3 3 6 5 C5 + C4 + 2– 4 C3 R2 Speaker Figure 7. Optional Connection to AOUT for a Call Progress Speaker Table 8. Component Values—Optional Connection to AOUT Symbol C1 C2, C3, C5 C4 C6 R1 R2 R3 U1 Value 2200 pF, 16 V, ±20% 0.1 µF, 16 V, ±20% 100 µF, 16 V, Elec. ±20% 820 pF, 16 V, ±20% 10 kΩ, 1/10 W, ±5% 10 Ω, 1/10 W, ±5% 47 kΩ, 1/10 W, ±5% LM386 Rev. 1.0 11 S i3016 4. Functional Description The Si3016 is an integrated direct access arrangement (DAA) that provides a programmable line interface to meet global telephone line interface requirements. The device implements Silicon Laboratories’ proprietary capacitive isolation technology which offers the highest level of integration by replacing an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid with a 16-pin small outline integrated circuit (SOIC) package in conjunction with a system-side module that is integrated into another device. The Si3016 chip can be fully programmed to meet international requirements and is compliant with FCC, CTR21, JATE, and various other country-specific PTT specifications as shown in Table 9. In addition, the Si3016 has been designed to meet the most stringent global requirements for out-of-band energy, emissions, immunity, lightning surges, and safety. The Si3016 is intended for single-channel applications. For multi-channel applications, up to eight Si3044 DAAs can be daisy-chained together on one serial port. Table 9. Country Specific Register Settings Register Country Argentina Australia1 Austria Bahrain Belgium Brazil1 Bulgaria Canada Chile China1 Colombia Croatia CTR211,2 Cyprus Czech Republic Denmark Ecuador Egypt1 El Salvador Finland France Germany Greece Guam Hong Kong OHS 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT 0 1 0 or 1 0 0 or 1 0 1 0 0 0 0 1 0 or 1 1 1 0 or 1 0 0 0 0 or 1 0 or 1 0 or 1 0 or 1 0 0 16 DCT[1:0] 10 01 11 10 11 01 11 10 10 01 10 11 11 11 11 11 10 01 10 11 11 11 11 10 10 RZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 LIM 0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 18 VOL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes: 1. See "4.9. DC Termination Considerations" on page 17 for more information. 2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 3. Supported for loop current ≥ 20 mA. 12 Rev. 1.0 S i3016 Table 9. Country Specific Register Settings Register Country Hungary Iceland India Indonesia Ireland Israel Italy Japan1 Jordan1 Kazakhstan1 Kuwait Latvia Lebanon Luxembourg Macao Malaysia1,3 Malta Mexico Morocco Netherlands New Zealand Nigeria Norway Oman1 Pakistan1 Peru Philippines1 Poland Portugal Romania Russia1 Saudi Arabia Singapore Slovakia Slovenia South Africa South Korea OHS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ACT 0 0 or 1 0 0 0 or 1 0 or 1 0 or 1 0 0 0 0 0 or 1 0 or 1 0 or 1 0 0 0 or 1 0 0 or 1 0 or 1 1 0 or 1 0 or 1 0 0 0 0 0 0 or 1 0 0 0 0 0 0 0 0 16 DCT[1:0] 10 11 10 10 11 11 11 01 01 01 10 11 11 11 10 01 11 10 11 11 10 11 11 01 01 10 01 10 11 10 01 10 10 10 10 10 10 RZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 RT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 17 LIM 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 18 VOL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes: 1. See "4.9. DC Termination Considerations" on page 17 for more information. 2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 3. Supported for loop current ≥ 20 mA. Rev. 1.0 13 S i3016 Table 9. Country Specific Register Settings Register Country Spain Sweden Switzerland Syria1 Taiwan1 Thailand1 UAE United Kingdom USA Yemen OHS 0 0 0 0 0 0 0 0 0 0 ACT 0 or 1 0 or 1 0 or 1 0 0 0 0 0 or 1 0 0 16 DCT[1:0] 11 11 11 01 01 01 10 11 10 10 RZ 0 0 0 0 0 0 0 0 0 0 RT 0 0 0 0 0 0 0 0 0 0 17 LIM 1 1 1 0 0 0 0 1 0 0 18 VOL 0 0 0 0 0 0 0 0 0 0 Notes: 1. See "4.9. DC Termination Considerations" on page 17 for more information. 2. CTR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 3. Supported for loop current ≥ 20 mA. 4.1. Initialization When the integrated system-side module and the Si3016 are initially powered up, the DAA registers will have default values that guarantee the line-side chip (Si3016) is powered down with no possibility of loading the line (i.e., off-hook). An example initialization procedure is outlined below: 1. Program the desired sample rate with the Sample Rate Control Register. 2. Wait until the Si3016 PLL is locked. This time is between 100 µs and 1 ms. 3. Write a 00H into the DAA Control 2 Register. This powers up the line-side chip (Si3016) and enables the AOUT for call progress monitoring. 4. Set the desired line interface parameters (i.e., DCT[1:0], ACT, OHS, RT, LIM[1:0], and VOL) as defined by “Country Specific Register Settings” shown in Table 9, “Country Specific Register Settings,” on page 12. After this procedure is complete, the Si3016 is ready for ring detection and off-hook. 4.3. Isolation Barrier The Si3016 achieves an isolation barrier through lowcost, high-voltage capacitors in conjunction with Silicon Laboratories’ proprietary signal processing techniques. These techniques eliminate any signal degradation due to capacitor mismatches, common mode interference, or noise coupling. As shown in Figure 6 on page 9, the C1, C4, C24, and C25 capacitors isolate the system side from the Si3016 (line side). All transmit, receive, control, ring detect, and caller ID data are communicated through this barrier. The isolated communications link is disabled by default. To enable it, the PDL bit must be cleared. No communication between the system-side module and the Si3016 can occur until this bit is cleared. When the PDL bit is cleared, a check is performed to ensure that the line-side device is an Si3016 device. If it is not, the system-side module will not function. 4.4. Transmit/Receive Full Scale Level The Si3016 supports programmable maximum transmit and receive levels. The full-scale TX/RX level is established by writing the FULL bit in Register 18. With FULL = 1, the full scale TX/RX level is increased to 3.2 dBm to support certain FCC voice applications that require higher TX/RX levels. When FULL = 1, R2 must be changed from 402 Ω to 243 Ω. The default full scale value is –1 dBm (FULL = 0). Note that this higher TX/ RX full-scale mode must be used in FCC/600 Ω termination mode. 4.2. Power Supply When on-hook, the Si3016 draws power across the isolation link from the system-side module. When offhook, power is drawn from the 2-wire line. Thus, no power supply connections are needed for the Si3016. 14 Rev. 1.0 S i3016 4.5. Parallel Handset Detection The Si3016 is capable of detecting a parallel handset going off-hook. When the Si3016 is off-hook, the loop current can be monitored via the LVCS bits. A significant drop in loop current can signal a parallel handset going off-hook. If a parallel handset causes the LVCS bits to read all 0s, the Drop-Out Detect (DOD) bit may be checked to verify that a valid line still exists. When on-hook, the LVCS bits may also be read to determine the line voltage. Significant drops in line voltage may also be used to detect a parallel handset. For the Si3016 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to support two off-hook DAAs on the same line. The OFF bit in Register 16 is designed to improve parallel handset operation by changing the dc impedance from 50 Ω to 800 Ω and reducing the DCT pin voltage. determine the following: When on-hook, detect if a line is connected. When on-hook, detect if a parallel phone is off-hook. When off-hook, detect if a parallel phone goes on or off-hook. Detect if enough loop current is available to operate. Detect if there is an overload condition which could damage the DAA (see overload protection feature). 4.6.1. Line Voltage Measurement The Si3016 reports the line voltage with the LVCS bits in Register 19. LVCS has a full scale of 87 V with an LSB of 2.75 V. The first code (0 → 1) is skewed such that a 0 indicates that the line voltage is < 3 V. The accuracy of the LVCS bits is ±20%. The user can read these bits directly through the LVCS register when it is on-hook and the MODE bit is set to 1. A typical transfer function is shown in Figure 8. 4.6.2. Loop Current Measurement When the Si3016 is off-hook, the LVCS bits measure loop current in 3 mA/bit resolution. These bits enable the user to detect another phone going off-hook by monitoring the dc loop current. The line voltage current sense transfer function is shown in Figure 9 and is detailed in Table 10. 4.6. Line Voltage/Loop Current Sensing The Si3016 has the ability to measure both line voltage and loop current. The five bit LVCS register reports line voltage measurements when on-hook, loop current measurements when off-hook, or on-hook line monitor data depending on the state of the MODE, OH, and ONHM bits. Using the LVCS bits, the user can 30 25 LVCS BITS 20 15 10 5 0 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 Loop Voltage (V) 100 Figure 8. Typical Loop Voltage LVCS Transfer Function Rev. 1.0 15 S i3016 Overload 30 25 20 LVCS BITS 15 CTR21 10 5 0 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93 Loop Current (mA) 140 Figure 9. Typical Loop Current LVCS Transfer Function Table 10. Loop Current Transfer Function LVCS[4:0] 00000 Condition Insufficient line current for normal operation. Use the DOD bit to determine if a line is still connected. Minimum line current for normal operation. Loop current is excessive (overload). Overload > 140 mA in all modes except CTR21. Overload > 54 mA in CTR21 mode. the 12/Fs filter group delay. If necessary, for the shortest delay, a higher Fs may be established prior to executing the off-hook, such as an Fs of 10.286 kHz. The delay allows for line transients to settle prior to normal use. 4.8. DC Termination The Si3016 has four programmable dc termination modes that are selected with the DCT[1:0] bits in Register 16. FCC mode (DCT[1:0] = 10 b), shown in Figure 10, is the default dc termination mode and supports a transmit full scale level of –1 dBm at TIP and RING. This mode meets FCC requirements in addition to the requirements of many other countries. 12 Voltage Across DAA (V) 11 10 9 8 7 6 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 Loop Current (A) FCC DCT Mode 00001 11111 4.7. Off-Hook The communication system generates an off-hook command by setting the OH bit. With the OH bit set, the system is in an off-hook state. The off-hook state is used to seize the line for incoming/ outgoing calls and can also be used for pulse dialing. When the DAA is on-hook, negligible dc current flows through the hookswitch. When the DAA is placed in the off-hook state, the hookswitch transistor pair, Q1 and Q2, turn on. This applies a termination impedance across TIP and RING and causes dc loop current to flow. The termination impedance has both an ac and dc component. When executing an off-hook sequence, the Si3016 requires 1548/Fs seconds to complete the off-hook and provide phone-line data on the serial link. This includes Figure 10. FCC Mode I/V Characteristics CTR21 mode (DCT[1:0] = 11 b), shown in Figure 11, 16 Rev. 1.0 S i3016 provides current limiting while maintaining a transmit full scale level of –1 dBm at TIP and RING. In this mode, the dc termination will current limit before reaching 60 mA if the LIM bit is set. 45 Voltage Ac ros s D AA ( V ) 40 35 30 25 20 15 10 5 .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 10.5 Low Voltage Mode Voltage Across DAA (V) 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5.0 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 CTR21 DCT Mode Loop Current (A) Loop Current (A) Figure 11. CTR21 Mode I/V Characteristics Japan mode (DCT[1:0] = 01 b), shown in Figure 12, is a lower voltage mode and supports a transmit full scale level of –2.71 dBm. Higher transmit levels for DTMF dialing are also supported. See "4.13. DTMF Dialing" on page 19. The low-voltage requirement is dictated by countries, such as Japan and Malaysia. 10.5 Voltage Across DAA ( V ) 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 Loop Current (A) .1 .11 Japan DCT Mode Figure 13. Low Voltage Mode I/V Characteristics 4.9. DC Termination Considerations Under certain line conditions, it may be beneficial to use other dc termination modes not intended for a particular world region. For instance, in countries that comply with the CTR21 standard, improved distortion characteristics can be seen for very low loop current lines by switching to FCC mode. Thus, after going off-hook in CTR21 mode, the loop current monitor bits (LVCS[4:0]) may be used to measure the loop current, and if LVCS[4:0] < 6, it is recommended that FCC mode be used. Additionally, for very low-voltage countries, such as Japan and Malaysia, the following procedure should be used to optimize distortion characteristics and maximize transmit levels: 1. When first going off-hook, use the Low Voltage mode with the VOL bit set to 1. 2. Measure the loop current using the LVCS[4:0] bits. 3. If LVCS[4:0] ≤ 2, maintain the current settings, and proceed with normal operation. 4. If LVCS[4:0] > 2 or < 6, switch to Japan mode, leave the VOL bit set, and proceed with normal operation. 5. If LVCS[4:0] ≥ 6, switch to FCC mode, set the VOL bit to 0, and proceed with normal operation. Note: A single decision of dc termination mode following offhook is appropriate for most applications. However, during PTT testing, a false dc termination I/V curve may be generated if the dc I/V curve is determined following a single off-hook event. Figure 12. Japan Mode I/V Characteristics Low Voltage mode (DCT[1:0] = 00b), shown in Figure 13, is the lowest line voltage mode supported on the Si3016, with a transmit full scale level of –5 dBm. Higher transmit levels for DTMF dialing are also supported. See "4.13. DTMF Dialing" on page 19. This low-voltage mode is offered for situations that require very low line voltage operation. It is important to note that this mode should only be used when necessary, as the dynamic range will be significantly reduced, and thus the Si3016 will not be able to transmit or receive large signals without clipping them. Finally, Australia has separate dc termination requirements for line seizure versus line hold. Japan mode may be used to satisfy both requirements. However, if a higher transmit level for modem operation is desired, switch to FCC mode 500 ms after the initial Rev. 1.0 17 S i3016 off-hook. This will satisfy the Australian dc termination requirements. 4.10. AC Termination The Si3016 has two ac Termination impedances, which are selected with the ACT bit. ACT = 0 is a real, nominal 600 Ω termination, which satisfies the impedance requirements of FCC part 68, JATE, and other countries. This real impedance is set by circuitry internal to the Si3016 as well as the resistor R2 connected to the REXT pin. ACT = 1 is a complex impedance, which satisfies the impedance requirements of Australia, New Zealand, South Africa, CTR21, and some European NET4 countries, such as the UK and Germany. This complex impedance is set by circuitry internal to the Si3016 as well as the complex network formed by R12, R13, and C14 connected to the REXT2 pin. The RDT bit acts as a one shot. Whenever a new ring signal is detected, the one shot is reset. If no new ring signals are detected prior to the one shot counter counting down to zero, the RDT bit will return to zero. The length of this count (in seconds) is 65536 divided by the sample rate. The RDT will also be reset to zero by an off-hook event. The second ring detect method uses the internal serial output of the integrated system-side module (SDO) to transmit ring data. If the link is active (PDL = 0) and the device is not off-hook or not in on-hook line monitor mode, the ring data will be sent by the system-side module to the host processor. The waveform on SDO depends on the state of the RFWE bit. When the RFWE bit is 0, SDO will be –32768 (0x8000) while the RNG1-RNG2 voltage is between the thresholds. When a ring is detected, SDO will transition to +32767 while the ring signal is positive, then go back to –32768 while the ring is near zero and negative. Thus, a near square wave is presented on SDO that swings from –32768 to +32767 in cadence with the ring signal. When the RFWE bit is 1, SDO will sit at approximately +1228 while the RNG1-RNG2 voltage is between the thresholds. When the ring goes positive, SDO will transition to +32767. When the ring signal goes near zero, SDO will remain near 1228. Then, as the ring goes negative, the SDO will transition to –32768. This will repeat in cadence with the ring signal. The best way to observe the ring signal on SDO is simply to observe the MSB of the data. The MSB will toggle in cadence with the ring signal independent of the ring detector mode. This is adequate information for determining the ring frequency. The MSB of SDO will toggle at the same frequency as the ring signal. 4.11. Ring Detection The ring signal is capacitively coupled from TIP and RING to the RNG1 and RNG2 pins. The Si3016 supports either full- or half-wave ring detection. With full-wave ring detection, the designer can detect a polarity reversal as well as the ring signal. See "4.18. Caller ID" on page 20. The ring detection threshold is programmable with the RT bit. The ring detector output can be monitored in one of two ways. The first method uses the register bits, RDTP, RDTN, and RDT. The second method uses the SDO output internal to the integrated system-side module. The DSP must detect the frequency of the ring signal in order to distinguish a ring from pulse dialing by telephone equipment connected in parallel. A positive ringing signal is defined as a voltage greater than the ring threshold across RNG1-RNG2. RNG1 and RNG2 are pins 5 and 6 of the Si3016. Conversely, a negative ringing signal is defined as a voltage less than the negative ring threshold across RNG1-RNG2. The first ring detect method uses the ring detect bits, RDTP, RDTN, and RDT. RDTP and RDTN behavior is based on the RNG1-RNG2 voltage. Whenever the signal on RNG1-RNG2 is above the positive ring threshold, the RDTP bit is set. Whenever the signal on RNG1-RNG2 is below the negative ring threshold, the RDTN bit is set. When the signal on RNG1-RNG2 is between these thresholds, neither bit is set. The RDT behavior is also based on the RNG1-RNG2 voltage. When the RFWE bit is a 0 or a 1, a positive ringing signal will set the RDT bit for a period of time. The RDT bit will not be set for a negative ringing signal. 4.12. Ringer Impedance The ring detector in many DAAs is ac-coupled to the line with a large, 1 µF, 250 V decoupling capacitor. The ring detector on the Si3016 is also capacitively coupled to the line, but it is designed to use smaller, less expensive 1.8 nF capacitors. Inherently, this network produces a high ringer impedance to the line of approximately 800 to 900 kΩ. This value is acceptable for the majority of countries, including FCC and CTR21. Several countries including Poland, South Africa, and Slovenia, require a maximum ringer impedance that can be met with an internally-synthesized impedance by setting the RZ bit in Register 16. 18 Rev. 1.0 S i3016 4.13. DTMF Dialing In CTR21 dc termination mode, the DIAL bit should be set during DTMF dialing if the LVCS[4:0] bits are less than 12. Setting this bit increases headroom for large signals. This bit should not be used during normal operation or if the LVCS[4:0] bits are greater than 11. In Japan dc termination mode, the system-side module attenuates the transmit output by 1.7 dB to meet headroom requirements. Similarly, in Low Voltage termination mode, the system-side module attenuates the transmit output by 4 dB. However, when DTMF dialing is desired in these modes, this attenuation must be removed. This is achieved by entering the FCC dc termination mode and setting either the FJM or the FLVM bits. When in the FCC dc termination modes, these bits will enable the respective lower loop current termination modes without the associated transmit attenuation. Increased distortion may be observed, which is acceptable during DTMF dialing. After DTMF dialing is complete, the attenuation should be enabled by returning to either the Japan dc termination mode (DCT[1:0] = 01b) or the Low Voltage termination mode (DCT[1:0] = 00b). The FJM and the FLVM bits have no effect in any other termination mode other than the FCC dc termination mode. Higher DTMF levels may also be achieved if the amplitude is increased and the peaks of the DTMF signal are clipped at digital full scale (as opposed to wrapping). Clipping the signal will produce some distortion and intermodulation of the signal. Generally, somewhat increased distortion (between 10–20%) is acceptable during DTMF signaling. Several dB higher DTMF levels can be achieved with this technique, compared with a digital full-scale peak signal. dealing with this problem is to put a parallel RC shunt across the hookswitch relay. The capacitor is large (~1 µF, 250 V) and relatively expensive. In the Si3016, the OHS bit can be used to slowly ramp down the loop current to pass these tests without requiring additional components. 4.15. Billing Tone Detection “Billing tones” or “metering pulses” generated by the central office can cause modem connection difficulties. The billing tone is typically either a 12 kHz or 16 kHz signal and is sometimes used in Germany, Switzerland, and South Africa. Depending on line conditions, the billing tone may be large enough to cause major errors related to the modem data. The Si3016 has a feature that allows the device to provide feedback as to whether a billing tone has occurred and when it ends. Billing tone detection is enabled by setting the BTE bit. Billing tones less than 1.1 VPK on the line will be filtered out by the low-pass digital filter on the Si3016. The ROV bit is set when a line signal is greater than 1.1 VPK, indicating a receive overload condition. The BTD bit is set when a line signal (billing tone) is large enough to excessively reduce the line-derived power supply of the line-side device (Si3016). When the BTD bit is set, the dc termination is changed to an 800 Ω dc impedance. This ensures minimum line voltage levels even in the presence of billing tones. The OVL bit should be polled following a billing tone detection. When the OVL bit returns to zero, indicating that the billing tone has passed, the BTE bit should be written to zero to return the dc termination to its original state. It will take approximately one second to return to normal dc operating conditions. The BTD and ROV bits are sticky, and they must be written to zero to be reset. After the BTE, ROV, and BTD bits are all cleared, the BTE bit can be set to re-enable billing tone detection. Certain line events, such as an off-hook event on a parallel phone or a polarity reversal, may trigger the ROV or the BTD bits, after which the billing tone detector must be reset. The user should look for multiple events before qualifying whether billing tones are actually present. Although the DAA will remain off-hook during a billing tone event, the received data from the line will be corrupted when a large billing tone occurs. If the user wishes to receive data through a billing tone, an external LC filter must be added. A modem manufacturer can provide this filter to users in the form of a dongle that connects on the phone line before the DAA. This keeps the manufacturer from having to include a costly LC filter internal to the modem when it may only be necessary to support a few countries/customers. 4.14. Pulse Dialing Pulse dialing is accomplished by going off- and on-hook to generate make and break pulses. The nominal rate is 10 pulses per second. Some countries have very tight specifications for pulse fidelity, including make and break times, make resistance, and rise and fall times. In a traditional solid-state dc holding circuit, there are a number of issues in meeting these requirements. The Si3016 dc holding circuit has active control of the on-hook and off-hook transients to maintain pulse dialing fidelity. Spark quenching requirements in countries, such as Italy, the Netherlands, South Africa, and Australia deal with the on-hook transition during pulse dialing. These tests provide an inductive dc feed, resulting in a large voltage spike. This spike is caused by the line inductance and the sudden decrease in current through the loop when going on-hook. The traditional way of Rev. 1.0 19 S i3016 Alternatively, when a billing tone is detected, the system software may notify the user that a billing tone has occurred. This notification can be used to prompt the user to contact the telephone company and have the billing tones disabled or to purchase an external LC filter. The billing tone filter affects the ac termination and return loss. The current complex ac termination will pass worldwide return loss specifications both with and without the billing tone filter by at least 3 dB. The ac termination is optimized for frequency response and hybrid cancellation, while having greater than 4 dB of margin with or without the dongle for South Africa, Australia, CTR21, German, and Swiss country-specific specifications. 4.16. Billing Tone Filter (Optional) In order to operate without degradation during billing tones in Germany, Switzerland, and South Africa, an external LC notch filter is required. (The Si3016 can remain off-hook during a billing tone event, but modem data will be lost in the presence of large billing tone signals.) The notch filter design requires two notches, one at 12 KHz and one at 16 KHz. Because these components are fairly expensive and few countries supply billing tone support, this filter is typically placed in an external dongle or added as a population option for these countries. Figure 14 shows an example billing tone filter. L1 must carry the entire loop current. The series resistance of the inductors is important to achieve a narrow and deep notch. This design has more than 25 dB of attenuation at both 12 KHz and 16 KHz. C1 4.17. On-Hook Line Monitor The Si3016 allows the user to receive line activity when in an on-hook state. This is accomplished through a low-power ADC located on-chip that digitizes the signal passed across the RNG1/2 pins and then sends this signal digitally across the isolation link to the systemside module. This mode is typically used to detect caller ID data (see the “Caller ID” section). There are two lowpower ADCs on the Si3016. One is enabled by setting the ONHM bit in Register 5. This ADC draws approximately 450 µA of current from the line when activated. A lower-power ADC also exists on the Si3016, which enables a reduced current draw from the line of approximately 7 µA. This lower power ADC is enabled by setting the MODE bit (in conjunction with the ONHM bit) to 1. (See the MODE bit description in the “Control Registers” section.) Regardless of which ADC is being used, the on-hook line monitor function must be disabled before the device is taken off-hook. Thus, ensure that the ONHM bit is cleared before setting the OH bit. The signal to the lower power ADC can be attenuated to accommodate larger signals. This is accomplished through the use of the ARX[2:0] bits. It is important to note that while these ARX bits provide gain to the normal receive path of the DAA, they also function as attenuation bits for the on-hook line monitor low-power ADC. Attenuation settings include 0, 1, 2.2, 3.5, and 5 dB. It is recommended that the new lower-power ADC be used for on-hook line monitoring. C2 L1 TIP From Line L2 C3 To DAA RING Figure 14. Billing Tone Filter Table 11. Component Values—Optional Billing Tone Filters Symbol C1,C2 C3 L1 L2 Value 0.027 µF, 50 V, ±10% 0.01 µF, 250 V, ±10% 3.3 mH, >120 mA, 40 mA, 140 mA in all modes except CTR21. Overload > 54 mA in CTR21 mode. OVL Overload Detected. This bit has the same function as ROV in Register 17 but will clear itself after the overload has been removed. See "4.15. Billing Tone Detection" on page 19. This bit is only masked by the off-hook counter and is not affected by the BTE bit. 0 = Normal receive input level. 1 = Excessive receive input level. Recal/Dropout Detect. When the line-side device is off-hook, it is powered from the line itself. If this line-derived power supply collapses, such as when the line is disconnected, this bit is set to 1. Sixteen frames (16/Fs) after the line-derived power supply returns, this bit is set to 0. When on-hook, this bit is set to 0. 0 = Normal operation. 1 = Line supply dropout detected when on-hook. Overload Protect Detected. 0 = Inactive. 1 = Overload protection active. Note: See description of overload protect operation (OPE bit). 2 1 DOD 0 OPD 40 Rev. 1.0 S i3016 Rev. 1.0 41 S i3016 APPENDIX A—UL1950 3RD EDITION Although designs using the Si3016 comply with UL1950, 3rd Edition, and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 16 shows two designs that can pass the UL1950 overvoltage tests, as well as electromagnetic emissions. The top schematic of Figure 16 shows the configuration in which the ferrite beads (FB1, FB2) are on the unprotected side of the sidactor (RV1). For this configuration, the current rating of the ferrite beads needs to be 6 A. However, the higher current ferrite beads are less effective in reducing electromagnetic emissions. C24 75 Ω @ 100 MHz, 6 A The bottom schematic of Figure 16 shows the configuration in which the ferrite beads (FB1, FB2) are on the protected side of the sidactor (RV1). For this design, the ferrite beads can be rated at 200 mA. In a cost-optimized design, it is important to remember that compliance to UL1950 does not always require overvoltage tests. It is best to plan ahead and know which overvoltage tests will apply to your system. System-level elements in the construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. Consult with your professional testing agency during the design of the product to determine which tests apply to your system. 1.25 A FB1 TIP RV1 75 Ω @ 100 MHz, 6 A FB2 RING C25 C24 600 Ω @ 100 MHz, 200 mA FB1 1.25 A TIP RV1 FB2 RING 600 Ω @ 100 MHz, 200 mA C25 Figure 16. Circuits that Pass all UL1950 Overvoltage Tests 42 Rev. 1.0 S i3016 APPENDIX B—CISPR22 COMPLIANCE Various countries are expected to adopt the IEC CISPR22 standard over the next few years. For example, the European Union (EU) has adopted a standard entitled EN55022, which is based on the CISPR22 standard. Adherence to this standard will be necessary to display the CE mark on designs intended for sale in the EU. The typical schematic and global bill of materials (BOM) (see Figure 6 and Table 7) contained in this data sheet are designed to be compliant to the CISPR22 standard. If smaller inductors are desired, a notch filter may be used and compliance to CISPR22 still achieved. As shown in Figure 17, a series capacitor-resistor in parallel with L1 and L2 forms the simple notch filter. Table 14 shows corresponding values used for C24, C25, C38, C39, L1, L2, R31, and R32. C38 R31 The direct current resistance (DCR) of the listed inductors is an important consideration. If the DCR of the inductors used is less than 3 Ω each, then country PTT specifications which require 300 Ω or less of dc resistance at TIP and RING with 20 mA of loop current can be satisfied with the Japan dc termination mode. If the DCR of the inductors is at or slightly above 3 Ω, the low-voltage termination mode may need to be used to satisfy the 300 Ω dc resistance requirement at 20 mA of loop current. In all cases, "4.9. DC Termination Considerations" on page 17 should be followed. If compliance to the CISPR22 standard and certain other country PTT requirements are not desired, then L1 and L2 may be removed. If these inductors are removed, C24 and C25 should be increased to 2200 pF, and C9 should be changed to 22 nF, 250 V. With these changes, PTT compliance in the following countries will not be achieved: India (I/Fax-03/03 standard), Taiwan (ID0001 standard), Chile (Decree No. 220 1981 standard), and Argentina (CNC-St2-44.01 standard). For questions concerning compliance to CISPR22 or other relevant standards, contact a Silicon Laboratories technical representative. L1 C24 To DAA FB1 TIP C39 R32 L2 C25 FB2 RING Figure 17. Notch Filter for CISPR22 Compliance Table 14. Notch Filter Component Values C24/C25 1000 pF C38/C39 33 pF, 50 V L1/L2 150 µH, DCR < 3 Ω, I > 120 mA R31/R32 680 Ω, 1/10 W Rev. 1.0 43 S i3016 6. Pin Descriptions: Si3016 QE2 DCT IGND C1B RNG1 RNG2 QB QE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FILT2 FILT RX REXT REXT2 REF VREG2 VREG Table 15. Si3016 Pin Descriptions Pin # 1 2 3 4 Pin Name QE2 DCT IGND C1B Transistor Emitter 2. Connects to the emitter of Q4. DC Termination. Provides dc termination to the telephone network. Isolated Ground. Connects to ground on the line-side interface. Also connects to capacitor C2. Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. Used to communicate with the systemside module. Ring 1. Connects through a capacitor to the TIP lead of the telephone line. Provides the ring and caller ID signals to the Si3016. Ring 2. Connects through a capacitor to the RING lead of the telephone line. Provides the ring and caller ID signals to the Si3016. Transistor Base. Connects to the base of transistor Q3. Used to go on/off-hook. Transistor Emitter. Connects to the emitter of transistor Q3. Used to go on/off-hook. Voltage Regulator. Connects to an external capacitor to provide bypassing for an internal power supply. Voltage Regulator 2. Connects to an external capacitor to provide bypassing for an internal power supply. Reference. Connects to an external resistor to provide a high-accuracy reference current. External Resistor 2. Sets the complex ac termination impedance. External Resistor. Sets the real ac termination impedance. Description 5 RNG1 6 RNG2 7 8 9 10 11 12 13 QB QE VREG VREG2 REF REXT2 REXT 44 Rev. 1.0 S i3016 Table 15. Si3016 Pin Descriptions (Continued) Pin # 14 15 16 Pin Name RX FILT FILT2 Description Receive Input. Serves as the receive side input from the telephone network. Filter. Provides filtering for the dc termination circuits. Filter 2. Provides filtering for the bias circuits. Rev. 1.0 45 S i3016 7. Ordering Guide Part Number Si3016-KS Si3016-F-FS Si3016-BS Package 16-pin SOIC 16-pin SOIC 16-pin SOIC Pb-Free No Yes No Temp Range 0 to 70 °C 0 to 70 °C –40 to 85 °C 46 Rev. 1.0 S i3016 8. Package Outline: SOIC Figure 18 illustrates the package details for the Si3016. Table 16 lists the values for the dimensions shown in the illustration. 16 9 h E H 0.010 θ GA UGE PLA NE L Detail F 1 B 8 D A2 e A1 A C L1 See Detail F Seating Plane γ Figure 18. 16-Pin Small Outline Integrated Circuit (SOIC) Package Table 16. Package Diagram Dimensions Symbol A A1 A2 B C D E e H h L L1 γ θ Millimeters Min Max 1.35 1.75 .10 .25 1.30 1.50 .33 .51 .19 .25 9.80 10.01 3.80 4.00 1.27 BSC — 5.80 6.20 .25 .50 .40 1.27 1.07BSC — — 0.10 0º 8º Rev. 1.0 47 S i3016 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Pages 9-10: Updated schematic and BOM. Page 16: updated Figure 13. Page 44: added Appendix B Revision 0.3 to Revision 0.41 Table 9 updated. “Appendix B—CISPR22 Compliance” updated. The “Ringer Impedance Network” figure and the “Component Values—Optional Ringer Impedance Network” table were deleted from the “Ringer Impedance”section as well as a paragraph discussing Czech Republic designs. The “Dongle Applications Circuit” figure was deleted. Revision 0.41 to Revision 0.42 Page 1: updated Features list. Table 2, page 5: revised Note 3. Page 12: added single-channel information to Functional Description. Revision 0.42 to Revision 0.44 Table 3 on page 6 updated. Page 26: removed SB from Register 1, bit 0. Register 1, bit 0: removed SB and description from register. Register 5, bits 6,1 and 5,0: revised transmit path attenuation transmit and receive controls. Revision 0.44 to Revision 1.0 Updated "7. Ordering Guide" on page 46. Updated "4.27. Revision Identification" on page 25. 48 Rev. 1.0 S i3016 NOTES: Rev. 1.0 49 S i3016 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 50 Rev. 1.0