SI3068

Si3068 FCC+ EMBEDDED DIRECT ACCESS ARRANGEMENT Features 80 dB dynamic range TX/RX paths to support up to V.92 modem speeds Compliant with 49 PTTs, including FCC, JATE, China, and Korea Integrated analog front end (AFE) and 2- to 4-wire hybrid Integrated ring detector Pulse dialing support Patented >6000 V isolation technology Proprietary isolation capacitor interface to integrated DAA module Line voltage monitor Loop current monitor Caller ID support Lead-free and RoHS-compliant 8-pin ESOIC package Ordering Information See page 36. Pin Assignments Si3068 Applications V.92 modems Digital televisions PDAs Set-top boxes Fax machines ePOS terminals Internet appliances Multi-function printers Si3068 C1B C2B VREG CID 1 2 3 4 9 Description The Si3068 is an integrated direct access arrangement (DAA) for use with an integrated DAA system-side module. It includes a V.92 quality codec, dc termination, ac termination, and an integrated hybrid, eliminating the need for an analog front end (AFE), isolation transformer, relays, optoisolator, and a 2- to 4-wire hybrid. It interfaces directly to the integrated system-side module and features Silicon Laboratories’ patented isolation technology. The Si3068 dramatically reduces the board space, component count, and cost required to implement a DAA compliant with the regulatory requirements of 49 different PTTs including FCC, JATE, China, and Korea. IGND 8 7 6 5 RX DCT QB QE US Patent # 5,870,046 US Patent # 6,061,009 Other Patents Pending Functional Block Diagram Si3068 RX Silicon Laboratories Embedded System-side DAA Module C1B Hybrid and dc Termination Isolation Interface DCT TIP BOM RING VREG IGND C2B Ring Detect Off-Hook CID QB QE Rev. 1.0 9/05 Copyright © 2005 by Silicon Laboratories Si3068 S i3068 Rev. 1.0 2 Si3068 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Telephone Line Interface Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.2. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4. Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5. Line Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.9. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.10. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.11. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.12. DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.14. Receive Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. On-Hook Line Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.16. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.18. Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.19. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.20. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.21. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7. Package Outline: 8-Pin Exposed Pad SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev. 1.0 3 S i3068 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter* Ambient Temperature Symbol TA Test Condition F-Grade Min 0 Typ 25 Max 70 Unit °C *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. Table 2. DAA Loop Characteristics (VD = 3.0 to 3.6 V, TA = 0 to 70 °C, see Figure 1) Parameter DC Termination Voltage DC Termination Voltage On-Hook Leakage Current Operating Loop Current DC Ring Current Ring Detect Voltage* Ring Frequency Ringer Equivalence Number Symbol VTR VTR ILK ILP Test Condition IL = 20 mA IL = 120 mA VTR = –100 V Min — 9 — 15 Typ — — — — 1.5 15 — — Max 7.5 — 12 120 3 35 68 0.2 Unit V V µA mA µA Vrms Hz dc current flowing through ring detection circuitry VRD FR REN — 10 15 — *Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above the maximum. TIP + 600 Ω Si3068 V TR 10 µF – IL RING Figure 1. Test Circuit for Loop Characteristics 4 Rev. 1.0 S i3068 Table 3. DAA AC Characteristics (TA = 0 to 70 °C, Fs = 8 kHz) Parameter Sample Rate Receive Frequency Response Transmit Full Scale Dynamic Range Level1 1,2 Symbol Fs Test Condition Low –3 dBFS Corner Min Typ Max 7.2 — — — — — — — — — — 5 0.98 0.98 80 80 75 –78 50 6 16 — — — — — — — — — Unit kHz Hz VPEAK VPEAK dB dB dB dB dB VPP VFS VFS DR DR 5,6 –1 dBm –1 dBm IL = 100 mA IL = 20 mA IL = 20 mA IL = 20 mA VIN = 1 kHz, –13 dBm Receive Full Scale Level 3,4,5 Dynamic Range3,4,5 Transmit Total Harmonic Distortion Receive Total Harmonic Dynamic Range (caller ID Caller ID Full Scale Level mode)7 Distortion5,6 THD THD DRCID VCID Notes: 1. Measured at TIP and RING with 600 Ω. termination at 1 kHz, as shown in Figure 1. 2. Receive full scale level produces –0.9 dBFS. 3. DR = 20 x log (rms VFS/rms VIN)+ 20 x log (rms VIN/rms noise, excluding harmonics). VFS is the –1 dBm full-scale level. 4. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. 5. VIN = 1 kHz, –3 dBFS 6. THD = 20 x log (rms distortion / rms signal). 7. DRCID = 20 x log (rms VCID/rms VIN)+ 20 x log (rms VIN/rms noise). VCID is the 6 V full-scale level. Rev. 1.0 5 S i3068 Table 4. Digital FIR Filter Characteristics—Transmit and Receive (Sample Rate = 8 kHz, TA = 0 to 70 °C) Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Symbol F(0.1 dB) F(3 dB) Min 0 0 –0.1 — –74 Typ — — — 4.4 — 12/Fs Max 3.3 3.6 0.1 — — — Unit kHz kHz dB kHz dB s tgd — Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 2, 3, 4, and 5. 6 Rev. 1.0 S i3068 Attenuation—dB Attenuation—dB Input Frequency—Hz Input Frequency—Hz Figure 2. FIR Receive Filter Response Figure 4. FIR Transmit Filter Response Attenuation—dB Input Frequency—Hz Attenuation—dB Input Frequency—Hz Figure 3. FIR Receive Filter Passband Ripple Figure 5. FIR Transmit Filter Passband Ripple For Figures 2–5, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows: F(0.1 dB) = 0.4125 Fs F(–3 dB) = 0.45 Fs where Fs is the sample frequency. Rev. 1.0 7 S i3068 2. Typical Application Schematic 8 Rev. 1.0 S i3068 3. Bill of Materials Component C1, C2 C3 C4 C5 C8, C9 C11 C12 D1, D2, D3, D41 FB1, FB2, FB3, FB42 Q1, Q3 Q2 RV1 R13 R2 4 Value 33 pF, Y2, X7R, ±10% 10 nF, 250 V, X7R, ±20% 1.0 µF, 35 V, Elec, ±20% 0.1 µF, 16 V, X7R, ±20% 680 pF, Y2, X7R, ±10% 220 pF, 50 V, X7R, ±10% DNP 0.1 µF, 16 V, X7R, ±20% Diode, 400 V, 1N4004 Ferrite Bead, BLM18AG601SN1B NPN, 300 V, MPSA42 PNP, 300 V, MPSA92 Sidactor, 275 V, 100A 205 Ω, 1 W, 1% 243 Ω, 1 W, 1% 3.9 kΩ, 1/16 W, 5% 100 kΩ, 1/16 W, 5% 10 MΩ, 1/16 W, 5% 1 kΩ, 1/16 W, 5% 56 Ω, 1/16 W, 1% DNP 0 Ω, 1/16 W, 5% 1.5 MΩ, 1/16 W, 5% 180 kΩ, 1/16 W, 5% 3 MΩ, 1/16 W, 5% Si3068 Zener Diode, 20 V, 1/2 W Supplier(s) Panasonic, Murata, Vishay Venkel, SMEC Panasonic Venkel, SMEC Panasonic, Murata, Vishay Venkel, SMEC Venkel, SMEC Central Semiconductor Murata OnSemi, Fairchild OnSemi, Fairchild Teccor, Protek, ST Micro Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Venkel, SMEC, Panasonic Silicon Laboratories General Semiconductor R4 R5, R6 R7, R8 R10 R12, R13 R22 R18 R19 R20, R21 U2 Z1, Z2 Notes: 1. Several diode bridge configurations are acceptable, parts such as a single DF-04S or two CMPD2004S dual diodes may be used (suppliers include General Semiconductor, Diodes Inc., etc.) 2. 0 Ω may be substituted for FB3, FB4 depending on emissions performance. 3. Three 619 Ω 1/4 W 1% in parallel configuration may be substituted for R1. 4. Three 732 Ω 1/4 W 1% in parallel configuration may be substituted for R2. Rev. 1.0 9 S i3068 4. Telephone Line Interface Functional Description Together, the integrated system-side and Si3068 comprise an integrated direct access arrangement (DAA) that provides a programmable line interface to meet the telephone line interface requirements of countries worldwide. The device implements Silicon Laboratories’ patented isolation technology, which offers the highest level of integration by replacing an analog front end (AFE), an isolation transformer, relays, optoisolators, a 2- to 4-wire hybrid, and other circuitry. The Si3068 can be fully programmed to meet international requirements and is compliant with FCC, JATE, and numerous other country-specific PTT specifications as shown in Table 5. Also, the Si3068 meets the most stringent requirements for out-of-band energy, emissions, immunity, lightning surges, and safety. 4.3. Parallel Handset Detection The Si3068 can detect a parallel handset going offhook. When the DAA is off-hook, the loop current can be monitored via the LCS bits (Register 12, bits 4:0). A significant drop in loop current can signal a parallel handset going off-hook. If a parallel handset causes the LCS bits to read 0s, the DropOut Detect Interrupt bit (Register 4, bit 3) can be checked to verify that a valid line still exists. For the Si3068 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination impedance to support two DAAs off hook on the same line. Table 5. Country-Specific PTT Specifications Country Argentina Kyrgyzstan Armenia Macao Bahamas Mexico Bangladesh Moldova Belarus New Zealand2 Bermuda Paraguay Brazil Peru Brunei Puerto Rico Canada Russia Caribbean Saudi Arabia Chile Singapore China South Korea3 Colombia Sri Lanka Costa Rica Taiwan Dominican Republic Thailand Ecuador Tunisia El Salvador UAE Georgia Ukraine Guam Uruguay Hong Kong Uzbekistan India USA Indonesia Venezuela 1 Vietnam Japan Kazakhstan Yemen Kuwait Notes: 1. DCR exceeds 300 Ω; disclaimer required in product documentation. 2. 600 Ω ac termination used; disclaimer required in product documentation. 3. Additional components required to pass ringer impedance specifications. 4.1. Initialization The following is an example initialization procedure: 1. Select the desired sample rate using the SRC bits (Register 7, bits 3:0). 2. Power up the line side by clearing the PDL bit (Register 6, bit 4). 3. Enable AOUT (if applicable) by setting ARM[7:0] (Register 20, bits 7:0) and ATM[7:0] (Register 21, bits 7:0) to the desired level. 4. Prior to receiving or transmitting data, ensure FDT (Register 12) is set indicating the Si3068 is ready for normal operation. After the procedure is complete, the DAA is ready for off-hook, on-hook line monitoring, and ring detection. 4.2. Isolation Barrier The Si3068 achieves an isolation barrier through lowcost, high-voltage capacitors in conjunction with Silicon Laboratories’ proprietary signal processing techniques. These techniques eliminate signal degradation from capacitor mismatches, common mode interference, or noise coupling. The C1, C2, C8, and C9 capacitors isolate the system-side device from the Si3068 line-side device. All transmit, receive, control, ring detect, and caller ID data are communicated through this barrier. Y2 class capacitors can be used to achieve surge performance of 6 kV or greater. The isolated communications link is disabled by default. To enable it, the PDL bit (Register 6, bit 4) must be cleared. No communication between the system-side and Si3068 can occur until this bit is cleared and the FDT bit (Register 12, bit 6) is high. 10 Rev. 1.0 S i3068 4.4. Loop Current Sensing The Si3068 measures loop current when off-hook. The LCS[4:0] bits measure loop current with 3.3 mA/bit resolution. The following functions can be performed with the LCS bits: While off-hook, detect if a parallel phone goes on- or off-hook. Determine if sufficient loop current is available for proper operation. Detect if there is an overload condition. 4.4.1. Loop Current Measurement When the DAA is off-hook, the LCS[4:0] bits measure loop current with 3.3 mA/bit resolution. These bits can be used to detect another device going off-hook by monitoring the dc loop current. The transfer function for LCS is shown in Figure 6 and is detailed in Table 6. The LCS bits report loop current down to the minimum operating loop current for the DAA. Below this threshold, the reported value of loop current is unpredictable and may vary between zero and the minimum operating current. When the LCS bits have reached their maximum value, the Loop Current Sense Overload Interrupt bit fires; however, LCSOI firing does not necessarily guarantee that an overload situation has occurred. Overload 30 25 20 LCS BITS 15 10 5 0 0 13.2 Loop Current (mA) 102.3 160 Figure 6. Typical LCS Transfer Function Table 6. Loop Current Sense Transfer Function LCS[4:0] 00000b – 00011b 00100b – 11110b 11111b Condition Insufficient line current for normal operation. Use the DODI bit (Register 4, bit 3) to determine if a line is still connected. Normal operation. Loop current is excessive (>160 mA). Rev. 1.0 11 S i3068 4.5. Line Voltage Sensing The Si3068 measures line voltage when on-hook. The LVS[6:0] bits (register 29) report line voltage with 1 V/bit resolution (typical). The LVS bits can be used to determine if a line is present and, if so, if it is idle or in use. Since these operations can be performed while on-hook, there is no need to enter the off-hook state and possibly disturb a call in progress to determine the status of the line. The typical LVS transfer function is shown in Figure 7 and detailed in Table 7. 127 LVS 4 0 0 34 Line Voltage (V) 126 Figure 7. Line Voltage Status Transfer Function Table 7. Line Voltage Status Transfer Function LVS[6:0] 0000000b 0000100b – 1111110b 1111111b VLINE < 3.5 V 3.5 V < VLINE < 126.5 V VLINE > 126.5 V Line Voltage 12 Rev. 1.0 S i3068 4.6. Off-Hook The software generates an off-hook command by setting the OH bit (Register 5, bit 0). This seizes the line for incoming/outgoing calls and can also be used for pulse dialing. When on-hook, negligible dc current flows through the hookswitch. When off-hook, the hookswitch transistor pair, Q1 and Q2, turn on. A termination impedance is applied across TIP and RING and causes dc loop current to flow. Several events occur internally to the DAA when the OH bit is set. There is a 250 µs latency for the off-hook command to communicate to the line-side device. When the line-side device goes off-hook, an off-hook counter forces a delay before transmission or reception can occur. After this, an ADC calibration is performed for 256 ms. The ADC calibration can be disabled by setting the ADCC bit (Register 17, bit 5). Refer to Section "4.20. Calibration" on page 16 for more information on automatic calibration. To calculate the total time required to go off-hook and start transmission or reception, the digital filter delay (typically 1.5 ms with the FIR filter) should be included in the calculation. 4.7. DC Termination The Si3068 dc I/V characteristics, shown in Figure 8, support a transmit full scale level of –1 dBm at TIP and RING. This meets FCC requirements and the requirements of many other countries. DCIV 25 20 Vtip-ring (Volts) 15 10 5 0 0 20 40 60 Loop Current (mA) 80 100 120 Figure 8. DC I/V Characteristics Rev. 1.0 13 S i3068 4.8. Transhybrid Balance The Si3068 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. 4.10. Ring Validation This feature prevents false ring detection by validating the ring parameters. Invalid signals, such as linevoltage changes when a parallel handset goes off-hook, pulse dialing, polarity reversals, and high-voltage line tests, are ignored. Ring validation can be enabled during normal operation and in low-power sleep mode. The ring validation circuit operates by calculating the time between alternating crossings of positive and negative ring thresholds to validate that the ring frequency is within tolerance. High- and low-frequency tolerances are programmable in the RAS[5:0] and RMX[5:0] fields. The RCC[2:0] bits define the length of time the ring signal must be within tolerance. Once the duration of the ring frequency is validated by the RCC bits, the circuitry stops checking for frequency tolerance and begins checking for the end of the ring signal, which is defined by a lack of additional threshold crossings for a period of time configured by the RTO[3:0] bits. When the ring frequency is first validated, a timer defined by the RDLY[2:0] bits is started. If the RDLY[2:0] timer expires before the ring timeout, the ring is validated, and a valid ring is indicated. If the ring timeout expires before the RDLY[2:0] timer, a valid ring is not indicated. Ring validation requires five parameters: Timeout parameter to place a lower limit on the frequency of the ring signal on the RAS[5:0] bits (Register 24, bits 5:0). The frequency is measured by calculating the time between crossings of positive and negative ring thresholds. Minimum count to place an upper limit on the frequency on the RMX[5:0] bits (Register 22, bits [5:0]). Time interval over which the ring signal must be the correct frequency on the RCC[2:0] bits (Register 23, bits [2:0]). Timeout period that defines when the ring pulse has ended with the most recent ring threshold crossing on the RTO [3:0] bits (Register 23, bits 6:3). Delay period between when the ring signal is validated and when a valid ring signal is indicated to help accommodate distinctive ring on the RDLY [2] bit (Register 23, bit 7). The ring validation enable bit, RNGV (Register 24, bit 7), enables or disables the ring validation feature in normal operating mode and low-power sleep mode. For further details, see “AN72: Ring Detection/Validation with the Si305x DAAs.” 4.9. Ring Detection Ring detection can be performed by monitoring the ring detector output or by observing the audio CODEC data. The ring detector output can be monitored with the register bits, RDTN, RDTP, and RDT (Register 5, bits 6, 5, and 2). Software must detect the frequency of the ring signal to distinguish a ring from pulse dialing by telephone equipment connected in parallel. Alternatively, hardware ring validation can be used. See Section "4.10. Ring Validation". The ring detector output is controlled by the RFWE bit (Register 18, bit 1). When the RFWE bit is 0 (default mode), only positive ring signals are reported by the ring detector. A positive ring signal is defined as a voltage greater than the ring threshold at the QE pin. Conversely, a negative ring signal is defined as a voltage less than the negative ring threshold. When the RFWE bit is 1, the ring detector reports both positive and negative ring signals. The RDTP and RDTN behavior is based on the ring voltage. When the signal is above the positive ring threshold, the RDTP bit is set. When the signal is below the negative ring threshold, the RDTN bit is set. When the signal is between these thresholds, neither bit is set. The RDT behavior is also based on the ring voltage. When the RFWE bit is 0, a positive ring signal sets the RDT bit for a period of time. When the RFWE bit is 1, either a positive or negative ring signal sets the RDT bit. The audio CODEC data also signals ring events when on-hook. If the RFWE bit is 0, the CODEC output is fixed at –32768 when a ring is not present. The CODEC data becomes +32767 upon detection of a positive ring. Negative rings will be ignored and have no effect on the CODEC data while RFWE is 0. When on-hook with RFWE = 1, the CODEC data is fixed at +1228 when a ring is not present. The CODEC data becomes +32767 upon detection of a positive ring or –32768 upon detection of a negative ring. The RDT bit acts like a one shot. When a new ring signal is detected, the one shot is reset. If no new ring signals are detected before the one shot counter reaches 0 (5 seconds), the RDT bit returns to 0. The RDT bit is also reset to 0 by an off-hook event. 14 Rev. 1.0 S i3068 4.11. Ringer Impedance and Threshold The ring detector in many DAAs is ac-coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ring detector on the Si3068 is resistively coupled to the line. The network presents a high ringer impedance to the line of approximately 5 MΩ to meet the majority of PTT specifications, including FCC. The ringer impedance network shown in Figure 9 is required for compliance with the ringer impedance requirements of South Korea. This network is only required if the application will be deployed in South Korea. The network components are detailed in Table 8. DTMF signaling. DTMF levels several dB higher can be achieved with this technique, compared with a digital full-scale peak signal. 4.13. Pulse Dialing Going off- and on-hook to generate make and break pulses accomplishes pulse dialing. The nominal rate is 10 pulses per second. 4.14. Receive Overload Certain line events, such as an off-hook event on a parallel phone, a billing tone, or a polarity reversal, can cause a receiver overload. Although the DAA may remain off-hook during such an event, the data received from the line may be corrupted. If a disturbance on the line causes the loop current to collapse below the minimum operating current, the dropout detect bit, DOD, is set. An interrupt will be generated if the dropout detect interrupt mask bit, DODM, is set. TIP C 15 R 14 Z2 Z3 4.15. On-Hook Line Monitor Mode The DAA monitors line activity when in on-hook linemonitor mode. This mode detects caller ID data, and no line current is drawn. See Section “4.16. Caller ID” on page 15. This mode is enabled by setting the ONHM bit (Register 5, bit 3). ARX [2:0] (Register 15, bits 2:0) provides gain to the normal receive path of the DAA and functions as a gain bit for the on-hook line monitor. RING Figure 9. South Korea Ringer Impedance Network Table 8. South Korea Ringer Impedance Network Components Item C15 R14 Z2 Z3 Value 1 mF, 250 V 7.5 kΩ, 1/4 W 18 V 18 V 4.16. Caller ID The DAA can pass caller ID data from the phone line to a software caller ID decoder. 4.16.1. Type I Caller ID Type I Caller ID sends the CID data while the phone is on-hook. In systems where the caller ID data is passed on the phone line between the first and second rings, utilize the following method to capture the caller ID data: 1. After identifying a ring signal using one of the methods described in Section "4.9. Ring Detection" on page 14, determine when the first ring has completed. 2. Assert the ONHM bit (Register 5, bit 3) to enable the caller ID ADC. This low-current ADC, which is powered from the system-side device, digitizes the caller ID data. 3. Clear the ONHM bit after the caller ID data is received. 4.12. DTMF Dialing The Si3068 meets all the country requirements for DTMF dialing listed in Table 5 on page 10. Higher DTMF levels can be achieved if the amplitude is increased and the peaks of the DTMF signal are clipped at digital full scale, avoiding wrapping the waveform. Clipping the signal produces distortion and intermodulation of the signal. Generally, increased distortion between 10 and 20% is acceptable during Rev. 1.0 15 S i3068 4.16.2. Type II Caller ID Type II Caller ID sends the CID data while the phone is off-hook and is often referred to as caller ID/call waiting (CID/CW). To receive the CID data while off-hook, use the following procedure: 1. The Caller Alert Signal (CAS) tone is sent from the Central Office (CO) and is digitized along with the line data. The software must detect the presence of this tone. 2. Since the DAA is the only device on the line and is Type II CID-compliant, the software must mute its upstream data output to avoid propagation of its reply tone and the subsequent CID data. After muting its upstream data output, the software must then return an acknowledgement (ACK) tone to the CO to request the transmission of the CID data. 3. The CO then responds with the CID data, and the software unmutes the upstream data output and continues with normal operation. 4. The muting of the upstream data path by the software mutes the handset in a telephone application so the user cannot hear the acknowledgement tone and CID data being sent. The CID data presented to the software could have up to a 10% dc offset. The software caller ID decoder must either use a high-pass or a band-pass filter to accurately retrieve the caller ID data. except for the isolated capacitor link. No communication between the system side and Si3068 can occur during reset operation. Register bits associated with the Si3068 are not valid in this mode. The most common mode of operation is normal operation. The PDL and PDN bits are cleared, and the capacitive link is passing information between the system side and the Si3068. A valid sample rate must be programmed before entering this mode. The Si3068 supports a low-power sleep mode for the wake-up-on-ring feature of many modems. The sample rate must be programmed with a valid non-zero value before enabling sleep mode. The PDN bit must then be set; the PDL bit cleared. To take the DAA out of sleep mode, pulse (RESET) low. In summary, the powerdown sequence for sleep mode is as follows: 1. SRC[3:0] must have a valid non-zero value. 2. Set the PDN bit (Register 6, bit 3) and clear the PDL bit (Register 6, bit 4). The power-up sequence is as follows: 1. Reset the DAA by pulsing the RESET pin. 2. Program registers to required settings. The Si3068 also supports an additional powerdown mode. When the PDN and PDL bits are set, the DAA enters a complete powerdown mode and draws negligible current (deep sleep mode). Normal operation is restored using the same process for taking the DAA out of sleep mode. 4.17. Gain Control The Si3068 supports multiple receive gain and transmit attenuation settings (Register 15). The receive path supports gains of 0, 3, 6, 9, and 12 dB, as selected with the ARX[2:0] bits. The receive path can be muted with the RXM bit. The transmit path supports attenuations of 0, 3, 6, 9, and 12 dB, as selected with the ATX[2:0] bits. The transmit path can be muted with the TXM bit. 4.20. Calibration The Si3068 initiates an auto-calibration by default when the device goes off-hook or experiences a loss in line power. Calibration removes offsets that are present in the on-chip ADC and could affect the ADC dynamic range. Auto-calibration is initiated after the DAA dc termination stabilizes and takes 273 ms to complete. 4.18. Sample Rate Converter The SRC [3:0] bits (Register 7, bits 3:0) are used to select the sample rate. The following sample rates are supported: 7200, 8000, 8229, 8400, 9000, 9600, 10286, 12000, 13714, and 16000 Hz. 4.21. Revision Identification The revision of the system-side module and line-side (Si3068) can be determined using the REVA[3:0] bits (Register 11, bits 3:0) and REVB[3:0] bits (Register 13, bits 5:2), respectively. Table 9 lists the revision values. 4.19. Power Management The Si3068 supports four basic power management operation modes: normal operation, reset operation, sleep mode, and full powerdown mode. The power management modes are controlled by the PDL and PDN bits (Register 6, bits [4:3]). Upon powerup or following a reset, the Si3068 is in reset operation. The PDL bit is set, and the PDN bit is cleared. The system-side module is fully operational Table 9. Si3068 Revision Levels Si3068 Revision A B Si3068 REVB[3:0] 1000 1001 16 Rev. 1.0 S i3068 5. Register Summary Offset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–59 60 Name Control 1 Control 2 Interrupt Mask Interrupt Status DAA Control 1 DAA Control 2 Sample Rate Control Reserved Reserved DAA Control 3 System-Side Revision Line-Side Status Line-Side Revision Reserved TX/RX Gain Control Reserved Calibration International Control 3 Dropout Detect Call Progress RX Attenuation Call Progress TX Attenuation Ring Validation Control 1 Ring Validation Control 3 Reserved Reserved Reserved Reserved Line Voltage Status Reserved Line-side ID LSID4 LVS[6:0] RDLY[1:0] RTO[3:0] RAS[5:0] RNGV Ring Validation Control 2 RDLY[2] ARM[7:0] ATM[7:0] RMX[5:0] RCC[2:0] ADCC RFWE DOD TXM ATX[2:0] RXM ARX[2:0] LSID[3:0] FDT REVB[3:0] REVA[3:0] LCS[4:0] DDL RDTM RDTI RDTN FDTM FDTI RDTP PDL Bit 7 SR Bit 6 Bit 5 Bit 4 WDTE Bit 3 PWME AL DODM DODI ONHM PDN SRC[3:0] RDM LCSM LCSI RDT OH Bit 2 Bit 1 IDL HBE RXE Bit 0 PWMM[1:0] Rev. 1.0 17 S i3068 DAA Register 1. Control 1 Bit Name Type D7 SR R/W D6 D5 D4 D3 PWME R/W D2 D1 IDL R/W D0 PWMM[1:0] R/W Reset settings = 0000_0x0x Bit 7 Name SR Function Software Reset. 0 = Enables DAA for normal operation. 1 = Sets all registers to their reset value. Note: Bit clears automatically after being set. 6 5:4 Reserved PWMM[1:0] Always write as zero. Reads undefined. Pulse-Width Modulation Mode. Selects the type of signal on the call progress AOUT pin. 00 = PWM output clocked at 16.384 MHz. A local density of 1s and 0s tracks the combined transmit and receive signal. 01 = Balanced conventional PWM output signal has high and low portions of the modulated pulse centered on the 32 kHz sample clock. 10 = Conventionally PWM output signal returns to 0 at 32 kHz intervals and rises at a time in the 32 kHz period proportional to the instantaneous amplitude. 11 = Reserved. Pulse-Width Modulation Enable. 0 = Call progress PWM AOUT disabled. 1 = Call progress PWM AOUT enabled. Read returns zero. Isolation Digital Loopback. 0 = Digital loopback across isolation barrier disabled. 1 = Enables digital loopback mode across isolation barrier. The line-side device must be enabled and off-hook before setting this mode. This data path includes RX and TX filters. A valid phone line is not necessary for this mode. Read returns zero. 3 PWME 2 1 Reserved IDL 0 Reserved 18 Rev. 1.0 S i3068 DAA Register 2. Control 2 Bit Name Type Reset settings = xxx0_0011 Bit 7:5 4 Name Reserved WDTE Function Always write this bit to zero. Reads undefined. DAA Watchdog Timer Enable. 0 = Watchdog timer disabled. 1 = Watchdog timer enabled. When set, this bit is cleared only by a hardware reset. The watchdog timer monitors DAA register writes. If a register write does not occur within a 4.096 second window, the DAA is put into an on-hook state. Only a write of a DAA register restarts the timer. Analog Loopback. 0 = Analog loopback mode disabled. 1 = Enables external analog loopback mode. Ring Detect Mode. 0 = Ring detect on positive threshold. 1 = Ring detect on positive and negative threshold. Hybrid Enable. 0 = Disconnects hybrid in transmit path. 1 = Connects hybrid in transmit path. Receive Enable. 0 = Receive path disabled. 1 = Enables receive path. D7 D6 D5 D4 WDTE D3 AL R/W D2 RDM R/W D1 HBE R/W D0 RXE R/W R/W 3 AL 2 RDM 1 HBE 0 RXE Rev. 1.0 19 S i3068 DAA Register 3. Interrupt Mask Bit Name Type D7 RDTM R/W D6 D5 FDTM R/W D4 D3 DODM R/W D2 LCSM R/W D1 D0 Reset settings = 0x0x_00xx Bit 7 Name RDTM Function Ring Detect Interrupt Mask. 0 = A ring signal does not cause an interrupt. 1 = A ring signal causes an interrupt. Always write this bit to zero. Reads undefined. Frame Detect Interrupt Mask. 0 = Isolation capacitor frame lock does not cause an interrupt. 1 = Isolation capacitor frame lock causes an interrupt. Always write this bit to zero. Reads undefined. Drop Out Detect Interrupt Mask. 0 = A line supply dropout does not cause an interrupt. 1 = A line supply dropout causes an interrupt. Loop Current Sense Overload Interrupt Mask. 0 = Loop current sense overload does not cause an interrupt. 1 = Loop current sense overload causes an interrupt. 1:0 Reserved Always write this bit to zero. Reads undefined. 6 5 Reserved FDTM 4 3 Reserved DODM 2 LCSM 20 Rev. 1.0 S i3068 DAA Register 4. Interrupt Status Bit Name Type D7 RDTI R/W D6 D5 FDTI R/W D4 D3 DODI R/W D2 LCSI R/W D1 D0 Reset settings = 0x0x_00xx Bit 7 Name RDTI Ring Detect Interrupt Status. 0 = No ring. 1 = Ring detected. Write 0 to clear. Always write this bit to zero. Reads undefined. Frame Detect Interrupt Status. 0 = Frame detect established. 1 = Frame detect lost. Write 0 to clear. Always write this bit to zero. Reads undefined. Drop Out Detect Interrupt Status. 0 = Line-side power available. 1 = Line-side power unavailable. Loop Current Sense Overload Interrupt. 0 = The LCS bits have not reached max (all ones). 1 = The LCS bits have reached max value. If the LCSM bit is set, a hardware interrupt occurs. This bit must be written to 0 to clear it. Always write this bit to zero. Reads undefined. Function 6 5 Reserved FDTI 4 3 Reserved DODI 2 LCSI 1:0 Reserved Rev. 1.0 21 S i3068 DAA Register 5. DAA Control 1 Bit Name Type Reset settings = x00x_00x0 Bit 7 6 Name Reserved RDTN Function Always write this bit to zero. Reads undefined. Ring Detect Signal Negative. 0 = No ring signal is occurring. 1 = A negative ring signal is occurring. Ring Detect Signal Positive. 0 = No ring signal is occurring. 1 = A positive ring signal is occurring. Always write this bit to zero. Reads undefined. On-Hook Line Monitor. 0 = Normal on-hook mode. 1 = Enables low-power monitoring mode allowing the DAA to receive line activity without going off-hook. This mode is used for caller-ID detection. Ring Detect. 0 = Reset either five seconds after last positive ring is detected or when the system executes an off-hook. 1 = Indicates a ring is occurring. Always write this bit to zero. Reads undefined. Off-Hook. 0 = Line-side device on-hook. 1 = Causes the line-side device to go off-hook. D7 D6 RDTN R D5 RDTP R D4 D3 ONHM R/W D2 RDT R D1 D0 OH R/W 5 RDTP 4 3 Reserved ONHM 2 RDT 1 0 Reserved OH 22 Rev. 1.0 S i3068 DAA Register 6. DAA Control 2 Bit Name Type Reset settings = xxx1_0xxx Bit 7:5 4 Name Reserved PDL Function Always write this bit to zero. Reads undefined. Powerdown Line-Side Chip. 0 = Normal operation. Program the clock generator before clearing this bit. 1 = Powers down the Si3068. Powerdown DAA. 0 = Normal operation. 1 = Powers down the DAA logic. A DAA soft reset is required to restore normal operation. Always write this bit to zero. Reads undefined. D7 D6 D5 D4 PDL R/W D3 PDN R/W D2 D1 D0 3 PDN 2:0 Reserved Rev. 1.0 23 S i3068 DAA Register 7. Sample Rate Control Bit Name Type Reset settings = xxxx_0001 Bit 7:4 3:0 Name Reserved SRC[3:0] Sample Rate Control. Sets the sampling rate. 0000 = 7200 Hz 0001 = 8000 Hz 0010 = 8229 Hz 0011 = 8400 Hz 0100 = 9000 Hz 0101 = 9600 Hz 0110 = 10286 Hz 0111 = 12000 Hz 1000 = 13714 Hz 1001 = 16000 Hz 1010–1111 = Reserved Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 SRC[3:0] R/W D1 D0 DAA Register 8. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name Reserved Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 D1 D0 24 Rev. 1.0 S i3068 DAA Register 9. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name Reserved Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 D1 D0 DAA Register 10. DAA Control 3 Bit Name Type Reset settings = xxxx_xxx0 Bit 7:1 0 Name Reserved DDL Function Always write this bit to zero. Reads undefined. Digital Data Loopback. 0 = Normal Operation. 1 = Loopback transmit to receive before the filters. Output data is identical to input data. D7 D6 D5 D4 D3 D2 D1 D0 DDL R/W DAA Register 11. System-Side Revision Bit Name Type Reset settings = xxxx_xxxx Bit 7:4 3:0 Name LSID[3:0] REVA[3:0] Line-Side ID. 1011 = Si3068 System-Side Revision. Four bit value indicating the revision of the system-side device. Function D7 D6 LSID[3:0] R D5 D4 D3 D2 R D1 D0 REVA[3:0] Rev. 1.0 25 S i3068 DAA Register 12. Line-Side Status Bit Name Type Reset settings = xxxx_xxxx Bit 7 6 Name Reserved FDT Read returns zero. Frame Detect. 0 = Indicates isolation capacitor link has not established frame lock. 1 = Indicates isolation capacitor link frame lock is established. Always write this bit to zero. Reads undefined. Loop Current Sense. Five-bit value returning the loop current in 3.3 mA/bit resolution when the DAA is in an offhook state. 00000–00011 = Indicates the loop current is less than required for normal operation. 00100 = Indicates minimum loop current for normal operation. 00101 = 11110 = Normal operation 11111 = Indicates loop current is > 160 mA. Function D7 D6 FDT R D5 D4 D3 D2 LCS[4:0] R D1 D0 5 4:0 Reserved LCS[4:0] DAA Register 13. Line-Side Revision Bit Name Type Reset settings = xxxx_xxxx Bit 7:6 5:2 Name Reserved REVB[3:0] Function Always write this bit to zero. Reads undefined. Line-Side Revision. Four-bit value indicating the revision of the Si3068 device. 1000 = Revision A; 1001 = Revision B Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 D1 D0 REVB[3:0] R 1:0 Reserved 26 Rev. 1.0 S i3068 DAA Register 14. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name Reserved Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 D1 D0 DAA Register 15. TX/RX Gain Control Bit Name Type D7 TXM R/W D6 D5 ATX[2:0] R/W D4 D3 RXM R/W D2 D1 ARX[2:0] R/W D0 Reset settings = 0000_0000 Bit 7 Name TXM Transmit Mute. 0 = Transmit signal is not muted. 1 = Mutes the transmit signal. Analog Transmit Attenuation. 000 = 0 dB attenuation 001 = 3 dB attenuation 010 = 6 dB attenuation 011 = 9 dB attenuation 1xx = 12 dB attenuation Receive Mute. 0 = Receive signal is not muted. 1 = Mutes the receive signal. Analog Receive Gain. 000 = 0 dB gain 001 = 3 dB gain 010 = 6 dB gain 011 = 9 dB gain 1xx = 12 dB gain Function 6:4 ATX[2:0] 3 RXM 2:0 ARX[2:0] Rev. 1.0 27 S i3068 DAA Register 16. Reserved Bit Name Type Reset settings = xxx1_xxxx Bit Name Function D7 D6 D5 D4 D3 D2 D1 D0 7:0 Reserved Always write this bit to zero. Reads undefined. DAA Register 17. Calibration Bit Name Type Reset Settings = xx0x_xxxx Bit 7:6 5 4:0 Name Reserved ADCC Reserved Function Always write this bit to zero. Reads undefined. ADC Calibration. 1 = Calibration disabled. Always write this bit to zero. Reads undefined. D7 D6 D5 ADCC R/W D4 D3 D2 D1 D0 28 Rev. 1.0 S i3068 DAA Register 18. International Control 3 Bit Name Type Reset Settings = xxxx_xx0x Bit 7:2 1 Name Reserved RFWE Function Always write this bit to zero. Reads undefined. Ring Detector Full-Wave Rectifier Enable. When RNGV is disabled, this bit controls the ring detector mode. When RNGV is enabled, this bit configures the RDT bit to either follow the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter timeout of approximately five seconds. RNGV RFWE RDT bit 0 0 Half-Wave 0 1 Full-Wave 1 0 Validated Ring Envelope 1 1 Ring Threshold Crossing One-Shot Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 D1 RFWE R/W D0 0 Reserved DAA Register 19. Dropout Detect Bit Name Type Reset Settings = xxxx_xxxx Bit 7:2 1 Name DOD Dropout Detect. 0 = Normal operation. 1 = Dropout detected. Function D7 D6 D5 D4 D3 D2 D1 DOD R D0 Reserved Always write this bit to zero. Reads undefined. 0 Reserved Always write this bit to zero. Reads undefined. Rev. 1.0 29 S i3068 DAA Register 20. Call Progress Receive Attenuation Bit Name Type Reset settings = xxxx_0000 Bit 7:0 Name ARM[7:0] Function AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for call progress monitoring. Setting the bits to 0s mutes the AOUT receive path. 0111_1111 = +6 dB (gain) 0100_0000 = 0 dB 0010_0000 = –6 dB (attenuation) 0001_0000 = –12 dB ... 0000_0000 = Mute D7 D6 D5 D4 ARM[7:0] R/W D3 D2 D1 D0 DAA Register 21. Call Progress Transmit Attenuation Bit Name Type Reset settings = xxxx_0000 Bit 7:0 Name ATM[7:0] Function AOUT Transmit Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT transmit path signal used for call progress monitoring. Setting the bits to 0s mutes the AOUT transmit path. 0111_1111 = +6 dB (gain) 0100_0000 = 0 dB 0010_0000 = –6 dB (attenuation) 0001_0000 = –12 dB ... 0000_0000 = Mute D7 D6 D5 D4 ATM[7:0] R/W D3 D2 D1 D0 30 Rev. 1.0 S i3068 DAA Register 22. Ring Validation Control 1 Bit Name Type D7 D6 D5 D4 D3 RMX[5:0] R/W D2 D1 D0 RDLY[1:0] R/W Reset settings = 1001_0110 Bit 7:6 Name RDLY[1:0] Function Ring Delay. These bits, in combination with the RDLY[2] bit, set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2] RDLY[1:0] Delay 0 00 0 ms 0 01 256 ms 0 10 512 ms ... 1 11 1792 ms Ring Assertion Maximum Count. These bits set the maximum ring frequency for a valid ring signal within a 10% margin of error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the RMX[5:0] field, and, if it exceeds the value in RMX[5:0], the frequency of the ring is too high and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min, f_max], the following equation should be used: 1 RMX [ 5:0 ] = RAS [ 5:0 ] – -------------------------------------------- , RMX ≤ RAS 2 × f_max × 2 ms 5:0 RMX[5:0] To compensate for error margin and ensure a sufficient ring detection window, it is recommended that the calculated value of RMX[5:0] be incremented by 1. Rev. 1.0 31 S i3068 DAA Register 23. Ring Validation Control 2 Bit Name Type D7 RDLY[2] R/W D6 D5 RTO[3:0] R/W D4 D3 D2 D1 RCC[2:0] R/W D0 Reset settings = 0010_1101 Bit 7 Name RDLY[2] Function Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits, sets the amount of time between when a ring signal is validated and when a valid ring signal is indicated. RDLY[2] RDLY[1:0] Delay 0 00 0 ms 0 01 256 ms 0 10 512 ms ... 1 11 1792 ms Ring Timeout. Determine when ringing is finished after the most recent ring threshold crossing. 0000 = Invalid 0001 = 128 x 1 = 128 ms 0010 = 128 x 2 = 256 ms ... 1111 = 128 x 15 = 1920 ms Ring Confirmation Count. Determine the time interval over which the ring signal must meet tolerances defined by RAS[5:0] and RMX[5:0] to be classified as a valid ring signal. 000 = 100 ms 001 = 150 ms 010 = 200 ms 011 = 256 ms 100 = 384 ms 101 = 512 ms 110 = 640 ms 111 = 1024 ms 6:3 RTO[3:0] 2:0 RCC[2:0] 32 Rev. 1.0 S i3068 DAA Register 24. Ring Validation Control 3 Bit Name Type D7 RNGV R/W D6 D5 D4 D3 RAS[5:0] R/W D2 D1 D0 Reset settings = 0x01_1001 Bit 7 Name RNGV Function Ring Validation Enable. 0 = Ring validation feature is disabled. 1 = Ring validation feature is enabled in normal operating mode and low-power mode. Always write this bit to zero. Reads undefined. Ring Assertion Time. These bits set the minimum ring frequency for a valid ring signal. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a regular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out, the frequency of the ring is too low and the ring is invalidated. The difference between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range [f_min, f_max], the following equation should be used: 1 -, RAS [ 5:0 ] ≥ ------------------------------------------ RMX ≤ RAS 2 × f_min × 2 ms 6 5:0 Reserved RAS[5:0] DAA Register 25-28. Reserved Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 Reset settings = xxxx_xxxx Bit 7:0 Name Reserved Function Always write this bit to zero. Reads undefined. Rev. 1.0 33 S i3068 DAA Register 29. Line Voltage Status Bit Name Type Reset settings = xxxx_xxxx Bit 7 6:0 Name Reserved LVS Line Voltage Status 1 LSB = 1 V Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 LVS[6:0] R D2 D1 D0 DAA Register 30-59. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name Reserved Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 D1 D0 DAA Register 60. Line-Side ID Bit Name Type Reset settings = xxxx_x1xx Bit 7:3 2 1:0 Name Reserved LSID4 Reserved Line-Side ID. LSID = 1 for Si3068 Always write this bit to zero. Reads undefined. Function Always write this bit to zero. Reads undefined. D7 D6 D5 D4 D3 D2 LSID4 R/W D1 D0 34 Rev. 1.0 S i3068 6. Pin Descriptions C1B C2B VREG CID 1 2 3 4 9 8 7 6 5 IGND RX DCT QB QE Pin # 1 Pin Name C1B Description Isolation Capacitor 1B. Connects to one side of isolation capacitor C1 and communicates with the system-side module. Isolation Capacitor 2B. Connects to one side of isolation capacitor C2 and communicates with the system-side module. Voltage Regulator. Connects to an external capacitor to provide bypassing for an internal power supply. Caller ID. Caller ID input. Transistor Emitter. Connects to the emitter of Q3. Transistor Base. Connects to the base of transistor Q3. Used to go on- and off-hook. DC Termination. Provides dc termination to the telephone network. Receive Input. Serves as the receive side input from the telephone network. Isolated Ground (exposed pad). Connects to ground on the line-side interface. 2 C2B 3 4 5 6 7 8 9 VREG CID QE QB DCT RX IGND Rev. 1.0 35 S i3068 7. Ordering Guide Part Number* Si3068-B-FS Package e-Pad SOIC Lead-Free Yes Temp Range 0 to 70 °C *Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 36 Rev. 1.0 S i3068 8. Package Outline: 8-Pin Exposed Pad SOIC Figure 10 illustrates the package details for the Si3068. Table 10 lists the values for the dimensions shown in the illustration. α Figure 10. 8-pin Exposed Pad Small Outline Integrated Circuit (SOIC) Package Rev. 1.0 37 S i3068 Table 10. Package Diagram Dimensions Dimension A A1 A2 B C D D1 E E1 e H h L ∝ 5.80 0.25 0.40 0° Millimeters Min 1.35 0.00 1.40 REF 0.33 0.19 4.80 2.14 3.80 2.14 1.27 BSC 6.20 0.50 1.27 8° Max 1.75 0.15 1.55 REF 0.51 0.25 5.00 2.44 4.00 2.44 Notes: 1. All dimensions shown are in millimeters (mm). 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD020C specification for Small Body Components. 38 Rev. 1.0 S i3068 NOTES: Rev. 1.0 39 S i3068 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. 40 Rev. 1.0