SI3200-X-FS

S i 3 2 2 0/25 DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC Features Performs all BORSCHT functions Ideal for applications up to 18 kft Internal balanced ringing to 65 Vrms (Si3220) External bulk ringer support (Si3225) Software-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape (Si3220) Two-wire ac impedance Transhybrid balance DC current loop feed (18–45 mA) Loop closure and ring trip thresholds Ground key detect threshold Automatic switching of up to three battery supplies On-hook transmission Loop or ground start operation with smooth/abrupt polarity reversal Modem/fax tone detection DTMF generation/decoding Dual tone generators A-Law/µ-Law, linear PCM companding PCM and SPI bus digital interfaces with programmable interrupts GCI mode support 3.3 or 5 V operation GR-909 loop diagnostics Audio diagnostics with loopback 12 kHz/16 kHz pulse metering (Si3220) FSK caller ID generation Lead-free/RoHS-compliant Part Number Si3220 Si3225 Ringing Method Internal External Ringer Applications Digital loop carriers Central Office telephony Pair gain remote terminals Wireless local loop Private Branch Exchange (PBX) systems Cable telephony Voice over IP/voice over DSL ISDN terminal adapters Ordering Information See “Dual ProSLIC Selection Guide” on page 109. U.S. Patent #6,567,521 U.S. Patent #6,812,744 Other patents pending Description The Dual ProSLIC® is a series of low-voltage CMOS devices that integrate both SLIC and codec functionality into a single IC to provide a complete dual-channel analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI specifications. The Si3220 includes internal ringing generation to eliminate centralized ringers and ringing relays, and the Si3225 supports centralized ringing for long loop and legacy applications. On-chip subscriber loop and audio testing allows remote diagnostics and fault detection with no external test equipment or relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed interface IC performs all high-voltage functions and operates from a 3.3 V or 5 V supply as well as single or dual battery supplies up to 100 V. The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is available in a thermally-enhanced 16-pin small outline (SOIC) package. Functional Block Diagram INT RESET Si3220/25 CS SCLK SDO SDI SPI Control Interface Pulse Metering Subscriber Line Diagnostics Ringing Generator & Ring Trip Sense Dual Tone Generators Modem Tone Detection 2-Wire AC Impedance Hybrid Balance DTMF Decode FSK text Caller ID Codec A SLIC A Linefeed Control DAC ADC Codec B TIP Linefeed Interface Channel A RING Linefeed Monitor DTX DRX FSYNC PCM / GCI Interface DSP SLIC B Linefeed Control Gain Adjust Loop Closure, & Ground Key Detection Relay Drivers DAC ADC TIP Linefeed Interface Channel B RING PCLK PLL Programmable Audio Filters Linefeed Monitor Rev. 1.2 2/06 Copyright © 2006 by Silicon Laboratories Si3220/25 S i3220/25 2 Rev. 1.2 S i3220/25 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1. Dual ProSLIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4. Adaptive Linefeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5. Ground Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.7. Loop Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.8. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.10. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.11. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.12. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.13. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.14. Ringing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.15. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.16. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.17. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.18. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.19. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.20. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.21. Caller ID Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.22. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.23. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.24. Modem Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.25. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.26. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.27. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 3.28. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.29. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.30. PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.31. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.32. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4. Pin Descriptions: Si3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5. Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Rev. 1.2 3 S i3220/25 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information1 Parameter Supply Voltage, Si3200 and Si3220/Si3225 High Battery Supply Voltage, Si32002 Low Battery Supply Voltage, Si3200 TIP or RING Voltage, Si3205 Symbol VDD, VDD1–VDD4 VBATH VBAT,VBATL VTIP,VRING Test Condition Continuous 10 ms Continuous Continuous Pulse < 10 µs Pulse < 4 µs Value –0.5 to 6.0 0.4 to –104 0.4 to –109 VBATH Unit V V V TIP, RING Current, Si3200 STIPAC, STIPDC, SRINGAC, SRINGDC Current, Si3220/Si3225 Input Current, Digital Input Pins Si3220/25 Analog Ground Differential Voltage (GND1 to ePad, GND2 to ePad, or GND1 to GND2)3 Si3220/25 Digital Ground Differential Voltage (GND3 to GND4)3 Si3220/25 Analog to Digital Ground Differential Voltage (GND1/GND2/ePad to GND3/GND4)3 Digital Input Voltage Operating Temperature Range Storage Temperature Range Si3220/Si3225 Thermal Resistance, Typical3 (TQFP-64 ePad) Si3200 Thermal Resistance, Typical4 (SOIC-16 ePad) Continuous Power Dissipation, Si32005 Continuous Power Dissipation, Si3220/25 ITIP, IRING –104 VBATH –15 VBATH –35 ±100 ±20 ±10 ±50 ±50 ±200 mA mA mA mV mV mV IIN ∆VGNDA ∆VGNDD ∆VGND,A–D VIND TA TSTG θJA θJA PD PD Continuous –0.3 to (VDDD + 0.3) V –40 to 100 °C –40 to 150 °C 25 °C/W 55 TA = 85 °C, SOIC-16 TA = 85 °C, TQFP-64 1 1.6 °C/W W W Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/µs. 3. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to the GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are not exceeded under any operating condition in addition to providing thermal dissipation. 4. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC® User Guide” or to the Si3220/3225 evaluation board data sheet for specific layout examples. 5. On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For optimal reliability, junction temperatures above 140 °C should be avoided. 4 Rev. 1.2 S i3220/25 Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 Symbol TA TA VDD1–VDD4 VDD VBATH VBATL Test Condition K/F-Grade B/G-Grade Min* 0 –40 3.13 3.13 –15 –15 Typ 25 25 3.3/5.0 3.3/5.0 — — Max* 70 85 5.25 5.25 –99 VBATH Unit oC oC V V V V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. Table 3. 3.3 V Power Supply Characteristics1 (VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter VDD1–VDD4 Supply Current (Si3220/ Si3225) Symbol IVDD1–IVDD4 Test Condition Sleep mode, RESET = 0 Open (high-impedance) Active on-hook standby Forward/reverse active off-hook Min — — — — Typ 200 17 16 45 + ILIM + ABIAS 47 26 Max — — — — Unit µA mA mA mA Forward/reverse active OHT OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 Vrms, VBAT = –70 V, Sine Wave, 1 REN load2 — — — — mA mA Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional (VDD + |VBAT|) x ILOOP term. Rev. 1.2 5 S i3220/25 Table 3. 3.3 V Power Supply Characteristics1 (Continued) (VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter VDD Supply Current (Si3200) Symbol IVDD Test Condition Sleep mode, RESET = 0 Open (high-impedance) Active on-hook standby Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 Vrms, VBAT = –70 V, Sine Wave, 1 REN load Min — — — — — — Typ 110 110 110 110 110 110 Max — — — — — — Unit µA µA µA µA µA µA VBAT Supply Current (Si3200) IVBAT Sleep mode, RESET=0, VBAT = –70 V Open (high-impedance), VBAT = –70 V Active on-hook standby, VBAT = –70 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 Vrms, VBAT = –70 V, Sine Wave, 1 REN load2 — — — — 100 189 517 4.5 + ILIM 8.6 6.5 — — — — µA µA µA mA — — — — mA mA Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional (VDD + |VBAT|) x ILOOP term. 6 Rev. 1.2 S i3220/25 Table 3. 3.3 V Power Supply Characteristics1 (Continued) (VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Chipset Power Consumption Symbol PSLEEP POPEN PSTBY PACTIVE3 POHT PRING Test Condition Sleep mode, RESET = 0, VBAT = –70 V Open (high-impedance), VBAT = –70 V Active on-hook standby, VBAT = –70 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 vrms, VBAT = –70 V, 1 REN load2 Min — — — — — — Typ 8 69 89 267 757 541 Max — — — — — — Unit mW mW mW mW mW mW Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional (VDD + |VBAT|) x ILOOP term. Rev. 1.2 7 S i3220/25 Table 4. 5 V Power Supply Characteristics1 (VDD, VDD1 – VDD4 = 5 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter VDD1 – VDD4 Supply Current (Si3220/Si3225) Symbol IVDD1–IVDD4 Test Condition Sleep mode, RESET = 0 Open (high-impedance) Active on-hook standby Forward/reverse active off-hook Min — — — — Typ 1 22 21 62 + ILIM + ABIAS 65 31 110 110 110 110 110 110 Max — — — — Unit mA mA mA mA Forward/reverse active OHT OBIAS = 4 mA Ringing, VRING = 45 Vrms, VBAT = –70 V, 1 REN load2 VDD Supply Current (Si3200) IVDD Sleep mode, RESET = 0 Open (high-impedance) Active on-hook standby Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 Vrms, VBAT = –70 V, 1 REN load — — — — — — — — — — — — — — — — mA mA µA µA µA µA µA µA Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional (VDD + |VBAT|) x ILOOP term. 8 Rev. 1.2 S i3220/25 Table 4. 5 V Power Supply Characteristics1 (Continued) (VDD, VDD1 – VDD4 = 5 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter VBAT Supply Current (Si3200) Symbol IVBAT Test Condition Sleep mode, RESET = 0, VBAT = –70 V Open (high-impedance), VBAT = –70 V Active on-hook standby, VBAT = –70 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 Vrms, VBAT = –70 V, 1 REN load2 Min — — — — Typ 125 190 700 4.7 + ILIM 8.8 6.5 Max — — — — Unit µA µA µA mA — — — — mA mA Chipset Power Consumption PSLEEP POPEN PSTBY PACTIVE3 POHT PRING Sleep mode, RESET = 0, VBAT = –70 V Open (high-impedance), VBAT = –70 V Active on-hook standby, VBAT = –70 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = –24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = –70 V Ringing, VRING = 45 Vrms, VBAT = –70 V, 1 REN load2 — — — — — — 13.8 123 154 436 941 610 — — — — — — mW mW mW mW mW mW Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional (VDD + |VBAT|) x ILOOP term. Rev. 1.2 9 S i3220/25 Table 5. AC Characteristics (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Overload Level Overload Compression Single Frequency Distortion 1 Test Condition TX/RX Performance 2-Wire – PCM 2-Wire – PCM or PCM – 2-Wire: 200 Hz to 3.4 kHz PCM – 2-Wire – PCM: 200 Hz – 3.4 kHz, 16-bit Linear mode 200 Hz to 3.4 kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZT 0 dBm0, Active off-hook, and OHT, any ZT Min 2.5 Figure 6 — — Typ — — –85 –87 Max — — –65 –65 Unit VPK dB dB Signal-to-(Noise + Distortion) Ratio2 Audio Tone Generator Signal-toDistortion Ratio2 Intermodulation Distortion Gain Accuracy 2 Figure 5 — — 46 — — –41 +0.25 — — — dB dB dB — — — Attenuation Distortion vs. Freq. Group Delay vs. Frequency Gain Tracking3 Round-Trip Group Delay Crosstalk between Channels TX or RX to TX TX or RX to RX Gain Step Increment4 2-Wire Return Loss5 — — 2-Wire to PCM or PCM to 2-Wire –0.25 — 1014 Hz, Any gain setting 0 dBm 0 Figure 7,8 — Figure 9 — 1014 Hz sine wave, — — reference level –10 dBm Signal level: 3 dB to –37 dB — — –37 dB to –50 dB — — –50 dB to –60 dB — — 1014 Hz, Within same time-slot — 600 0 dBm0, 300 Hz to 3.4 kHz — –108 300 Hz to 3.4 kHz — –108 Step size around 0 dB — ±0.0005 200 Hz to 3.4 kHz 26 30 ± 0.25 ± 0.5 ± 1.0 700 –75 –75 — — dB dB dB µs dB dB dB dB Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the complete range. See "3.25. Audio Path Processing" on page 69. 5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients. 6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and offhook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application. 10 Rev. 1.2 S i3220/25 Table 5. AC Characteristics (Continued) (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Transhybrid Balance Idle Channel Noise 6 5 Test Condition 300 Hz to 3.4 kHz Noise Performance C-Message weighted Psophometric weighted 3 kHz flat RX and TX, dc to 3.4 kHz RX and TX, dc to 3.4 kHz Longitudinal Performance 200 Hz to 1 kHz 1 kHz to 3.4 kHz 200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register-dependent OBIAS/ABIAS 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA Active off-hook 200 Hz to 3.4 kHz Register-dependent OBIAS/ABIAS 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA Min 34 — — — 40 60 58 53 40 Typ 40 12 –78 — — — 70 58 — Max — 15 –75 18 — — — — — Unit dB dBrnC dBmP dBrn dB dB dB dB dB PSRR from VDD1 – VDD4 PSRR from VBAT Longitudinal to Metallic/PCM Balance (forward or reverse) Metallic/PCM to Longitudinal Balance Longitudinal Impedance7 — — — — 50 25 25 20 — — — — Ω Ω Ω Ω Longitudinal Current per Pin7 — — — — 4 8 8 10 — — — — mA mA mA mA Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the complete range. See "3.25. Audio Path Processing" on page 69. 5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients. 6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and offhook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application. Rev. 1.2 11 S i3220/25 Table 6. Linefeed Characteristics (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Maximum Loop Resistance (adaptive linefeed disabled1) Symbol RLOOP Test Condition RDC,MAX = 430 Ω, ILOOP = 18 mA, VBAT = –52 V, ABIAS = 8 mA VOCDELTA = 0 RDC,MAX2 = 430 Ω, ILOOP = 18 mA, VBAT = –52 V, ABIAS = 8 mA VOCDELTA ≠ 0 ILIM = 18 mA Active Mode; VOC = 48 V, VTIP – VRING 2 Min 1870 Typ — Max — Unit Ω Maximum Loop Resistance (adaptive linefeed enabled1) RLOOP 2030 — — Ω DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance DC On-Hook Voltage Accuracy—Ground Start DC Output Resistance—Ground Start DC Output Resistance—Ground Start Loop Closure Detect Threshold Accuracy Ground Key Detect Threshold Accuracy Ring Trip Threshold Accuracy RDO VOHTO RROTO RTOTO — — — — — 300 — — — — — 320 — 320 — ±10 ±10 ±4 ±10 ±4 — ±4 — — ±15 ±15 ±5 % V Ω V Ω kΩ % % mA ILOOP < ILIM IRING150 kΩ). Figure 17 illustrates the ground-start VRING/IRING behavior using VOC = 48 V and ILIM = 24 mA in the TIP-OPEN linefeed state. The ground key current thresholds are programmable via the LONGLOTH and LONGHITH RAM addresses. The LONGLPF RAM address provides filtering of the measured longitudinal currents, and the LONGDBI RAM address provides debouncing. The LONGHI status bit in register LCRRTP indicates when a ground key event has been detected. Upon detecting a ground key event, the linefeed automatically transitions to the FORWARD ACTIVE (if initially in TIP-OPEN) or REVERSE ACTIVE (if initially in RING-OPEN). See “3.11. Ground Key Detection” on page 45 for additional details. The two thresholds, VOCLTH and VOCHTH, control adaptive linefeed hysteresis as shown in Figure 16. VOCTRACK is a RAM location and is the actual opencircuit voltage that is being fed to the line. VOCTRACK is dependent on the measured VBAT voltage. The behavior of VOCTRACK is as shown in the equation below. As long as VBAT is sufficient to supply VOC + VOV + VCM, VOCTRACK is equal to the programmed VOC. However, if VBAT becomes too small to support VOC + VOV + VCM, then VOCTRACK will track the battery voltage so that the programmed VOV and VCM are satisfied at the expense of a reduced VOC voltage. In the example of Figure 16, therefore, VOCTRACK = VOC = 48 V. The following equation describes VOCTRACK behavior: | VBAT |≥ VOC + VOV + VCM ⇒ VOCTRACK= VOC | VBAT |< VOC + VOV + VCM ⇒ VOCTRACK=| VBAT | −(VOV + VCM ) The values of VOCLTH and VOCHTH are set relative to VOCTRACK. In the example shown in Figure 16, VOCLTH is given as –7 V and VOCHTH as +2 V. This implies that the VOCLTH threshold is located 7 V below the prevailing value of VOCTRACK, while the VOCHTH threshold is located 2 V above the prevailing value of VOCTRACK. Rev. 1.2 35 S i3220/25 0 mA -0 V 24 mA IRING ILIM = 24 mA -20 V -40 V 6 40 Ω VOCLTH VOCHTH 320 Ω -48 V VOC DELTA -80 V V RING Figure 17. Ground Start VRING/IRING Behavior 3.6. Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL register bit. This bit automatically resets upon completion of the calibration cycle. A calibration should be executed following system powerup. Upon release of the chip reset, the chipset will be in the open state, and calibration may be initiated. Only one calibration should be necessary if the system remains powered up. To optimize Dual ProSLIC performance, the calibration routine in “AN58: Si3220/Si3225 Programmer’s Guide” should be followed. (VTIP – VRING) and the loop current are also reported. For ground start operation, the values reported are VRING and the current flowing in the RING lead. Table 20 lists the register set associated with the loop monitoring functions. The Dual ProSLIC chipsets also include the ability to perform loop diagnostic functions as outlined in "3.32.2. Line Test and Diagnostics" on page 95. 3.8. Power Monitoring and Power Fault Detection The Dual ProSLIC line monitoring functions can be used to protect the high-voltage circuitry against excessive power dissipation and thermal overload conditions. The Dual ProSLIC devices can prevent thermal overloads by regulating the total power inside the Si3200 or in each of the external bipolar transistors (if using a discrete linefeed circuit). The DSP engine performs all power calculations and provides the ability to automatically transition the device into the OPEN state and generate a power alarm interrupt when excessive power is detected. Table 21 on page 40 describes the register and RAM locations used for power monitoring. 3.7. Loop Voltage and Current Monitoring The Dual ProSLIC chipset continuously monitors the TIP and RING voltages and currents. These values are available in registers. An internal 8-bit A/D converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. The A/D updates the samples at an 800 Hz rate for all inputs except VRNGNG and IRNGNG, which are sampled at 8 kHz to provide higher resolution for zero-crossing detection in external ringing applications. Two derived values, the loop voltage 36 Rev. 1.2 S i3220/25 Table 20. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Register/RAM Bits Measurement Range LSB Size Effective Resolution Loop Voltage Sense (VTIP – VRING) TIP Voltage Sense RING Voltage Sense Loop Current Sense Battery Voltage Sense Longitudinal Current Sense External Ringing Generator Voltage Sense External Ringing Generator Current Sense VLOOP VTIP VRING ILOOP VBAT ILONG VRNGNG IRNGNG VLOOP[15:0] VTIP[15:0] VRING[15:0] ILOOP[15:0] VBAT[15:0] ILONG[15:0] VRNGNG[15:0] IRNGNG[15:0] 0 to 64.07 V 64.07 to 160.173 V 0 to 64.07 V 64.07 to 160.173 V 0 to 64.07 V 64.07 to 160.173 V 0 to 101.09 mA 0 to 63.3 V 0 to 160.173 V 0 to 101.09 mA 332.04 V 662.83 mA 4.907 mV 4.907 mV 4.907 mV 3.097 µA 4.907 mV 3.097 µA 10.172 mV 20.3 µA 251 mV 628 mV 251 mV 628 mV 251 mV 628 mV 500 µA* 251 mV 628 mV 500 µA* 1.302 V 2.6 mA *Note: ILOOP and ILONG are calculated values based on measured IQ1–IQ4 currents. The resulting effective resolution is approximately 500 µA. ITIPN ITIPP IRINGP IRINGN Q4 Q1 Q2 Q3 RBQ6 TIP RING RBQ5 Q8 Q7 Q10 Q6 Q5 Q9 R6*gain 1.74k R6 82.5 R7 82.5 1.74k R7*gain VBAT Figure 18. Discrete Linefeed Circuit for Power Monitoring Rev. 1.2 37 S i3220/25 3.8.1. Transistor Power Equations (Using Discrete Transistors) Si3200 power calculation method to work correctly. 3.8.3. Power Filter and Alarms When using the Si3220 or Si3225 with discrete bipolar transistors, it is possible to control the total power of the solution by individually regulating the power in each discrete transistor. Figure 18 illustrates the basic transistor-based linefeed circuit for one channel. The power dissipation of each external transistor is estimated based on the A/D sample values. The approximate power equations for each external BJT are as follows: PQ1 ≅ VCE1 x IQ1 ≅ (|VTIP| + 0.75 V) x (IQ1) PQ2 ≅ VCE2 x IQ2 ≅ (|VRING| + 0.75 V) x (IQ2) PQ3 ≅ VCE3 x IQ3 ≅ (|VBAT| – R7 x IQ5) x (IQ3) PQ4 ≅ VCE4 x IQ4 ≅ (|VBAT| – R6 x IQ6) x (IQ4) PQ5 ≅ VCE5 x IQ5 ≅ (|VBAT| – |VRING| – R7 x IQ5) x (IQ5) PQ6 ≅ VCE6 x IQ6 ≅ (|VBAT| – |VTIP| – R6 x IQ6) x (IQ6) The maximum power threshold for each device is software-programmable and should be set based on the characteristics of the transistor package, PCB design, and available airflow. If the peak power exceeds the programmed threshold for any device, the power-alarm bit is set for that device. Each external bipolar has its own register bit (PQ1S–PQ6S bits of the IRQVEC3 register), which goes high on a rising edge of the comparator output and remains high until the user clears it. Each transistor power alarm bit is also maskable by setting the PQ1E–PQ6E bits in the IRQEN3 register. 3.8.2. Si3200 Power Calculation The power calculated during each A/D sample period must be filtered before being compared to a userprogrammable maximum power threshold. A simple digital low-pass filter is used to approximate the transient thermal behavior of the package, with the output of the filter representing the effective peak power within the package or, equivalently, the peak junction temperature. For Q1, Q2, Q3, and Q4 in SOT23 and Q5 and Q6 in SOT223 packages, the settings for thermal low-pass filter poles and power threshold settings are (for an ambient temperature of 70 °C) calculated as follows: If the thermal time constant of the package is τthermal, the decimal values of RAM locations PLPF12, PLPF34, and PLPF56 are given by rounding to the next integer the value given by the following equation: 3 4096 PLPFxx (decimal value) = ------------------------------------ × 2 800 × τ thermal Where 4096 is the maximum value of the 12-bit plus sign RAM locations PLPF12, PLPF34, and PLPF56, and 800 is the power calculation clock rate in Hz. The equation is an excellent approximation of the exact equation for τthermal = 1.25 ms … 5.12 s. With the above equations in mind, example values of the RAM locations, PTH12, PTH34, PTH56, PLPF12, PLPF34, and PLPF56, are as follows: PTH12 = power threshold for Q1, Q2 = 0.3 W (0x25A) PTH34 = power (0x1B5E) threshold for Q3, Q4 = 0.22 W When using the Si3200, it is also possible to detect the thermal conditions of the linefeed circuit by calculating the total power dissipated within the Si3200. This case is similar to the transistor power equations case, with the exception that the total power from all transistor devices is dissipated within the same package enclosure, and the total power result is placed in the PSUM RAM location. The power calculation is derived using the following equations: PQ1 ≅ (|VTIP| + 0.75 V) x IQ1 PQ2 ≅ (|VRING| + 0.75 V) x IQ2 PQ3 ≅ (|VBAT |+ 0.75 V) x IQ3 PQ4 ≅ (|VBAT| + 0.75 V) x IQ4 PQ5 ≅ (|VBAT| – |VRING|) x IQ5 PQ6 ≅ (|VBAT| – |VTIP|) x IQ6 PSUM = total dissipated power = PQ1 + PQ2 + PQ3 + PQ4 + PQ5 + PQ6 Note: The Si3200 THERM pin must be connected to the THERM a/b pin of the Si3220/Si3225 in order for the PTH56 = power threshold for Q5, Q6 = 1 W (0x7D8) PLPF12 = Q1/Q2 thermal LPF pole = 0x0012 (for SOT–89 package) PLPF34 = Q3/Q4 thermal LPF pole = 0x008C (for SOT–23 package) PLPF56 = Q5/Q6 thermal LPF pole = 0x000E (for SOT–223 package) In the case where the Si3200 is used, thermal filtering needs to be performed only on the total power reflected in the PSUM RAM location. When the filter output exceeds the total power threshold, an interrupt is issued. The PTH12 RAM location is used to preset the total power threshold for the Si3200, and the PLPF12 RAM location is used to preset the thermal low-pass filter pole. 38 Rev. 1.2 S i3220/25 When the THERM pin is connected from the Si3220 or Si3225 to the Si3200 (indicating the presence of an Si3200), the resolution of the PTH12 and PSUM RAM locations is modified from 498 µW/LSB to 1059.6 µW/ LSB. Additionally, the τTHERMAL value must be modified to accommodate the Si3200. For the Si3200, τTHERMAL is typically 0.7 s, assuming the exposed pad is connected to the recommended ground plane as stated in Table 1 on page 4. τTHERMAL decreases if the PCB layout does not provide sufficient thermal conduction. See “AN58: Si3220/Si3225 Programmer’s Guide” for details. Example calculations for PTH12 and PLPF12 in Si3200 mode are shown below: PTH12 = Si3200 power threshold = 1 W (0x3B0) PLPF12 = Si3200 thermal LPF pole = 2 (0x0010) 3.8.4. Automatic State Change Based on Power Alarm The Si3200’s thermally-enhanced SOIC-16 package offers an exposed pad that improves thermal dissipation out of the package when soldered to a topside PCB pad connected to inner power planes. Using appropriate layout practices, the Si3200 can provide thermal performance of 55 °C/W. The exposed path should be connected to a low-impedance ground plane via a topside PCB pad directly under the part. See package outlines for PCB pad dimensions. In addition, an opposite-side PCB pad with multiple vias connecting it to the topside pad directly under the exposed pad will further improve the overall thermal performance of the system. Refer to “AN55: Dual ProSLIC User Guide” for optimal thermal dissipation layout guidelines. The Dual ProSLIC chipset is designed with the ability to source long loop lengths in excess of 18 kft but can also accommodate short loop configurations. For example, the Si3220 can operate from one of two battery supplies depending on the operating state. When in the on-hook state, the on-hook loop feed is generated from the ringing battery supply, generally –70 V or more. Once the SLIC transitions to the off-hook state, a lower offhook battery supply (typically –24 V) supplies the required current to power the loop if the loop length is sufficiently short to accommodate the lower battery supply. This battery switching method allows the SLIC chipset to dissipate less power than when operating from a –70 V battery supply. See “3.9. Automatic Dual Battery Switching” for more details. In long loop applications, there is generally a single battery supply (e.g., –48 V) available for powering the loop in the off-hook state. When sourcing loop lengths similar to the maximum specified service distance (e.g., 18 kft.), most of the power is dissipated in the impedance of the line. SLICs used in long-loop applications must also be able to provide phone service to customers who are located much closer to the line card than the maximum loop length specified for the system. This situation may cause substantial power to be dissipated inside the SLIC chipset. A special power offload circuit is recommended for single-battery extended-loop applications. Refer to “AN91: Si3200 Power Off-load Circuit” for power offload circuit usage guidelines. If either of the following situations occurs, the device automatically transitions to the OPEN state: Any of the transistor power alarm thresholds is exceeded in the case of the discrete transistor circuit. The total power threshold is exceeded when using the Si3200. To provide optimal reliability, the device automatically transitions into the open state until the user changes the state manually, independent of whether or not the power alarm interrupt has been masked. The PQ1E–PQ6E bits of the IRQEN3 register enable the interrupts for each transistor power alarm, and the PQ1S to PQ6S bits of the IRQVEC3 register are set when a power alarm is triggered in the respective transistor. When using the Si3200, the PQ1E bit enables the power alarm interrupt, and the PQ1S bit is set when a Si3200 power alarm is triggered. 3.8.5. Power Dissipation Considerations The Dual ProSLIC devices rely on the Si3200 to power the line from the battery supply. The PCB layout and enclosure conditions should be designed to allow sufficient thermal dissipation out of the Si3200, and a programmable power alarm threshold ensures product safety under all operating conditions. See "3.8. Power Monitoring and Power Fault Detection" on page 36 for more details on power alarm considerations. Rev. 1.2 39 S i3220/25 Table 21. Register and RAM Locations Used for Power Monitoring and Power Fault Detection Parameter Register/ RAM Mnemonic Register/RAM Bits Measurement Range Resolution Si3200 Total Power Output Monitor Si3200 Power Alarm Interrupt Pending Si3200 Power Alarm Interrupt Enable Q1/Q2 Power Alarm Threshold (discrete) Q1/Q2 Power Alarm Threshold (Si3200) Q3/Q4 Power Alarm Threshold Q5/Q6 Power Alarm Threshold Q1/Q2 Thermal LPF Pole Q3/Q4 Thermal LPF Pole Q5/Q6 Thermal LPF Pole Q1–Q6 Power Alarm Interrupt Pending Q1–Q6 Power Alarm Interrupt Enable PSUM IRQVEC3 IRQEN3 PTH12 PTH34 PTH56 PLPF12 PLPF34 PLPF56 IRQVEC3 IRQEN3 PSUM[15:0] PQ1S PQ1E PTH12[15:0] PTH34[15:0] PTH56[15:0] PLPF12[15:3] PLPF34[15:3] PLPF56[15:3] PQ1S–PQ6S PQ1E–PQ6E 0 to 34.72 W N/A N/A 0 to 16.319 W 0 to 34.72 W 0 to 1.03 W 0 to 16.319 W 1059.6 µW N/A N/A 498 µW 1059.6 µW 31.4 µW 498 µW See “3.8.3. Power Filter and Alarms” See “3.8.3. Power Filter and Alarms” See “3.8.3. Power Filter and Alarms” N/A N/A N/A N/A 40 Rev. 1.2 S i3220/25 3.9. Automatic Dual Battery Switching The Dual ProSLIC chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. Two specific scenarios where this method may be required follow: Ringing to off-hook state transition (Si3220): During the on-hook operating state, the Dual ProSLIC chipset must operate from the ringing battery supply to provide the desired ringing signal when required. Once an off-hook condition is detected, the Dual ProSLIC chipset must transition to the lower battery supply (typically –24 V) to reduce power dissipation during the active state. The low current consumed by the Dual ProSLIC chipset during the on-hook state results in very little power dissipation while being powered from the ringing battery supply, which can have an amplitude as high as –100 V depending on the desired ringing amplitude. On-hook to off-hook state, short loop feed (Si3225): When sourcing both long and short loop lengths, the Dual ProSLIC chipset can automatically switch from the typical –48 V off-hook battery supply to a lower off-hook battery supply (e.g., –24 V) to reduce the total off-hook power dissipation. The Dual ProSLIC chipset continuously monitors the TIPRING voltage and selects the lowest battery voltage required to power the loop when transitioning from the on-hook to the off-hook state, thus assuring the lowest power dissipation. The BATSELa and BATSELb pins switch between the two battery voltages based on the operating state and the TIP-RING voltage. Figure 19 illustrates the chip connections required to implement an automatic dual battery switching scheme. When BATSEL is pulled LOW, the desired channel is powered from the VBLO supply. When BATSEL is pulled HIGH, the VBHI source supplies power to the desired channel. The BATSEL pins for both channels are controlled using the BATSEL bit of the RLYCON register and can be programmed to automatically switch to the lower battery supply (VBLO) when the off-hook TIP-RING voltage is low enough to allow proper operation from the lower supply. When using the Si3220, this mode should always be enabled to allow seamless switching between the ringing and off-hook states. The same switching scheme is used with the Si3225 to reduce power by switching to a lower off-hook battery when sourcing a short loop. Automatic battery selection should be disabled before using the manual battery select control bit (BSEL bit, Register 5—RLYCON, bit 5). Contact Silicon Laboratories for information on how to disable automatic battery selection. Two thresholds are provided to enable battery switching with hysteresis. The BATHTH RAM location specifies the threshold at which the Dual ProSLIC device switches from the low battery (VBLO) to the high battery (VBHI) due to an off-hook-to-on-hook transition. The BATLTH RAM location specifies the threshold at which the Si3220/Si3225 switches from VBHI to VBLO due to a transition from the on-hook or ringing state to the offhook state or because the overhead during active OffHook mode is sufficient to feed the subscriber loop using a lower battery voltage. The low-pass filter coefficient is calculated using the following equation and is entered into the BATLPF RAM location: BATLPF = [(2πf x 4096)/800] x 23 Where f = the desired cutoff frequency of the filter The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 Hz (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. Table 22 provides the register and RAM locations used for programming the battery switching functions. Rev. 1.2 41 S i3220/25 Table 22. Register and RAM Locations Used for Battery Switching Parameter Register/RAM Mnemonic Register/RAM Bits Programmable Range Resolution (LSB Size) High Battery Detect Threshold Low Battery Detect Threshold Ringing Battery Switch (Si3220 only) Battery Select Indicator Battery Switching LPF BATHTH BATLTH RLYCON RLYCON BATLPF BATHTH[14:7] BATLTH[14:7] GPO BSEL BATLPF[15:3] 0 to 160.173 V* 0 to 160.173 V* Toggle Toggle 0 to 4000h 628 mV (4.907 mV) 628 mV (4.907 mV) N/A N/A N/A *Note: Usable range for BATHTH and BATLTH is limited to the VBHI voltage. Si3220 Si3225 SVBAT Battery Sense Circuit Battery Control Logic BATSEL 40.2 kΩ 806 kΩ Si3200 Linefeed Circuitry BATSEL Battery Select Control VBLO VBATL VBAT VBHI VBATH Figure 19. External Battery Switching Using the Si3220/Si3225 42 Rev. 1.2 S i3220/25 When generating a high-voltage ringing amplitude using the Si3220, the power dissipated during the OHT state typically increases due to operating from the ringing battery supply in this mode. To reduce power, the Si3220/Si3200 chipset provides the ability to accommodate up to three separate battery supplies by implementing a secondary battery switch using a few low-cost external components as illustrated in Figure 22. The Si3220’s BATSEL pin is used to switch between the VBHI (typically –48 V) and VBLO (typically –24 V) rails using the switch internal to the Si3200. The Si3220’s GPO pin is used along with the external transistor circuit to switch the VBRING rail (the ringing voltage battery rail) onto the Si3200’s VBAT pin when ringing is enabled. The GPO signal is driven automatically by the ringing cadence provided that the RRAIL bit of the RLYCON register is set to 1 (signifying that a third battery rail is present). 806 kΩ SVBAT Si3220 BATSEL R101 Q1 CXT5401 R102 Q2 D1 IN4003 CXT5551 10 kΩ 402 kΩ R103 GPO 0.1 µF Si3200 VBAT R9 40.2 kΩ VBRING VBLO 0.1 µF VBATH VBATL BATSEL VBHI Figure 20. 3-Battery Switching with Si3220/Si3200 Table 23. Three-Battery Switching Components Component Value Comments D1 Q1 Q2 R101 R102 R103 200 V, 200 mA 100 V PNP 100 V NPN 1/10 W, ± 5% 10 kΩ,1/10 W, ± 5% 402 kΩ,1/10 W,± 1% 1N4003 or similar CXT5401 or similar CXT5551 or similar 2.4 kΩ for VDD=3.3 V 3.9 kΩ for VDD=5 V Rev. 1.2 43 S i3220/25 3.10. Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active, OnHook Transmission (forward or reverse polarity), and ringing linefeed states. The functional blocks required to implement a loop closure detector are shown in Figure 21, and the register set for detecting a loop closure event is provided in Table 24. The primary input to the system is the loop current sense value from the voltage/current/power monitoring circuitry and is reported in the ILOOP RAM address. The loop current (ILOOP) is computed by the input signal processor (ISP) using the equations shown below. Refer to Figure 18 on page 37 for the discrete bipolar transistor references) used in the equation below (Q1, Q2, Q5 and Q6 – note that the Si3200 has corresponding MOS transistors). The same ILOOP equation applies to the discrete bipolar linefeed as well as the Si3200 linefeed device. The following equation is conditioned by the CMH status bit in register LCRRTP and by the linefeed state as indicated by the LFS field in the LINEFEED register. I loop = I Q1 – I Q6 + I Q5 – I Q2 in TIP-OPEN or RING-OPEN I Q1 – I Q6 + I Q5 – I Q2 = --------------------------------------------------- in all other states 2 and LFS field (LINEFEED Register) states can be summarized as follows: IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3)) IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7)) The output of the ISP is the input to a programmable digital low-pass filter that removes unwanted ac signal components before threshold detection. The low-pass filter coefficient is calculated using the following equation and is entered into the LCRLPF RAM location: LCRLPF = [(2πf x 4096)/800] x 23 Where f = the desired cutoff frequency of the filter. The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. The output of the low-pass filter is compared to a programmable threshold, LCROFFHK. Hysteresis is enabled by programming a second threshold, LCRONHK, to detect the loop going to an open or onhook state. The threshold comparator output feeds a programmable debounce filter. The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LCRDBI. There is also a loop closure mask interval, LCRMASK, that is used to mask transients caused when an internal ringing burst (with no offset) ends in the presence of a high REN load. If the debounce interval has been satisfied, the LCR bit is set to indicate that a valid loop closure has occurred. If the CMHITH (RAM 36) threshold is exceeded, the CMH bit is 1, and IQ1 is forced to zero in the FORWARD-ACTIVE and TIP-OPEN states, or IQ2 is forced to zero in the REVERSE-ACTIVE and RINGOPEN states. The other currents in the equation are allowed to contribute normally to the ILOOP value. The conditioning due to the CMH bit (LCRRTP Register) IQ1 IQ2 IQ5 IQ6 Input Signal Processor ILOOP Digital LPF + – Loop Closure Mask Debounce Filter LCR LCRLPF CMH LFS Loop Closure Threshold LOOPE LCROFFHK LCRONHK LCRMASK LCRDBI Interrupt Logic LOOPS Figure 21. Loop Closure Detection Circuitry 44 Rev. 1.2 S i3220/25 Table 24. Register and RAM Locations Used for Loop Closure Detection Parameter Loop Closure Interrupt Pending Loop Closure Interrupt Enable Linefeed Shadow Loop Closure Detect Status Loop Closure Detect Debounce Interval Loop Current Sense Loop Closure Threshold (on-hook to off-hook) Loop Closure Threshold (off-hook to on-hook) Loop Closure Filter Coefficient Loop Closure Mask Interval Register/RAM Mnemonic IRQVEC2 IRQEN2 LINEFEED LCRRTP LCRDBI ILOOP LCROFFHK LCRONHK LCRLPF LCRMASK Register/RAM Bits LOOPS LOOPE LFS[2:0] LCR LCRDBI[15:0] ILOOP[15:0] LCROFFHK[15:0] LCRONHK[15:0] LCRLPF[15:3] LCRMASK[15:0] Programmable Range Yes/No Yes/No Monitor only Monitor only 0 to 40.96 s 50.54 to 101.09 mA 0 to 101.09 mA2 0 to 101.09 mA2 0 to 4000h 0 to 40.96s LSB Size N/A N/A N/A N/A 1.25 ms 3.097 µA 3.097 µA 3.097 µA N/A 1.25 ms Effective Resolution N/A N/A N/A N/A 1.25 ms 500 µA1 396.4 µA 396.4 µA N/A 1.25 ms Notes: 1. The effective ILOOP resolution is approximately 500 µA. 2. The usable range for LCRONHK and LCROFFHK is limited to 61 mA. Entering a value > 61 mA will disable threshold detection. 3.11. Ground Key Detection Ground key detection detects an alerting signal from the terminal equipment during the tip open or ring open linefeed states. The functional blocks required to implement a ground key detector are shown in Figure 22 on page 47, and the register set for detecting a ground key event is provided in Table 27 on page 48. The primary input to the system is the longitudinal current sense value provided by the voltage/current/ power monitoring circuitry and reported in the ILONG RAM address. The ILONG value is produced in the ISP provided the LFS bits in the linefeed register indicate the device is in the tip open or ring open state. The longitudinal current (ILONG) is computed as shown in the following equation. Refer to Figure 18 on page 37 for the transistor references used in the equation (Q1, Q2, Q5, and Q6—note that the Si3200 has corresponding MOS transistors). The same ILONG equation applies to the discrete bipolar linefeed as well as the Si3200 linefeed device. I Q1 – I Q6 – I Q5 + I Q2 I LONG = --------------------------------------------------2 The output of the ISP (ILONG) is the input to a programmable, digital low-pass filter, which removes unwanted ac signal components before threshold detection. The low-pass filter coefficient is calculated using the following equation and is entered into the LONGLPF RAM location: ( 2 π f × 4096 ) 3 LONGLPF = -------------------------------- × 2 800 Where f = the desired cutoff frequency of the filter. The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. The output of the low-pass filter is compared to the programmable threshold, LONGHITH. Hysteresis is enabled by programming a second threshold, LONGLOTH, to detect when the ground key is released. The threshold comparator output feeds a programmable debounce filter. Rev. 1.2 45 S i3220/25 The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the LONGHI bit is set to indicate that a valid ground key event has occurred. When the Si3220/25 detects a ground key event, the linefeed automatically transitions from the TIP-OPEN (or RING-OPEN) state to the FORWARD-ACTIVE (or REVERSE-ACTIVE) state. However, this automatic state transition is triggered by the LCR bit becoming active (i.e., =1), and not by the LONGHI bit. While ILONG is used to generate the LONGHI status bit, a transition from TIP-OPEN to the FORWARD-ACTIVE state (or from the RING-OPEN to the REVERSEACTIVE state) occurs when the RING terminal (or TIP terminal) is grounded and is based on the LCR bit and implicitly on exceeding the LCROFFHK threshold. As an example of ground key detection, suppose that the Si3220/25 has been programmed with the current values shown in Table 25. Table 25. Settings for Ground Key Example ILIM LCROFFHK LCRONHK LONGHITH LONGLOTH 21 mA 14 mA 10 mA 7 mA 5 mA With the settings of Table 25, the behavior of ILOOP, ILONG, LCR, LONGHI, and CMHIGH is as shown in Table 26. The entries under “Loop State” indicate the condition of the loop, as determined by the equipment terminating the loop. The entries under “LINEFEED Setting” indicate the state initially selected by the host CPU (e.g., TIP-OPEN) and the automatic transition to the FORWARD-ACTIVE state due to a ground key event (when RING is connected to GND). The transition from state #2 to state #3 in Table 26 is the automatic transition from TIP-OPEN to FWD-ACTIVE in response to LCR = 1. 46 Rev. 1.2 S i3220/25 Table 26. State Transitions During Ground Key Detection # Loop State LINEFEED State ILOOP (mA) ILONG (mA) LCR LONGHI CMHIGH 1 2 3 4 5 LOOP OPEN RING-GND RING-GND LOOP CLOSURE LOOP OPEN LFS = 3 (TIP-OPEN) LFS = 3 (TIP-OPEN) LFS = 1 (FWD-ACTIVE) LFS = 1 (FWD-ACTIVE) LFS = 1 (FWD-ACTIVE) 0 22 22 21 0 0 –11 –11 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 IQ1 IQ2 IQ5 IQ6 LONGLPF LFS Ground Key Threshold LONGE LONGHITH LONGLOTH LONGDBI Interrupt Logic LONGS Input Signal Processor ILONG Digital LPF + – Debounce Filter LONGHI Figure 22. Ground Key Detection Circuitry Rev. 1.2 47 S i3220/25 Table 27. Register and RAM Locations Used for Ground Key Detection Parameter Register/ RAM Mnemonics Register/RAM Bits Programmable Range LSB Size Resolution Ground Key Interrupt Pending Ground Key Interrupt Enable Ground Key Linefeed Shadow Ground Key Detect Status Ground Key Detect Debounce Interval Longitudinal Current Sense Ground Key Threshold (enabled) Ground Key Threshold (released) Ground Key Filter Coefficient IRQVEC2 IRQEN2 LINEFEED LCRRTP LONGDBI ILONG LONGHITH LONGLOTH LONGLPF LONGS LONGE LFS[2:0] LONGHI LONGDBI[15:0] ILONG[15:0] LONGHITH[15:0] LONGLOTH[15:0] LONGLPF[15:3] Yes/No Yes/No Monitor only Monitor only 0 to 40.96 s Monitor only 0 to 101.09 mA* 0 to 101.09 mA* 0 to 4000h N/A N/A N/A N/A 1.25 ms N/A N/A N/A N/A 1.25 ms See Table 20 3.097 µA 3.097 µA N/A 396.4 µA 396.4 µA N/A *Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a value >16 mA will disable threshold detection. 48 Rev. 1.2 S i3220/25 3.12. Ringing Generation The Si3220-based Dual ProSLIC® chipset provides a balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and the RING lines using ringing waveforms that are 180° out of phase with each other. The resulting ringing signal seen across TIP-RING is twice the amplitude of the ringing waveform on either the TIP or the RING line, which allows the ringing circuitry to withstand half the total ringing amplitude seen across TIP-RING. VRING RING RLOOP ROUT + VRING RLOAD VTERM – Figure 24. Simplified Loop Circuit During Ringing The following equation can be used to determine the TIP-RING ringing amplitude required for a specific load and loop condition: R LOAD V TERM = V RING × -------------------------------------------------------------------( R LOAD + R LOOP + R OUT ) SLIC VTIP VOFF TIP where R LOOP = ( 0.09 Ω per foot for 26AWG wire ) GND VTIP V PK VCM R OUT = 320 Ω VOFF and 7000 Ω R LOAD = ------------------#REN VRING VBATH VOV Figure 23. Balanced Ringing An internal ringing scheme provides >40 Vrms into a 5 REN load at the terminal equipment using a userprovided ringing battery supply. The specific ringing supply voltage required depends on the desired ringing voltage. The ringing amplitude at the terminal equipment also depends on the loop impedance and the load impedance in REN. The simplified circuit in Figure 24 shows the relationship between loop impedance and load impedance. When ringing longer loop lengths, adding a dc offset voltage is necessary to reliably detect a ring trip condition (off-hook phone). Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases the power dissipation in the Si3200 and may require additional airflow or modified PCB layout to maintain acceptable operating temperatures in the line feed circuitry. The Dual ProSLIC chipset automatically applies and removes the ringing signal during VOCcrossing periods to reduce noise and crosstalk to adjacent lines. Table 28 provides a list of registers required for internal ringing generation Rev. 1.2 49 S i3220/25 Table 28. Register and RAM Locations Used for Ringing Generation Parameter Register/RAM Register/RAM Bits Mnemonic Programmable Range Resolution (LSB Size) Ringing Waveform Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Monitor Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) On-Hook Line Voltage Ringing Voltage Offset Ringing Frequency Ringing Amplitude External Ringing Generator Voltage Sense External Ringing Generator Current Sense Ringing Initial Phase Sinusoidal Trapezoid External Ringing Ringing Relay Driver Enable (Si3225 only) Ringing Overhead Voltage Ringing Speedup Timer RINGCON RINGCON RINGCON RINGCON RINGTALO/ RINGTAHI RINGTILO/ RINGTIHI LINEFEED VOC RINGOF RINGFRHI/ RINGFRLO RINGAMP VRNGNG IRNGNG RINGPHAS TRAP TAEN TIEN RINGEN RINGTA[15:0] RINGTI[15:0] LF[2:0] VOC[15:0] RINGOF[15:0] RINGFRHI[14:3]/ RINGFRLO[14:3] RINGAMP[15:0] VRNGNG[15:0] IRNGNG[15:0] RINGPHAS[15:0] Sinusoid/Trapezoid Enabled/Disabled Enabled/Disabled Enabled/Disabled 0 to 8.19 s 0 to 8.19 s 000 to 111 0 to 63.3 V 0 to 63.3 V 4 to 100 Hz 0 to 160.173 V 332.04 V 662.83 mA N/A N/A N/A N/A 125 µs 125 µs N/A 1.005 V (4.907 mV) 1.005 V (4.907 mV) 628 mV (4.907 mV) 1.302 V (10.172 mV) 2.6 mA (20.3 µA) N/A 0 to 1.024 s 0 to 662.83 mA RELAYCON VOVRING SPEEDUPR RDOE VOVRING[15:0] SPEEDUPR[15:0] Enabled/Disabled 0 to 63.3 V 0 to 40.96 s N/A 31.25 µs 2.6 mA (20.3 µA) N/A 1.005 V (4.907 mV) 1.25 ms 50 Rev. 1.2 S i3220/25 3.12.1. Internal Sinusoidal Ringing 3.12.2. Internal Trapezoidal Ringing A sinusoidal ringing waveform is generated by the onchip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated at a 1 kHz rate. The ringing generator is programmed via the RINGFREQ, RINGAMP, and RINGPHAS registers. The equations are as follows: 2πf coeff = cos ⎛ -------------------- ⎞ ⎝ 1000Hz⎠ RINGFREQ = coeff × 2 23 In addition to the traditional sinusoidal ringing waveform, the Dual ProSLIC can generate a trapezoidal ringing waveform similar to the one illustrated in Figure 26. The RINGFREQ, RINGAMP, and RINGPHAS RAM addresses are used for programming the ringing wave shape as follows: RINGPHAS = 4 x Period x 8000 RINGAMP = (Desired V/160.8 V) x (215) RINGFREQ = (2 x RINGAMP)/(tRISE x 8000) RINGFREQ is a value that is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. 3 1t RISE = -- T ⎛ 1 – ----------⎞ 2⎠ 4⎝ CF DesiredV PK 15 1 1 – coeff RINGAMP = -- ----------------------- × ( 2 ) × --------------------------------160.173V 4 1 + coeff RINGPHAS = 0 For example, to generate a 60 Vrms (87 VPK), 20 Hz ringing signal, the equations are as follows: 2 π 20 coeff = cos ⎛ -------------------- ⎞ = 0.9921 ⎝ 1000Hz⎠ RINGFREQ = 0.9921 × ( 2 ) = 8322461 = 0x7EFD9D 15 1 00789 85 RINGAMP = -- -------------------- × ( 2 ) × -------------------- = 273 = 0x111 4 1.99211 160.173 23 where 1T = Period = ------------f RING CF = desired crest factor So, for a 90 VPK, 20 Hz trapezoidal waveform with a crest factor of 1.3, the period is 0.05 s, and the rise time requirement is 0.015 s. RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640) RINGAMP = 90/160.8 x (215) = 18340 (0x47A5) RINGFREQ = (2 x RINGAMP)/(0.0153 x 8000) = 300 (0x012C) The time registers and interrupts described in the sinusoidal ring description also apply to the trapezoidal ring waveform: In addition to the variable frequency and amplitude, a selectable dc offset (VOFF), which can be added to the waveform, is included. The dc offset is defined in the RINGOF RAM location. As with the tone generators, the ringing generator has two timers which function as described above. They allow on/off cadence settings up to 8 s on/8 s off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. To initiate ringing, the user must program the RINGFREQ, RINGAMP, and RINGPHAS RAM addresses as well as the RINGTA and RINGTI registers and select the ringing waveshape and dc offset. After this is done, TAEN and TIEN bits are set as desired. The ringing state is invoked by a write to the linefeed register. At the expiration of RINGTA, the Dual ProSLIC® turns off the ringing waveform and goes to the on-hook transmission state. At the expiration of RINGTI, ringing is initiated again. This process continues as long as the two timers are enabled and the linefeed register remains in the ringing state. 3.13. Internal Unbalanced Ringing The Si3220 also provides the ability to generate a traditional battery-backed unbalanced ringing waveform for ringing terminating devices that require a high dc content or for use in ground-start systems that cannot tolerate a ringing waveform on both the TIP and RING leads. The unbalanced ringing scheme applies the ringing signal to the RING lead; the TIP lead remains at the programmed VCM voltage that is very close to ground. A programmable dc offset can be preset to provide dc current for ring trip detection. Figure 25 illustrates the internal unbalanced ringing waveform. Rev. 1.2 51 S i3220/25 3.14. Ringing Coefficients VRING RING Si3220 DC Offset TIP The ringing coefficients are calculated in decimals for sinusoidal and trapezoidal waveforms. The RINGPHAS and RINGAMP hex values are decimal to hex conversions in 16-bit 2’s complement representations for their respective RAM locations. To obtain sinusoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to a 24-bit 2’s complement value. The lower 12 bits are placed in RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are cleared to 0. The upper 12 bits are set in a similar manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the sign bit, and RINGFRHI bits 2:0 are cleared to 0. For example, the register values RINGFREQ = 0x7EFD9D are as follows: RINGFRHI = 0x3F78 RINGFRLO = 0x6CE8 To obtain trapezoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to an 8-bit, 2’s complement value. This value is loaded into RINGFRHI. RINGFRLO is not used. for GND VTIP DC Offset VCM VOFF -80V VBATR VRING V OVRING Figure 25. Internal Unbalanced Ringing To enable unbalanced ringing, set the RINGUNB bit of the RINGCON register. As with internal balanced ringing, the unbalanced ringing waveform is generated by using one of the two on-chip tone generators provided in the Si3220. The tone generator used to generate ringing tones is a two-pole resonator with programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate. The ringing generator is programmed via the RINGAMP, RINGFREQ, and RINGPHAS registers. The RINGOF register is used in to set the dc offset position around which the RING lead will oscillate. Unbalanced ringing is centered at –80 V instead of VBAT / 2. Use the ring offset register (RINGOF, indirect Register 56) to position the dc offset as desired. The dc offset is set at a dc point equal to VCM – (–80 V + VOFF), where VOFF is the value that is input into the RINGOF RAM location. Positive VOFF values will cause the dc offset point to move closer to ground (lower dc offset), and negative VOFF values will have the opposite effect. The dc offset can be set to any value; however, the ringing signal will be clipped digitally if the dc offset is set to a value that is less than half the ringing amplitude. In general, the following equation must hold true to ensure the battery voltage is sufficient to provide the desired ringing amplitude: |VBATR| > |VRING,PK + (–80 V + VOFF) + VOVRING| It is possible to create reverse polarity unbalanced ringing waveforms (the TIP lead oscillates while the RING lead stays constant) by setting the UNBPOLR bit of the RINGCON register. In this mode, the polarity of VOFF must also be reversed (in normal ringing polarity VOFF is subtracted from –80 V, and in reverse polarity, ringing VOFF is added to –80 V). VTIP-RING VOFF T = 1/freq tRISE time Figure 26. Trapezoidal Ringing Waveform 3.14.1. Ringing DC Offset Voltage A dc offset voltage can be added to the Si3220’s ac ringing waveform by programming the RINGOF RAM location to the appropriate setting. The value of RINGOF is calculated as follows: V OFF 15 RINGOF = -------------- × 2 160.8 52 Rev. 1.2 S i3220/25 3.14.2. External Unbalanced Ringing The Si3225 supports centralized, battery-backed unbalanced ringing schemes by providing a ringing relay driver as well as inputs from an external ring trip circuit. Using this scheme, line-card designers can use the Dual ProSLIC chipset in existing system architectures with minimal system changes. 3.14.3. Linefeed Overhead Voltage Considerations During Ringing The system design is flexible to address varying loop lengths of different applications. An ac ring trip detection scheme cannot reliably detect an off-hook condition when sourcing longer loop lengths, as the 20 Hz ac impedance of an off-hook long loop is indistinguishable from a heavily-loaded (5 REN) short loop in the on-hook state. Therefore, a dc ring trip detection scheme is required when sourcing longer loop lengths. The Si3220 can implement either an ac or dc-based ring trip detection scheme depending on the application. The Si3225 allows external dc ring trip detection when using a battery-backed external ringing generator by monitoring the ringing feed path through two sensing inputs on each channel. By monitoring this path, the Dual ProSLIC detects a dc current flowing in the loop once the end equipment has gone off-hook. Table 29 provides recommended register and RAM settings for various applications, and Table 30 lists the register and RAM addresses that must be written or monitored to correctly detect a ring trip condition. The ringing mode output impedance allows ringing operation without overhead voltage modification (VOVR = 0). If an offset of the ringing signal from the ring lead is desired, VOVR can be used for this purpose. 3.14.4. Ringing Power Considerations The total power consumption of the Si3220/Si3200 chipset using internal ringing generation is dependent on the VDD supply voltage, desired ringing amplitude, total loop impedance, and ac load impedance (number of REN). The following equations can be used to approximate the total current required for each channel during ringing mode: V RING,PK 2 -I DD,AVE = ---------------------- × -- + I DD,OH Z LOOP π V RING,PK 2 -I BAT,AVE = ---------------------- × -Z LOOP π where: V RING,PK = V RING,RMS × 2 Z LOOP = R LOOP + R LOAD + R OUT RLOAD = 7000/REN (for North America) RLOOP = loop impedance ROUT = ProSLIC output impedance = 320 Ω IDD,OH = IDD overhead current = 22 mA for VDD = 3.3 V = 26 mA for VDD = 5 V 3.15. Ring Trip Detection A ring trip event signals that the terminal equipment has transitioned to an off-hook state after ringing has commenced, ensuring that the ringing signal is removed before normal speech begins. The Dual ProSLIC is designed to implement either an ac or dc-based internal ring trip detection scheme or a combination of both schemes. Figure 27 illustrates the internal functional blocks that correctly detect and process a ring trip event. The primary input to the system is the loop current sense (ILOOP) value provided by the loop monitoring circuitry and reported in the ILOOP RAM location register. The ILOOP RAM location value is processed by the ISP block when the LFS bits in the linefeed register indicate the device is in the ringing state. The output of the ISP then feeds into a pair of programmable, digital low-pass filters, one for the ac ring trip detection path and one for the dc path. The ac path also includes a full-wave rectifier block prior to the LPF block. The outputs of each low-pass filter block are then passed on to a programmable ring trip threshold (RTACTH for ac detection and RTDCTH for dc detection). Each threshold block output is then fed to a programmable debounce filter to ensure a valid ring trip event. The output of each debounce filter remains constant unless the input remains in the opposite state for the entire period of time set using the ac and dc ring trip debounce interval registers, RTACDB and RTDCDB. The outputs of both debounce filter blocks are then ORed together. If either the ac or the dc ring trip circuits indicate that a valid ring trip event has occurred, the RTP bit is set. Either the ac or dc ring trip detection circuits are disabled by setting the respective ring trip threshold sufficiently high so that it does not trip under any condition. A ring trip interrupt is also generated if the RTRIPE bit is enabled. Rev. 1.2 53 S i3220/25 3.15.1. Ringtrip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that will monitor the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter a sufficient amount of time (RTCOUNT x 1.25 ms/LSB) for the mode to switch to On-hook Transmission or Active. The mode that is being exited to is governed by whether the command to exit ringing is a ringing active timer expiration (on-hook transmission) or ringtrip/manual RTACTH mode change (active mode). The ringtrip timeout counter ensures ringing is exited within its time setting (RTCOUNT x 1.25 ms/LSB, typically 200 ms). 3.15.2. Ringtrip Debounce Interval The ac and dc ring trip debounce intervals can be calculated based on the following equations: RTACDB = tdebounce (1600/RTPER) RTDCDB = tdebounce (1600/RTPER) LFS AC Ring Trip Threshold _ ILOOP Input Signal Processor Full Wave Rectifier Digital LPF + Debounce Filter_AC RTP RTPER RTACDB Interrupt Logic RTRIPS Digital LPF + _ DC Ring Trip Threshold RTRIPE Debounce Filter_DC RTDCDB RTDCTH Figure 27. Ring Trip Detect Processing Circuitry 54 Rev. 1.2 S i3220/25 Table 29. Recommended Values for Ring Trip Registers and RAM Addresses1 Ringing Method Ringing Frequency 16–32 Hz Internal (Si3220) DC Offset Added? Yes No Yes 33–60 Hz No External (Si3225) 16–32 Hz 33–60 Hz Yes Yes RTPER RTACTH RTDCTH RTACDB/ RTDCDB 800/fRING 800/fRING 2(800/ fRING) 2(800/ fRING) 800/fRING 2(800/ fRING) 221 x RTPER 1.59 x VRING,PK x RTPER 221 x RTPER 1.59 x VRING,PK x RTPER 32767 32767 0.577(RTPER x VOFF) 32767 0.577(RTPER x VOFF) 32767 0.067 x RTPER x VOFF 0.067 x RTPER x VOFF See Note 2 Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations. Table 30. Register and RAM Locations Used for Ring Trip Detection Parameter Register/RAM Mnemonic Register/RAM Bits Programmable Range Resolution Ring Trip Interrupt Pending Ring Trip Interrupt Enable AC Ring Trip Threshold DC Ring Trip Threshold Ring Trip Sample Period Linefeed Shadow (monitor only) Ring Trip Detect Status (monitor only) AC Ring Trip Detect Debounce Interval DC Ring Trip Detect Debounce Interval Loop Current Sense (monitor only) 3.15.3. Loop Closure Mask IRQVEC2 IRQEN2 RTACTH RTDCTA RTPER LINEFEED LCRRTP RTACDB RTDCDB ILOOP RTRIPS RTRIPE RTACTH[15:0] RTDCTH[15:0] RTPER[15:0] LFS[2:0] RTP RTACDB[15:0] RTDCDB[15:0] ILOOP[15:0] Yes/No Enabled/Disabled See Table 29 See Table 29 See Table 29 N/A N/A 0 to 40.96 s 0 to 40.96 s 0 to 101.09 mA N/A N/A N/A N/A 1.25 ms 1.25 ms See Table 20 3.15.4. Si3220 Ring Trip Detection The Dual ProSLIC implements a loop closure mask to ensure mode change between ringing and active or onhook transmission without causing an erroneous loop closure detection. The loop closure mask register, LCRMASK, should be set such that loop closure detection is ignored for the time (LCRMASK 1.25 ms/ LSB). The programmed time is set to mask detection of transitional currents that occur when exiting the ringing mode while driving a reactive load (i.e., 5 REN). A typical setting is 80 ms (LCRMASK = 0x40). The Si3220 provides the ability to process a ring trip event using an ac-based detection scheme. Using this scheme eliminates the need to add dc offset to the ringing signal, which reduces the total power dissipation during the ringing state and maximizes the available ringing amplitude. This scheme is valid for shorter loop lengths only since it cannot reliably detect a ring trip event if the off-hook line impedance overlaps the onhook impedance at 20 Hz. Rev. 1.2 55 S i3220/25 The Si3220 can also add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state. Although adding dc offset reduces the maximum available ringing amplitude (using the same ringing supply), this method is required to reliably detect a valid ring trip event when sourcing longer loop lengths. The dc offset can be programmed from 0 to 64.32 V in the RINGOF RAM address as required to produce adequate dc loop current in the offhook state. Depending on the loop length and the ring trip method, the ac or dc ring trip detection circuits are disabled by setting their respective ring trip thresholds, RTACTH or RTDCTH, sufficiently high so that they do not trip under any condition. 3.15.5. Si3225 Ring Trip Detection VDD Si3220/ Si3225 3 V/5 V Relay (polarized or non-polarized) Relay Driver Logic VCC RRDa/b TRD1a/b TRD2a/b GDD The Si3225 implements an external ring trip detection scheme when using a standard battery-backed external ringing generator. In this application, the centralized ringing generator produces an unbalanced ringing signal that is distributed to individual TIP/RING pairs. A per-channel ringing relay is required to disconnect the Si3225 from the TIP/RING pair and apply the ringing signal. By monitoring the ringing feed path across a ring feed sense resistor (RRING in Figure 31 on page 59) in series with the ringing source, the Si3225 can detect the dc current path created when the hook switch inside the terminal equipment closes. The internal ring trip detection circuitry is identical to that illustrated in Figure 27. Figure 31 illustrates the typical external ring trip circuitry required for the Si3225. Because of the long loop nature of these applications, a dc ring trip detection scheme is typically used. The user can disable the ac ring trip detection circuitry by setting the RTACTH threshold sufficiently high so it does not trip under any condition. Figure 28. Dual ProSLIC Internal Relay Drive Circuitry The internal driver logic and drive circuitry are powered by the same VDD supply as the chip’s main VDD supply (VDD1–VDD4 pins). When operating external relays from a VCC supply equal to the chip’s VDD supply, an internal diode network provides protection against overvoltage conditions from flyback spikes when the relay is opened. Either 3 V or 5 V relays can be used in the configuration shown in Figure 28, and either polarized or non-polarized relays are acceptable if the VCC and VDD supplies are identical. The input impedance, RIN, of the relay driver pins is a constant 11 Ω while sinking less than the maximum rated 85 mA into the pin. If the operating voltage of the relay (VCC) is higher than the Dual ProSLIC VDD supply voltage, an external drive circuit is required to eliminate leakage from VCC to VDD through the internal protection diode. In this configuration, a polarized relay will provide optimal overvoltage protection and minimal external components. Figure 29 illustrates the required external drive circuit, and Table 31 provides recommended values for RDRV for typical relay characteristics and VCC supplies. The output impedance, ROUT, of the relay driver pins is a constant 63 Ω while sourcing less than the maximum rated 28 mA out of the pin. 3.16. Relay Driver Considerations The Dual ProSLIC devices include up to three dedicated relay drivers to drive external ringing and/or test relays. Test relay drivers TRD1a, TRD1b, TRD2a, and TRD2b are provided in all product versions, and ringing relay drivers RRDa and RRDb are included for the Si3225 only. In most applications, the relay can be driven directly from the Dual ProSLIC with no external relay drive circuitry required. Figure 28 illustrates the internal relay driver circuitry using a 3 V or 5 V relay. 56 Rev. 1.2 S i3220/25 VDD Si3220/ Si3225 VCC Polarized relay IDRV Q1 RDRV RRDa/b TRD1a/b TRD2a/b Figure 29. Driving Relays with VCC > VDD The maximum allowable RDRV value can be calculated with the following equation: ( V DD,MIN – 0.6 V ) ( R RELAY ) ( β Q1,MIN ) MaxR DRV = ------------------------------------------------------------------------------------------------ – R SOURCE V CC,MAX – 0.3 V Where βQ1,MIN ~ 30 for a 2N2222. Table 31. Recommended RDRV Values ProSLIC VDD Relay VCC Relay RCOIL Maximum RDRV Recommended 5% Value 3.3 V ±5% 5 V ±5% 3.3 V ±5% 3.3 V ±5% 3.3 V ±5% 3.3 V ±5% 5 V ±5% 5 V ±5% 5 V ±5% 3.3 V ±5% 5 V ±5% 5 V ±5% 12 V ±10% 24 V ±10% 48 V ±10% 12 V ±10% 24 V ±10% 48 V ±10% 64 Ω 178 Ω 178 Ω 1028 Ω 2880 Ω 7680 Ω 1028 Ω 2880 Ω 7680 Ω Not Required Not Required 2718 Ω 6037 Ω 8364 Ω 11092 Ω 9910 Ω 13727 Ω 18202 Ω — — 2.7 kΩ 5.6 kΩ 8.2 kΩ 11 kΩ 9.1 kΩ 13 kΩ 18 kΩ Rev. 1.2 57 58 D 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 S i3220/25 IRINGXSCAL ZERDELAY COUNTER0 0 1 2 COUNTER1 RINGEN Rev. 1.2 On Off Ringing LFSDELAY RRD On Off LF Active LFSDELAY LFS Ringing OHT Ringing Active Figure 30. Timing Characteristics for Ringing Relay Control S i3220/25 VOFF VRING _ 510 Ω + 806 kΩ BLkRING RTRP 806 kΩ Relay Phone RING Si3225 RRD Si3200 TIP Protection Hook Switch VDD Figure 31. Si3225 External Ring Trip Circuitry 3.16.1. Ringing Relay Activation During Zero Crossings timing sequence for a typical ringing relay control application. During a typical ringing sequence, the Si3225 monitors both the ringing relay current (IRNGNG) and the RINGEN bit of the RINGCON register. The RINGEN bit toggles because of pre-programmed ringing cadence or a change in operating state. COUNTER0 and COUNTER1 are restarted at each alternating zero current crossing event, and the delay period, ZERDELAY, equal to the ringing frequency period less the desired advance firing time, D, is entered by the user. If either counter reaches the same value as ZERDELAY, the relay control signal is enabled when the RINGEN bit transition has already occurred. During typical ringing bursts, the LFS bits of the linefeed register toggle between the RINGING and OHT states based on the pre-programmed ringing cadence. The transition from OHT to RINGING is synchronized with the RRD state transitions, so the ringing burst starts immediately. The transition from RINGING to OHT is gated by a user-programmed delay period, LFSDELAY, which ensures the ringing burst has ceased before going to the OHT state or to the ACTIVE state in response to a linefeed state change. The Si3225 is for applications that use a centralized ringing generator and a per-channel ringing relay to connect the ringing signal to the TIP/RING pair. The Si3225 has one relay driver output per channel (RRDa and RRDb) that can drive a mechanical or solid-state DPDT relay. To reduce impulse noise that can couple into adjacent lines, the relay should be closed when there is zero voltage across the relay contacts and opened during periods when there is zero current through the contacts. 3.16.2. Closing the Relay at Zero Voltage Internal voltage monitoring circuitry closes the relay at zero voltage with respect to the line voltage. By observing the phase of the ringing signal and constantly monitoring the open-circuit T-R voltage, VOC, the Si3225 can detect the next time when there is zero voltage across the relay contacts. 3.16.3. Opening the Relay at Zero Current Opening the ringing relay at zero current also is accomplished using the internal monitoring circuitry and prevents arcing from excess current flow when the relay contacts are opened. The current flowing through the ringing relay is continuously monitored in the IRNGNG RAM address, and two internal counters (COUNTER0 and COUNTER1) detect time elapsed since the last two zero current crossings based on the ringing period and predict when the next zero crossing occurs. The ringing relay current and internal counters are both updated at an 8 kHz rate. To account for the mechanical delay of the relay, a programmable advance firing timer allows the user to initiate relay opening up to 10 ms prior to the zero current crossing event. Figure 30 illustrates the 3.17. Polarity Reversal The Dual ProSLIC devices support polarity reversal for message-waiting functionality and various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. A wink function is provided for special equipment that responds to a smooth ramp to VOC = 0 V. Table 32 illustrates the register bits required to program the polarity reversal modes. Rev. 1.2 59 S i3220/25 Setting the linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. For example, to transition from Forward Active mode to Reverse Active mode changes LF[2:0] from 001 to 101. Polarity reversal is accommodated in the OHT and ground start modes. The POLREV bit is a read-only bit that reflects if the device is in polarity reversal mode. For smooth polarity reversal, set the PREN bit to 1 and the RAMP bit to 0 or 1 depending on the desired ramp rate (see Table 32). Polarity reversal is then accomplished by toggling the linefeed register from forward to reverse modes as desired. A wink function slowly ramps down the TIP-RING voltage (VOC) to 1 followed by a return to the original VOC value (set in the VOC RAM location). This scheme lights a message-waiting lamp in certain handsets. No change to the linefeed register is necessary to enable this function. Instead, the user sets the VOCZERO bit to 1 so that the TIP-RING voltage collapses to 0 V at the rate programmed by the RAMP bit. Setting the VOCZERO bit back to 0 returns the TIP-RING voltage to its normal setting. With a software timer, the user can automate the cadence of the wink function. Figure 32 illustrates the wink function. Table 32. Register and RAM Locations used for Polarity Reversal Parameter Programmable Range Register/RAM Register/RAM Bits Mnemonic Linefeed Polarity Reversal Status Wink Function (Smooth transition to Voc=0V) Smooth Polarity Reversal Enable Smooth Polarity Reversal Ramp Rate See Table 17 Read only 1 = Ramp to 0 V 0 = Return to previous VOC 0 = Disabled 1 = Enabled 0 = 1 V/125 µs 1 = 2 V/125 µs LF[2:0] POLREV VOCZERO PREN RAMP LINEFEED POLREV POLREV POLREV POLREV Set VOCZERO bit to 1 0 0 10 20 30 Set VOCZERO bit to 0 40 50 60 70 80 Vcm Time (ms) VTIP -10 -20 2 V/125 µs slope set by RAMP bit -30 Voc -40 -50 Vov V RING V BAT V TIP/RING ( V) Figure 32. Wink Function with Programmable Ramp Rate 60 Rev. 1.2 S i3220/25 3.18. Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop thus minimizing the receive path signal reflected back onto the transmit path. The Dual ProSLIC chipset provides on-chip, digitally-programmable, two-wire impedance synthesis to meet return loss requirements against virtually any global two-wire impedance requirement. Real and complex two-wire impedances are realized by a programmable digital filter block. (See ZA and ZD blocks in Figure 11 on page 24.) Where: ZT is the termination impedance presented to the TIP/RING pair RPROT is the series resistance caused by protection devices RS is the series portion of the synthesized impedance RP||CP is the parallel portion of the synthesized impedance The user must enter the value of RPROT into the software so the equalizer block can compensate for additional series impedance. (See Figure 11 on page 24.) Figure 34 illustrates the simplified two-wire impedance circuit including external protection resistors, where ZL is the actual line impedance for the specific geographical region. The Dual ProSLIC devices can accomodate up to 50 Ω of series protection impedance per leg. The ac impedance generation scheme is comprised of analog and DSP-based coefficients. To turn off the analog coefficients (RS, ZP, and ZZ bits in the ZRS and ZZ registers), the user can simply set the ZSDIS bit of the ZZ register to 0. To turn off the DSP coefficients (ZA1H1 through ZB3LO registers), each register must be loaded with 0x00. RP RS CP Figure 33. Two-Wire Impedance Synthesis Configuration Table 33. Two-Wire Impedance Synthesis Limitations Desired Configuration Programmable Limits RS only RS + CP RS + RP||CP 100–1000 Ω RS x CP > 0.5 ms RS/(RS + RP) > 0.1 TIP RPROT Si3200 ZL ZT Dual ProSLIC The two-wire impedance is programmed by loading the desired real or complex impedance value into the Si322X coefficient generator software in the format RS + RP||CP, as shown in Figure 33. The software calculates the appropriate hex coefficients and loads them into the appropriate control registers (registers 33–52). The twowire impedance can be set to any real or complex value within the boundaries set in Table 33. The actual impedance presented to the subscriber loop varies with series impedance from protection devices placed between the Dual ProSLIC chipset outputs and the TIP/ RING pair according to the following equation: Z T = 2R PROT + ( R S + R P || C P ) RING RPROT Figure 34. Two-Wire Impedance Simplified Circuit 3.18.1. Impedance Synthesis Initialization and Control The Si322x utilizes a digital IIR filter to implement SLIC impedance synthesis. Under normal operation, the Si322x state machine controls the clocks to this filter automatically such that the filter clocks are turned OFF during those times when the filter is not required. During pulse dialing, for example, the clocks are shut OFF during the break period and turned back ON during the make period. When the clocks are shut OFF, the IIR filter holds the last sample values in its storage elements. When the Rev. 1.2 61 S i3220/25 clocks are turned back ON, the IIR filter experiences a discontinuity in the input signal. By writing power-down register 124 (decimal) with 0xC0, the clocks to the digital synthesis filter are forced to be continuously ON at all times, and the TX audio path is also kept ON so that the IIR filter continues to run and receive continuous signal samples from the TX channel no matter what state the SLIC is in. Register 124 is a protected register, which must be unlocked, then written, then locked again to prevent unintended modification of its contents. The sequence to write register 124 is as follows: 1. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal) \\unlock protected registers 2. 0xC0 -> Reg.124 (decimal) \\force HSP (high-speed processing) clocks to ON 3. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal) \\lock protected registers To ensure proper device operation, the digital impedance synthesis coefficients (registers 33-52, decimal) should be programmed while the LINEFEED state is set to zero (OPEN) and register 124 is set to 0x80. After loading the digital impedance synthesis coefficients, register 124 should be set to 0xC0. The following sequence should always be used to program the digital impedance synthesis coefficients: Channel A 1. 0x2, 0x6, 0xC, 0x0 → Reg. 87 (decimal) ;unlock protected registers 2. 0x80 → Reg. 124 (decimal) ;disable clock Channel B 3. 0x80 → Reg. 124 (decimal) ;disable clock Both channels 4. Write registers 331–52 with the digital impedance synthesis coefficients Channel A 5. 0xC0 → Reg. 124 (decimal) ;enable clock Channel B 6. 0xC0 → Reg. 124 (decimal) ;enable clock 7. 0x2, 0x6, 0xC, 0x0 → Reg. 87 (decimal) ;lock protected registers During device initialization, steps 1, 5, 6, and 7 should always be performed even if the digital impedance synthesis coefficients are not programmed. 3.19. Transhybrid Balance Filter The Dual ProSLIC devices provide a transhybrid balance function via a digitally-programmable balance filter block. (See “H” block in Figure 11.) The Dual ProSLIC devices implement an 8-tap FIR filter and a second-order IIR filter, both running at a 16 kHz sample rate. These two filters combine to form a digital replica of the reflected signal (echo) from the transmit path inputs. The user can filter settings on a per-line basis by loading the desired impedance cancellation coefficients into the appropriate registers. The Si322x Coefficient Generator software interface is provided for calculating the appropriate coefficients for the FIR and IIR filter blocks. The transhybrid balance filters can be disabled to implement loopback diagnostic modes. To disable the transhybrid balance filter (zero cancellation), set the HYBDIS bit in the DIGCON register to 1. Note: The user must enter values into each register location to ensure correct operation when the hybrid balance block is enabled. 3.20. Tone Generators Dual ProSLIC devices have two digital tone generators that allow a wide variety of single or dual tone frequency and amplitude combinations that spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. The tones are sent to the receive or transmit paths. (See Figure 11 on page 24.) 3.20.1. Tone Generator Architecture A simplified diagram of the tone generator architecture is shown in Figure 35. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected for flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. The register set for tone generation is summarized in Table 34. 62 Rev. 1.2 S i3220/25 8 kHz Clock OSCnEN ZEROENn Zero Cross Zero Cross Logic ENSYNCn Enable 8 kHz Clock to TX Path 16-Bit Modulo Counter OSCnTA Expire OSCnTI Expire Load Logic Two-Pole Resonant Register Oscillator Load Signal Routing to RX Path OSCnTA OSCnTAEN OSCnTI OSCnTIEN INT Logic INT Logic OSnTIS REL* OSCnFREQ ROUTn OSCnAMP OSnTIE OSnTAS OSnTAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively OSCnPHAS Figure 35. Tone Generator Diagram 3.20.2. Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonant oscillator circuit with a programmable frequency and amplitude, which are programmed via RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS, OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample rate for the two oscillators is 8000 Hz. The equations are as follows: coeffn = cos(2π fn/8000 Hz), where fn is the frequency to be generated; OSCnFREQ = coeffn x (214); 15 1 - -------------------OSC1AMP = -- 0.21556 × ( 2 – 1 ) × 0.5 = 1424 4 1.78434 = 0x590 OSC2FREQ = 0.49819 (214) = 8162 = 0x1FE2 1 15 - -------------------OSC2AMP = -- 0.50181 × ( 2 – 1 ) × 0.5 = 2370 4 1.49819 = 0x942 OSC2PHAS = 0 The preceding computed values are written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs. FSK frequency coefficients, FSKFREQ0/1 and FSKAMP0/1, are calculated from the oscillator equations and changing the sample rate from 8000 Hz to 24000 Hz. 3.20.3. Tone Generator Cadence Programming 15 1 1 – coeff Desired Vrms OSCnAMP = -- ----------------------- × ( 2 – 1 ) × --------------------------------------4 1 + coeff 1.11 Vrms where Desired Vrms is the amplitude to be generated; OSCnPHAS = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming we want to generate half-scale values (ignoring twist), the following values are calculated: 2 π 852 coeff 1 = cos ⎛ ---------------- ⎞ = 0.78434 ⎝ 8000 ⎠ OSC1FREQ = 0.78434 ( 2 ) = 12851 = 0x3233 14 OSC1PHAS = 0 coeff2 = cos (2π 1336 / 8000) = 0.49819 Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 µs steps. The active period time interval is set using OSC1TA for tone generator 1 and OSC2TA for tone generator 2. Rev. 1.2 63 S i3220/25 To enable automatic cadence for tone generator 1, define the OSC1TA and OSC1TI registers and set the OSC1TAEN and OSC1TIEN bits. This enables each of the timers to control the state of the oscillator enable bit, OSC1EN. The 16-bit counter counts until the active timer expires, at which time the 16-bit counter resets to zero and begins counting until the inactive timer expires. The cadence continues until the user clears the OSC1TA and OSC1TIEN control bits. Setting the ZEROEN1 bit implements the zero crossing detect feature. This ensures that each oscillator pulse ends without a dc component. The timing diagram in Figure 36 is an example of an output cadence that uses the zero crossing feature. One-shot oscillation is possible with OSC1EN and OSC1TAEN. Direct control over the cadence is achieved by setting the OSC1EN bit directly if OSC1TAEN and OSC1TIEN are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers. Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator because of resource sharing within the hardware. Table 34. Register and RAM Locations Used for Tone Generation Tone Generator 1 Parameter Register/RAM Mnemonics Register/RAM Bits Description/Range (LSB Size) Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 Initial Phase Coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control OSC1FREQ OSC1AMP OSC1PHAS O1TALO/O1TAHI O1TILO/O1TIHI OMODE, OCON OSC1FREQ[15:3] OSC1AMP[15:0] OSC1PHAS[15:0] OSC1TA[15:0] OSC1TI[15:0] FSKSSEN, OSC1FSK, ZEROEN1, ROUT1, ENSYNC1, OSC1TAEN, OSC1TIEN, OSC1EN Sets oscillator frequency Sets oscillator amplitude Sets initial phase (default = 0) 0 to 8.19 s (125 µs) 0 to 8.19 s (125 µs) Enables all Oscillator 1 parameters Oscillator 1 Interrupts IRQVEC1, IRQEN1 OS1TAS, OS1TIS, OS1TAE, OS1TIE Tone Generator 2 Location Register/RAM Address Interrupt enable/status Parameter Description/Range Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 Initial Phase Coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer Oscillator 2 Control OSC2FREQ OSC2AMP OSC2PHAS O2TALO/O2TAHI O2TILO/O2TIHI OMODE, OCON OSC2FREQ[15:3] OSC2AMP[15:0] OSC2PHAS[15:0] OSC2TA[15:0] OSC2TI[15:0] ZEROEN2, ROUT2, ENSYNC2, OSC2TAEN, OSC2TIEN, OSC2EN OS2TAS, OS2TIS, OS2TAE, OS2TIE Sets oscillator frequency Sets oscillator amplitude Sets initial phase (default = 0) 0 to 8.19 s (125 µs) 0 to 8.19 s (125 µs) Enables all Oscillator 2 parameters Interrupt enable/status Oscillator 2 Interrupts IRQVEC1, IRQEN1 64 Rev. 1.2 S i3220/25 OSC1EN 0,1 ... ..., OSC1TA 0,1 ... ..., OSC1TI 0,1 ... ..., OSC1TA 0,1 ... ... ... ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Channel Seizure Mark Data Packet Second Ring Burst Message Type Message Length Parameter 1 Parameter 2 Message Body Parameter n Checksum Message Header Parameter Type Data Length Data Content Figure 37. On-Hook Caller ID Transmission Sequence Rev. 1.2 65 S i3220/25 3.20.4. Tone Generator Interrupts requirements. The register and RAM locations for caller ID generation are listed in Table 36. Caller ID data is entered into the 8-bit FSKDAT register. The data byte is double buffered so that the Dual ProSLIC can generate an interrupt indicating the next data byte can be written when processing begins on the current data byte. The caller ID data can be transmitted in one of two modes controlled by the O1FSK8 register bit. When O1FSK8 = 0 (default case), the 8-bit caller ID data is transmitted with a start bit and stop bit to create a 10-bit data sequence. If O1FSK8 = 1, the caller ID data is transmitted as a raw 8-bit sequence with no start or stop bits. The value programmed into the OSC1TA register determines the bit rate, and the interrupt rate is equal to the bit rate divided by the data sequence length (8 or 10 bits). Both the active and inactive timers can generate an interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the OS1TAE and OS1TIE bits. Timer interrupts for tone generator 2 are OS2TAE and OS2TIE. A pending interrupt for each of the timers is determined by reading the OS1TAS, OS1TIS, OS2TAS, and OS2TIS bits in the IRQVEC1 register. 3.21. Caller ID Generation The Dual ProSLIC devices generate caller ID signals in compliance with various Bellcore and ITU specifications as described in Table 35 by providing continuous phase binary frequency shift keying (FSK) modulation. Oscillator 1 is required because it preserves phase continuity during frequency shifts whereas Oscillator 2 does not. Figure 37 illustrates a typical caller ID transmission sequence in accordance with Bellcore Parameter Table 35. FSK Modulation Requirements ITU-T V.23 Bellcore GR-30-CORE Mark Frequency (logic 1) Space Frequency (logic 0) Transmission Rate 1300 Hz 2100 Hz 1200 Hz 2200 Hz 1200 baud Table 36. Register and RAM Locations used for Caller ID Generation Parameter Register/RAM Mnemonic Register/RAM Bits Description/Range (LSB Size) FSK Start & Stop Bit Enable Oscillator 1 Active Timer FSK Data Byte FSK Frequency for Space FSK Frequency for Mark FSK Amplitude for Space FSK Amplitude for Mark FSK 0-1 Transition Freq, High FSK 0-1 Transition Freq, Low FSK 1-0 Transition Freq, High FSK 1-0 Transition Freq, Low OMODE O1TALO/O1TAHI FSKDAT FSKFREQ0 FSKFREQ1 FSKAMP0 FSKAMP1 FSK01HI FSK01LO FSK10HI FSK10LO O1FSK8 OSC1TA[15:0] FSKDAT[7:0] FSKFREQ0[15:3] FSKFREQ1[15:3] FSKAMP0[15:3] FSKAMP1[15:3] FSK01HI[15:3] FSK01LO[15:3] FSK10HI[15:3] FSK10LO[15:3] Enable/disable 0 to 2.73 s (41.66 µs)* Caller ID data Audio range Audio range *Note: Oscillator 1 active timer range and LSB stage valid only for FSK mode. 66 Rev. 1.2 S i3220/25 3.22. Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "3.20.1. Tone Generator Architecture" on page 62 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz. The equation is as follows: 2πf Coeff = cos ⎛ -------------------------⎞ ⎝ 64000 Hz⎠ PMFREQ = coeff × ( 2 14 – 1) Desired V PK 15 1 1 – coeff PMAMPL = -- ----------------------- × ( 2 – 1 ) × --------------------------------------FullScale V PK 4 1 + coeff where Full Scale VPK = 0.5 V. The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The ramp is controlled by the value in the PMRAMP RAM address, and the sinusoidal generator output is multiplied by this volume before it is sent to the pulse metering DAC. The volume value is incremented by the value in PMRAMP at an 8 kHz rate. The volume will ramp from 0 to 7FFF in increments of PMRAMP to allow the value of PMRAMP to set the slope of the ramp. The clip detector stops the ramp once the signal seen at the transmit path exceeds the amplitude threshold set by PMAMPTH, which provides an automatic gain control (AGC) function to prevent the audio signal from clipping. When the pulse metering signal is turned off, the volume ramps down to 0 by decrementing according to the value of PMRAMP. Figure 38 illustrates the functional blocks involved in pulse metering generation, and Table 37 presents the required register and RAM locations that must be set to generate pulse metering signals. Table 37. Register and RAM Locations Used for Pulse Metering Generation Parameter Register/RAM Mnemonic Register/RAM Bits Description/Range (LSB Size) Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering, Control Interrupt PMFREQ PMAMPL PMRAMP PMTALO/PMTAHI PMTILO/PMTIHI IRQVEC1, IRQEN1 PMFREQ[15:3] PMAMPL[15:0] PMRAMP[15:0] PULSETA[15:0] PULSETI[15:0] PULSTAE, PULSTIE, PULSTAS, PULSTIS PMAMPTH[15:0] ENSYNC TAEN TIEN PULSE1 Sets oscillator frequency Sets oscillator amplitude 0 to PMAMPL (full amplitude) 0 to 8.19 s (125 µs) 0 to 8.19 s (125 µs) Interrupt Status and control registers Pulse Metering AGC Amplitude Threshold PM Waveform Present PM Active Timer Enable PM Inactive Timer Enable Pulse Metering Enable PMAMPTH PMCON PMCON PMCON PMCON 0 to 500 mV Indicates signal present Enable/disable Enable/disable Enable/disable Rev. 1.2 67 S i3220/25 ADC Decimation Filter 12/16 kHz Bandpass Peak Detector – IBUF ZA + + PMAMPTH + DAC PMRAMP Pulse Metering DAC + x + ± Pulse Metering Oscillator Volume Clip Logic 7FFF or 0 8 kHz Figure 38. Pulse Metering Generation Block Diagram 3.23. DTMF Detection On-chip DTMF detection, also known as touch tone, is available in the Si3220 and Si3225. It is an in-band signaling system that replaces the pulsedial signaling standard. In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. The row and column tones and corresponding digits are shown in Table 38. DTMF detection is performed using a modified Goertzel algorithm to compute the DFT for each of the eight DTMF frequencies and their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the 8 DTMF fundamental tones are computed. The row results are sorted to determine the strongest row frequency, and the column frequencies are sorted as well. Upon completion of this process, checks are made to determine if the strongest row and column tones constitute a DTMF digit. The detection process occurs twice within the 45 ms minimum tone time. A digit must be detected on two consecutive tests after a pause to be recognized as a new digit. If all tests pass, an interrupt is generated, and the DTMF digit value is loaded into the DTMF register according to Table 38. If tones occur at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not overwritten by a new one. There is no buffering of the digit information. Table 38. DTMF Row/Column Tones 697 Hz 770 Hz 852 Hz 941 Hz 1 4 7 * 1209 Hz 2 5 8 0 1336 Hz 3 6 9 # 1477 Hz A B C D 1633 Hz 68 Rev. 1.2 S i3220/25 Table 39 outlines the hex codes corresponding to the detected DTMF digits. The threshold for declaring the presence or absence of 2100 Hz energy should be based on Table 40. A suitable threshold for most applications is >0x20, corresponding to a level of –15 dBm. Table 39. DTMF Hex Codes Digit Hex code Table 40. 2100 Hz Level vs. RAM Hex Value TIP and RING Level Across 600 W (dBm) TX Path: RAM 410 (154) or RX Path: RAM 413 (157) (Hex) 1 2 3 4 5 6 7 8 9 0 * # A B C D 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x0 +3 0 –3 –6 –9 –12 –15 0x838 0x420 0x20a 0x107 0x83 0x41 0x20 The following steps are used to access RAM address 410 and 413: 1. Write 0x02, 0x06, 0x0C, 0x00 to Reg. 87 (un-protect test registers/bits) 2. Write 0x40 to Reg. 4 (access upper RAM space) 3. Write 0x02, 0x06, 0x0C, 0x00 to Reg. 87 (protect test registers/bits) 4. For TX path use RAMAddress = 154 for the RX path use RAMAddress = 157: if (readRAM(RAMAddress) > 0x20) Tone2100 Hz = 1; else Tone2100 Hz = 0; endif 3.24. Modem Tone Detection The Dual ProSLIC devices are capable of detecting a 2100 Hz modem tone as described in ITU-T Recommendation V.8. The detection scheme can be implemented in both transmit and receive paths and is enabled by programming the appropriate register bit. The detection scheme should be disabled for power conservation after the modem tone window has passed. Once a valid modem tone is detected, a register bit is set accordingly, and the user can check the results by reading the register value. A programmable debounce interval is provided to eliminate false detection and can be programmed in increments of 67 ms by writing to the appropriate register. The outputs of the 2100 Hz modem tone detectors are located at RAM addresses 410 and 413 for the TX and RX paths, respectively. The contents of registers 410 and 413 indicate the presence or absence of 2100 Hz energy. Table 40 indicates the relationship between the contents of these RAM addresses and the level of the 2100 Hz energy present in the corresponding signal path (TX or RX). 3.25. Audio Path Processing Unlike traditional SLICs, the Dual ProSLIC devices integrate the codec function into the same IC. The onchip 16-bit codec offers programmable gain/attenuation blocks and multiple loopback modes for self testing. The signal path block diagram is shown in Figure 11 on page 24. 3.25.1. Transmit Path In the transmit path, the analog signal fed by the external ac coupling capacitors is passed through an anti-aliasing filter before being processed by the A/D converter. An analog mute function is provided directly prior to the A/D converter input. The output of the A/D converter is an 8 kHz, 16-bit wide, linear PCM data stream. The standard requirements for transmit path Rev. 1.2 69 S i3220/25 attenuation for signals above 3.4 kHz are part of the combined decimation filter characteristic of the A/D converter. One more digital filter, THPF, is available in the transmit path. THPF implements the high-pass attenuation requirements for signals below 65 Hz. An equalizer block then equalizes the transmit signal path to compensate for series protection resistance, RPROT, outside of the ac-sensing inputs. The linear PCM data stream output from the equalizer block is amplified by the transmit-path programmable gain amplifier, TPGA, which can be programmed from –∞ to 6 dB. The DTMF decoder receives the linear PCM data stream and performs the digit extraction if enabled by the user. The final step in the transmit path signal processing is the A-law or µ-law compression, which can reduce the data stream word width to 8 bits. Depending on the PCM mode select register selection, every 8-bit compressed serial data word occupies one time slot on the PCM highway, or every 16-bit uncompressed serial data word occupies two time slots on the PCM highway. 3.25.2. Receive Path 3.25.4. TXEQ/RXEQ Equalizer Blocks The TXEQ and RXEQ blocks (see Figure 11 on page 24) represent 4-tap filters that can be used to equalize the transmit and receive paths, respectively. The transmit path equalizer is controlled by the TXEQCO0TXEQCO3 RAM locations, and the receive path equalizer is controlled by the RXEQCO0-RXEQCO3 RAM locations. The Si322x Coefficient Generator software uses these filters in calculating the ac impedance coefficients for optimal ac performance. Refer to “AN63: Si322x Coefficient Generator User’s Guide” for detailed information regarding the calculation of ac impedance coefficients. TPGA or RPGA PCM In X M PCM Out In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process so that two 8-bit words are assembled into one 16-bit word. RPGA is the receive path programmable gain amplifier, which can be programmed from –∞ dB to 6 dB. An 8 kHz, 16-bit signal is then provided to a D/A converter. An analog mute function is provided directly after the D/A converter. When not muted, the resulting analog signal is applied at the input of the transconductance amplifier, Gm, which drives the off-chip current buffer, IBUF. 3.25.3. TPGA/RPGA Gain/Attenuation Blocks where M = {0, 1/16384, 2/16384,...32767/16384} Figure 39. TPGA and RPGA structure 3.25.5. Audio Characteristics The dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the µ-law or the A-law compression process. Figure 5 on page 20 specifies the minimum Signal-to-Noise and Distortion Ratio for either path for a sine wave input of 200 Hz to 3400 Hz. The TPGA and RPGA blocks are essentially linear multipliers with the structure illustrated in Figure 39. Both blocks can be independently programmed from –∞ to +6 dB (0 to 2 linear scale). The TXGAIN and RXGAIN RAM locations are used to program each block. A setting of 0000h mutes all audio signals; a setting of 4000h passes the audio signal with no gain or attenuation (0 dB), and a setting of 7FFFh provides the maximum 6 dB of gain to the incoming audio signal. The device signal scaling assumes that dBm is always referenced to 600 Ω. To compensate for this, the correct RXGAIN and TXGAIN settings are given in the coefficient generator software. The DTXMUTE and DRXMUTE bits in the DIGCON register are also available to allow muting of the transmit and receive paths without requiring modifications to the TXGAIN or RXGAIN settings. Both the µ-law and the A-law speech encoding allow the audio codec to transfer and process audio signals larger than 0 dBm0 without clipping. The maximum PCM code is generated for a µ-law encoded sine wave of 3.17 dBm0 or an A-law encoded sine wave of 3.14 dBm0. The device overload clipping limits are driven by the PCM encoding process. Figure 6 on page 21 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of the device. The transmit path gain distortion versus frequency is shown in Figure 7 on page 21. The same figure also presents the minimum required attenuation for out-ofband analog signals applied on the line. The presence of a high-pass filter transfer function ensures at least 30 dB of attenuation for signals below 65 Hz. The lowpass filter transfer function attenuates signals above 3.4 kHz. It is implemented as part of the A-to-D converter. 70 Rev. 1.2 S i3220/25 The receive path transfer function requirement, shown in Figure 8 on page 22, is very similar to the transmit path transfer function. The PCM data rate is 8 kHz; so, no frequencies greater than 4 kHz are digitally-encoded in the data stream. At frequencies greater than 4 kHz, the plot in Figure 8 is interpreted as the maximum allowable magnitude of spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 Hz to 3.4 kHz at a level of 0 dBm0 is applied at the digital input. The group delay distortion in either path is limited to no more than the levels indicated in Figure 9 on page 23. The reference in Figure 9 is the smallest group delay for a sine wave in the range of 500 Hz to 2500 Hz at 0 dBm0. The block diagram for the voice-band signal processing paths is shown in Figure 11 on page 24. Both the receive and the transmit paths employ the optimal combination of analog and digital signal processing for maximum performance while maintaining sufficient flexibility for users to optimize their particular application of the device. The two-wire (TIP/RING) voice-band interface to the device is implemented with a small number of external components. The receive path interface consists of a unity-gain current buffer, IBUF, while the transmit path interface is an ac coupling capacitor. Signal paths, although implemented differentially, are shown as single-ended for simplicity. 3.26. System Clock Generation The Dual ProSLIC devices generate the internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 786 kHz, 1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined by a counter clocked by PCLK. The three-bit ratio information is transferred into an internal register, PLL_MULT, after a device reset. The PLL_MULT controls the internal PLL, which multiplies PCLK to generate the rate required to run the internal filters and other circuitry. The PLL clock synthesizer settles quickly after powerup or update of the PLL-MULT register. The PLL lock process begins immediately after the RESET pin is pulled high and takes approximately 5 ms to achieve lock after RESET is released with stable PCLK and FSYNC. However, the settling time depends on the PCLK frequency and can be predicted based on the following equation: 64 T settle = -------------f PCLK Note: Therefore, the RESET pin must be held low during powerup and should only be released when both PCLK and FSYNC signals are known to be stable. PCLK PFD DIV M RESET PLL_MULT VCO ÷2 ÷2 28.672 MHz Figure 40. PLL Frequency Synthesizer Rev. 1.2 71 S i3220/25 3.27. Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Ground Key detected Power alarm DTMF digit detected Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Pulse metering active timer expired Pulse metering inactive timer expired RAM address access complete Receive path modem tone detected Transmit path modem tone detected The interface to the interrupt logic consists of six registers. Four interrupt status registers (IRQ0–IRQ3) contain 1 bit for each of the above interrupt functions. These bits are set when an interrupt is pending for the associated resource. Three interrupt mask registers (IRQEN1–IRQEN3) also contain 1 bit for each interrupt function. For interrupt mask registers, the bits are active high. Refer to the appropriate functional description text for operational details of the interrupt functions. When a resource reaches an interrupt condition, it signals an interrupt to the interrupt control block. The interrupt control block sets the associated bit in the interrupt status register if the mask bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ asserts low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource requests service. All interrupt bits in the interrupt status registers IRQ0–IRQ3 are cleared following a register read operation. If the interrupt status registers are non-zero, the INT pin remains asserted. 3.28. SPI Control Interface The control interface to the Dual ProSLIC devices is a 4-wire SPI bus modeled after microcontroller and serial peripheral devices. The interface consists of a clock, SCLK, chip select, CS, serial data input, SDI, and serial data output, SDO. In addition, the Dual ProSLIC devices include a serial data through output (SDI_THRU) to support daisy-chain operation of up to eight devices (up to sixteen channels). Figure 41 illustrates the daisychain connections. Note that the SDITHRU pin of the last device in the chain must not be connected to ground (SDITHRU = 0 indicated GCI mode). The device operates with both 8-bit and 16-bit SPI controllers. Each SPI operation consists of a control byte, an address byte (of which only the seven LSBs are used internally), and either one or two data bytes depending on the width of the controller and whether the access is to an 8-bit register or 16-bit RAM address. Bytes are always transmitted MSB first. The variations of usage on this four-wire interface are as follows: Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must be asserted before the falling edge of SCLK on which the first bit of data is expected during a read cycle and must remain low for the duration of the 8-bit transfer (command/ address or data), going high after the last rising of SCLK after the transfer. Clock during transfer only. In this mode, the clock is cycling only during the actual byte transfers. Each byte transfer consists of eight clock cycles in a return to “1” format. SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tri-stating its output during the data byte transfer of a read operation. Soft reset. The SPI state machine resets whenever CS asserts during an operation on an SCLK cycle that is not a multiple of eight. This is a mechanism for the controller to force the state machine to a known state when the controller and the device are out of synchronization. As shown in the application schematics in Figure 12 on page 25 and Figure 13 on page 26, a pulldown resistor is required on the SDO pin to ensure proper operation. A pullup resistor is not allowed on the SDO pin. 72 Rev. 1.2 S i3220/25 The control byte has the following structure and is presented on the SDI pin MSB first: 7 6 5 4 3 2 1 0 BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3] See Table 41 for bit definitions. Table 41. SPI Control Interface 7 BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only valid for write operations since it would cause contention on the SDO pin during a read. R/W Read/Write Bit. 0 = Write operation. 1 = Read operation. 6 5 REG/RAM Register/RAM Access Bit. 0 = RAM access. 1 = Register access. Reserved CID[3:0] Indicates the channel that is targeted by the operation. Note that the 4-bit channel value is provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.) As the CID information propagates down the daisy chain, each channel decrements the CID by 1. The SDI nodes between devices reflect a decrement of 2 per device since each device contains two channels. The device receiving a value of 0 in the CID field responds to the SPI transaction. (See Figure 42.) If a broadcast to all devices connected to the chain is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is presented to all channels regardless of the CID values. 4 3:0 Rev. 1.2 73 S i3220/25 SDI0 SDO SDI CPU CS SDI CS SDO Channel 0 SDI1 Dual ProSLIC #1 Channel 1 SPI Clock SCLK SDITHRU SDI2 SDI CS SDO Channel 2 SDI3 Dual ProSLIC #2 Channel 3 SCLK SDITHRU SDI4 SDI14 SDI CS SDO Channel 14 SDI15 Dual ProSLIC #8 Channel 15 SCLK SDITHRU Figure 41. SPI Daisy-Chain Mode 74 Rev. 1.2 S i3220/25 In Figure 42, the CID field is zero. As this field is decremented (in LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between channels of the same device. A unique CID is presented to each channel, and the channel receiving a CID value of zero is the target of the operation (channel 0 in this case). The last line of Figure 42 illustrates that in Broadcast mode, all bits pass through the chain without permutation. Figures 43 and 44 illustrate WRITE and READ operations to register addresses via an 8-bit SPI controller. These operations are performed as a 3-byte transfer. CS is asserted between each byte, which is required for CS to be asserted before the first falling edge of SCLK after the DATA byte to indicate to the state machine that one byte only should be transferred. The state of SDI is a “don’t care” during the DATA byte of a read operation. SPI Control Word BRDCST SDI0 SDI1 (Internal) SDI2 SDI3 (Internal) 0 0 0 0 R/W A A A A REG/RAM B B B B Reserved C C C C CID[0] 0 1 0 1 CID[1] 0 1 1 0 CID[2] 0 1 1 1 CID[3] 0 1 1 1 SDI 14 SDI15 (Internal) 0 0 A A B B C C 0 1 1 0 0 0 0 0 SDI0-15 1 A B C D E F G Figure 42. Sample SPI Control Word to Address Channel 0 CS SCLK SDI SDO CONTROL ADDRESS DATA [7:0] Hi-Z Figure 43. Register Write Operation via an 8-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS XXXXXXXX Data [7:0] Figure 44. Register Read Operation via an 8-Bit SPI Port Rev. 1.2 75 S i3220/25 Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data indicates to the SPI state machine that eight more SCLK pulses follow to complete the operation. For a WRITE operation, the last eight bits are ignored. For a read operation, the 8-bit data value repeats so that the data is captured during the last half of a data transfer if required by the controller. During register accesses, the CONTROL, ADDRESS, and DATA are captured in the SPI module. At the completion of the ADDRESS byte of a READ access, the contents of the addressed register move into the data register of the SPI data register. At the completion of the DATA byte of a WRITE access, the data is transferred from the SPI to the addressed register. Figures 47–50 illustrate the various cycles for accessing RAM addresses. RAM addresses are 16-bit entities; therefore, the accesses always require four bytes. During RAM address accesses, the CONTROL, ADDRESS, and DATA are captured in the SPI module. At the completion of the ADDRESS byte of a READ access, the contents of the channel-based data buffer CS SCLK SDI SDO CONTROL ADDRESS Data [7:0] XXXXXXXX move into the data register in the SPI for shifting out during the DATA portion of the SPI transfer. This is the data loaded into the data buffer in response to the previous RAM address read request. Therefore, there is a one-deep pipeline nature to RAM address READ operations. At the completion of the DATA portion of the READ cycle, the ADDRESS is transferred to the channel-based address buffer register, and a RAM address is logged for that channel. The RAMSTAT bit in each channel is polled to monitor the status of RAM address accesses that are serviced twice per sample period at dedicated windows in the DSP algorithm. A RAM access interrupt in each channel indicates that the pending RAM access request is serviced. For a RAM access, the ADDRESS and DATA is transferred from the SPI registers to the address and data buffers in the appropriate channel. The RAM WRITE request is logged. As for READ operations, the status of the pending request is monitored by either polling the RAMSTAT bit for the channel or enabling the RAM access interrupt for the channel. By keeping the address, data buffers, and RAMSTAT register on a perchannel basis, RAM address accesses can be scheduled for both channels without interface. Hi - Z Figure 45. Register Write Operation via a 16-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS XXXXXXXX XXXXXXXX Data [7:0] Data [7:0] Same byte repeated twice. Figure 46. Register Read Operation via a 16-Bit SPI Port 76 Rev. 1.2 S i3220/25 CS SCLK SDI SDO CONTROL ADDRESS DATA [15:8] DATA [7:0] Hi-Z Figure 47. RAM Write Operation via an 8-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS xxxxxxxx DATA [15:8] xxxxxxxx DATA [7:0] Figure 48. RAM Read Operation via an 8-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS Data [15:8] Data [7:0] Hi - Z Figure 49. RAM Write Operation via a 16-Bit SPI Port CS SCLK SDI SDO CONTROL ADDRESS Data [15:8] Data [7:0] Figure 50. RAM Read Operation via a 16-Bit SPI Port Rev. 1.2 77 S i3220/25 3.29. PCM Interface The Dual ProSLIC devices contain a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCLK and FSYNC inputs, PCM Mode Select, PCM Transmit Start Count (PCMTXHI/ PCMTXLO), and PCM Receive Start Count (PCMRXHI/ PCMRXLO) registers. The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to PCLK frequencies of 256 kHz to 8.192 MHz in power-of-2 increments. (768 kHz, 1.536 MHz, and 1.544 MHz are also available for T1 and E1 support.) Timeslots for data transmission and reception are independently configured with the PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO. Special consideration must be given to the PCM Receive Start Count (PCMRXHI / PCMRXLO) registers. Changing the PCMRXHI (Reg. 57), PCMRXLO (Reg. 56) on-the-fly while the Si3220/25 is actively passing audio can cause the digital impedance synthesis block to perform improperly producing an audible loud white noise signal across TIP and RING. To ensure proper device operation, the RX timeslot registers (PCMRXHI and PCMRXLO, registers 56–57) should be set during the initialization procedure immediately after power-up and prior to both enabling the PCM bus and setting the linefeed to the active state. The TX timeslot registers (PCMTXHI and PCMTXLO, registers 54–55) may be changed at any time to establish audio connections on the PCM bus. Setting the correct starting point of the data configures the part to support long FSYNC and short FSYNC variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time PCLK slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit. DTX returns to highimpedance on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. This is based on the setting of the PCMTRI bit of the PCM Mode Select register. Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. In addition to 8-bit data modes, a 16-bit mode is provided for testing. This mode can be activated via the PCMF bits of the PCM Mode Select register. Setting the PCMTXHI/PCMTXLO or PCMRXHI/PCMRXLO register greater than the number of PCLK cycles in a sample period stops data transmission because neither PCMTXHI/PCMTXLO nor PCMRXHI/PCMRXLO equal the PCLK count. Figures 51–54 illustrate the usage of the PCM highway interface to adapt to common PCM standards. As shown in the application schematics in Figures 12 and 13, a pulldown resistor is required on the DTX pin. A pullup resistor is not allowed on the DTX pin. Additionally, the PCLK frequency should be chosen such that there is at least one empty timeslot (hi-Z timeslot) per 8 kHz frame. If a PCLK is chosen such that DTX has valid data during the entire frame, choose the next higher valid PCLK frequency to ensure one or more empty timeslots in each frame. If an application requires heavy capacitive loading on the DTX pin, or more than eight Si322x devices connected to the same PCM bus, consult your local Silicon Laboratories sales representative to determine what value of pulldown resistor should be used. FSYNC PCLK_CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB DTX HI-Z MSB LSB HI-Z Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1) 78 Rev. 1.2 S i3220/25 PCLK FSYNC PCLK_CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB DTX HI-Z MSB LSB HI-Z Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) PCLK FSYNC PCLK_CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB DTX HI-Z MSB LSB HI-Z Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) 3.30. PCM Companding The Dual ProSLIC devices support both µ-255 Law (µLaw) and A-Law companding formats in addition to Linear Data mode. The data format is selected via the PCMF bits of the PCM Mode Select register. µ-Law mode is more commonly used in North America and Japan, and A-Law is primarily used in Europe and other countries. These 8-bit companding schemes follow a segmented curve formatted as a sign bit (MSB) followed by three chord bits and four step bits. A-Law typically uses a scheme of inverting all even bits while µ-Law does not. Dual ProSLIC devices also support A-Law with inversion of even bits, inversion of all bits, or no bit inversion by programming the ALAW bits of the PCM Mode Select register to the appropriate setting. Table 42 on page 81 and Table 43 on page 82 define the µ-Law and A-Law encoding formats. The Dual ProSLIC devices also support a 16-bit linear data format with no companding. This Linear mode is typically used in systems that convert to another companding format, such as adaptive differential PCM (ADPCM) or systems that perform all companding in an external DSP. The data format is 2s complement with MSB first (sign bit). Transmitting and receiving data via Linear mode requires two continuous time slots. An 8-bit Linear mode enables 8-bit transmission without companding. Rev. 1.2 79 S i3220/25 PCLK FSYNC PCLK_CNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB DTX HI-Z MSB LSB HI-Z Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC 80 Rev. 1.2 S i3220/25 Table 42. µ-Law Encode-Decode Characteristics* Segment Number 8 #Intervals X Interval Size 16 X 256 Value at Segment Endpoints 8159 . . . 4319 4063 . . . 2143 2015 . . . 1055 991 . . . 511 479 . . . 239 223 . . . 103 95 . . . 35 31 . . . 3 1 0 Digital Code 10000000b Decode Level 8031 10001111b 4191 7 16 X 128 10011111b 2079 6 16 X 64 10101111b 1023 5 16 X 32 10111111b 495 4 16 X 16 11001111b 231 3 16 X 8 11011111b 99 2 16 X 4 11101111b 33 1 15 X 2 __________________ 1X1 11111110b 11111111b 2 0 *Note: Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. Rev. 1.2 81 S i3220/25 Table 43. A-Law Encode-Decode Characteristics1,2 Segment Number #intervals X interval size Value at segment endpoints Digital Code Decode Level 7 16 X 128 4096 3968 . . 2176 2048 . . . 1088 1024 . . . 544 512 . . . 272 256 . . . 136 128 . . . 68 64 . . . 2 0 10101010b 4032 10100101b 2112 6 16 X 64 10110101b 1056 5 16 X 32 10000101b 528 4 16 X 16 10010101b 264 3 16 X 8 11100101b 132 2 16 X 4 11110101b 66 1 32 X 2 11010101b 1 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of even-numbered bits. Other available formats include inversion of odd bits, inversion of all bits, or no bit inversion. See "3.30. PCM Companding" on page 79 for more details. 82 Rev. 1.2 S i3220/25 3.31. General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control and data information onto a GCI bus. The PCM and GCI interfaces are both four-wire interfaces and share the same pins. The SPI control interface is not used as a communication interface in the GCI mode but rather as hard-wired channel selector pins. The selection between PCM and GCI modes is performed out of reset using the SDITHRU pin. Tables 44 and 45 illustrate how to select the communication mode and how the pins are used in each mode. If GCI mode is selected, the following pins must be tied to the correct state to select one of eight subframe timeslots in the GCI frame (described below). These pins must remain in this state while the Dual ProSLIC is operating. Selecting a particular subframe causes that individual Dual ProSLIC device to transmit and receive on the appropriate subframe in the GCI frame, which is initiated by an FSYNC pulse. No further register settings are needed to select which subframe a device uses, and the subframe for a particular device cannot be changed while in operation. Table 46. GCI Mode Subframe Selection SDI SDO CS Table 44. PCM or GCI Mode Selection SDITHRU SCLK Mode Selected GCI Subframe 0 Selected (Voice channels 1–2) GCI Subframe 1 Selected (Voice channels 3–4) GCI Subframe 2 Selected (Voice channels 5–6) GCI Subframe 3 Selected (Voice channels 7–8) GCI Subframe 4 Selected (Voice channels 9–10) GCI Subframe 5 Selected (Voice channels 11–12) GCI Subframe 6 Selected (Voice channels 13–14) GCI Subframe 7 Selected (Voice channels 15–16) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 x GCI Mode—1x PCLK (2.048 MHz) GCI Mode—2x PCLK (4.096 MHz) PCM Mode Note: Values shown are the states of the pins at the rising edge of RESET. Table 45. Pin Functionality in PCM or GCI Mode Pin Name PCM Mode GCI Mode CS SCLK SDI SDO SDITHRU SPI Chip Select SPI Clock Input SPI Serial Data Input SPI Serial Data Output SPI Data Throughput pin for Daisy Chaining Operation (Connects to the SDI pin of the subsequent device in the daisy chain) PCM Frame Sync Input PCM Input Clock PCM Data Transmit PCM Data Receive Channel Selector, bit 0 PCLK Rate Selector Channel Selector, bit 2 Channel Selector, bit 1 PCM/GCI Mode Selector FSYNC PCLK DTX DRX GCI Frame Sync Input GCI Input Clock GCI Data Transmit GCI Data Receive Note: This table denotes pin functionality after the rising edge of RESET and mode selection. In GCI mode, the PCLK input requires either a 2.048 MHz or a 4.096 MHz clock signal, and the FSYNC input requires an 8 kHz frame sync signal. The overall unit of data used to communicate on the GCI highway is a frame 125 µs in length. Each frame is initiated by a pulse on the FSYNC pin whose rising edge signifies the beginning of the next frame. In 2x PCLK mode, the user sees twice as many PCLK cycles during each 125 µs frame versus 1x PCLK mode. Each frame consists of eight fixed timeslot subframes that are assigned by the subframe select pins as described above (SDI, SDO, and CS). Within each subframe are four channels (bytes) of data including two voice data channels, B1 and B2, one Monitor channel, M, used for initialization and setup of the device, and one Signaling and Control channel, SC, used for communicating the status of the device and initiating commands. Within the SC channel are six Command/Indicate (C/I) bits and two Rev. 1.2 83 S i3220/25 handshaking bits, MR and MX. The C/I bits indicate status and command communication while the handshaking bits Monitor Receive, MR, and Monitor Transmit, MX, exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. 3.31.1. 16-Bit GCI Mode Table 47. Subframe Selection 16-Bit GCI Mode SDI SDO GCI Subframe 0 Selected (Voice channels 0–1) GCI Subframe 1 Selected (Voice channels 2–3) GCI Subframe 2 Selected (Voice channels 4–5) GCI Subframe 3 Selected (Voice channels 6–7) 3.31.2. Monitor Channel 1 1 0 0 1 0 1 0 In addition to the standard 8-bit GCI mode, the Dual ProSLIC devices also offer a 16-bit GCI mode for passing 16-bit voice data to the upstream host processor. This mode can be used for testing purposes or for passing non-companded voice data to an upstream DSP for further processing. In 16-bit GCI mode, both of the 8-bit voice data channels (B1 and B2 in Figure 56) of each subframe are required to pass the 16-bit voice data to the host. Each 125 µs frame can, therefore, accommodate up to eight voice channels (the Dual ProSLIC can accommodate up to sixteen voice channels in 8-bit GCI mode). Table 47 describes the GCI mode subframe selection for 16-bit GCI mode. The Monitor channel is used for initialization and setup of the Dual ProSLIC devices. It is also used for general communication with the Dual ProSLIC by allowing read and write access to the Dual ProSLIC devices registers. Use of the monitor channel requires manipulation of the 125 µs = 1 Frame FS SF0 Sub-Frame SF1 SF2 SF3 SF4 SF5 SF6 SF7 8 B1 0 Channel 8 B2 1 8 M 2 SC 3 1 C/I 1 MR MX Figure 55. Time-Multiplexed GCI Highway Frame Structure 84 Rev. 1.2 S i3220/25 125 µs = 1 Frame FS CH0 Sub-Frame CH1 CH2 CH3 16 B1 8 M 6 C/I 1 MR 1 MX 16 B2 16 Unused Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode 1st Byte 2nd Byte 3rd Byte MX Transm itter MX MR Receiver MR ACK 1st Byte 125 µ s ACK 2nd Byte ACK 3rd Byte Figure 57. Monitor Handshake Timing Rev. 1.2 85 S i3220/25 The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This signals the Dual ProSLIC that a transmission has begun on the Monitor channel and it should begin accepting data from it. After reading the data on the monitor channel, the Dual ProSLIC acknowledges the initial transmission by placing the upstream MR bit in an active state. The data is received, and the upstream MR becomes active in the frame immediately following the downstream MX activation. The upstream MR then remains active until either the next byte is received or an end of message is detected (signaled by the downstream MX being held inactive for two or more consecutive frames). Upon receiving acknowledgement from the Dual ProSLIC that the initial data was received (signaled by the upstream MR bit transitioning from an active to an inactive state), the host device places the downstream MX bit in the inactive state for one frame and then either transmits another byte by placing the downstream MX bit in an active state again or signals an end of message by leaving the downstream MX bit inactive for a second frame. When the host is performing a write command, the host only manipulates the downstream MX bit, and the Dual ProSLIC only manipulates the upstream MR bit. If a read command is performed, the host initially manipulates the downstream MX bit to communicate the command but then manipulates the downstream MR bit in response to the Dual ProSLIC responding with the requested data. Similarly, the Dual ProSLIC initially manipulates its upstream MR bit to receive the read command and then manipulates its upstream MX bit to respond with the requested data. If the host is transmitting data, the Dual ProSLIC always transmits a $FF value on its Monitor data byte. While the Dual ProSLIC is transmitting data, the host should always transmit a $FF value on its Monitor byte. If the Dual ProSLIC is transmitting data and detects a value other than a $FF on the downstream Monitor byte, the Dual ProSLIC signals an abort. For read and write commands, an initial address must be specified. The Dual ProSLIC responds to a read or a write command at this address and then subsequently increments this address after every register access. In this manner, multiple consecutive registers can be read or written in one transmission sequence. By correctly manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached. To end a transmission sequence, the host processor must signal an End-of-Message (EOM) by placing the downstream MX and MR bits inactive for two consecutive frames. The transmission can also be stopped by the Dual ProSLIC by signaling an abort. This is signaled by placing the upstream MR bit inactive for at least two consecutive cycles in response to the downstream MX bit going active. An abort is signaled by the Dual ProSLIC for the following reasons: A read or write to an invalid memory address is attempted. An invalid command sequence is received. A data byte was not received for at least two consecutive frames. A collision occurs on the Monitor data bytes while the Dual ProSLIC is transmitting data. Downstream monitor byte not $FF while upstream monitor byte is transmitting. MR/MX protocol violation. Whenever the Dual ProSLIC aborts due to an invalid command sequence, the state of the Dual ProSLIC does not change. If a read or write to an invalid memory address is attempted, all previous reads or writes in that transmission sequence are valid up to the read or write to the invalid memory address. If an end-of-message is detected before a valid command sequence is communicated, the Dual ProSLIC returns to the idle state and remains unchanged. The data presented to the Dual ProSLIC in the downstream Monitor bits must be present for two consecutive frames to be considered valid data. The Dual ProSLIC is designed to ensure it has received the same data in two consecutive frames. If it does not, it does not acknowledge receipt of the data byte and waits until it does receive two consecutive identical data bytes before acknowledging to the transmitter that it has received the data. If the transmitter attempts to signal transmission of a subsequent data byte by placing the downstream MX bit in an inactive state while the Dual ProSLIC is still waiting to receive a valid data byte transmission of two consecutive identical data bytes, the Dual ProSLIC signals an abort and ends the transmission. Figure 58 shows a state diagram for the Receiver Monitor channel for the Dual ProSLIC. Figure 59 shows a state diagram for the Transmitter Monitor channel for the Dual ProSLIC. 86 Rev. 1.2 S i3220/25 Idle MR = 1 M X * LL MX 1s t By te Rec eiv ed MR = 0 Initial S tate MX A bort MR = 1 MX MX ABT A ny S tate MX By te V alid MR = 0 MX M X * LL Wait f or LL MR = 0 M X * LL MX M X * LL M X * LL MX New By te MR = 1 nth by te rec eiv ed MR = 1 M X * LL MX Wait f or LL MR = 0 MX MR : MR bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX: MX b it received d ata dow n s trea m (D R X) lin e. LL: Las t look of m onitor b yte received on D R X line. ABT: Abort ind ication to in terna l s ource. Figure 58. Dual ProSLIC Monitor Receiver State Diagram Rev. 1.2 87 S i3220/25 M R * M XR M XR Idle MR = 1 M R * M XR Wait MX = 1 M R * M XR A bort MX = 1 Initial S tate M R * RQT MR 1s t By te MX = 0 M R * RQT EOM MX = 1 MR M R * RQT nth By te ac k MX = 1 MR MR M R * RQT Wait f or ac k MX = 0 M R * RQT CLS /A B T A ny S tate MR : MR bit received on D R X line. MX: MX bit calculated and expected on D TX line. MXR : MX bit s am pled on D TX line. C LS: C ollis ion w ithin the m onitor data byte on D TX line. R QT: R eques t for trans m is s ion from internal s ource. ABT: Abort reques t/indication. Figure 59. Dual ProSLIC Monitor Transmitter State Diagram 88 Rev. 1.2 M onitor Da ta Dow nstre a m $91 $81 $81 $10 $10 $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $91 125 µ s 1 Frame M X Dow nstre a m Bit M R Dow nstre a m Bit EOM Signalled M onitor Da ta Upstre a m $FF $FF $FF $FF $FF $FF $91 $91 C ontents of C ontents of C ontents of C ontents of C ontents of R eg ister $10 R eg ister $10 R eg ister $11 R eg ister $11 R eg ister $12 (ig nored by host) Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for correct communication with the Dual ProSLIC. Devices that do not accept this “best case” timing scenario will not be able to communicate with the Dual ProSLIC. Rev. 1.2 s ends addres s before data $FF $FF $FF $FF M X Upstre a m Bit M R Upstre a m Bit = Acknow ledgem ent of data reception EOM Acknow ledge S i3220/25 Figure 60. Example Read of Registers $10 and $11 in Channel 0 of the Dual ProSLIC 89 S i3220/25 Monitor Data Downstream $FF $FF 125 µs 1 Frame $91 $91 $01 $01 $10 $10 Data to be written to $10 Data to be written to $10 Data to be written to $11 Data to be written to $11 $FF $FF MX Downstream Bit MR Downstream Bit EOM Signalled Monitor Data Upstream $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit = Acknowledgement of data reception EOM Acknowledge Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC 90 Rev. 1.2 S i3220/25 3.31.3. Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer status or operating mode information to and from the host processor. Communication with the Dual ProSLIC should be in the following format: Byte 1: Device Address Byte Byte 2: Command Byte Byte 3: Register Address Byte Bytes 4-n: Data Bytes Bytes n+1, N+2: EOM 3.31.4. Device Address Byte Immediately after the last bit of the CID command is received, the Dual ProSLIC responds with a fixed twobyte identification code as follows: MSB Bit Address Byte Command Byte 7 1 1 654321 00A000 011111 LSB 0 0 0 A = 1: Channel A is the source A = 0: Channel B is the source Upon sending the two-byte CID command, the Dual ProSLIC sends an EOM signal (MR = MX = 1) for two consecutive frames. When C = 0, B must be 0, or the Dual ProSLIC signals an abort due to an invalid command. In this mode, only bit C is programmable. 3.31.6. Command Byte The device address byte identifies which device receives the particular message. This address must be the first byte sent to the Dual ProSLIC at the beginning of each transmission sequence. The device address byte has the following structure: MSB 7 1 A = 1: A = 0: B = 1: B = 0: C = 1: C = 0: 6 0 5 0 4 A 3 B 2 0 1 0 LSB 0 C The command byte has the following structure: MSB RW CMD[6:0] LSB Channel A receives the command. Channel A does not receive the command. Channel B receives the command. Channel B does not receive the command. Normal command follows. Channel identification command. RW = 1: A Read operation is performed from the Dual ProSLIC RW = 0: A Write operation is performed to the Dual ProSLIC CMD[6:0] = 0000001: Read or Write from the Dual ProSLIC CMD[6:0] = 0000010-1111111: Reserved 3.31.7. Register Address Byte When C = 1, bits A and B are channel enable bits. When these bits are set to 1, the corresponding channels receive the command in the next command byte. The channels with corresponding bits set to 0 ignore the subsequent command byte. 3.31.5. Channel Identification (CID) Command The register address byte has the following structure: MSB ADDRESS[7:0] This byte contains the actual 8-bit address of the register to be read or written. 3.31.8. SC Channel The lowest programmable bit of the device address byte, C, enables a special channel identification command to identify itself by software. When C = 0, the structure of this command is as follows: A = 1: Channel A is the destination A = 0: Channel B is the destination MSB Bit Address Byte Command Byte 7 1 0 654321 00A000 000000 LSB 0 0 0 LSB The downstream and upstream SC channels are continuously carrying I/O information to and from the Dual ProSLIC during every frame. The upstream processor has immediate access to the receive (downstream) and transmit (upstream) data present on the Dual ProSLIC digital I/O port when used in GCI mode. The SC channel consists of six C/I bits and two handshaking bits as described in the tables below. The functionality of the handshaking bits is defined in the Rev. 1.2 91 S i3220/25 monitor channel section. This section defines the functionality of the six C/I bits whether they are being transmitted to the GCI bus via the DTX pin (upstream) or received from the GCI bus via the DRX pin (downstream). The structure of the SC channel is shown in Figure 62. MSB 7 CI2A 6 CI1A 5 CI0A 4 CI2B 3 CI1B 2 CI0B 1 MR LSB 0 MX Figure 63 illustrates the transmission protocol for the C/I bits within the downstream SC channel. New data received by either channel must be present and match for two consecutive frames to be considered valid. When a new command is communicated via the downstream C/I bits, this data must be sent for at least two consecutive frames to be recognized by the Dual ProSLIC. The current state of the C/I bits is stored in a primary register, P. If the received C/I bits are identical to the current state, no action is taken. If the received C/I bits differ from those in register P, the new set of C/I bits is loaded into secondary register S, and a latch is set. When the next set of C/I bits is received during the frame that immediately follows, the following rules apply: If the received C/I bits are identical to the contents of register S, the stored C/I bits are loaded into register P, and a valid C/I bit transition is recognized. The latch is reset, and the Dual ProSLIC responds accordingly to the command represented by the new C/I bits. If the received C/I bits differ from both the contents of register S and the contents of register P, the newlyreceived C/I bits are loaded into register S, and the latch remains set. This cycle continues as long as any new set of C/I bits differs from the contents of registers S and P. If the newly-received C/I bits are identical to the contents of register P, the contents of register P remain unchanged, and the latch is reset. Figure 62. SC Channel Structure 3.31.9. Downstream (Receive) SC Channel Byte The first six bits in the downstream SC channel control both channels of the Dual ProSLIC where the C/I bits are defined as follows: CI2A, CI1A, CI0A CI2B, CI1B, CI0B MR, MX Used to select operating mode for channel A Used to select operating mode for channel B Monitor channel handshake bits Table 48. Programming Operating Modes Using Downstream SC Channel C/I Bits Channel Specific C/I bits CI2x 0 0 0 0 1 1 1 1 CI1x 0 0 1 1 0 0 1 1 CI0x 0 1 0 1 0 1 0 1 Dual ProSLIC Operating Mode Open (high impedence, no line monitoring) Forward Active Forward On-Hook Transmission Ground Start (Tip Open) Ringing Reverse Active Reverse On-Hook Transmission Ground Start (Ring Open) Note: x = A or B, corresponding to Channel A or Channel B. 92 Rev. 1.2 S i3220/25 Receive New C/I Code = P? No Store in S Yes P: C/I Primary Register Contents S: C/I Secondary Register Contents Receive New C/I Code = S? No Yes Load C/I Register With New C/I Bits = P? No Yes Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC When the Dual ProSLIC is set to GCI mode at initialization, the default setting ignores the downstream SC channel byte and allows linefeed state commands to be directed through the monitor channel. This default configuration is enabled by initializing the GCILINE bit of the PCMMODE register to 0, which prevents the Dual ProSLIC from transitioning between linefeed operating states due to invalid data that may exist within the downstream SC channel byte. To transfer direct linefeed control to the downstream SC channel, the user must set the GCILINE bit to 1. Once the GCILINE bit has been set, the Dual ProSLIC follows the commands that are contained in the downstream SC channel byte as described in Figure 62. The Dual ProSLIC architecture also enables automatic transitions between linefeed operating states to reduce the amount of interaction required between the host processor and the Dual ProSLIC. When a GCI bus is implemented, the user must ensure that these automatic linefeed state transitions are consistent with the linefeed commands contained within the downstream SC channel byte. In normal operation, these automatic linefeed state transitions are accompanied by the setting of a threshold detection flag and an interrupt bit, if enabled. To allow the Dual ProSLIC to automatically detect the appropriate thresholds and control the linefeed transitions, the downstream SC channel byte should be updated accordingly once the interrupt bit is read from the upstream SC channel byte. To disable the automatic transitions, the user must set the GCILINE bit. Enabling this manual mode requires the host processor to read the upstream SC channel information and provide the appropriate downstream SC channel byte command to program the correct linefeed state. Table 49 presents the automatic linefeed state transitions and their associated registers that cause the transition. The transition to the OPEN state stemming from power alarm detection is intended to protect the Dual ProSLIC circuit in the event that too much power is dissipated in the Si3200 LFIC. This alarm is typically due to a fault in the application circuit or on the subscriber loop but can be caused by intermittent power spikes depending on the threshold to which the alarm is set. The user can reinitialize the linefeed operating state that was in effect just prior to the power alarm by toggling the downstream SC channel byte to the OPEN state for two consecutive cycles and then resetting the downstream SC channel byte to the intended linefeed state for two consecutive cycles. If the Dual ProSLIC continues to automatically transition to the OPEN state, the power alarm threshold Rev. 1.2 93 S i3220/25 might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is probable, and the user should take measures to diagnose the problem. 3.31.10. Upstream (Transmit) SC Channel Byte represent a valid transfer. The upstream C/I bits are defined as follows: CI2A, CI1A, CI0A CI2B, CI1B, CI0B MR, MX Monitors status data for channel A Monitors status data for channel B Monitor channel handshake bits (see Monitor Channel section) The upstream SC channel byte looks similar to the downstream SC channel byte except that the information quickly transfers the most time-critical information from the Dual ProSLIC to the GCI bus. Each upstream SC channel byte transfer from the Dual ProSLIC lasts for at least two consecutive frames to Table 49. Automatic Linefeed State Transitions Initiating Action Automatic Linefeed State Transition Detection/Control Bits Interrupt Enable/Status Bits Loop closure detected On-hook active → off-hook active, Off-hook active → on-hook active Ring trip detected Ringing burst cadence Power alarm detected Ringing → off-hook active Ringing → on-hook transmission On-hook transmission → ringing Any state → open LCR (Register 9) RTP (Register 9) T1EN, T2EN (Register 23) PQ1DL (RAM 50) LOOPE, LOOPS (Register 16/19) RTRIPE, RTRIPS (Register 16/19) RINGT1E, RINGT2E, RINGT1S, RINGT2S (Register 15/18) PQ1E, PQ1S (Registers 17/20) Table 50. Monitored Data via Upstream SC Channel C/I Bits C/I Bit Information Provided Mirrored Register Bits Context CI2A Interrupt information on channel A Hook status information on channel A Ground key information on channel A Interrupt information on channel B Hook status information on channel B Ground key information on channel B IRQ0[0]+ IRQ0[1]+ IRQ0[2] LCRRTP[0] (LCR bit) LCRRTP[2] (LONGHI bit) IRQ0[4]+ IRQ0[5]+ IRQ0[6] LCRRTP[0] (LCR bit) LCRRTP[2] (LONGHI bit) CI2A = 0: No interrupt on channel A CI2A = 1: Interrupt present on channel A CI1A = 0: Channel A is on-hook CI1A = 1: Channel A is off-hook CI0A = 0: No longitudinal current detected CI0A = 1: Longitudinal current detected in channel A CI2A = 0: No interrupt on channel B CI2A = 1: Interrupt present on channel B CI1A = 0: Channel B is on-hook CI1A = 1: Channel B is off-hook CI0A = 0: No longitudinal current detected CI0A = 1: Longitudinal current detected in channel B CI1A CI0A CI2B CI1B CI0B 94 Rev. 1.2 S i3220/25 The interrupt information for channels A and B is a single bit that indicates that one or more interrupts might exist on the respective channel. Each of the individual interrupt flags (see registers 18–20) can be individually masked by writing the appropriate bit in registers 21–23 to ignore specific interrupts. When using the GCI mode, the user should verify that each of the desired interrupt bits are set so the upstream SC channel byte includes the required interrupt functions. A third digital loopback takes the digital stream at the output of the µ-Law/A-Law expander and feeds it back to the input of the µ-Law/A-Law compressor. (See DLM1 path in Figure 11.) This path verifies that the host is connected correctly with the Dual ProSLIC through the PCM interface and that the PCLK and FSYNC signals are correctly set. This mode also can test the µ-Law/A-Law companding process. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can also connect directly to the 16-bit data to eliminate the µ-Law/A-Law companding process when testing the PCM interface. 3.32.2. Line Test and Diagnostics 3.32. System Testing The Dual ProSLIC devices include a complete suite of test tools to test the functionality of the line card and detect fault conditions present on the TIP/RING pair. Using one of the loopback test modes with the signal generation and measurement tools eliminates the need for per-line test relays and centralized test equipment. 3.32.1. Loopback Modes Three loopback test options are available for the Dual ProSLIC devices: The codec loopback path encompasses almost entirely the electronics of both the transmit and receive paths. The analog signal at the output of the receive path is fed back to the input of the transmit path through a feedback path on the analog side of the audio codec. Both the impedance synthesis and transhybrid balance functions are disabled in this mode. (See DLM3 path in Figure 11 on page 24.) The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16bit data. A second digital loopback takes the receive path digital stream and routes it back to the transmit path via the transhybrid feedback path. (See DLM2 path through block H in Figure 11.) This mode characterizes the transhybrid filter response. The transhybrid block can also be disabled (set to unity gain) in this mode for diagnosing the digital gain blocks and filter stages in both transmit and receive paths. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data. The Dual ProSLIC devices provide a variety of signal generation and measurement tools that facilitate fault detection and parametric diagnostics on the TIP/RING pair and line card functionality verification. The Dual ProSLIC generates test signals, measures the appropriate voltage/current/signal levels, and processes the results to provide a meaningful result to the user. Interaction is required from the host microprocessor to load the test parameters into the appropriate registers, initiate the test(s), and read the results from the registers. In some cases, the host processor might also be required to perform some simple mathematics to achieve the results. Software modules are available to simplify integration of the diagnostics functions into the system. The need for test relays and a separate test head is eliminated in most applications. To address legacy applications, all versions of the Dual ProSLIC include test-in and test-out relay drivers to switch in a centralized test card. The Dual ProSLIC line test and diagnostics capabilities are categorized into three sections: signal generation tools, measurement tools, and diagnostics capabilities. Using these signal generation and measurement tools, a variety of other diagnostic functions can be performed to meet the unique requirements of specific applications. Table 51 summarizes the ranges and capabilities of the signal generation and measurement tools. Rev. 1.2 95 S i3220/25 Table 51. Summary of Signal Generation and Measurement Tools Function Range Accuracy/Resolution Comments Signal Generation Tools DC Current Generation DC Voltage Generation Audio Tone Generation Ringing Signal Generation 18 to 45 mA 0 to 63.3 V 200 to 3400 Hz 4 to 15 Hz 16 to 100 Hz Measurement Tools 0.875 mA 1.005 V — ±5% ±1% 8-Bit dc/Low-Frequency Monitor A/D Converter High Range: 0 to 160.173 V 0 to 101.09 mA Low Range: 0 to 64.07 V 0 to 50.54 mA 628 mV 396.4 µA 251 mV 198.2 µA 125 µs — 38 µV — — 800 Hz update rate acrms, acPK, and dc post-processing blocks Programmable Timer AC Low-Pass Filter 16-Bit Audio A/D Converter Transmit Path Notch Filter Transmit Path Bandpass Filter 3.32.3. Signal Generation Tools 0 to 8.19 s 3 to 400 Hz 0 to 2.5 V 300 to 3400 Hz 300 to 3400 Hz Single or dual notch, ≥90 dB attenuation TIP/RING dc signal generation. The Dual ProSLIC line feed D/A converter can program a constant current linefeed from 18–45 mA in 0.87 mA steps with a ±10% total accuracy. In addition, the opencircuit TIP/RING voltage can be programmed from 0 to 63 V in 1 V steps. The linefeed circuitry can also generate a controlled polarity reversal. Tone generation. The Dual ProSLIC devices can generate single or dual tones over the entire audio band and can direct them into either the transmit or receive path depending on the diagnostic requirements. Ringing signals from 4–100 Hz can also be generated. Diagnostics mode ringing generation. The Dual ProSLIC devices can generate an internal low-level ringing signal to test for the presence of REN without causing the terminal equipment to ring audibly. This ringing signal can be either balanced or unbalanced depending on the state of the RINGUNB bit of the RINGCON register. This feature is also available with the Si3225 provided that sufficient battery voltage is present. 96 Rev. 1.2 S i3220/25 PEAK DETECT VTIP VRING VLOOP VLONG ILOOP ILONG VRING,EXT IRING,EXT FULL WAVE RECTIFY DIAGACCO DIAGDCCO DIAGPK LPF DIAGDC LPF DIAGAC Figure 64. SLIC Diagnostic Filter Structure 3.32.4. Measurement Tools 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low-frequency voltage and current data from TIP to ground and RING to ground. Two additional values, TIP – RING and TIP + RING, are calculated and stored in on-chip registers to analyze metallic and longitudinal effects. The A/D operates at an 800 Hz update rate to allow measurement bandwidth from dc to 400 Hz. A dualrange capability allows high-voltage/high-current measurement in the high range but can also measure lower voltages and currents with a tighter resolution. Programmable bandpass filter. A bandpass filter discriminates certain frequency ranges, such as ringing frequencies and 50 Hz/60 Hz induction, from nearby or crossed power leads. SLIC diagnostics filter. Several post-processing filter blocks monitor peak dc and ac characteristics of the Monitor A/D converter outputs and values derived from these outputs. Setting the SDIAG bit in the DIAG register enables the filters. There are separate filters for each channel, and their control is independent. These filters require DSP processing, which is available only when voice band processing is not being performed. If an off-hook or ring trip condition is detected while the SDIAG bit is set, the bit is cleared, and the diagnostic information is not processed. The following parameters can be selected as inputs to the diagnostic block by setting the SDIAG bits in the DIAG register to values 0–7 corresponding to the order below: VTIP = voltage on the TIP lead VRI NG = voltage on the RING lead VLOOP = VTIP-VRING = metallic (loop) voltage VLONG = (VTIP+VRING)/2 = longitudinal voltage ILOOP = ITIP-IRING = metallic (loop) current ILONG = (ITIP+IRING)/2 = longitudinal current VRING, EXT = ringing voltage when using an external ringing source (Si3225 only) IRING,EXT = ringing current when using an external ringing source (Si3225 only) The SLIC diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. The topology is illustrated in Figure 64. The peak detect filter block reports the magnitude of the largest positive or negative value without sign. The dc filter block consists of a single pole IIR low-pass filter with a coefficient held in the DIAGDCCO RAM location. The filter output is read from the DIAGDC RAM location. The ac filter block consists of a full-wave rectifier followed by a single-pole IIR low-pass filter with a coefficient held in the DIAGACCO RAM location. The peak value is read from the DIAGPK RAM location. The peak value is cleared and the filters are flushed on the 0-1 transition of the SDIAG bit and when the input source changes. The user can write 0 to the DIAGPK RAM location to get peak information for a specific time interval. 16-bit audio A/D converter. The A/D converter portion of the audio codec is made available for processing test data received back through the transmit audio path. The audio path offers a 2.5 V peak voltage measurement capability and a coarse attenuation stage for scenarios where the incoming signal amplitude must be attenuated by as much as 3 dB to bring it into the allowable input range without clipping. Rev. 1.2 97 S i3220/25 Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on and off times of the ringing and pulse-metering signals. The tone generation oscillator can be used to program a time period for averaging specific measured test parameters. Transmit audio path diagnostics filter. Transmit path audio diagnostics are facilitated by implementing a sixth-order IIR filter followed by peak detection and power estimation blocks. This filter can be programmed to eliminate or amplify specific signals for the purpose of measuring the peak amplitude and power content of individual components in the audio spectrum. Figure 11 on page 24 illustrates the location of the diagnostics filter block. The sixth order IIR filter operates at an 8 kHz sample rate and is implemented as three second-order filter stages in cascade. Each second-order filter offers five fully-programmable coefficients (a1, a2, b0, b1, and b2) with 25-bit precision by providing several user-accessible registers. Each filter stage is implemented with the following format: ( b0 + b1z + b2z ) H ( z ) = ------------------------------------------------------–1 –2 ( 1 – a1z – a2z ) –1 –2 The power averaging filter time constant is absolute value programmable, and the average power result is read from the TESTAVO RAM location. 3.32.5. Diagnostics Capabilities Foreign voltages test. The Dual ProSLIC devices can detect the presence of foreign voltages according to GR-909 requirements of ac voltages > 10 V and dc voltages > 6 V from T-G or R-G. This test is performed when it has been determined that a hazardous voltage is not present on the line. Resistive faults (leakage current) test. Resistive fault conditions are measured from T-G, R-G, or T-R for dc resistance per GR-909 specifications. If the dc resistance is < 150 kΩ, it is considered a resistive fault. To perform this test, program the Dual ProSLIC chipset to generate a constant open-circuit voltage, and measure the resulting current. The resistance is then calculated. Receiver off-hook test. Uses a similar procedure as described in the resistive faults test above but is measured across T-R only. In addition, two measurements must be performed at different opencircuit voltages to verify the resistive linearity. If the calculated resistance has more than 15% nonlinearity between the two calculated points and the voltage/current origin, it is determined to be a resistive fault. Ringers (REN) test. Verifies the presence of REN at the end of the TIP/RING pair per GR-909 specifications. It can be implemented by generating a 20 Hz ringing signal between 7 Vrms and 17 Vrms and measuring the 20 Hz ac current using the 8-bit monitor ADC. The resistance (REN) can then be calculated using the software module. The acceptable REN range is >0.175 REN (