Si3219x: ProSLIC® Single FXS Solution
ProSLIC® Single-Channel FXS Solutions
KEY FEATURES
The Si3219x Single FXS ProSLIC® devices implement a complete foreign exchange
station (FXS) telephony interface solution in a single package that conforms to all
relevant global specifications. The Si3219x ProSLIC ICs operate from a 3.3 V supply
and have a 3-wire ISI digital interface with 1.8 to 3.3 V I/O. The Si3219x devices are
designed to operate with a capacitive boost tracking battery supply for lower power,
cost, and footprint than other tracking supplies in the industry. Self-testing and metallic
loop testing (MLT) are facilitated by the built-in DSP, monitor ADC, and test load. The
devices are available with wideband audio for better-than-PSTN voice quality and DTMF
detection. The Si3219x devices are available in a 4 x 6 mm, 38-pin QFN package.
• Complete FXS solution in a single 4 x 6
mm package
• Performs all BORSCHT functions
• Ideal for short- or medium-loop
applications
• Ultra-low power consumption
• Patented low-power ringing
• Adaptive ringing
• Dynamic overhead control
• Ringing current limiting
Applications:
• VoIP Gateways and Routers
• xDSL IADs
• Optical Network Terminals/Units (ONT/U)
• Analog Terminal Adapters (ATA)
• Cable eMTA
• Wireless Fixed Terminals (WFT)
• Wireless Local Loop (WLL)
• WiMAX CPE
• Simplified configuration and diagnostics
• Supported by ProSLIC API
• Audio diagnostics with loopback
• Integrated test load
• Global programmability
• Wideband voice support
• On-hook transmission
• Loop or ground start operation
• Smooth polarity reversal
Programmable
AC Impedance
and Hybrid
DTMF
and
DTMF
&
Tone
ToneGen
Gen
Caller ID
Host Interface
3-wire ISI
Ringing
Ringing
Generator
Generator
DSP
Line
LineDiagnostics
Diagnostics
CODEC
CODEC
CODEC
SLIC
SLIC
ADC
ADC
Linefeed
Linefeed
Control
Control
DAC
DAC
Linefeed
Linefeed
Monitor
Monitor
Linefeed
• A-Law/µ-Law companding, linear PCM
• Flexible integrated tracking dc-dc
controller supporting patent-pending lowcost capacitive boost configuration
TIP
FXS
RING
• Software-programmable parameters:
• Ringing frequency, amplitude, cadence,
and waveshape
• Two-wire ac impedance
• Transhybrid balance
• DC current loop feed (10–45 mA)
• Loop closure and ring trip thresholds
• Ground key detect threshold
PLL
DC-DC Controller
• Pulse metering
• DTMF generation
Si3219x
• DTMF detection (Si32193)
• 3.3 V operation
• Support for 1.8 V I/O
• Maximum battery up to –100 V
• Pb-free/RoHS-compliant packaging
• 3-wire Integrated Serial Interface (ISI)
1
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 6, 2021
1
Table of Contents
1. Ordering Guide
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1.1 Product Identification .
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2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. FXS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 DC Feed Characteristics.
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4.2 Linefeed Operation States .
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4.3 Line Voltage and Current Monitoring.
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4.4 Power Monitoring and Power Fault Detection .
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4.5 Thermal Overload Shutdown .
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4.6 Loop Closure Detection .
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4.7 Ground Key Detection
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4.8 Ringing Generation
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4.9 Polarity Reversal .
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4.10 Two-wire Impedance Synthesis .
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4.11 Transhybrid Balance Figure .
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4.12 Tone Generators .
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4.13 DTMF Detection (Si32193 Only).
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4.14 Pulse Metering
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4.15 DC-DC Controller
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4.16 Wideband Audio .
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4.17 Test Facilities .
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.21
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5. System Interfaces
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5.1 Integrated Serial Interface .
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5.2 Input/Output Voltage Selection.
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6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.1 Pin Descriptions: 38 Pin QFN (Si32192/3) .
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7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.1 Package Outline: 38-Pin QFN .
8. Land Pattern
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.30
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9.1 Top Marking 38-pin QFN.
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8.1 Land Pattern: 38-Pin QFN .
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Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 6, 2021
2
Si3219x: ProSLIC® Single FXS Solution • Ordering Guide
1. Ordering Guide
Table 1.1. Si3219x Ordering Guide
P/N
Description
Package Type2
Max VBAT
Temperature
Si32192-A-FM1
Wideband FXS, ISI interface,
parametric MLT
QFN38
–100 V
0 to 70 °C
Si32192-A-GM1
Wideband FXS, ISI interface,
parametric MLT
QFN38
–100 V
–40 to 85 °C
Si32193-A-FM1
Wideband FXS, ISI interface,
parametric MLT, DTMF detection
QFN38
–100 V
0 to 70 °C
Si32193-A-GM1
Wideband FXS, ISI interface,
parametric MLT, DTMF detection
QFN38
–100 V
–40 to 85 °C
Si32192-A-ZM1
Wideband FXS, ISI interface,
parametric MLT, customer-specific
QFN38
–100 V
0 to 70 °C
Si32192-A-ZM2
Wideband FXS, ISI interface,
parametric MLT, customer-specific
QFN38
–100 V
0 to 70 °C
Si32193-A-ZM1
Wideband FXS, ISI interface,
parametric MLT, DTMF detection, customer-specific
QFN38
–100 V
0 to 70 °C
Si32193-A-ZM2
Wideband FXS, ISI interface,
parametric MLT, DTMF detection, customer-specific
QFN38
–100 V
0 to 70 °C
Note:
1. Adding the suffix "R" to the part number (e.g. Si3219x-A-FMR) denotes tape and reel.
2. QFN - Quad-Flat No-leads.
Table 1.2. Ordering GuideSi3219x Evaluation Kits
Part Number
Description
VBAT Max1
Si32193ACB10SL0EVB
ISI Wideband FXS with DTMF detection and low-cost capacitive boost dc-dc converter EVB
–100 V
Note:
1. EVB VBAT max may be limited by BOM option.
3
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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3
Si3219x: ProSLIC® Single FXS Solution • Ordering Guide
1.1 Product Identification
The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special
customer part number.
Example:
Si32193-A-FM1R
Product Designator
Revision
Shipping Option
Blank = Trays
R = Tape and Reel
Package Type
M1 or M2 = QFN
Part Type / Lead Finish
F = Commercial / RoHS-Compliant
G = Industrial / RoHS-Compliant
Z = Commercial / RoHS-Compliant, Customer-Specific
4
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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4
Si3219x: ProSLIC® Single FXS Solution • Functional Description
Programmable
AC Impedance
and Hybrid
DTMF
and
DTMF
&
Tone
Gen
Tone Gen
Caller ID
Host Interface
3-wire ISI
Ringing
Ringing
Generator
Generator
CODEC
CODEC
CODEC
SLIC
SLIC
ADC
ADC
Linefeed
Linefeed
Control
Control
DAC
DAC
Linefeed
Linefeed
Monitor
Monitor
Linefeed
2. Functional Description
TIP
FXS
RING
DSP
Line
LineDiagnostics
Diagnostics
PLL
DC-DC Controller
Si3219x
Figure 2.1. Si3219x Functional Block Diagram
The Si3219x series provides all SLIC, codec, DTMF detection, and signal generation functions needed for one complete analog
telephone interface. The Si3219x performs all battery, over-voltage, ringing, supervision, codec, hybrid, and test (BORSCHT) functions;
it also supports extensive metallic loop and self-test capabilities.
The Si3219x supports wideband audio (150 Hz–6.8 kHz) compliant with PKT-SP-HDV-104-120823, and is configurable to support the
full ITU-T-G.722-201209 bandwidth (50 Hz–7 kHz). The wideband mode provides an expanded audio band with a 16 kHz sample rate
for enhanced audio quality.
The Si3219x series supports a 3-wire ISI digital interface.
The Si3219x incorporates a programmable dc-dc converter controller that reacts to line conditions to provide the optimal battery voltage
required for each line-state. Si3219x ICs are available with voltage ratings of –100 V.
Programmable on-hook voltage, programmable off-hook loop current, reverse polarity operation, loop or ground start operation, and
on-hook transmission are supported. Loop current and voltage are continuously monitored by an integrated monitoring ADC.
The Si3219x single ProSLIC devices support ringing with or without a programmable dc offset and can operate in low-power ringing
and adaptive-ringing modes. The available voltage offset, frequency, waveshape, and cadence options are designed to ring the widest
variety of terminal devices and to reduce external controller requirements.
A complete audio transmit and receive path is integrated, including ac impedance and hybrid gain. These features are software-programmable, allowing a single hardware design to meet global requirements.
5
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
3. Electrical Specifications
Table 3.1. Recommended Operating Conditions
Parameter
Ambient Temperature
Symbol
TA
Test Condition
Min
Typ
Max
Unit
F-grade,
Z-grade
0
25
70
°C
G-grade
–40
25
85
°C
Silicon Junction Temperature, High Voltage Die
TJHV
Continuous
—
—
Internally
Limited
°C
Silicon Junction Temperature, Low Voltage Die
TJLV
Continuous
—
—
125
°C
Supply Voltages
VDDD, VDDA
3.13
3.3
3.47
V
Battery Voltage2
VBAT
–100
—
–15
V
IO Supply Voltage
VDDIO
1.71
—
3.47
V
Note:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at nominal
supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. Minimum and maximum battery voltage limits are dependent upon loop conditions and dc-dc converter configuration.
6
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Table 3.2. Power Supply Characteristics
Parameter
Symbol
Supply Currents:
IDD
IVBAT
Reset
Supply Currents:
High Impedance, Open
Supply Currents:
Forward/Reverse, On-hook
Supply Currents:
Forward/Reverse, On-hook
Supply Currents:
Tip/Ring Open, On-hook
Supply Currents:
Tip/Ring Open, On-hook
Supply Currents:
Forward/Reverse OHT, On-hook
Supply Currents:
Forward/Reverse Active, Offhook
Supply Currents:
Ringing
IDD
IVBAT
Test Condition
VT and VR = Hi-Z , RSTB = 0
VT and VR = Hi-Z
Min
Typ
Max
Unit
—
5.13
—
mA
—
—
—
mA
—
11.15
—
mA
—
0.6
—
mA
IDD
VTR = –48 V,
—
11.6
—
mA
IVBAT
Automatic Power Save Mode Enabled
—
0.6
—
mA
IDD
VTR = –48 V,
—
30.44
—
mA
IVBAT
Automatic Power Save Mode Disabled
—
2.1
—
mA
IDD
VT or VR = –48 V
—
11.5
—
mA
—
0.4
—
mA
—
30.6
—
mA
—
1.3
—
mA
—
44.7
—
mA
—
2.9
—
mA
—
44.4
—
mA
—
21.65
—
mA
—
33.8
—
mA
—
24.4
—
mA
IVBAT
IDD
IVBAT
IDD
IVBAT
VR or VT = Hi-Z,
Automatic Power Save Mode Enabled
VT or VR = –48 V
VR or VT = Hi-Z,
Automatic Power Save Mode Disabled
VTR = 48 V
IDD
IVBAT
IDD
IVBAT
ILOOP = 20 mA, RLOAD = 200 Ω
VTR = 55 VRMS + 0 VDC,
low power ringing, sinusoidal,
f = 20 Hz, RLOAD = 3 REN = 2333 Ω
Note:
1. All specifications are for a tracking low-cost capacitive boost dc-dc converter at 25 °C. VDDD, VDDA = 3.3 V; VDC = 12 V.
2. IDD includes IDDIO + IDDD + IDDA.
7
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Table 3.3. AC Characteristics
Parameter
Test Condition
Min
Typ
Max
Unit
2-Wire - PCM
See Figure
3.4 Overload
Compression Performance on
page 14.
—
—
200 Hz to 3.4 kHz (µ-law/A-law)
—
—
–40
dB
200 Hz to 3.4 kHz (16-bit linear)
—
—
–63
dB
200 Hz to 3.4 kHz
See Figure
3.3 Transmit
and Receive
Path SNDR
on page 13.
—
—
46
—
—
dB
—
—
–41
dB
–0.2
—
0.2
dB
TX/RX Performance
Overload Compression
Single Frequency Distortion
Signal-to-(Noise + Distortion) Ratio1
transmit or receive path
Active off-hook, and OHT, any ZT
Audio Tone Generator Signal-toDistortion Ratio1
0 dBm0, Active off-hook, and OHT,
any ZT
Intermodulation Distortion
Gain Accuracy1
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
Attenuation Distortion vs. Frequency
0 dBm 0 5
See Figure 3.5 Receive Path Frequency Response on
page 14 and Figure 3.6 Transmit Path Frequency Response on page 15.
See Figure 3.7 Transmit Group Delay Distortion on page
15 and Figure 3.8 Receive Group Delay Distortion on
page 16.
Group Delay vs. Frequency
1014 Hz sine wave,
—
—
—
—
3 dB to –37 dB
—
—
0.25
dB
–37 dB to –50 dB
—
—
0.5
dB
–50 dB to –60 dB
—
—
1.0
dB
1014 Hz, Within same time-slot
—
450
500
μs
2-Wire Return Loss3
200 Hz to 3.4 kHz
26
30
—
dB
Transhybrid Balance3
300 Hz to 3.4 kHz
26
30
—
dB
C-Message weighted
—
8
14
dBrnC
Psophometric weighted
—
–82
–76
dBmP
RX and TX, 200 Hz to 3.4 kHz
—
55
—
dB
reference level –10 dBm,
Gain Tracking2
Round-Trip Group Delay
Signal level:
Noise Performance
Idle Channel Noise4
PSRR from VDDD, VDDIO @ 3.3 V
Longitudinal Performance
8
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Parameter
Longitudinal to Metallic/PCM Balance (forward or reverse)
Metallic/PCM to Longitudinal Balance
Longitudinal Impedance
Longitudinal Current Capability
Test Condition
Min
Typ
Max
Unit
200 Hz to 1 kHz
—
60
—
dB
1 kHz to 3.4 kHz
—
58
—
dB
200 Hz to 3.4 kHz
—
—
—
dB
200 Hz to 3.4 kHz at TIP or RING
—
50
—
Ω
—
25
—
mA
Active off-hook 60 Hz
Reg 73 = 0x0B
Note:
1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2. The quantization errors inherent in the μ/A-law companding process can generate slightly worse gain tracking performance in the
signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate.
3. VDD = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. 0 dBm 0 is equal to 0 dBm into 600 Ω.
9
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 6, 2021
9
Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Table 3.4. Linefeed Characteristics
Parameter
Symbol
DC Feed Current
DC Loop Current Accuracy
DC Open Circuit Voltage Accuracy
DC Differential Output Resistance
RDO
Test Condition
Min
Typ
Max
Unit
Differential
—
—
45
mA
Common Mode
—
—
30
mA
Differential + Common Mode
—
—
45
mA
ILIM = 18 mA
—
—
10
%
Active Mode; VOC = 48 V,
VTIP – VRING
—
—
4
V
ILOOP < ILIM
160
—
640
Ω
—
—
4
V
IRING < ILIM; VRING wrt ground,
DC On-Hook Voltage AccuracyGround Start (TIP Open)
VOHTO
DC Output Resistance-Ground
Start (TIP Open)
RROTO
IRING < ILIM; RING to ground
160
—
640
Ω
DC Output Resistance-Ground
Start (TIP Open)
RTOTO
TIP to ground
400
—
—
kΩ
Loop Closure Detect Threshold
Accuracy
ITHR = 13 mA
—
—
10
%
Ground Key Detect Threshold
Accuracy
ITHR = 13 mA
—
—
10
%
AC detection, VRING = 70 Vpk,
no offset, ITH = 80 mA
—
—
4
mA
DC detection, 20 V dc offset, ITH
= 13 mA
—
—
1
mA
VRINGING
Open circuit, VBAT = –100 V
–100
—
—
VPK
RTHD
50 VRMS, 0 VOFFSET, 0–5 REN
—
1
—
%
f = 16 Hz to 60 Hz
—
—
1
%
Accuracy of ON/OFF times
—
—
50
ms
Loop Voltage Sense Accuracy
VTIP – VRING = 48 V
—
2
4
%
Loop Current Sense Accuracy
ILOOP = 18 mA
—
7
10
%
Ring Trip Threshold Accuracy
Ringing Amplitude
Sinusoidal Ringing Total Harmonic Distortion
Ringing Frequency Accuracy
Ringing Cadence Accuracy
VRING = –51 V
Table 3.5. Digital I/O Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High-Level Input Voltage
VIH
PSCLK, RSTB, ISI_MOSI
0.7 x VDDIO
—
VDDIO
V
Low-Level Input Voltage
VIL
PSCLK, RSTB, ISI_MOSI
—
—
0.3 x VDDIO
V
High-Level Output Voltage
VOH
ISI_MISO, IO = –4 mA
VDDIO – 0.6
—
—
V
Low-Level Output Voltage
VOL
ISI_MISO, IO = 4 mA
—
—
0.4
V
—
—
10
μA
Input Leakage Current
10
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Table 3.6. Charge Pump Characteristics
Parameter
Symbol
Output Voltage (DCDRV, DCFF)
Output Current
Test Condition
Min
Typ
Max
Unit
VCP
2 x VDDD – 1
—
2 x VDDD
V
ICP
—
—
31
mA
Note:
1. Peak drive current capability is >60 mA.
Table 3.7. Switching Characteristics (General Inputs)
Parameter
Symbol
Min
Typ
Max
Unit
RSTB Pulse Width
tRST
200
—
—
μs
RSTB High to First Register/RAM
Access
tRCS
5
—
—
ms
Note:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDIO – 0.4 V, VIL = 0.4 V. Rise and Fall
times are referenced to the 20% and 80% levels of the waveform.
2. MSIF_LOCK signal on SoC must be active before valid SPI communication.
ISI Interface
tRST
PSCLK
RSTB
tRCS
Register Access
Figure 3.1. Si3219x Reset Timing Diagram
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Table 3.8. Switching Characteristics (ISI)
Parameter
Symbol
Min
Typ
Max
Unit
Setup Time, ISI_MOSI to PSCLK Fall
tsu
7.5
—
—
ns
Hold Time, ISI_MOSI to PSCLK Fall
th
5
—
—
ns
Delay Time, PSCLK Rise to ISI_MISO
td
—
—
16
ns
PSCLK Period
tp
—
40.69
—
ns
40
50
60
%
PSCLK Duty Cycle
Note:
1. Timing should be guaranteed by ISI-enabled host SoC.
tp
PSCLK
tsu
th
ISI_ MOSI
td
ISI_ MISO
Figure 3.2. ISI Timing Diagram
Table 3.9. Thermal Conditions
Parameter
Storage Temperature Range
Thermal Resistance, Typical QFN-381
Symbol
Value
Unit
TSTG
–55 to 150
°C
θJA
35
°C/W
θJC
15
°C/W
Internally Limited
°C
125
°C
Maximum Junction Temperature, (High Voltage Die)3
TJHV
Maximum Junction Temperature (Low Voltage Die)2
TJLV
Test Condition
Continuous
Note:
1. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout guidelines
are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of
at least equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large
internal/bottom copper plane. Thermal resistance values are empirical measurements taken from 2-Layer EVBs.
2. Operation of the Si3219x above 125 °C junction temperature may degrade device reliability.
3. Si3219x linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction temperature
exceeds the thermal shutdown threshold. The thermal shutdown threshold is normally set to 145 °C; when in the ringing state the
thermal shutdown is set to 200 °C.
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Table 3.10. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
VDD, VDDIO
–0.5 to 4.0
V
Digital Input Voltage
VIND
–0.3 to VDDIO + 0.5
V
Battery Supply Voltage
VBAT
+0.4 to 102
V
Tip or Ring Voltage
VTIP, VRING
VBAT – 0.4
V
TIP, RING Current
ITIP, IRING
±100
mA
Supply Voltage
Note:
1. Permanent device damage may occur or the reliability of the device may be affected if the device is operated at or above the
absolute maximum ratings.
Operating Region
Figure 3.3. Transmit and Receive Path SNDR
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Figure 3.4. Overload Compression Performance
Figure 3.5. Receive Path Frequency Response
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Typical Response
Typical Response
Figure 3.6. Transmit Path Frequency Response
Typical Response
Figure 3.7. Transmit Group Delay Distortion
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Typical Response
Figure 3.8. Receive Group Delay Distortion
Typical Response
Figure 3.9. Receive Wideband Frequency Response
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Si3219x: ProSLIC® Single FXS Solution • Electrical Specifications
Typical Response
Figure 3.10. Transmit Wideband Frequency Response
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Si3219x: ProSLIC® Single FXS Solution • FXS Features
4. FXS Features
4.1 DC Feed Characteristics
ProSLIC internal linefeed circuitry provides completely programmable dc feed characteristics.
When in the active state, the ProSLIC operates in one of three dc linefeed operating regions: a constant-voltage region, a constant-current region, or a resistive region, as shown in the figure below. The constant-voltage region has a low resistance, typically 160 Ω. The
constant-current region approximates infinite resistance.
VTR(V)
Constant-V
Region
VOC
Resistive
Region
VRES
VILIM
e=
slop
0
Constant-I
Region
OP
RLO
IRES
ISC
ILOOP(mA)
Figure 4.1. Dual ProSLIC DC Feed Characteristics
4.2 Linefeed Operation States
The linefeed interface includes eight different register-programmable operating states as listed in Table 4.1 Linefeed Operating States
on page 19. The Open state is the default condition in the absence of any preloaded register settings. The device may also
automatically enter the open state in the event of a linefeed fault condition.
4.3 Line Voltage and Current Monitoring
The ProSLIC continuously monitors the TIP, RING, and battery voltages and currents via an on-chip Monitor ADC and stores the
resulting values in individual RAM locations. Additionally, VTIP, VRING, loop current, and longitudinal current values are calculated
based on the differential and common mode voltage measurements. The ADC updates all registers at a rate of 2 kHz or greater.
4.4 Power Monitoring and Power Fault Detection
The Si3219x line monitoring functions are used to continuously protect against excessive power conditions.
If the Si3219x detects an overpower condition, it automatically sets that device to the open state and generates a "power alarm"
interrupt.
The interrupt can be masked, but masking the automatic transition to open is not recommended since it is used to protect the Si3219x
HVIC under excessive power conditions.
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Si3219x: ProSLIC® Single FXS Solution • FXS Features
4.5 Thermal Overload Shutdown
If the die temperature exceeds the maximum junction temperature threshold, TJmax, of 145 °C or 200 °C (depending on the operating
state), the device has the ability to shut itself down to a low-power state without user intervention. A thermal alarm interrupt is generated
to notify host that the device has been switched to open state.
Table 4.1. Linefeed Operating States
Linefeed State
Description
Open
Output is high-impedance and audio is not transmitted. This is the default state after powerup or following
a hardware reset. This state can also be used in the presence of line fault conditions and to generate
open switch intervals (OSIs). This state is used in line diagnostics mode as a high impedance state
during linefeed testing. A power fault condition may also force the device into the open state.
Forward Active
Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more positive than the
RING lead; in Reverse Active state, the RING lead is more positive than the TIP lead.
Reverse Active
Forward OHT
Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID data between
ringing bursts). Linefeed circuitry and audio are active. In Forward OHT state, the TIP lead is more
positive than the RING lead; in Reverse OHT state, the RING lead is more positive than the TIP lead.
Reverse OHT
TIP Open
Provides an active linefeed on the RING lead and sets the TIP lead to high impedance (≥400 kΩ) for
ground start operation in forward polarity. Loop closure and ground key detect circuitry are active.
RING Open
Provides an active linefeed on the TIP lead and sets the RING lead to high impedance (≥400 kΩ) for
ground start operation in reverse polarity. Loop closure and ground key detect circuitry are active.
Ringing
Drives programmable ringing signal onto TIP and RING leads with or without dc offset.
4.6 Loop Closure Detection
The Si3219x provides a completely programmable loop closure detection mechanism. The loop closure detection scheme provides two
unique thresholds to allow hysteresis, and also includes a programmable debounce filter to eliminate false detection. A loop closure
detect status bit provides continuous status, and a maskable interrupt bit is also provided.
4.7 Ground Key Detection
The Si3219x provides a ground key detect mechanism using a programmable architecture similar to the loop closure scheme. The
ground key detect scheme provides two unique thresholds to allow hysteresis and also includes a programmable debounce filter to
eliminate false detection. A ground key detect status bit provides continuous status, and a maskable interrupt bit is also provided.
4.8 Ringing Generation
The Si3219x supports the patented Low-Power Ringing (LPR) method exclusively, which when used with a tracking battery scheme,
maximizes the ringing power transfered to the load and reduces overall power consumption. Ringing is fully programmable including
frequency, amplitude, dc offset, wave shape and crest factor. The Si3219x also supports automatic ring cadencing and ringtrip detection
(AC and DC).
Balanced
GND
TIP
RING
VBAT
Unbalanced
GND
TIP
LPR
GND
TIP
RING
VBAT
RING
VBAT
Figure 4.2. Ringing Mode
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Si3219x: ProSLIC® Single FXS Solution • FXS Features
4.9 Polarity Reversal
The Si3219x supports polarity reversal for message waiting and various other signaling modes. The ramp rate can be programmed for
a smooth or abrupt transition to accommodate different application requirements.
4.10 Two-wire Impedance Synthesis
The ac two-wire impedance synthesis is generated on-chip using a DSP-based scheme to optimally match the output impedance
of the Si3219x to the reference impedance. Most real or complex two-wire impedances can be generated with appropriate register
coefficients.
4.11 Transhybrid Balance Figure
The trans-hybrid balance function is implemented on-chip using a DSP-based scheme to effectively cancel the reflected receive path
signal from the transmit path.
4.12 Tone Generators
The Si3219x includes two digital tone generators that allow a wide variety of single- or dual-tone frequency and amplitude combinations. Each tone generator has its own set of registers that hold the desired frequency, amplitude, and cadence to allow generation of
DTMF and call progress tones for different requirements. The tones can be directed to either receive or transmit paths.
4.13 DTMF Detection (Si32193 Only)
In DTMF, two tones generate a DTMF digit. One tone is chosen from four possible row tones, and one tone is chosen from four possible
column tones. The sum of these tones constitutes one of 16 possible DTMF digits.
4.14 Pulse Metering
The pulse metering system for the Si3219x is designed to inject a 12 or 16 kHz billing tone into the audio path with maximum amplitude
of 0.85 VRMS at TIP and RING into a 200 Ω ac load impedance. The tone is generated in the DSP via a table lookup that guarantees
spectral purity by not allowing drift. The tone will ramp up until it reaches a host-programmed threshold, at which point it will maintain
that level until instructed to ramp down, thuscreating a trapezoidal envelope.
The amplitude is controlled by an automatic gain control circuit (AGC). While the tone is ramping up, the AGC takes the feedback audio
and applies it to a band pass filter, which is programmed for the 12 or 16 kHz frequency of interest. When the peak is detected, the
ramp is stopped.
4.15 DC-DC Controller
The Si3219x-C devices integrate a dc-dc controller to control an external tracking dc-dc converter which generates the high voltage
supply (VBAT) to the SLIC. The tracking VBAT voltage generated from a single positive dc input is optimized to minimize power
consumption by closely tracking the SLIC state, even tracking the ringing waveforms.
The dc-dc controller output DCDRV is driven by an internal charge pump which allows it to connect directly to the gate of the MOSFET
switch of the dc-dc converter. This eliminates the need for the MOSFET predrive circuit that is typically required when other SLICs are
used with a MOSFET with VTH greater than VDDD. See Table 3.6 Charge Pump Characteristics on page 11.
4.16 Wideband Audio
The Si3219x supports wideband audio (150 Hz–6.8 kHz) compliant with PKT-SP-HDV-104-120823, and is configurable to support the
full ITU-T-G.722-201209 bandwidth (50 Hz–7 kHz). The wideband provides an expanded audio band at a 16-bit, 16 kHz sample rate
for enhanced audio quality while maintaining standard telephony audio compatibility. Wideband audio samples are transmitted and
received at an effective 16 kHz rate by using multiple timeslots in a single 8 kHz frame.
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Si3219x: ProSLIC® Single FXS Solution • FXS Features
4.17 Test Facilities
The Si3219x supports a rich set of metallic loop tests to diagnose external faults, as well as a set of inward self-tests to support
diagnostics of the Si3219x-based voice port. Implementation of metallic loop tests required the ProSLIC® MLT API, while the inward
self-tests are included in the standard ProSLIC® API.
Table 4.2. Supported Tests
Test
Description
Metallic Loop Tests
Voltages
Measures ac and dc voltages from T-R, T-G, and R-G.
Receiver Off-hook
Discriminates between resistive fault and off-hook terminating device.
REN
Measures Ringer Equivalence Number (REN).
REN Capacitance
Measures T-R capacitance of on-hook load.
Capacitance
Measures 3-Terminal Capacitance.
Resistance
Measures resistance from T-R, T-G, or R-G.
Inward Self-Tests
PCM Loopback
Configures Si3219x for 8- or 16-bit PCM loopback.
DC Feed
Verify dc Feed I/V and loop closure using integrated test load.
Ringing and Ringtrip
Verify ringing voltage (ac and dc). Optional ringtrip check to support system level signaling verification.
Battery
Verify VBAT.
Audio Gain
Measure gain of RX (host to line) and TX (line to host) paths without using an external
load, test equipment, or requiring the host to provide audio samples.
In addition to these specific test suites, the user is free to use the general test facilities listed in the following table:
Table 4.3. General Test Facilities
Test
Description
Monitor ADC
Provides TIP/RING voltages (inside and outside overcurrent protection), TIP/RING currents and VBAT voltage.
Audio Diagnostic Filters
Three cascaded second-order Biquad filters with peak hold and averaging capabilities.
Loopback Modes
Digital and analog loopback modes to isolate portions of the audio path.
Tone Generators
The dual-tone generators may be used as general-purpose test signal generators.
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Si3219x: ProSLIC® Single FXS Solution • System Interfaces
5. System Interfaces
5.1 Integrated Serial Interface
The ISI interface supported on select Si3219x devices is a three-wire proprietary interface which serializes SPI and PCM communications and interrupts, reducing the SoC interface from nine wires to three (PSCLK, ISI_MISO, ISI_MOSI). SPI communications and PCM
data transfers are embedded in the serial data. The host side of the ISI is integrated onto selected SoCs from several vendors.
ISI is a point to point interface; therefore, it is not possible to daisy-chain more than one ISI ProSLIC device.
Both µ-255 Law (μ-Law) and A-law companding formats are supported in addition to 16-bit linear data mode with no companding.
5.2 Input/Output Voltage Selection
The digital host interface I/O (ISI) on the Si3219x may directly interface to 1.8 V to 3.3 V devices. The I/O voltage selection is made by
supplying the VDDIO pin with the appropriate I/O supply voltage.
To avoid power supply sequencing issues, VDDIO should be connected to the same supply as VDD in 3.3 V interface designs. Other
voltages between 1.8 V and 3.3 V can also be used for VDDIO (for example 2.5 V), but steps must be taken to ensure that the VDDIO
supply comes up after the VDD supply if VDDIO is not connected to VDD.
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Si3219x: ProSLIC® Single FXS Solution • Pin Descriptions
6. Pin Descriptions
TIP
NC
RING
NC
VBAT
NC
VDDHV
6.1 Pin Descriptions: 38 Pin QFN (Si32192/3)
38
37
36
35
34
33
32
NC 1
31 STIPC
NC 2
30 SRINGC
NC 3
29 SRINGDC
VDDIO 4
28 SRINGAC
27 STIPAC
GND 5
PSCLK 6
26 STIPDC
EPAD
GND 7
25 VDDA
ISI_MISO 8
24 GND
ISI_MOSI 9
23 IREF
22 CAPM
NC 10
13
14
15
16
17
18
19
VDDD
VDDREG
RSTB
SVBAT
20 GND
SDCH
NC 12
SDCL
21 CAPP
DCDRV
DCFF 11
Table 6.1. Si3219x Pin Descriptions
23
Pin #
Pin Name
1
NC
2
NC
3
NC
4
VDDIO
5
GND
6
PSCLK
7
GND
Description
No connection.
This pin should be left unconnected.
No connection.
This pin should be left unconnected.
No connection.
This pin should be left unconnected.
Digital IO Supply Voltage.
3.3 V or 1.8 V digital power supply for internal circuitry.
Ground.
Connect to ground.
ISI Bus Clock Input.
Clock input for ISI bus timing.
Ground.
Connect to ground.
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Si3219x: ProSLIC® Single FXS Solution • Pin Descriptions
24
Pin #
Pin Name
8
ISI_MISO
9
ISI_MOSI
10
NC
11
DCFF
12
NC
13
DCDRV
14
SDCL
15
SDCH
16
VDDD
17
VDDREG
18
RSTB
19
SVBAT
20
GND
21
CAPP
22
CAPM
23
IREF
24
GND
25
VDDA
26
STIPDC
Description
Transmit ISI Output.
ISI Master Input, Slave Output. Output data to ISI bus.
Transmit ISI Input.
ISI Master Output, Slave input. Input data from ISI bus.
No connection.
This pin should be left unconnected.
DC-DC Charge Pump Output.
No connection.
This pin should be left unconnected.
DC Drive.
DC-DC converter control signal output which drives external transistor.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the converter.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the converter.
IC Voltage Supply.
3.3 V digital power supply for internal circuitry.
Regulated Core Power Supply.
Reset Input.
Active low input. Hardware reset used to place all control registers in the default state.
VBAT Sense.
Input used to sense voltage on DC-DC converter output voltage lead.
Ground.
Connect to ground.
SLIC Stabilization Capacitor.
Capacitor used in dc feed low-pass filter.
SLIC Stabilization Capacitor.
Capacitor used in dc feed low-pass filter.
Current Reference Input.
Connects to an external resistor used to provide a high accuracy reference current.
Ground.
Connect to ground.
Analog Supply Voltage.
Analog 3.3 V power supply for internal analog circuitry.
TIP DC Sense.
Analog DC input used to sense voltage on TIP lead.
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Si3219x: ProSLIC® Single FXS Solution • Pin Descriptions
25
Pin #
Pin Name
27
STIPAC
28
SRINGAC
29
SRINGDC
30
SRINGC
31
STIPC
32
VDDHV
33
NC
34
VBAT
35
NC
36
RING
37
NC
38
TIP
—
EPAD
Description
TIP AC Sense.
Analog AC input used to sense voltage on TIP lead.
RING AC Sense.
Analog AC input used to sense voltage on RING lead.
RING DC Sense.
Analog DC input used to sense voltage on RING lead.
RING Coarse Sense Input.
Voltage sensing outside protection circuit.
TIP Coarse Sense Input.
Voltage sensing outside protection circuit.
Analog Supply Voltage.
Analog 3.3 V power supply for internal analog circuitry.
No connection.
This pin should be left unconnected.
Battery Voltage Supply.
Connect to battery supply from DC-DC converter.
No connection.
This pin should be left unconnected.
RING Terminal.
Connect to the RING lead of the subscriber loop.
No connection.
This pin should be left unconnected.
TIP Terminal.
Connect to the TIP lead of the subscriber loop.
Exposed paddle.
Connect to ground.
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Si3219x: ProSLIC® Single FXS Solution • Package Outline
7. Package Outline
7.1 Package Outline: 38-Pin QFN
The figure below illustrates the package details for the Si3219x in a 38-pin QFN package. The table below lists the values for the
dimensions shown in the illustration.
Figure 7.1. 38-Pin QFN Package
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Si3219x: ProSLIC® Single FXS Solution • Package Outline
Table 7.1. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
A3
0.20REF
b
0.18
0.20
0.25
D
3.90
4.00
4.10
D2
2.50
2.60
2.70
e
0.40 BSC.
E
5.90
6.00
6.10
E2
4.50
4.60
4.70
L
0.30
0.40
0.50
aaa
—
—
0.10
bbb
—
—
0.07
ccc
—
—
0.10
ddd
—
—
0.05
eee
—
—
0.08
fff
—
—
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si3219x: ProSLIC® Single FXS Solution • Land Pattern
8. Land Pattern
8.1 Land Pattern: 38-Pin QFN
The figure below shows the recommended land pattern details for the 38-Pin QFN package. The table below lists the values for the
dimensions shown in the illustration.
Figure 8.1. 38-Pin QFN Land Pattern
28
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Si3219x: ProSLIC® Single FXS Solution • Land Pattern
Table 8.1. PCB Land Pattern
Dimension
mm
C1
4.00
C2
6.00
e
0.40
X1
0.20
Y1
0.80
X2
2.70
Y2
4.70
Note:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
4. A 4x3 array of 0.85 mm square openings on 1.2 mm pitch should be used for the center ground pad to achieve a target solder
coverage of ~50%.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
29
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Si3219x: ProSLIC® Single FXS Solution • Top Marking
9. Top Marking
9.1 Top Marking 38-pin QFN
Figure 9.1. 38-Pin QFN Top Marking
Table 9.1. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Circle = 0.50 mm Diameter (BottomLeft-Justified)
Font Size
0.60 mm Right-Justified
Line 1 Mark Format:
Device Part Number
Si32192FM1
Line 2 Mark Format:
YY = Year
Manufacturing Code from the Assembly Purchase Order
form.
WW = Work Week
Line 3 Mark Format:
TTTTTT = Mfg Code
Assigned by the Assembly House. Corresponds to the
year and work week of the assembly release.
Circle = 1.0 mm Diameter
"e3" Pb-Free Symbol
Center-Justified
TH, TW, or CN
CC = Country of Origin ISO Code
Abbreviation
30
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Si3219x: ProSLIC® Single FXS Solution • Revision History
10. Revision History
Revision 1.0
June, 2018
• Updated Table 3.2 Power Supply Characteristics on page 7.
• Updated Table 3.3 AC Characteristics on page 8.
• Updated Idle Channel Noise specification.
• Numerous clarifications throughout.
Revision 0.9
April, 2017
• Initial revision.
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