SI3220PPT-EVB

S i 3 2 2 0 P P T- E V B E V A L U A T I O N B O A R D F O R T H E S i3220 D U A L P R O S LIC Description This document describes the operation of the Silicon Laboratories Si3220 Dual ProSLIC™ device evaluation platform. The Dual ProSLIC evaluation platform is designed to provide observation of the ProSLIC’s functionality. The Dual ProSLIC platform consists of a ProSLIC motherboard, an Si3220 daughter card (Si3220DC0-EVB), and the ProSLIC LINC™ software. The ProSLIC LINC software is a GUI-based program that can run in Microsoft Windows® environments. Equipment requirements: PC running Windows 95, 98, ME, NT, or 2000 5 V, 1 A power supply 3 V, 1 A power supply (optional) –24 V, 0.5 A power supply –75 V, 0.5 A power supply Balanced audio generator and analyzer (optional) (e.g., Audio Precision System 2 and/or HP TIMS set and/or Wandel and Goltermann PCM-4) Features Silicon Laboratories Dual ProSLIC device Stackable cards for up to 16 channels All components necessary for linecard implementation Layout for optional secondary protections Control I/O through standard parallel port On-board oscillator for stand-alone operation PCM I/O set up for Audio Precision System 2 or Wandel and Goltermann PCM-4 Full access to PCM highway ProSLIC power selection (3 V or 5 V) 8 kHz PCM signal generator and analyzer (optional) (e.g., Audio Precision System 2 and Audio Precision SIA-2322 and/or Wandel and Goltermann PCM-4) Function Block Diagram VBHI, VBLO, +3 V, +5 V Power In Parallel Port PCM Transmit Si3220 Si3200 PCM Receive Si3200 Si3220DC0-EVB Rev. 1.2 4/03 Copyright © 2003 by Silicon Laboratories Si3220PPT-EVB-12 S i3220PPT-EVB ProSLIC LINC Evaluation Software The ProSLIC LINC software is an executable program that allows control and monitoring of the ProSLIC. It utilizes the primary LPT port of a standard PC to communicate to the ProSLIC’s SPI port. To install the software, insert the Silicon Laboratories ProSLIC CD into the computer. The setup routine can be invoked by running the setup.exe program in the root directory of the CD. Invoking the ProSLIC LINC is achieved by double clicking the ProSLIC LINC icon. Refer to the ProSLIC LINC User Guide for software operation. PCLK and FS signals. The DIP switch (S2) sets the PCLK frequency and controls the FS enable. See Table 1 for S2 settings. JP3 and JP4 select this internal clock source or an external PCM clock source. The ProSLIC motherboard has been designed to directly connect to an Audio Precision SIA-2322 Serial Interface Adapter through the 15 pin d-connectors P2 and P3. See Table 2 for the Audio Precision settings. The ProSLIC evaluation board has also been designed to interface with a Wandel and Goltermann PCM-4 through J8, J9, J10, and J11. See Table 3 for PCM-4 settings. A header, J5, allows access to the ProSLIC’s PCM signals for connection to other PCM testing devices or an actual telephone system PCM bus. TIP and RING of the two-wire analog interface is present at the RJ-11 connectors, J1 and J11 of the Dual ProSLIC daughter card. The schematics of the ProSLIC motherboard are found in Figures 8, 9, and 10. Figure 8 shows the connections from the motherboard to the daughter card. Figure 9 illustrates the LPT port connection to the SPI drivers. The PCM highway and LED indicators are shown in Figure 10. The ProSLIC evaluation board is voltage programmable with specific jumper settings. JP1 selects 3 V or 5 V ProSLIC operation. JP2 selects 3 V or 5 V PCM source level compatibility. These should be placed on the expected setting. Power is connected to the ProSLIC at J2, J3 and J4. The 5 V is always required for the buffers, U2 and U3, to interface to the parallel port. The ProSLIC can be powered from 5 V or 3 V with the placement of a jumper on JP1. The Protection Return connections on J6 should be connected to an appropriate ground for TIP/RING fault testing. This return is tied to signal ground on-board though it has a dedicated trace for high current conditions. Serial control of the ProSLIC is achieved by toggling select bits of a standard parallel port. The parallel port connection is available at P1 and J1. Multiple dual ProSLIC cards can be daisy-chained by stacking the cards. Stack up to eight cards by aligning JS1–JS5 and pressing together. The ProSLIC LINC Software allows channel selection for RAM and register manipulation. Si3220PPT-EVB Dual ProSLIC Evaluation Board Description The schematics for the Dual ProSLIC evaluation daughter card are shown in Figures 1 through 4. The schematic in Figure 1 shows the Dual ProSLIC linecard implementation. All circuitry pertaining to the telephony function of the Dual ProSLIC is found here. Figure 2 contains a number of options for secondary fault protection. Secondary protection components can be selected for a given level of protection against expected faults. Figure 3 is the schematic that describes the serial control interface, PCM interface, daisy chain ports, and power supply filtering and connections. These schematics represent typical linefeed components for the ProSLIC. Figure 4 is the circuit for an optional third battery switch. This circuit should be installed for testing with medium length loops where VBATL and VBATH may be used as off-hook batteries and VBATR is maximized for ringing. Follow the instructions on this schematic page to change the hardware. To change the battery switch logic to use the ringing battery, perform the following steps in the LINC software: 1. Click “User Mode” on. 2. Write RLYCON=0x3B. 3. Click “User Mode” off. The layout of the Dual ProSLIC evaluation daughter card is found in Figures 5, 6, and 7. Figure 5 shows the component placement while Figures 6 and 7 show the two layers of component interconnect. For optimum thermal performance of the Si3200, the daughter card has inner VDD and GND layers. These layers are omitted from the figures in this data sheet. The signal flow is digital PCM on the left to two-wire analog on the right. Signal requirements for ProSLIC operation are PCLK (PCM clock), FS (frame sync), and Serial IO. The ProSLIC motherboard has a local oscillator with a programmable logic device to provide the ProSLIC 2 Rev. 1.2 S i3220PPT-EVB Si3220PPT-EVB Dual ProSLIC Evaluation Platform Setup To prepare the Dual ProSLIC evaluation platform for use, perform the following steps: 1. Set power supplies to 3.3 V, 5 V, –24 V, and –75 V. 2. With these supplies off, connect them to J2, J3, and J4 corresponding to the silk screen designators. 3. Connect the PC’s parallel port (LPT1) to P1 (or J1) using a 25 pin D male-to-male cable. 4. Select the on-board PCM clock source or select external PCM source with JP3, JP4 and connect an Audio Precision SIA-2322 to P2 and P3 or a Wandel and Goltermann PCM-4 to J8, J9, J10, and J11. 5. TIP/RING connection can be made from the RJ-11s to a phone or telephony test equipment. 6. Invoke the ProSLIC LINC software. 7. Turn the power supplies on and press the ProSLIC motherboard reset button (S1). 8. Click the “Reinitialize” button in the ProSLIC LINC software panel. The Dual ProSLIC is now ready to perform its linecard function. To achieve an end-to-end connection with 600 Ω: 1. Verify that R11 is shorted. 2. Click RESET. 3. Click REINITIALIZE. 4. Click REGISTER SET. 5. Click Broadcast box. 6. Write “1” to LINEFEED register. This connects the evaluation platform end-to-end per daughter card RF-11 connector pairs. Table 1. On-Board PCLK Settings (S2) S2-1,2,3 PCLK frequency 0,0,0 = 8.192 MHz 0,0,1 = 4.096 MHz 0,1,0 = 2.048 MHz 0,1,1 = 1.024 MHz 1,x,x = 512 kHz Note: 1 = on. S2-4 unused x S2-5 unused x S2-6 unused x S2-7 unused x S2-8 FS enable 0 = FS disabled 1 = FS enabled Table 2. Audio Precision SIA-2322 DIP Switch Setting Receiver Mode 10111001 00000110 01111101 01111001 1000001 Transmitter Mode 00000110 01111101 01111001 Note: 256 kHz PCLK and 8 kHz FS. Table 3. Wandel and Goltermann PCM-4 Settings General Configuration General Configuration General Configuration General Configuration General Configuration 2.14 3.13 4.13 7.12 7.22 For µ-law add the following: Rev. 1.2 3 6 5 4 3 2 1 RJ-11 SMD 1 TP2 VBATa 1 U1 C3 10n 100V TP5 TP6 TP7 TP8 C4 10n 100V 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 STIPDCa STIPACa SRINGACa SRINGDCa ITIPNa IRINGNa ITIPPa VDD1 GND1 IRINGPa THERMa NC NC TRD1a TRD2a BATSELa 1 1 1 1 R11 C11 C12 VDD J11 402k J5 0.1u 100V X7R 0.1u 100V X7R 402k R13 R14 4.7k GPOb 4.7k GPOb 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 STIPDCb STIPACb SRINGACb SRINGDCb ITIPNb IRINGNb ITIPPb VDD2 GND2 IRINGPb THERMb NC TRD1b TRD2b GPOb BATSELb 1 1 4 TP1 J1 Protection TIPa_ext TIPa TIPa RINGa U2 Si3200 VDD VDD RINGa_ext RINGa C32 0.1u 100V VBATH C30 0.1u 100V VBLO C2 C1 0.1u 100V X7R 0.1u 100V X7R 402k R4 R3 4.7k J2 4.7k S i3220PPT-EVB 1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL GND 16 15 14 13 12 11 10 9 epad R2 BATSWa R6 40.2k BATSELa 402k 1 2 J3 TRD1a R1 1 2 J4 TRD2a 1 2 GPOa R5 R8 R7 C5 1u 6V C15 1u 6V C6 1u 6V R10 C16 1u 6V R17 R18 R15 806k 182 182 40.2k 182 182 806k C13 10n 100V C14 10n 100V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb Si3220 GPOa /CS SDITHRU SDI SDO SCLK VDD4 GND4 /INT PCLK GND3 VDD3 DTX DRX FSYNC /RST 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GPOa /CS SDITHRU SDI SDO SCLK /INT PCLK DTX DRX FSYNC /RESET GPOa Rev. 1.2 TP3 1 2 J6 GPOb 1 2 J7 TRD2b R12 Protection TIPb_ext TIPb TIPb RINGb U3 Si3200 6 5 4 3 2 1 RJ-11 SMD RINGb_ext RINGb TP4 VBATb C33 0.1u 100V VBATH C31 0.1u 100V VBLO 1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL GND 16 15 14 13 12 11 10 9 epad 1 2 TRD1b BATSWb R16 40.2k BATSELb Figure 1. Si3220DC-EVB Evaluation Circuit (1 of 4) RF1 1 2 F1250T RF5 TIPa_ext NI TS250-130-RA Optional* D3 NI P0901SC Optional* RV1 U4 TIPA c 1 1 2 3 4 2 C36 0.1u 100V VBPROT C37 0.1u 100V D4 NI P0901SC Optional* 8 7 6 5 TIP NC 6 5 4 K1 A A K2 K1 G NC K2 VREF GND RING B1101UC Optional* 3 NC c TISP61089B RF6 RINGa_ext NI TS250-130-RA Optional* RF2 RINGA 1 2 F1250T RF11 1 2 F1250T RF15 TIPb_ext NI TS250-130-RA Optional* D13 NI Optional* P0901SC RV2 U5 TIPB c 1 1 2 3 4 2 C38 0.1u 100V VBPROT C39 0.1u 100V D14 NI Optional* P0901SC 8 7 6 5 TIP NC 6 5 4 K1 A A K2 K1 G NC K2 VREF GND RING B1101UC Optional* 3 NC c TISP61089B RF16 RINGb_ext NI TS250-130-RA Optional* RINGB RF12 Rev. 1.2 5 1 2 F1250T * Optional protection devices: Battery tracking over voltage protection devices are required when using maximum battery voltage on Si3200. Fixed voltage thyristor protection devices, D3, D4, D13, D14 can be used in certain cases. The selection of the thyristor device voltage depends on the required battery voltage for ringing. The maximum clamp voltage for the device must be under the Si3200 maximum voltage. The minimum clamping voltage of the device must be above the maximum battery voltage. For example, the Teccor P0901SC is shown for applications that operate from a maximum negative battery of -72V. Over current devices should be selected for application requirements and over voltage protection device current limitations. Figure 2. Si3220DC-EVB Evaluation Circuit (protection) (2 of 4) S i3220PPT-EVB 10 8 6 4 2 DTX PCLK FSY NC DRX 4 2 JS2 2 4 JS1 10 8 6 4 2 4 2 AUX Cntl 9 7 5 3 1 3 1 9 7 5 3 1 3 1 1 3 CONN SOCKET 5x2 CONN SOCKET 2x2/SM 1 3 2 4 1 3 5 7 9 2 4 6 8 10 1 3 5 7 9 Thermal pad vias 2 4 6 8 10 6 JP2 SDO /CS 12 34 56 78 9 10 SCLK SDI JP1 CONN HEADER 2x2/SM (Farside) SDITHRU VDD 1 3 5 7 9 1 3 5 7 9 VBLO VBHI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDO SCLK /CS /INT PCLK DRX DTX FSYNC /RESET SDI JS4 2 4 6 8 10 2 4 6 8 10 JS3 9 7 5 3 1 9 7 5 3 1 10 8 6 4 2 10 8 6 4 2 VBRNG CONN SOCKET 5x2 CONN SOCKET 5x2 JS5 S i3220PPT-EVB Rev. 1.2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 CONN SOCKET 5x2 VDD C20 0.1u VBLO C21 0.1u C22 0.1u C23 0.1u C24 0.1u C25 0.1u C34 0.1u 100V C35 0.1u 100V Figure 3. Si3220DC-EVB Evaluation Circuit (interconnect) (3 of 4) D1 VBATa NI DL4003 R103 VBHI R102 10k CXT5401 Q2 402k Q1 CXT5551 For three battery operation: a) Install the switch components for both channels as described at left side of this schematic page. b) Move zero Ohm resistor from R120 to R121 c) Move 40.2kOhm resistors from R6 and R16 and place them in R9 and R19. R120 R121 * R101 NI VBHI 0 NI VBRNG * VDD R101/R111 3V 2.4k 5V 3.9k D100 BATSELa BATSELb VBATH DL4003 * Rev. 1.2 D11 VBATb NI DL4003 R111 NI CXT5401 Q3 BATSWa VBPROT R9 GPOa NI R112 10k R113 BATSWb 402k Q4 CXT5551 VBHI NI R19 GPOb S i3220PPT-EVB Figure 4. Si3220DC-EVB Evaluation Circuit Third Battery (4 of 4) 7 S i3220PPT-EVB Bill of Materials Table 4. Si3220DC0-EVB Application Circuit Component(s) C1, C2, C11, C12 C3, C4, C13, C14 C5, C15 C6, C16 C30–C33 C20–C25 R1, R2, R11, R12 R3, R4, R13, R14 R5, R15 R6, R16 R7, R8, R17, R18 R10 Value 100 nF, 100 V, X7R, ±20% 10 nF, 100 V, X7R, ±20% 1 µF, 6.3 V, X7R, ±20% 1 µF, 6.3 V, X7R, ±20% 0.1 µF, 100 V, Y5V 0.1 µF, 10 V, Y5V 402 kΩ, 1/10 W, ±1% 4.7 kΩ, 1/10 W, ±1% 806 kΩ, 1/10 W, ±1% 40.2 kΩ, 1/10 W, ±5% 182 Ω, 1/10 W, ±1% 40.2 kΩ, 1/10 W, ±1% Function Filter capacitors for TIP, RING ac sensing inputs. TIP/RING compensation capacitors. Low pass filter capacitors to stabilize common mode SLIC feedback loops. Low pass filter capacitors to stabilize differential SLIC feedback loops. Decoupling for battery voltage supply pins. Decoupling for analog and digital chip supply pins. Sense resistors for TIP and RING voltage sensing nodes. Sense resistors for TIP, RING ac sensing inputs. Sense resistor for battery voltage sensing nodes. Sets bias current for battery switching circuit. Bias resistors for internal transconductance amplifier. Generates a high accuracy reference current. Table 5. Si3220DC0-EVB Protection Circuit Component(s) C36–C39 D3, D4,D13,D14* RF1, RF2,RF11,RF12 RF5, RF6,RF15,RF16* RV1,RV2,U4,U5 Description 0.1 µF, 100 V, Y5V Teccor P0721SC transient voltage suppressor Teccor F1250T, 250 V/1.25 A, TeleLink fuse Raychem TS-250-130-RA resettable fuse Teccor B1101UC Dual Negative BATTRAX SLIC Protector or Bourns TISP61089B Function/Comments Decoupling for B1101UC and TISP61089B. Overvoltage protection (optional). Overcurrent protection. Overcurrent protection PTC (optional). Battery-tracking overvoltage protection. *Note: Optional protection components not used on Si3232DC0-EVB. Usage depends on application. 8 Rev. 1.2 Rev. 1.2 9 Figure 5. Si3220DC-EVB Silkscreen S i3220PPT-EVB 10 Rev. 1.2 S i3220PPT-EVB Figure 6. Si3220DC-EVB Component Side Rev. 1.2 11 Figure 7. Si3220DC-EVB Solder Side S i3220PPT-EVB 4 2 JS1 10 8 6 4 2 10 8 6 4 2 4 2 9 7 5 3 1 3 1 9 7 5 3 1 3 1 Power, Ground 1 3 5 7 9 1 3 5 7 9 Figure 8. ProSLIC Motherboard (ProSLIC IF) 2 4 6 8 10 2 4 6 8 10 12 Power LPT Port JS2 JS3 CONN SOCKET 2x2 9 7 5 3 1 9 7 5 3 1 10 8 6 4 2 10 8 6 4 2 CONN SOCKET 5x2 +VIN SPI 2 4 6 8 10 JS4 2 4 6 8 10 1 3 5 7 9 1 3 5 7 9 VBLO VBHI JS5 CONN SOCKET 5x2 VDD S i3220PPT-EVB External PCM SDI DIN TEST SDO SCLK /CS /INT DOUT PCLK DRX DTX FSYNC /RESET CONN SOCKET 5x2 VBRNG VRNGSOURCE JS3 PCM CONN SOCKET 5x2 ProSLIC Motherboard Rev. 1.2 VDD +5V R1 R2 R3 8 7 6 5 8 7 6 5 U1 /RESET TEST /CS SDI DIN SCLK VDD 13 14 15 16 17 18 19 20 21 22 23 24 GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB 4245A 100 pF GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 12 11 10 9 8 7 6 5 4 3 2 1 S1 Reset Push Button 200k 8 7 6 5 200k 1 2 3 4 1 2 3 4 TP D6 TP D5 /RESET TEST /CS SDI DIN SCLK 1 2 3 4 P1 /RST /CS_IN SDI_IN SCLK_IN /STROBE /AUTOFD D0 ERROR D1 INIT D2 /SELECT D3 D4 D5 D6 D7 /ACK BUSY PAPEREND SELECT 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25F Parallel port R6 C1 470 C2 0.1 uF 6Vmin D7 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 OUT_EN DIN D5 D6 TEST_IN 2 4 6 8 10 12 14 16 18 20 22 24 26 Two Package Widths 8 7 6 5 8 7 6 5 R7 R5 10k U2 NI R4 10k 1 2 3 4 1 2 3 4 DTX DOUT SDO /INT TEST DTX DOUT SDO /INT TEST 13 14 15 16 17 18 19 20 21 22 23 24 GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB 4245A GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 12 11 10 9 8 7 6 5 4 3 2 1 SPARE DIGITAL OUT SDO_OUT /INT_OUT TEST _OUT HEADER 13X2 Parallel Port Hdr Ringing Battery High Battery Low Battery Common Common Common Two Package Widths +3V +5V +Vin SDO_OUT VRNGSOURCE NC RNG Source Return Protection Return Protection Return Protection Return 1 2 3 3 21 EMI Filt D1 Zener 6.8V C12 0.1 uF 6Vmin C13 100uF 10Vmin 1 23 EMI Filt C14 100uF 10Vmin D2 Zener 6.8V J5 J6 1 2 3 Rev. 1.2 13 1 2 3 1 2 3 J2 +3V VBRNG VBHI L1 VBLO J3 J4 +5V 1 2 3 CON3 CON3 CON3 +VIN +5V VDD C3 +5V VDD +3V JP1 1 2 3 1-2 : 3V operation 2-3 : 5V operation 0.1 uF 6Vmin C4 0.1 uF 6Vmin C5 0.1 uF 6Vmin C6 0.1 uF 6Vmin C7 0.1 uF 6Vmin C8 0.1 uF 6Vmin C9 0.1 uF 6Vmin C10 0.1 uF 6Vmin C11 0.1 uF 6Vmin L2 CON3 CON3 3V or 5V oper VRNGSOURCE Component Power Selection Single point connection to ground plane S i3220PPT-EVB Ringing Source Input Figure 9. ProSLIC Motherboard (LPT to SPI) 8 7 6 5 PCMVDD R8 330 C15 0.1 uF 6Vmin 1-2 : 3V 2-3 : 5V 8 7 6 5 1 2 3 4 D3 +5V D4 /INT LED /CS LED 1 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 OE VDD GND OUT 32.768MHz 8 5 U3 12 11 10 9 8 7 6 5 4 3 2 1 GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 4245A JP5 12 34 56 78 9 10 NI EXTFSYNC INTPCLK GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB 13 14 15 16 17 18 19 20 21 22 23 24 4 INTFSYNC U6 FPGA PLCC-44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10 24 EXTDRX INTDRX EXTDTX INTDTX EXTFSYNC INTFSYNC EXTPCLK INTPCLK 12 34 EXTFSYNC EXTDRX EXTPCLK EXTDTX S2 DIP Switch 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 JP6 10 8 6 4 2 NI S1 S2 S3 S4 S5 S6 S7 S8 CLK 9 7 5 3 1 15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 11 35 33 13 14 36 2 FS /RESET EXTDRX FS DB15M To Audio Prec RX P3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 1-2: Int 2-3: Ext 1 2 3 JP3 DRX FSYNC PCLK VCC VCC Two Package Widths R11 NI 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 SDI LED PCLK To ProSLICs DTX/DRX loopback U4 PCK /CS LED SCLK LED /INT LED SDO LED SDI LED EXTDTX 12 11 10 9 8 7 6 5 4 3 2 1 GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 4245A C16 GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB 13 14 15 16 17 18 19 20 21 22 23 24 /CS SCLK /INT SDO_OUT SDI DTX 1-2: Int 1 2 2-3: Ext 3 JP4 EXTPCLK SDO/IN1 Y0 Y1/RESET Y2/SCLK ispEN SDI/IN0 MODE/IN2 GOE0/IN3 } LED drive J8 EXTDRX J9 EXTFSYNC Omit Pin 5 GND GND +5V J7 HEADER 8X1 1 23 TEST_IN J13 NI 2 1 8 7 6 5 D7 D7 Two Package Widths EXTPCLK EXTDTX C17 0.01 uF 6Vmin R10 10k 0.1 uF 6Vmin J10 J11 External PCM On-board PCM Clocks Figure 10. ProSLIC Motherboard (PCM) 1 2 3 4 /RST LED U5 PCLK LED P2 FSYNC LED DB15F To Audio Prec TX SCLK LED SDO LED 1 2 3 4 14 Rev. 1.2 S i3220PPT-EVB +5V +5V +3V VDD +5V PCM bus 1 2 3 JP2 R9 330 S i3220PPT-EVB Document Change List Revision 1.1 to Revision 1.2 Figure 2 updated. Tables 4 and 5 added. Rev. 1.2 15 S i3220PPT-EVB Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, ProSLIC, and LINC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 16 Rev. 1.2