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SI3232 - DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING - Silicon Laboratories

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SI3232
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2329.73KB 共128页
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SILABS[SiliconLaboratories]
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SI3232 - DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING - Silicon Laboratories
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Si3232 DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING Features Ideal for customer premise applications Low standby power consumption: 61 mA disables threshold detection. Preliminary Rev. 0.96 33 S i3232 4.5.2. Ground Key Detection Ground key detection detects an alerting signal from the terminal equipment during the tip open or ring open linefeed states. The functional blocks required to implement a ground key detector are shown in Figure 15, and the register set for detecting a ground key event is provided in Table 22 on page 36. The primary input to the system is the longitudinal current sense value provided by the voltage/current/power monitoring circuitry and reported in the ILONG RAM address. The ILONG value is produced in the ISP provided the LFS bits in the linefeed register indicate the device is in the tip open or ring open state. The longitudinal current (ILONG) is computed as shown in the following equation. Refer to Figure 11 on page 26 for the transistor references used in the equation (Q1, Q2, Q5 and Q6 – note that the Si3200 has corresponding MOS transistors). The same ILONG equation applies to the discrete bipolar linefeed as well as the Si3200 linefeed device. I Q1 – I Q6 – I Q5 + I Q2 I LONG = --------------------------------------------------2 The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the LONGHI bit is set to indicate that a valid ground key event has occurred. When the Si3220/25 detects a ground key event, the linefeed automatically transitions from the TIP-OPEN (or RING-OPEN) state to the FORWARD-ACTIVE (or REVERSE-ACTIVE) state. However, this automatic state transition is triggered by the LCR bit becoming active (i.e., =1), and not by the LONGHI bit. While ILONG is used to generate the LONGHI status bit, a transition from TIP-OPEN to the FORWARD-ACTIVE state (or from the RING-OPEN to the REVERSEACTIVE state) occurs when the RING terminal (or TIP terminal) is grounded and is based on the LCR bit and implicitly on exceeding the LCROFFHK threshold. As an example of ground key detection, suppose that the Si3220/25 has been programmed with the current values shown in Table 20. The output of the ISP (ILONG) is the input to a programmable, digital low-pass filter, which removes unwanted ac signal components before threshold detection. The low-pass filter coefficient is calculated using the following equation and is entered into the LONGLPF RAM location: ( 2 π f × 4096 ) 3 LONGLPF = -------------------------------- × 2 800 Table 20. Settings for Ground Key Example ILIM LCROFFHK LCRONHK LONGHITH LONGLOTH 21 mA 14 mA 10 mA 7 mA 5 mA Where f = the desired cutoff frequency of the filter. The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. The output of the low-pass filter is compared to the programmable threshold, LONGHITH. Hysteresis is enabled by programming a second threshold, LONGLOTH, to detect when the ground key is released. The threshold comparator output feeds a programmable debounce filter. With the settings of Table 20, the behavior of ILOOP, ILONG, LCR, LONGHI, and CMHIGH is as shown in Table 21. The entries under “Loop State” indicate the condition of the loop, as determined by the equipment terminating the loop. The entries under “LINEFEED Setting” indicate the state initially selected by the host CPU (e.g., TIP-OPEN) and the automatic transition to the FORWARD-ACTIVE state due to a ground key event (when RING is connected to GND). The transition from state #2 to state #3 in Table 21 is the automatic transition from TIP-OPEN to FWD-ACTIVE in response to LCR = 1. 34 Preliminary Rev. 0.96 S i3232 Table 21. State Transitions During Ground Key Detection # 1 2 3 4 5 Loop State LOOP OPEN RING-GND RING-GND LOOP CLOSURE LOOP OPEN LINEFEED State LFS = 3 (TIP-OPEN) LFS = 3 (TIP-OPEN) LFS = 1 (FWD-ACTIVE) LFS = 1 (FWD-ACTIVE) LFS = 1 (FWD-ACTIVE) ILOOP (mA) ILONG (mA) 0 22 22 21 0 0 –11 –11 0 0 LCR 0 1 1 1 0 LONGHI 0 1 1 0 0 CMHIGH 0 0 1 0 0 IQ1 IQ2 IQ5 IQ6 LONGLPF LFS Ground Key Threshold LONGE LONGHITH LONGLOTH LONGDBI Interrupt Logic LONGS Input Signal Processor ILONG Digital LPF + – Debounce Filter LONGHI Figure 15. Ground Key Detection Circuitry Preliminary Rev. 0.96 35 S i3232 Table 22. Register and RAM Locations used for Ground Key Detection Parameter Register/ RAM Mnemonic IRQVEC2 IRQEN2 LINEFEED LCRRTP LONGDBI ILONG LONGHITH LONGLOTH LONGLPF Register/RAM Bits LONGS LONGE LFS[2:0] LONGHI LONGDBI[15:0] ILONG[15:0] LONGHITH[15:0] LONGLOTH[15:0] LONGLPF[15:3] Programmable Range Yes/No Yes/No Monitor only Monitor only 0 to 40.96 s Monitor only 0 to 101.09 mA* 0 to 101.09 mA* 0 to 4000h 3.097 µA 3.097 µA N/A LSB Size Resolutio n N/A N/A N/A N/A 1.25 ms See Table 14 396.4 µA 396.4 µA N/A Ground Key Interrupt Pending Ground Key Interrupt Enable Linefeed Shadow Ground Key Detect Status Ground Key Detect Debounce Interval Longitudinal Current Sense Ground Key Threshold (high) Ground Key Threshold (low) Ground Key Filter Coefficient N/A N/A N/A N/A 1.25 ms Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a value >16 mA will disable threshold detection 36 Preliminary Rev. 0.96 S i3232 4.6. Ringing Generation The Si3232 is designed to provide a balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are all register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and the RING lines using ringing waveforms that are 180° out of phase with each other. The resulting ringing signal seen across TIP-RING is twice the amplitude of the ringing waveform on either the TIP or the RING line, which allows the ringing circuitry to withstand only half the total ringing amplitude seen across TIP-RING. VRING RING The ringing amplitude at the terminal equipment depends on the loop impedance as well as the load impedance in REN. The following equation can be used to determine the TIP-RING ringing amplitude required for a specific load and loop condition. RLOOP ROUT + VRING RLOAD VTERM – SLIC VTIP VOFF TIP Figure 17. Simplified Loop Circuit During Ringing R LOAD V TERM = V RING × ---------------------------------------------------------------R LOAD + R LOOP + R OUT where GND VTIP V PK VOFF VCM R LOOP = 0.09 Ω per foot for 26 AWG wire R OUT = 320 Ω 7000 Ω R LOAD = ------------------# REN VRING VBATH VOV Figure 16. Balanced Ringing Waveform and Components The purpose of an internal ringing scheme is to provide >40 Vrms into a 5 REN load at the terminal equipment using a user-provided ringing battery supply. The specific ringing supply voltage required depends on the ringing voltage desired. When ringing longer loop lengths, adding a dc offset voltage is necessary to reliably detect a ring trip condition (off-hook phone). Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases the power dissipation in the Si3200 and may require additional airflow or a modified PCB layout to maintain acceptable operating temperatures. The Si3232 automatically applies and removes the ringing signal during VOC-crossing periods to reduce noise and crosstalk to adjacent lines. Table 23 provides a list of registers required for internal ringing generation. Preliminary Rev. 0.96 37 S i3232 Table 23. Register and RAM Locations used for Ringing Generation Parameter Ringing Waveform Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Monitor Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) On-Hook Line Voltage Ringing Voltage Offset Ringing Frequency Ringing Amplitude Ringing Initial Phase Sinusoidal Trapezoid Ringing Overhead Voltage Ringing Speedup Timer 4.6.1. Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by using an on-chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated at a 1 kHz rate. The ringing generator is programmed via the RINGFREQ, RINGAMP, and RINGPHAS RAM locations. The equations are as follows: 2πf coeff = cos ⎛ ---------------------- ⎞ ⎝ 1000 Hz⎠ Register/RAM Mnemonic RINGCON RINGCON RINGCON RINGCON RINGTALO/ RINGTAHI RINGTILO/ RINGTIHI LINEFEED VOC RINGOF RINGFRHI/ RINGFRLO RINGAMP Register/RAM Bits TRAP TAEN TIEN RINGEN RINGTA[15:0] RINGTI[15:0] LF[2:0] VOC[15:0] RINGOF[15:0] RINGFRHI[14:3]/ RINGFRLO[14:3] RINGAMP[15:0] Programmable Range Sinusoid/Trapezoid Enabled/Disabled Enabled/Disabled Enabled/Disabled 0 to 8.19 s 0 to 8.19 s 000 to 111 0 to 63.3 V 0 to 63.3 V 4 to 100 Hz 0 to 160.173 V Resolution (LSB Size) N/A N/A N/A N/A 125 ms 125 ms N/A 1.005 V (4.907 mV) 1.005 V (4.907 mV) 628 mV (4.907 mV) N/A 31.25 µs 1.005 V (4.907 mV) 1.25 ms 23 RINGPHAS VOVRING SPEEDUPR RINGPHAS[15:0] VOVRING[15:0] SPEEDUPR[15:0] N/A 0 to 1.024 s 0 to 63.3 V 0 to 40.96 s RINGFREQ = coeff × 2 Desired V PK 15 1 1 – coeff RINGAMP = -- ----------------------- × ( 2 ) × ----------------------------------4 1 + coeff 160.173 V RINGPHAS = 0 For example, to generate a 60 Vrms (87 VPK), 20 Hz ringing signal, the equations are as follows: 2 π 20 coeff = cos ⎛ ---------------------- ⎞ = . 99211 ⎝ 1000 Hz⎠ RINGFREQ = . 99211 × ( 2 ) = 8322461 = 0x7EFD9D 23 38 Preliminary Rev. 0.96 S i3232 15 1 . 00789 85 RINGAMP = -- -------------------- × ( 2 ) × -------------------- = 273 = 0x111 4 1.99211 160.173 RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640) RINGAMP = 90/160.8 x (215) = 18340 (0x47A5) RINGFREQ = (2 x RINGAMP) (0.0153 x 8000) = 300 (0x012C) The time registers and interrupts described in the sinusoidal ring description also apply to the trapezoidal ring waveform. In addition to the variable frequency and amplitude, there is a selectable dc offset (VOFF) that can be added to the waveform. The dc offset is defined in the RINGOF RAM location. The ringing generator has two timers which allow on/off cadence settings up to 8 s on/8 s off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. To initiate ringing, the user must program the RINGFREQ, RINGAMP, and RINGPHAS RAM addresses as well as the RINGTA, and RINGTI registers, and select the ringing waveshape and dc offset. Once this is done, the TAEN and TIEN bits are set as desired. Ringing state is invoked by a write to the linefeed register. At the expiration of RINGTA, the Si3232 turns off the ringing waveform and goes to the on-hook transmission state. At the expiration of RINGTI, ringing is initiated again. This process continues as long as the two timers are enabled and the linefeed register remains in the ringing state. 4.6.2. Internal Trapezoidal Ringing In addition to the traditional sinusoidal ringing waveform, the Si3232 can generate a trapezoidal ringing waveform similar to the one illustrated in Figure 19. The RINGFREQ, RINGAMP, and RINGPHAS RAM locations are used for programming the ringing wave shape as follows: RINGPHAS = 4 x Period x 8000 RINGAMP = (Desired V/160.8 V) x (215) RINGFREQ = (2 x RINGAMP) / (tRISE x 8000) RINGFREQ is a value that is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. 3 1t RISE = -- T ⎛ 1 – ----------⎞ 2⎠ 4⎝ CF 4.7. Internal Unbalanced Ringing The Si3232 also provides the ability to generate a traditional battery-backed unbalanced ringing waveform for ringing terminating devices that require a high dc content or for use in ground-start systems that cannot tolerate a ringing waveform on both the TIP and RING leads. The unbalanced ringing scheme applies the ringing signal to the RING lead; the TIP lead remains at the programmed VCM voltage that is very close to ground. A programmable dc offset can be preset to provide dc current for ring trip detection. Figure 18 illustrates the internal unbalanced ringing waveform. VRING RING Si3232 DC Offset TIP GND VTIP DC Offset VCM VOFF -80V VBATR VRING VOVRING Figure 18. Internal Unbalanced Ringing To enable unbalanced ringing, set the RINGUNB bit of the RINGCON register. As is the case with internal balanced ringing, the unbalanced ringing waveform is generated by using the on-chip ringing tone generator. The tone generator used to generate ringing tones is a two-pole resonator with programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate. The ringing generator is programmed via the RINGAMP, RINGFREQ, and RINGPHAS registers. The RINGOF register is used to set the dc offset position around where 1T = Period = ------------f RING CF = desired crest factor So, for a 90 VPK, 20 Hz trapezoidal waveform with a crest factor of 1.3, the period is 0.05 s, and the rise time requirement is 0.015 s. Preliminary Rev. 0.96 39 S i3232 which the RING lead oscillates. The dc offset is set at a dc point equal to VCM – (–80 V + VOFF), where VOFF is the value that is input into the RINGOF RAM location. Positive VOFF values cause the dc offset point to move closer to ground (lower dc offset), and negative VOFF values have the opposite effect. The dc offset can be set to any value; however, the ringing signal is clipped digitally if the dc offset is set to a value that is less than half the ringing amplitude. In general, the following equation must hold true to ensure the battery voltage is sufficient to provide the desired ringing amplitude: |VBATR| > |VRING,PK + (–80 V + VOFF) + VOVRING| It is possible to create reverse polarity unbalanced ringing waveforms (the TIP lead oscillates while the RING lead stays constant) by setting the UNBPOLR bit of the RINGCON register. In this mode, the polarity of VOFF must also be reversed (in normal ringing polarity, VOFF is subtracted from –80 V, and in reverse polarity, ringing VOFF is added to –80 V). 4.7.1. Ringing Coefficients The ringing coefficients are calculated in decimal for sinusoidal and trapezoidal waveforms. The RINGPHAS and RINGAMP hex values are decimal-to-hex conversions in 16-bit, 2’s complement representations for their respective RAM locations. To obtain sinusoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to a 24-bit 2’s complement value. The lower 12 bits are placed in RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are cleared to 0. The upper 12 bits are set in a similar manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the sign bit and RINGFRHI bits 2:0 are cleared to 0. For example, the register values RINGFREQ = 0x7EFD9D are as follows: RINGFRHI = 0x3F78 RINGFRLO = 0x6CE8 To obtain trapezoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to an 8-bit, 2’s complement value. This value is loaded into RINGFRHI. RINGFRLO is not used. for VTIP-RING V OFF T=1/freq t RISE time Figure 19. Trapezoidal Ringing Waveform 4.7.2. Ringing DC Offset Voltage A dc offset voltage can be added to the Si3232’s ac ringing waveform by programming the RINGOF RAM address to the appropriate setting. The value of RINGOF is calculated as follows: V OFF 15 RINGOF = -------------- × 2 160.8 4.7.3. Linefeed Overhead Voltage Considerations During Ringing The ringing mode output impedance allows ringing operation without overhead voltage modification (VOVR = OV). If an offset of the ringing signal from the RING lead is desired, VOVR can be used for this purpose. 4.7.4. Ringing Power Considerations The total power consumption of the Si3232/Si3200 chipset using internal ringing generation is dependent on the VDD supply voltage, the desired ringing amplitude, the total loop impedance, and the ac load impedance (number of REN). The following equations can be used to approximate the total current required for each channel during ringing mode. V RING,PK 2 -I DD,AVE = ---------------------- × -- + I DD,OH Z LOOP π V RING,PK 2 -I BAT,AVE = ---------------------- × -π Z LOOP Where: V RING,PK = V RING,RMS × 2 Z LOOP = R LOOP + R LOAD + R OUT 7000 R LOAD = ------------ (for North America) REN 40 Preliminary Rev. 0.96 S i3232 R LOOP = loop impedance R OUT = Si3232 ouput impedance = 320 Ω I DD,OH = I DD overhead current = 12 mA under any condition. Figure 20 illustrates the internal functional blocks that serve to correctly detect and process a ring trip event. The primary input to the system is the loop current sense (ILOOP) value provided by the loop monitoring circuitry and reported in the ILOOP RAM location register. This ILOOP register value is processed by the input signal processor block provided that the LFS bits in the Linefeed register value indicate the device is in the ringing state. The output of the input signal processor then feeds into a pair of programmable digital low-pass filters; one for the ac ring trip detection path and one for the dc path. The ac path also includes a fullwave rectifier block prior to the LPF block. The outputs of each low-pass filter block are then passed on to a programmable ring trip threshold (RTACTH for ac detection and RTDCTH for dc detection). Each threshold block output is then fed to a programmable debounce filter that ensures a valid ring trip event. The output of each debounce filter remains constant unless the input remains in the opposite state for the entire period of time set using the ac and dc ring trip debounce interval registers, RTACDB and RTDCDB, respectively. The outputs of both debounce filter blocks are then ORed together. If either the ac or the dc ring trip circuits indicate a valid ring trip event has occurred, the RTP bit is set. Either the ac or dc ring trip detection circuits can be disabled by setting the respective ring trip threshold sufficiently high so it will not trip under any condition. A ring trip interrupt is also generated if the RTRIPE bit has been enabled. 4.8. Ring Trip Detection A ring trip event signals that the terminal equipment has transitioned to an off-hook condition after ringing has commenced, thus ensuring that the ringing signal is removed before normal speech begins. The Si3232 is designed to implement either an ac- or dc-based internal ring trip detection scheme or a combination of both schemes. This allows system-design flexibility for addressing varying loop lengths of different applications. An ac ring trip detection scheme cannot reliably detect an off-hook condition when sourcing longer loop lengths, as the 20 Hz ac impedance of an off-hook long loop is indistinguishable from a heavilyloaded (5 REN) short loop in the on-hook state. Because of this situation, a dc ring trip detection scheme is required when sourcing longer loop lengths. The Si3232 can implement either an ac- or dc-based ring trip detection scheme depending on the application. Table 25 on page 43 lists the registers that must be written or monitored to correctly detect a ring trip condition. The Si3232 provides the ability to process a ring trip event using only an ac-based detection scheme. Using this scheme eliminates the need for adding dc offset to the ringing signal, which reduces the total power dissipation during the ringing state and maximizes the available ringing amplitude. This scheme is only valid for shorter loop lengths, as it may not be possible to reliably detect a ring trip event if the off-hook line impedance overlaps the on-hook impedance at 20 Hz. The Si3232 also provides the ability to add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state. Although adding dc offset reduces the maximum available ringing amplitude (using the same ringing supply), this method is required to reliably detect a valid ring trip event when sourcing longer loop lengths. The dc offset can be programmed from 0 to 63.3 V in the RINGOF RAM address as required to produce adequate dc loop current in the off-hook state. Depending on the loop length and the ring trip method desired, the ac or dc ring trip detection circuits can be disabled by setting their respective ring trip thresholds (RTACTH or RTDCTH) sufficiently high so it will not trip 4.9. Ring Trip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that monitors the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter amount of time (RTCOUNT x 1.25 ms/LSB) for the mode to switch to On-hook Transmission or Active. The mode that is being exited to is governed by whether the command to exit ringing is a ringing active timer expiration (on-hook transmission) or ringtrip/manual mode change (Active mode). The ringtrip timeout counter will assure ringing is exited within its time setting (RTCOUNT x 1.25 ms/LSB, typically 200 ms). 4.10. Ring Trip Debounce Interval The ac and dc ring trip debounce intervals can be calculated based on the following equations: RTACDB = tdebounce (1600/RTPER) RTDCDB = tdebounce (1600/RTPER) Preliminary Rev. 0.96 41 S i3232 4.11. Loop Closure Mask The Dual ProSLIC implements a loop closure mask to ensure mode change between Ringing and Active or On-hook Transmission without causing an erroneous loop-closure detection. The loop-closure mask register, LCRMASK, should be set such that loop-closure detections are ignored for (LCRMASK x 1.25 ms/LSB) RTACTH amount of time. The programmed time is set to mask detection of transitional currents that occur when exiting the ringing mode while driving a reactive load (i.e., 5 REN). A typical setting is 80 ms (LCRMASK = 0x40). LFS AC Ring Trip Threshold _ ILOOP Input Signal Processor Digital LPF + Debounce Filter_AC RTP RTPER RTACDB Interrupt Logic RTRIPS Digital LPF + _ DC Ring Trip Threshold RTRIPE Debounce Filter_DC RTDCDB RTDCTH Figure 20. Ring Trip Detect Processing Circuitry 42 Preliminary Rev. 0.96 S i3232 Table 24. Recommended Ring Trip Detection Values1 Ringing Frequency 16–32 Hz DC Offset Added? Yes No 33–60 Hz Yes No RTPER 800/fRING 800/fRING 2(800/fRING) 2(800/fRING) RTACTH 221 x RTPER 1.59 x VRING,PK x RTPER 221 x RTPER 1.59 x VRING,PK x RTPER RTDCTH 0.577(RTPER x VOFF) 32767 0.577(RTPER x VOFF) 32767 See Note 2 RTACDB/ RTDCDB Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations. Table 25. Register and RAM Locations for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable AC Ring Trip Threshold DC Ring Trip Threshold Ring Trip Sample Period Linefeed Shadow (monitor only) Ring Trip Detect Status (monitor only) AC Ring Trip Detect Debounce Interval DC Ring Trip Detect Debounce Interval Loop Current Sense (monitor only) Register/RAM Mnemonic IRQVEC2 IRQEN2 RTACTH RTDCTH RTPER LINEFEED LCRRPT RTACDB RTDCDB ILOOP Register/ RAM Bits RTRIPS RTRIPE RTACTH[15:0] RTDCTH[15:0] RTPER[15:0] LFS[2:0] RTP RTACDB[15:0] RTDCDB[15:0] ILOOP[15:0] Programmable Range Yes/No Enabled/Disabled See Table 24 See Table 24 See Table 24 N/A N/A 0 to 40.96 s 0 to 40.96 s 0 to 101.09 mA N/A N/A 1.25 ms 1.25 ms See Table 14 Resolution N/A N/A Preliminary Rev. 0.96 43 S i3232 4.12. Relay Driver Considerations The Si3232 includes a general-purpose driver output for each channel (GPOa, GPOb) to drive external test relays. In most applications, the relay can be driven directly from the Si3232 with no external relay drive circuitry required. Figure 21 illustrates the internal relay driver circuitry using a 3 V relay. VDD Si3232 3 V/5 V Relay (polarized or non-polarized) Relay Driver Logic VCC VDD Si3232 Polarized relay IDRV GPOa GPOb Q1 RDRV VCC Figure 22. Driving Relays with VCC > VDD GPOa/b The maximum allowable RDRV value can be calculated using the following equation: MaxR DRV = GND Figure 21. Si3232 Internal Relay Drive Circuitry The internal driver logic and drive circuitry is powered from the same 3.3 V supply as the chip’s main supply (VDD1–VDD4 pins). When operating external relays from a VCC supply that is equal to the chip’s VDD supply, an internal diode network provides protection against overvoltage conditions caused by flyback spikes when the relay is opened. Only 3 V relays may be used in the configuration shown in Figure 21, and either polarized or non-polarized relays are acceptable provided both VCC and VDD are powered by a 3.3 V supply. The input impedance, RIN, of the relay driver pins is a constant 11 Ω while sinking less than the maximum rated 85 mA into the pin. If the desired operating voltage of the relay, VCC, is higher than the Si3232’s VDD supply voltage, an external drive circuit is required to eliminate leakage from VCC to VDD through the internal protection diode. In this configuration, a polarized relay is recommended to provide optimal overvoltage protection with minimal external components. Figure 22 illustrates the required external drive circuit, and Table 26 provides recommended values for RDRV for typical relay characteristics and VCC supplies. The output impedance, ROUT, of the relay driver pins is a constant 63 Ω while sourcing less than the maximum rated 28 mA out of the pin. ( V DD,MIN – 0.6 V ) ( R RELAY ) ( β Q1,MIN ) ------------------------------------------------------------------------------------------------ – R SOURCE V CC,MAX – 0.3 V where βQ1,MIN ~ 30 for a 2N2222 Table 26. Recommended RDRV Values ProSLIC VDD 3.3 V ±5% 3.3 V ±5% 3.3 V ±5% 3.3 V ±5% 3.3 V ±5% Relay VCC 3.3 V ±5% 5V ±5% 12 V ±10% 24 V ±10% 48 V ±10% Relay RCOIL 64 Ω 178 Ω 1028 Ω 2880 Ω 7680 Ω Maximum RDRV Not Required 2718 Ω 6037 Ω 8364 Ω 11092 Ω Recommended 5% Value — 2.7 kΩ 5.6 kΩ 8.2 kΩ 11 kΩ 44 Preliminary Rev. 0.96 S i3232 4.12.1. Polarity Reversal The Si3232 supports polarity reversal for messagewaiting functionality as well as various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. A wink function is also provided for special equipment that responds to a smooth ramp to VOC = 0 V. Table 27 illustrates the register bits required to program the polarity-reversal modes. An immediate reversal (hard reversal) of the line polarity is achieved by setting the Linefeed register to the opposite polarity. For example, a transition from Forward Active mode to Reverse Active mode is achieved by changing LF[2:0] from 001 to 101. Polarity reversal can also be accommodated in the OHT and ground-start modes. The POLREV bit is a read-only bit that reflects whether the device is in polarity reversal mode. A smooth polarity reversal is achieved by setting the PREN bit to 1 and setting the RAMP bit to 0 or 1 depending on the desired ramp rate (see Table 27). Polarity reversal is then accomplished by toggling the linefeed register from forward to reverse modes as desired. A wink function is used to slowly ramp down the TIPRING voltage (VOC) to 1 followed by a return to the original VOC value (set in the VOC RAM 0 location). This scheme is used to light a message-waiting lamp in certain handsets. To enable this function, no change to the linefeed register is necessary. Instead, the user must set the VOCZERO bit to 1 to cause the TIP-RING voltage to collapse to 0 V at the rate programmed by the RAMP bit. Setting the VOCZERO bit back to 0 causes the TIP-RING voltage to return to its normal setting. A software timer provided by the user can automate the cadence of the wink function. Figure 23 illustrates the wink function. Table 27. Register and RAM Locations used for Polarity Reversal Parameter Linefeed Polarity Reversal Status Wink Function (Smooth transition to Voc = 0 V) Smooth Polarity Reversal Enable Smooth Polarity Reversal Ramp Rate Programmable Range See Table 12 Read only 1 = Ramp to 0 V 0 = Return to previous VOC 0 = Disabled 1 = Enabled 0 = 1 V/125 µs 1 = 2 V/125 µs Register/RAM Bits LF[2:0] POLREV VOCZERO PREN RAMP Location LINEFEED POLREV POLREV POLREV POLREV Preliminary Rev. 0.96 45 S i3232 Set VOCZERO bit to 1 0 0 10 20 30 Set VOCZERO bit to 0 40 50 60 70 80 Vcm Time (ms) VTIP -10 -20 2V/125 µs slope set by RAMP bit -30 Voc -40 -50 Vov VRING VBAT V TIP/RING (V) Figure 23. Wink Function with Programmable Ramp Rate 4.13. Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Si3232 to the impedance of the subscriber loop, thus minimizing the receive path signal reflected back onto the transmit path. The Si3232 provides on-chip selectable analog two-wire impedances to meet return loss requirements. The subscriber loop varies with any series impedance due to protection devices placed between the Si3200 outputs and the TIP/RING pair according to the following equation: Z T = 2R PROT + R A TIP RPROT Si3200 ZL ZT Si3232 RING RPROT Figure 24. Two-Wire Impedance Simplified Circuit 4.13.1. Transhybrid Balance Filter The Si3232 is intended to be used with DSP-based codecs that provide the transhybrid balance function. No transhybrid capability exists in the Si3232. 4.13.2. Pulse Metering Generation The Si3232 offers an internal tone generator suitable for generating tones above the audio frequency band. This oscillator is provided for the generation of billing tones which are typically 12 kHz or 16 kHz. The equations for calculating the pulse metering coefficients are as follows: Coeff = cos (2πf/64000 Hz) PMFREQ = coeff (214 – 1) • Where: ZT is the termination impedance presented to the TIP/RING pair RPROT is the series resistance caused by protection devices RA is the analog portion of the selected impedance Therefore, the user must also consider the value of RPROT when programming the on-chip analog impedance. The Si3232’s analog impedance synthesis scheme is sufficient for many short loop applications. If a unique complex ac impedance is required, the Si3232’s impedance scheme must be augmented or replaced by a DSP-based impedance generator. To turn off the analog impedance coefficients (RS, ZP, and ZZ), set the ZSDIS bit of the ZZ register to 0. 46 Preliminary Rev. 0.96 S i3232 Desired V PK 15 1 1 – coeff PMAMPL = -- ----------------------- × ( 2 – 1 ) × ----------------------------------------Full Scale V PK 4 1 + coeff where Full Scale VPK = 0.5 V. The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The ramp is controlled by the value entered into the PMRAMP RAM address, and the sinusoidal generator output is multiplied by this volume before being sent to the pulse metering DAC. The volume value is incremented by the value in PMRAMP at an 8 kHz rate. The volume ramps from 0 to 7FFF in increments of PMRAMP, thus allowing the value of PMRAMP to set the slope of the ramp. The clip detector stops the ramp once the signal seen at the transmit path exceeds the amplitude threshold set by PMAMPTH, thus providing an automatic gain control (AGC) function to prevent the audio signal from clipping. When the pulse metering signal is turned off, the volume ramps down to 0 by decrementing according to the value of PMRAMP. Figure 24 illustrates the functional blocks involved in pulse-metering generation, and Table 28 presents the register and RAM locations required that must be set to generate pulse-metering signals. Table 28. Register and RAM Locations Used for Pulse Metering Generation Parameter Register/RAM Mnemonic Register/RAM Bits Description / Range (LSB Size) Pulse-Metering Frequency Coefficient Pulse-Metering Amplitude Coefficient Pulse-Metering Attack/Decay Ramp Rate Pulse-Metering Active Timer Pulse-Metering Inactive Timer Pulse-Metering, Control Interrupt PMFREQ PMAMPL PMRAMP PMTALO/PMTAHI PMTILO/PMTIHI IRQVEC1, IRQEN1 PMFREQ[15:3] PMAMPL[15:0] PMRAMP[15:0] PULSETA[15:0] PULSETI[15:0] PULSTAE, PULSTIE, PULSTAS, PULSTIS PMAMPTH[15:0] ENSYNC TAEN1 TIEN1 PULSE1 Sets oscillator frequency Sets oscillator amplitude 0 to PMAMPL (full amplitude) 0 to 8.19 s (125 µs) 0 to 8.19 s (125 µs) Interrupt status and control registers Pulse-Metering AGC Amplitude Threshold PM Waveform Present PM Active Timer Enable PM Inactive Timer Enable Pulse-Metering Enable PMAMPTH PMCON PMCON PMCON PMCON 0 to 500 mV Indicates Signal Present Enable/disable Enable/disable Enable/disable Preliminary Rev. 0.96 47 S i3232 To VTX outputs 12/16 kHz Bandpass Peak Detector – IBUF ZA + PMAMPTH + From VRX inputs PMRAMP Pulse Metering DAC + – + + Pulse Metering Oscillator Volume Clip Logic 7FFF or 0 8 kHz Figure 25. Pulse Metering Generation Block Diagram 4.14. Audio Path Processing The Si3232 is designed to connect directly to integrated access device (IAD) chipsets, such as the Broadcom BCM3341, as well as other standard codecs that use a differential audio interface. Figure 3 on page 15 illustrates the simplified block diagram for the Si3232. 4.14.1. Transmit Path Table 29. ATX Attenuation Stage Settings ATXMUT E Setting ATX Setting Typical TX Path Gain 1 0 0 X 0 1 Mute (no output) –1.584 dB (G = 10/12) –4.682 dB (G = 7/12) In the transmit path, the analog signal fed by the external ac-coupling capacitors, C1 and C2, is amplified by the analog transmit amplifier, ATX, prior to the differential analog output to the A/D converter in the external codec. The ATX stage can be used to add 3 dB of attenuation by programming the ATX bit of the AUDGAIN register. A mute function is also available by setting the ATXMUTE bit of the AUDGAIN register to 1. The main role of the ATX stage is to attenuate incoming signals to best match the input scale of the external A/D converter to maximize signal-to-noise ratio. The resulting gain levels using the ATX stage are summarized in Table 29. All settings assume a 0 dBm0 TIP-RING audio input signal with the audio TX level measured differentially at VTXPa-VTXNa (for channel a) or VTXPb-VTXNb (for channel b). 4.14.2. Receive Path In the receive path, the incoming audio signal from the D/A converter in the external codec is passed through an ARX stage where the user can attenuate audio signals in the analog domain prior to transmission to TIP/RING. Settings of 0, –3, and –6 dB are available by programming the ARX[1:0] bits of the AUDGAIN register to the appropriate settings. A mute function is also available by setting the ARXMUTE bit of the AUDGAIN register to 1. When not muted, the resulting analog signal is applied at the input of the transconductance amplifier, Gm, which drives the offchip current buffer, IBUF. 48 Preliminary Rev. 0.96 S i3232 The resulting gain levels using the ARX stage are summarized in Table 30. All settings assume an external codec with 475 Ω per leg of source impedance driving the RX inputs differentially at VRXPa-VRXNa (for channel a) or VRXPb-VRXNb (for channel b) to achieve a 0 dBm0 TIP-RING audio output signal. or update of the PLL-MULT register. The PLL lock process begins immediately after the RESET pin is pulled high and will take approximately 5 ms to achieve lock after RESET is released with stable PCLK and FSYNC. However, the settling time depends on the PCLK frequency and can be predicted based on the following equation: tSETTLE = 64 / fPCLK Note: Therefore, the RESET pin must be held low during powerup and should only be released when both PCLK and FSYNC signals are known to be stable. Table 30. ARX Attenuation Stage Settings ARXMUTE Setting ARX[1:0] Setting Typical TX Path Gain 1 0 0 0 0 xx 00 01 10 11 Mute (no T-R output) 0 dB (G = 1) –3.52 dB (G = 2/3) –6.02 dB (G = 1/2) Reserved. Do not use. 4.15.1. Interrupt Logic The Si3232 is capable of generating interrupts for the following events: Loop current/ring ground detected. Ground key detected. Ring trip detected. Power alarm. Ringing active timer expired. Ringing inactive timer expired. Pulse metering active timer expired. Pulse metering inactive timer expired. RAM address access complete. The interface to the interrupt logic consists of six registers. Three interrupt status registers (IRQ0–IRQ3) contain one bit for each of the above interrupt functions. These bits are set when an interrupt is pending for the associated resource. Three interrupt mask registers (IRQEN1–IRQEN3) also contain one bit for each interrupt function. In the case of the interrupt mask registers, the bits are active high. Refer to the appropriate functional description text for operational details of the interrupt functions. 4.15. System Clock Generation The Si3232 generates the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 786 kHz, 1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined by a counter clocked by PCLK. The 3-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a device reset. PLL_MULT is used to control the internal PLL, which multiplies PCLK as needed to generate the rate required to run the internal filters and other circuitry. The PLL clock synthesizer settles quickly after powerup PCLK PFD VCO ÷2 ÷2 28.672 MHz DIV M RESET PLL_MULT Figure 26. PLL Frequency Synthesizer Preliminary Rev. 0.96 49 S i3232 When a resource reaches an interrupt condition, it signals an interrupt to the interrupt control block. The interrupt control block then sets the associated bit in the interrupt status register if the mask bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ asserts low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. All interrupt bits in the interrupt status registers, IRQ0–IRQ3, are cleared following a register read operation. While the interrupt status registers are non-zero, the INT pin remains asserted. There are a number of variations of usage on this fourwire interface as follows: Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CSB pin. CSB must be asserted before the falling edge of SCLK on which the first bit of data is expected during a read cycle and must remain low for the duration of the 8-bit transfer (command/ address or data), going high after the last rising of SCLK after the transfer. Clock only during transfer. In this mode, the clock cycles only during the actual byte transfers. Each byte transfer will consist of eight clock cycles in a return to 1 format. SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tri-stating its output during the data byte transfer of a read operation. Soft reset. The SPI state machine resets whenever CSB is asserted during an operation on an SCLK cycle that is not a multiple of eight. This provides a mechanism for the controller to force the state machine to a known state in the case where the controller and the device appear to be out of synchronization. The control byte has the following structure and is presented on the SDI pin MSB first. The bits are defined in Table 31. 4.16. SPI Control Interface The Si3232 has a 4-wire serial peripheral interface (SPI) control bus modeled after commonly-available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CSB), serial data input (SDI), and serial data output (SDO). In addition, the Si3232 includes a serial data through output (SDI_THRU) to support daisy chain operation of up to eight devices (up to sixteen channels). The device can operate with both 8-bit and 16-bit SPI controllers. Each SPI operation consists of a control byte, an address byte (of which only the seven LSBs are used internally), and either one or two data bytes depending on the width of the controller and whether the access is to a direct or indirect register. Bytes are always transmitted MSB first. 7 BRDCST 6 R/W 5 4 3 CID[0] 2 CID[1] 1 CID[2] 0 CID[3] REG/RAM Reserved 50 Preliminary Rev. 0.96 S i3232 Refer to "2. Typical Application Schematic" on page 17. The pulldown resistor on the SDO pin is required to allow this node to discharge after a logic high state to a tri-state condition. The discharge occurs while SDO is tri-stated during an 8 kHz transmission frame. The value of the pulldown resistor depends on the capacitance seen on the SDO pin. In the case of using a single Si3232, the value of the pulldown resistor is 39 kΩ. This assumes a 5 pF SDO pin capacitance and about a 15 pF load on the SDO pin. For applications using multiple Si3232 devices or different capacitive loads on the SDO pin, a different pulldown resistance needs to be calculated. The following design procedure is an example for calculating the pulldown resistor on the SDO pin in a system using eight Si3232 devices. A pullup resistor is not allowed on the SDO pin. 1. The SDO node must discharge and remain discharged for 244 ns. The discharge occurs during the Hi-Z state; therefore, the time to discharge is equal to the time in Hi-Z time minus the 244 ns. 4. We want to discharge and remain discharged for 244 ns. Therefore, the discharge time is: 992 ns – 244 ns = 748 ns 5. To allow for some margin, let’s discharge in 85% of this time. 748nS x 85% = 635.8 ns 6. Determine capacitive load on the SDO pin: a.Allow 5 pF for each Si3220 SDO pin that connected together. b.Allow ~2 pF/inch (~0.8 pF/cm) for PCB trace. c.Include the load capacitance of the host IC input. 7. For a system with eight Si3220 devices, the capacitance seen on the SDO pin would be: a.8 x 5 pF for each Si3220 = 40 pF b.Assume 5 inch of PCB trace: 5inch x 2 pF/ inch = 10 pF c.Host IC input of 5 pF d.Total capacitance is 55 pF 8. Using the equation t = RC, allowing five time constants to decay, and solving for R a.R = t / 5C = 635.8 ns / (5 x 55 pF) b.R = 2.3 kΩ So, R must be less than 2.3 kΩ to allow the node to discharge. 2. Allow five time constants for discharge where the time constant, t = RC 3. SDO will be in Hi-Z while SDI is sending control and address which are each 8 bits. Using the maximum SCLK frequency of 16.13 MHz, the SDO will be in Hi-Z for 16 / 16.13 MHz = 992 ns. 7 Table 31. SPI Control Interface BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only valid for write operations since it would cause contention on the SDO pin during a read. R/W Read/Write Bit. 0 = Write operation. 1 = Read operation. 6 5 REG/RAM Register/RAM Access. 0 = RAM access. 1 = Register access. Reserved CID[3:0] This field indicates the channel that is targeted by the operation. The 4-bit channel value is provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 26.) As the CID information propagates down the daisy chain, each channel decrements the CID by 1. The SDI nodes between devices will reflect a decrement of 2 per device since each device contains two channels. The device receiving a value of 0 in the CID field will respond to the SPI transaction. (See Figure 27.) If a broadcast to all devices connected to the chain is requested, the CID will not decrement. In this case, the same 8-bit or 16-bit data is presented to all channels regardless of the CID values. 4 3:0 Preliminary Rev. 0.96 51 S i3232 4.17. Si3232 RAM and Register Space The Si3232 is a highly-programmable telephone linecard solution that uses internal registers and RAM to program operational parameters and modes. The Register Summary and RAM Summary are compressed listings for single-entry quick reference. The Register Descriptions and RAM Descriptions give detailed information of each register or RAM location’s bits. All RAM locations are cleared upon a hardware reset. All RAM locations that are listed as “INIT” must be initialized to a meaningful value for proper functionality. Bit 4 of the MSTRSTAT register indicates the clearing process is finished. This bit should be checked before initializing the RAM space. Accessing register and RAM space is performed through the SPI. Register space is accessed by using the standard three-byte access as described in the next section. Bit 5 of the control byte specifies register access when set to a 1. All register space is comprised of 8-bit data. 4.17.1. RAM Access by Pipeline RAMDATLO and RAMDATHI registers. To write a RAM location in the Si3232, check for register RAMSTAT (bit 0) to indicate the previous access is completed and RAM is ready (0); then, write the 16 bits of RAM data to the RAMDATLO, RAMDATHI. Finally, write the RAM address to the RAMADDR register. 4.17.3. Chip Select For register or RAM space access, there are three ways to use chip select: byte length, 16-bit length, and access duration length. The byte length method releases chip select after every 8 bits of communication with the Si3232. The time between chip select assertions must be at least 220 ns. The 16-bit length chip select method is similar to the byte length method except that 16-bits are communicated with the Si3232. This means that Si3232 communication consists of a control byte, address byte for one 16-bit access, and two data bytes for a second 16-bit access. In a single data byte communication (control byte, address byte, data byte), the data byte should be loaded into either the high byte or both bytes of the second 16-bit access for a write. The 8-bit data exists in the high and low byte of a 16-bit access for a read. The time between chip select assertion must be at least 220 ns. Access duration length allows chip select to be pulled low for the length of a number of Si3232 accesses. There are two very specific rules for this type of communication. One rule is that the SCLK must be of a frequency that is less than 1/2x220 ns ( 10 V and dc voltages > 6 V from T-G or R-G. This test should only be performed once it has been determined that a hazardous voltage is not present on the line. Resistive faults test. Resistive fault conditions can be measured from T-G, R-G, or T-R for dc resistance per GR-909 specifications. If the dc resistance is < 150 kΩ, it is considered a resistive fault. This test can be performed by programming the Si3232 to generate a constant open-circuit voltage and measuring the resulting current. The resistance can then be calculated in the system DSP. Receiver off-hook test. This test can use a similar procedure as outlined in the Resistive Faults test above but is measured only across T-R. In addition, two measurements must be performed at different open-circuit voltages in order to verify the resistive DIAGACCO DIAGDCCO SDIAG_PK LPF SDIAG_DC LPF SDIAG_AC Figure 38. SLIC Diagnostic Filter Structure linearity. If the calculated resistance has more than 15% nonlinearity between the two calculated points and the voltage/current origin, it is determined to be a resistive fault. Ringers (REN) test. This test verifies the presence of REN at the end of the TIP/RING pair per GR-909 specifications. It can be implemented by generating a 20 Hz ringing signal between 7 Vrms and 17 Vrms and measuring the 20 Hz ac current using the 8-bit monitor ADC. The resistance (REN) can then be calculated using the system DSP. The acceptable REN range is > 0.175 REN ( 1400 Ω). A returned value of 40 kΩ is determined to be a loop with no handset attached. AC line impedance measurement. This test can determine the loop length across T-R. It can be implemented by sending out multiple discrete tones from the system DSP/codec, one at a time, and measuring the returned amplitude, with the system hybrid balance filter disabled. By calculating the voltage difference between the initial amplitude and the received amplitude and dividing the result by the audio current, the line impedance can then be calculated in the system processor. Line capacitance measurement. This test can be implemented in the same manner as the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized 2-wire impedance of the Si3232, the roll-off effect can be used to calculate the ac line capacitance. An external codec is required for this test. Preliminary Rev. 0.96 59 S i3232 Ringing voltage verification. This test verifies that the desired ringing signal has been correctly applied to the TIP/RING pair and can be measured in the 8bit monitor ADC, which senses low-frequency signals directly across T-R. Power induction measurement. This test can detect the presence of a power supply coupled onto the TIP/RING pair. It can be implemented by measuring the energy content at 50/60 Hz (normal induction) or at 100/120 Hz (rectified power induction). This is achieved by measuring the line voltage using a low-pass filter in the system DSP on the 8-bit monitor ADC while making certain there is no ringing signal present on the line. 60 Preliminary Rev. 0.96 S i3232 5. 8-Bit Control Register Summary1,2 Any register not listed here is reserved and must not be written. Shaded registers are read only. All registers are assigned a default value during initialization and following a system reset. Only registers 0, 2, 3, and 14 are available until a PLL lock is established or during a clock failure. (Ordered alphabetically by mnemonic.) Reg Addr3 Mnemonic Description Bit 7 Bit 6 Bit 5 Audio 21 AUDGAIN Audio Gain Control CMTXSEL ATXMUTE Calibration 11 12 CALR1 CALR2 Calibration Register 1 Calibration Register 2 CAL CALOFFR CALLKGR CALOFFT CALLKGT CALOFFRN CALMADC CALOFFTN CALDACO CALDIFG CALADCO CALCMG CALCMBAL Init Init R/W R/W 0x3F 0x3F ATX ARXMUTE ARX[1:0] Init R/W 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def. Hex Diagnostic Tools 13 DIAG Diagnostics Tool Enable IQ2HR IQ1HR TSTRING Chip ID 0 ID Chip ID PARTNUM[2:0]4 Loop Current Limit 10 ILIM Loop Current Limit Interrupts 14 15 16 17 18 19 20 IRQ0 IRQ1 IRQ2 IRQ3 IRQEN1 IRQEN2 IRQEN3 Interrupt Status 0 Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Enable 1 Interrupt Enable 2 Interrupt Enable 3 CMBALE CMBALS PULSTAE PULSTIE CLKIRQ4,6 PULSTAS IRQ3B4,6 PULSTIS IRQ2B4,6 RINGTAS RAMIRS PQ6S RINGTAE RAMIRE PQ6E IRQ1B4,6 RINGTIS DTMFS PQ5S RINGTIE DTMFE PQ5E VOCTRKE PQ4E LONGE PQ3E LOOPE PQ2E RTRIPE PQ1E VOCTRKS PQ4S LONGS PQ3S LOOPS PQ2S RTRIPS PQ1S IRQ3A4,6 IRQ2A4,6 IRQ1A4,6 Oper Oper Oper Oper Init Init Init R R/W R/W R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ILIM[4:0] Init R/W 0x05 REV[3:0]4 Init R 0x— TXFILT SDIAG SDIAGIN[2:0] Diag R/W Loopback Enable 22 LBCON Loopback Enable DLM Linefeed Control 9 6 LCRRTP LINEFEED Loop Closure/Ring Trip/ Ground Key Detection Linefeed CMH4 LFS[2:0]4 SPI 2 3 MSTREN MSTRSTAT Master Initialization Enable Master Initialization Status PLLFLT PLLFAULT FSFLT FSFAULT PCFLT PCFAULT SRCLR4 PLOCK4 FSDET4 FSVAL4 PCVAL4 Init Init R/W R/W 0x00 0x00 SPEED4 VOCTST4 LONGHI4 RTP4 LF[2:0] LCR4 Oper Oper R R/W 0x40 0x00 Diag R/W 0x00 Pulse Metering 28 30 PMCON PMTAHI Pulse Metering Control Pulse Metering Oscillator Active Timer— High Byte Pulse Metering Oscillator Active Timer— Low Byte ENSYNC4,7 TAEN17 TIEN17 PULSE17 Oper Init R/W R/W 0x00 0x00 PULSETA[15:8]7 29 PMTALO PULSETA[7:0]7 Init R/W 0x00 Notes: 1. 2. 3. 4. 5. 6. 7. Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per-channel bit(s). Si3220 only. Preliminary Rev. 0.96 61 S i3232 Reg Addr3 32 Mnemonic PMTIHI Description Pulse Metering Oscillator Inactive Timer— High Byte Pulse Metering Oscillator Inactive Timer— Low Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Init R/W R/W Def. Hex 0x00 PULSETI[15:8]7 31 PMTILO PULSETI[7:0]7 Init R/W 0x00 Polarity Reversal 7 POLREV Polarity Reversal Settings RAM Access 103 102 101 4 RAMADDR RAMDATHI RAMDATLO RAMSTAT RAM Address RAM Data— High Byte RAM Data— Low Byte RAM Address Status Soft Reset 1 RESET Soft Reset Ringing 23 25 24 27 26 RINGCON RINGTAHI RINGTALO RINGTIHI RINGTILO Ringing Configuration Ringing Oscillator Active Timer—High Byte Ringing Oscillator Active Timer—Low Byte Ringing Oscillator Inactive Timer—High Byte Ringing Oscillator Inactive Timer—Low Byte ENSYNC4 RDACEN4 RINGUNB TAEN TIEN RINGEN4 UNBPOLR TRAP Init Init Init Init Init R/W R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x00 RESETB RESETA Init R/W 0x00 RAMADDR[7:0] RAMDAT[15:8] RAMDAT[7:0] RAMSTAT4 Oper Oper Oper Init R/W R/W R/W R 0x00 0x00 0x00 0x00 POLREV4 VOCZERO PREN RAMP Init R/W RINGTA[15:8] RINGTA[7:0] RINGTI[15:8] RINGTI[7:0] Relay Configuration 5 RLYCON Relay Driver and Battery Switching Configuration BSEL5 RRAIL RDOE GPO Diag R/W 0x00 SLIC Bias Control 8 SBIAS SLIC Bias Control STDBY5 SQLCH5 CAPB5 BIASEN5 OBIAS[1:0]5 ABIAS[1:0]5 Init R/W 0xE0 Si3200 Thermometer 72 THERM Si3200 Thermometer STAT4 SEL5 Impedance Synthesis Coefficients 33 34 Notes: 1. 2. 3. 4. 5. 6. 7. ZRS ZZ Impedance Synthesis Analog Real Coeff Impedance Synthesis Analog Complex Coeff ZSDIS6 ZSOHT6 ZP[1:0]6 RS[3:0]6 ZZ[1:0]6 Init Init R/W R/W 0x00 0x00 Oper R/W 0x45 Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per-channel bit(s). Si3220 only. 62 Preliminary Rev. 0.96 S i3232 6. 8-Bit Control Descriptions AUDGAIN: Audio Gain Control (Register Address 21) (Register type: Initialization) D7 Name Type D6 D5 D4 D3 D2 D1 D0 CMTXSEL R/W ATXMUTE R/W ATX R/W ARXMUTE R/W ARX[1:0] R/W Reset settings = 0x00 Bit Name Function Transmit Path Common Mode Select. Selects common mode reference for transmit audio signal. 0 = VTXP/N pins will be referred to internal 1.5 V VCM level. 1 = VTXP/N pins will be referred to external common-mode level presented at the VCM pin. Analog Transmit Path Mute. 0 = Transmit signal passed. 1 = Transmit signal muted. 7 CMTXSEL 6 ATXMUTE 5 4 Reserved ATX Read returns zero. Analog Transmit Path Attenuation Stage. Selects analog transmit path attenuation. See "4.14. Audio Path Processing" on page 48. 0 = No attenuation. 1 = –3 dB attenuation. 3 2 Reserved ARXMUTE Read returns zero. Analog Receive Path Mute. 0 = Receive signal passed. 1 = Receive signal muted. Analog Receive Path Attenuation Stage. Selects analog receive path attenuation. See “4.14. Audio Path Processing” . 00 = No attenuation. 01 = –3 dB attenuation. 10 = –6 dB attenuation. 11 = Reserved. Do not use. 1:0 ARX[1:0] Preliminary Rev. 0.96 63 S i3232 CALR1: Calibration 1 (Register Address 11) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 CAL R/W CALOFFR CALOFFT CALOFFRN CALOFFTN CALDIFG R/W R/W R/W R/W R/W CALCMG R/W Reset settings = 0x3F Bit Name Function Calibration Control/Status Bit. Begins system calibration routine. 0 = Normal operation or calibration complete. 1 = Calibration in progress. 7 CAL 6 5 Reserved CALOFFR Read returns zero. RING Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. IRINGN Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ITIPN Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 4 CALOFFT 3 CALOFFRN 2 CALOFFTN 1 CALDIFG 0 CALCMG 64 Preliminary Rev. 0.96 S i3232 CALR2: Calibration 2 (Register Address 12) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 CALLKGR R/W CALLKGT R/W CALMADC CALDACO CALADCO CALCMBAL R/W R/W R/W R/W Reset settings = 0x3F Bit Name Function 7:6 5 Reserved CALLKGR Read returns zero. RING Leakage Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Leakage Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Monitor ADC Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. DAC Offset Calibration. Calibrates the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ADC Offset Calibration. Calibrates the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode Balance Calibration. Calibrates the ac longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 4 CALLKGT 3 CALMADC 2 CALDACO 1 CALADCO 0 CALCMBAL Preliminary Rev. 0.96 65 S i3232 DIAG: Diagnostic Tools (Register Address 13) (Register type: Diagnostics) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 IQ2HR R/W IQ1HR R/W TSTRING R/W TXFILT R/W SDIAG R/W SDIAGIN[2:0] R/W Reset settings = 0x00 Bit Name Function Monitor ADC IQ2 High-Resolution Enable. Sets MADC to high-resolution range for IQ2 conversion. 0 = MADC not set to high resolution. 1 = MADC set to high resolution. Monitor ADC IQ1 High-Resolution Enable. Sets MADC to high-resolution range for IQ1 conversion. 0 = MADC not set to high resolution. 1 = MADC set to high resolution. Test Ringing Generator Enable. Enables the capability of generating a low-level ringing signal for diagnostic purposes. 0 = Test-ringing generator disabled. 1 = Test-ringing generator enabled. Transmit Path Audio Diagnostics Filter Enable. Enables the transmit path diagnostics filters. 0 = Transmit audio path diagnostics filters disabled. 1 = Transmit audio path diagnostics filters enabled. SLIC Diagnostics Filter Enable. Enables the SLIC path diagnostics filters. 0 = SLIC diagnostics filters disabled. 1 = SLIC diagnostics filters enabled. SLIC Diagnostics Filter Input. Selects the input to the SLIC diagnostics filter for dc and low-frequency line parameters. 000 = TIP voltage. 001 = RING voltage. 010 = Loop voltage, VTIP – VRING. 011 = Longitudinal voltage, (VTIP + VRING)/2. 100 = Loop (metallic) current. 101 = Longitudinal current. 7 IQ2HR 6 IQ1HR 5 TSTRING 4 TXFILT 3 SDIAG 2:0 SDIAGIN[2:0] 66 Preliminary Rev. 0.96 S i3232 ID: Chip Identification (Register Address 0) (Register type: Initialization/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 PARTNUM[2:0] R REV[3:0] R Reset settings = 0xxx Bit Name Function 7 6:4 Reserved Read returns zero. PARTNUM[2:0] Part Number Identification. 000-010 = Reserved 011 = Si3232 100–111 = Reserved REV[3:0] Revision Number Identification. 0001 = Revision A 0010 = Revision B 0011 = Revision C 0100 = Revision D 0101 = Revision E 0110 = Revision F 0111 = Revision G 3:0 ILIM: Loop Current Limit (Register Address 10) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 ILIM[4:0] R/W Reset settings = 0x05 Bit Name Function 7:5 4:0 Reserved ILIM[4:0] Read returns zero. Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 18 mA (0x00) and 45 mA (0x20) in 0.875 mA steps. Preliminary Rev. 0.96 67 S i3232 IRQ0: Interrupt Status 0 (Register Address 14) (Register type: Operational/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 CLKIRQ R IRQ3B R IRQ2B R IRQ1B R IRQ3A R IRQ2A R IRQ1A R Reset settings = 0x00 Read this interrupt to indicate which interrupt status byte, from which channel, has a pending interrupt. Bit Name Function Clock Failure Interrupt Pending. 0 = No interrupt pending. 1 = Clock failure interrupt pending. Clock failure status indicated in MSTRSTAT register, bits 7:5. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 3 (IRQ3) for channel B. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 2 (IRQ2) for channel B. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 1 (IRQ1) for channel B. 7 CLKIRQ 6 IRQ3B 5 IRQ2B 4 IRQ1B 3 2 Reserved IRQ3A Read returns zero. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 3 (IRQ3) for channel A. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 2 (IRQ2) for channel A. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 1 (IRQ1) for channel A. 1 IRQ2A 0 IRQ1A 68 Preliminary Rev. 0.96 S i3232 IRQ1: Interrupt Status 1 (Register Address 15) (Register type: Operational/bits writable in GCI mode only) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PULSTAS PULSTIS RINGTAS Type RINGTIS R/W R/W R/W R/W Reset settings = 0x00 Bit Name Function Pulse Metering Active Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Pulse Metering Inactive Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Active Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Inactive Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. 7 PULSTAS 6 PULSTIS 5 RINGTAS 4 RINGTIS 3:0 Reserved Read returns zero. Preliminary Rev. 0.96 69 S i3232 IRQ2: Interrupt Status 2 (Register Address 16) (Register type: Operational/bits writable in GCI mode only) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RAMIRS R/W DTMFS R/W VOCTRKS R/W LONGS R/W LOOPS R/W RTRIPS R/W Reset settings = 0x00 Bit Name Function 7:6 5 Reserved RAMIRS Read returns zero. RAM Access Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. DTMF Tone Detect Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. VOC Tracking Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ground Key Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Loop Closure Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ring Trip Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. 4 DTMFS 3 VOCTRKS 2 LONGS 1 LOOPS 0 RTRIPS 70 Preliminary Rev. 0.96 S i3232 IRQ3: Interrupt Status 3 (Register Address 17) (Register type: Operational/bits writable in GCI mode only) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 CMBALS R/W PQ6S R/W PQ5S R/W PQ4S R/W PQ3S R/W PQ2S R/W PQ1S R/W Reset settings = 0x00 Bit Name Function Common Mode Balance Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. 7 CMBALS 6 5 Reserved PQ6S Read returns zero. Power Alarm Q6 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q5 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q4 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q3 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q2 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q1 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. 4 PQ5S 3 PQ4S 2 PQ3S 1 PQ2S 0 PQ1S Preliminary Rev. 0.96 71 S i3232 IRQEN1: Interrupt Enable 1 (Register Address 18) (Register type: Initialization) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PULSTAE PULSTIE RINGTAE Type RINGTIE R/W R/W R/W R/W Reset settings = 0x00 Bit Name Function Pulse Metering Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Pulse Metering Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 7 PULSTAE 6 PULSTIE 5 RINGTAE 4 RINGTIE 3:0 Reserved Read returns zero. 72 Preliminary Rev. 0.96 S i3232 IRQEN2: Interrupt Enable 2 (Register Address 19) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RAMIRE R/W DTMFE R/W VOCTRKE R/W LONGE R/W LOOPE R/W RTRIPE R/W Reset settings = 0x00 Bit Name Function 7:6 5 Reserved RAMIRE Read returns zero. RAM Access Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. DTMF Tone Detect Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. VOC Tracking Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ground Key Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Loop Closure Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 4 DTMFE 3 VOCTRKE 2 LONGE 1 LOOPE 0 RTRIPE Preliminary Rev. 0.96 73 S i3232 IRQEN3: Interrupt Enable 3 (Register Address 20) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 CMBALE R/W PQ6E R/W PQ5E R/W PQ4E R/W PQ3E R/W PQ2E R/W PQ1E R/W Reset settings = 0x00 Bit Name Function Common Mode Balance Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 7 CMBALE 6 5 Reserved PQ6E Read returns zero. Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 4 PQ5E 3 PQ4E 2 PQ3E 1 PQ2E 0 PQ1E 74 Preliminary Rev. 0.96 S i3232 LBCON: Loopback Enable (Register Address 22) (Register type: Diagnostic) Bit Name Type Bit 7 D7 D6 D5 D4 D3 D2 D1 D0 DLM R/W Name DLM Function Codec Loopback Mode Enable. 0 = Codec loopback mode disabled. 1 = Codec loopback mode enabled. Read returns zero. Reset settings = 0x00 6:0 Reserved LCRRTP: Loop Closure/Ring Trip/Ground Key Detection (Register Address 9) (Register type: Operational) Bit Name D7 D6 D5 D4 D3 D2 D1 D0 CMH R SPEED R VOCTST R LONGHI R RTP R LCR R Type Reset settings = 0x40 Bit 7:6 5 Name Reserved CMH Function 4 SPEED 3 VOCTST Read returns zero. Common Mode High Threshold. Indicates that common-mode threshold has been exceeded. 0 = Common-mode threshold not exceeded. 1 = Common-mode threshold exceeded. Speedup Mode Enable. 0 = Speedup disabled. 1 = Automatic speedup. VOC Tracking Status. Indicates that battery voltage has dropped and VOC tracking is enabled. 0 = VOC tracking threshold not exceeded, VTR on-hook = VOC. 1 = VOC tracking threshold exceeded, VTR on-hook = VOCtrack. Ground Key Detect Flag. 0 = Ground key event has not been detected. 1 = Ground key event has been detected. Ring Trip Detect Flag. 0 = Ring trip event has not been detected. 1 = Ring trip event has been detected. Loop Closure Detect Flag. 0 = Loop closure event has not been detected. 1 = Loop closure event has been detected. 2 LONGHI 1 RTP 0 LCR Note: Detect bits are not sticky bits. Refer to interrupt status for interrupt bit history indication. Preliminary Rev. 0.96 75 S i3232 LINEFEED: Linefeed Control (Register Address 6) (Register type: Operational) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 LFS[2:0] R LF[2:0] R/W Reset settings = 0x00 Bit Name Function 7 6:4 Reserved LFS[2:0] Read returns zero. Linefeed Shadow. This register reflects the actual realtime linefeed status. Automatic operations may cause actual linefeed state transitions regardless of the Linefeed register settings (e.g., when the Linefeed register is in the ringing state, the Linefeed Shadow register will reflect the ringing state during ringing bursts and the OHT state during silent periods between ringing bursts). 000 = Open 001 = Forward Active 010 = Forward On-hook Transmission (OHT) 011 = TIP Open 100 = Ringing 101 = Reverse Active 110 = Reverse On-hook Transmission 111 = RING Open 3 2:0 Reserved LF[2:0] Read returns zero. Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward Active 010 = Forward On-hook Transmission (OHT) 011 = TIP Open 100 = Ringing 101 = Reverse Active 110 = Reverse On-hook Transmission 111 = RING Open 76 Preliminary Rev. 0.96 S i3232 MSTREN: Master Initialization Enable (Register Address 2) (Register type: Initialization/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 PLLFLT R/W FSFLT R/W PCFLT R/W Reset settings = 0x00 Bit Name Function PLL Lock Fault Enable. 0 = PLLFAULT interrupt bit is enabled. 1 = PLLFAULT interrupt bit is disabled. FSYNC Clock Fault Enable. 0 = FSYNC interrupt bit is enabled. 1 = FSYNC interrupt bit is disabled. PCM Clock Fault Enable. 0 = PCM interrupt bit is enabled. 1 = PCM interrupt bit is disabled. 7 PLLFLT 6 FSFLT 5 PCFLT 4:0 Reserved Read returns zero. Preliminary Rev. 0.96 77 S i3232 MSTRSTAT: Master Initialization Status (Register Address 3) (Register type: Initialization/single value instance for both channels) Bit Type D7 D6 D5 D4 D3 D2 D1 D0 Name PLLFAULT FSFAULT PCFAULT SRCLR R PLOCK R FSDET R FSVAL R PCVAL R R/W R/W R/W Reset settings = 0x00 Bit 7 Name PLLFAULT Function PLL Lock Fault Status. This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to this bit clears the status. 0 = PLL lock is valid. 1 = PLL has lost lock. FSYNC Clock Fault Status. This bit is set when the FSVAL and FSDET bits transition low, indicating loss of valid FSYNC signal or invalid FSYNC-to-PCLK ratio. Writing 1 to this bit clears the status. 0 = Correct FSYNC to PCLK ration present. 1 = FSYNC to PCLK ratio lost. PCM Clock Fault Status. This bit will be set when the PCVAL bit transitions low. Writing 1 to this bit clears the status. 0 = Valid PCLK signal present. 1 = No valid PCLK signal present. SRAM Clear Status Detect. 0 = SRAM clear operation not initiated or in progress. 1 = SRAM clear operation has completed. PLL Lock Detect. Indicates the internal PLL is locked relative to FSYNC. 0 = PLL has lost lock relative to FSYNC. 1 = PLL locked relative to FSYNC. FSYNC to PCLK Ratio Detect. Indicates a valid FSYNC to PCLK ratio has been detected. 0 = Invalid FSYNC to PCLK ratio detected. 1 = Correct FSYNC to PCLK ratio present. FSYNC Clock Valid. Indicates that a minimum valid FSYNC signal is present. 0 = FSYNC signal is not valid. 1 = FSYNC signal is present. PCM Clock Valid. Indicates that a minimum valid PCLK signal is present. 0 = PCLK signal is ≤ 128 kHz. 1 = PCLK signal is ≥ 128 kHz. 6 FSFAULT 5 PCFAULT 4 SRCLR 3 PLOCK 2 FSDET 1 FSVAL 0 PCVAL 78 Preliminary Rev. 0.96 S i3232 PMCON: Pulse Metering Control (Register Address 28) (Register type: Operational) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ENSYNC Type TAEN1 R/W TIEN1 R/W PULSE1 R/W R Reset settings = 0x00 Bit Name Function Pulse Metering Waveform Present Flag. Indicates a pulse-metering waveform is present. 0 = No pulse metering waveform present. 1 = Pulse metering waveform present. 7 ENSYNC 6:5 4 Reserved TAEN1 Read returns zero. Pulse Metering Active Timer Enable. 0 = Timer disabled. 1 = Timer enabled. Pulse Metering Inactive Timer Enable. 0 = Timer disabled. 1 = Timer enabled. Pulse Metering Enable. 0 = Pulse metering disabled. 1 = Pulse metering enabled. 3 TIEN1 2 PULSE1 1:0 Reserved Read returns zero. PMTAHI: Pulse Metering Oscillator Active Timer—High Byte (Register Address 30) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 PULSETA[15:8] R/W Reset settings = 0x00 Bit Name Function 7:0 PULSETA[15:8] Pulse Metering Oscillator Active Timer. This register contains the upper 8 bits of the pulse metering oscillator active timer. Register 29 contains the lower 8 bits of this value. Preliminary Rev. 0.96 79 S i3232 PMTALO: Pulse Metering Oscillator Active Timer—Low Byte (Register Address 29) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 PULSETA[7:0] R/W Reset settings = 0x00 Bit Name Function Pulse Metering Oscillator Active Timer. This register contains the lower 8 bits of the pulse-metering oscillator active timer. Register 30 contains the upper 8 bits of this value. 1.25 µs/LSB. 7:0 PULSETA[7:0] PMTIHI: Pulse Metering Oscillator Inactive Timer—High Byte (Register Address 32) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 PULSETI[15:8] R/W Reset settings = 0x00 Bit Name Function 7:0 PULSETI[15:8] Pulse Metering Oscillator Inactive Timer. This register contains the upper 8 bits of the pulse-metering oscillator inactive timer. Register 29 contains the lower 8 bits of this value. PMTILO: Pulse Metering Oscillator Inactive Timer—Low Byte (Register Address 31) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 PULSETI[7:0] R/W Reset settings = 0x00 Bit Name Function Pulse Metering Oscillator Inactive Timer. This register contains the lower 8 bits of the pulse-metering oscillator inactive timer. Register 30 contains the upper 8 bits of this value. 1.25 µs/LSB. 7:0 PULSETI[7:0] 80 Preliminary Rev. 0.96 S i3232 POLREV: Polarity Reversal Settings (Register Address 7) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 POLREV R VOCZERO R/W PREN R/W RAMP R/W Reset settings = 0x00 Bit Name Function 7:4 3 Reserved POLREV Read returns zero. Polarity Reversal Status. 0 = Forward polarity. 1 = Reverse polarity. Wink Function Control. Enables a wink function by decrementing the open circuit voltage to zero. 0 = Maintain current VOC value. 1 = Decrement VOC voltage to 0 V. Smooth Polarity Reversal Enable. 0 = Disabled. 1 = Enabled. Smooth Polarity Reversal Ramp Rate. 0 = 1 V/1.25 ms ramp rate. 1 = 2 V/1.25 ms ramp rate. 2 VOCZERO 1 PREN 0 RAMP RAMADDR: RAM Address (Register Address 103) (Register type: Operational/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RAMADDR[7:0] R/W Reset settings = 0x00 Bit Name Function 7:0 RAMADDR[7:0] RAM Data—Low Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR into RAMDAT only at the next memory update (READ operation). Preliminary Rev. 0.96 81 S i3232 RAMDATHI: RAM Data—High Byte (Register Address 102) (Register type: Operational/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RAMDAT[15:8] R/W Reset settings = 0x00 Bit Name Function 7:0 RAMDAT[15:8] RAM Data—High Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR into RAMDAT only at the next memory update (READ operation). RAMDATLO: RAM Data—Low Byte (Register Address 101) (Register type: Operational/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RAMDAT[7:0] R/W Reset settings = 0x00 Bit Name Function 7:0 RAMDAT[15:8] RAM Data—Low Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR only into RAMDAT at the next memory update (READ operation). 82 Preliminary Rev. 0.96 S i3232 RAMSTAT: RAM Address Status (Register Address 4) (Register type: Operational) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RAMSTAT R Reset settings = 0x00 Bit Name Function 7:1 0 Reserved RAMSTAT Read returns zero. RAM Address Status. 0 = RAM ready for access. 1 = RAM access pending internally (busy). RESET: Soft Reset (Register Address 1) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RESETB R/W RESETA R/W Reset settings = 0x00 Bit Name Function 7:2 1 Reserved RESETB Read returns zero. Soft Reset, Channel B. 0 = Normal operation. 1 = Initiate soft reset to Channel B. Soft Reset, Channel A. 0 = Normal operation. 1 = Initiate soft reset to Channel A. 0 RESETA Note: Soft reset set to a single channel of a given device causes all register space to reset to default values for that channel. Soft reset set to both channels of a given device causes a hardware reset including PLL reinitialization and RAM clear. Preliminary Rev. 0.96 83 S i3232 RINGCON: Ringing Configuration (Register Address 23) (Register type: Initialization) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ENSYNC RDACEN RINGUNB Type TAEN R/W TIEN R/W RINGEN R UNBPOLR R/W TRAP R/W R R R/W Reset settings = 0x00 Bit Name Function Ringing Waveform Present Flag. 0 = No ringing waveform present. 1 = Ringing waveform present. Ringing Waveform Sent to Differential DAC. 0 = Ringing waveform not sent to differential DAC. 1 = Ringing waveform set to differential DAC. Unbalanced Ringing Enable. Enables internal unbalanced ringing generation. 0 = Unbalanced ringing not enabled. 1 = Unbalanced ringing enabled. Ringing Active Timer Enable. 0 = Ringing active timer disabled. 1 = Ringing active timer enabled. Ringing Inactive Timer Enable. 0 = Ringing inactive timer disabled. 1 = Ringing inactive timer enabled. Ringing Oscillator Enable Monitor. This bit will toggle when the ringing oscillator is enabled and disabled. 0 = Ringing oscillator is disabled. 1 = Ringing oscillator is enabled. Reverse Polarity Unbalanced Ringing Select. The RINGOF RAM location must be modified from its normal ringing polarity setting. Refer to “4.7. Internal Unbalanced Ringing” for details. 0 = Normal polarity ringing. 1 = Reverse polarity ringing. Ringing Waveform Selection. 0 = Sinusoid waveform. 1 = Trapezoid waveform. 7 ENSYNC 6 RDACEN 5 RINGUNB 4 TAEN 3 TIEN 2 RINGEN 1 UNBPOLR 0 TRAP 84 Preliminary Rev. 0.96 S i3232 RINGTAHI: Ringing Oscillator Active Timer—High Byte (Register Address 25) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RINGTA[15:8] R/W Reset settings = 0x00 Bit Name Function Ringing Oscillator Active Timer. This register contains the upper 8 bits of the ringing oscillator active timer (the on-time of the ringing burst). Register 24 contains the upper 8 bits of this value. 7:0 RINGTA[15:8] RINGTALO: Ringing Oscillator Active Timer—Low Byte (Register Address 24) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RINGTA[7:0] R/W Reset settings = 0x00 Bit Name Function Ringing Oscillator Active Timer. This register contains the lower 8 bits of the ringing oscillator active timer (the on-time of the ringing burst). Register 25 contains the upper 8 bits of this value. 1.25 µs/LSB. 7:0 RINGTA[7:0] RINGTIHI: Ringing Oscillator Inactive Timer—High Byte (Register Address 27) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RINGTI[15:8] R/W Reset settings = 0x00 Bit Name Function Ringing Oscillator Inactive Timer. This register contains the upper 8 bits of the ringing oscillator inactive timer (the silent period between ringing bursts). Register 26 contains the upper 8 bits of this value. 7:0 RINGTI[15:8] Preliminary Rev. 0.96 85 S i3232 RINGTILO: Ringing Oscillator Inactive Timer—Low Byte (Register Address 26) (Register type: Initialization) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RINGTI[7:0] R/W Reset settings = 0x00 Bit Name Function Ringing Oscillator Inactive Timer. This register contains the lower 8 bits of the ringing oscillator inactive timer (the silent time between ringing bursts). Register 27 contains the upper 8 bits of this value. 1.25 µs/ LSB. 7:0 RINGTI[7:0] RLYCON: Relay Driver and Battery Switching Configuration (Register Address 5) (Register type: Diagnostic) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 BSEL R RRAIL R/W RDOE R/W GPO R/W Reset settings = 0xA3 Bit Name Function 7:6 5 Reserved BSEL Read returns 10 binary. Battery Select Indicator. 0 = BATSEL pin is output low. (Si3200 internal battery switch open). 1 = BATSEL pin is output high. (Si3200 internal battery switch closed). Additional Ringing Rail Present (Third Battery). 0 = Ringing rail not present. 1 = Ringing rail present. For Si3220, RRD/GPO toggles with LINEFEED ringing cadence. Relay Driver Output Enable. 0 = Disabled. 1 = Enabled. General Purpose Output. 0 = GPO output low. 1 = GPO output high. 4 RRAIL 3 RDOE 2 GPO 1:0 Reserved Read returns zero. 86 Preliminary Rev. 0.96 S i3232 SBIAS: SLIC Bias Control (Register Address 8) (Register type: Initialization/protected register bits) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 STDBY R/W–P SQLCH R/W–P CAPB R/W–P BIASEN R/W–P OBIAS[1:0] R/W–P ABIAS[1:0] R/W–P Reset settings = 0xE0 Bit Name Function Low-power Standby Status. Writing to this bit causes temporary manual control of this bit until a subsequent on-hook or off-hook transition. 0 = low-power mode off (i.e. Active off-hook). 1 = low-power mode on (i.e. Active on-hook). Audio Squelch Control. Indicates squelch of audio during the setting time set by the SPEEDUP RAM coefficient. Writing to this bit causes temporary manual override until a speedup event occurs. 0 = Squelch off. 1 = Squelch on. Audio Filter Capacitor Bypass. Indicates filter capacitor pass during the setting time set by the SPEEDUP RAM coefficient. Writing to this bit causes temporary manual override until a speedup event occurs. 0 = Capacitors not bypassed. 1 = Capacitors bypassed. SLIC Bias Enable. Writing to this bit causes temporary manual control of SLIC bias until a subsequent onhook or off-hook state. 0 = SLIC bias off (i.e. Active on-hook). 1 = = SLIC bias on (i.e. Active off-hook). SLIC Bias Level, On-Hook Transmission State. DC bias current flowing in the SLIC circuit during on-hook transmission state. Increasing this value increases the ability of the SLIC to withstand longitudinal current artifacts. 00 = 4 mA per lead. 01 = 8 mA per lead. 10 = 12 mA per lead. 11 = 16 mA per lead. SLIC Bias Level, Active State. DC bias current flowing in the SLIC circuit during the active off-hook state. Increasing this value increases the ability of the SLIC to withstand longitudinal current artifacts. 00 = 4 mA per lead. 01 = 8 mA per lead. 10 = 12 mA per lead. 11 = 16 mA per lead. 7 STDBY 6 SQLCH 5 CAPB 4 BIASEN 3:2 OBIAS[1:0] 1:0 ABIAS[1:0] Note: Bit type “P” = user-protected bits. Refer to the protected register bit section in the text of this application note. Preliminary Rev. 0.96 87 S i3232 THERM: Si3200 Thermometer (Register Address 72) (Register type: Diagnostic/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 STAT R SEL R/W Reset settings = 0x00 Bit Name Function Si3200 Thermometer Status. Reads whether the Si3200 has shut down due to an over-temperature event. 0 = Si3200 operating within normal operating temperature range. 1 = Si3200 has exceeded maximum operating temperature. 7 STAT 6 SEL Si3200 Power Sensing Mode Select (Protected Register Bit). 0 = Transistor power sum used for power sensing (PSUM vs. threshold in PTH12) 1 = Si3200 therm diode used for power sensing. Read returns zero. 5:0 Reserved ZRS: Impedance Synthesis—Analog Real Coefficient (Register Address 33) (Register type: Initialization/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 RS[3:0] R/W Reset settings = 0x00 Bit Name Function 7:4 3:0 Reserved RS[3:0] Read returns zero. Impedance Synthesis Analog Real Coefficient. Refer to coefficient generation program. 88 Preliminary Rev. 0.96 S i3232 ZZ: Impedance Synthesis—Analog Complex Coefficient (Register Address 34) (Register type: Initialization/single value instance for both channels) Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 ZSDIS R/W ZSOHT R/W ZP[1:0] R/W ZZ[1:0] R/W Reset settings = 0x00 Bit Name Function Analog Impedance Synthesis Coefficient Disable. Enables/disables RS, ZSOHT, ZP, and ZZ coefficients. 0 = Analog ZSYNTH coefficients enabled. 1 = Analog ZSYNTH coefficients disabled. Analog Impedance Synthesis Complex Coefficients. Refer to coefficient generation program. 7 ZSDIS 6 5:4 3:2 1:0 ZSOHT ZP[1:0] Reserved ZZ[1:0] Preliminary Rev. 0.96 89 S i3232 7. 16-Bit RAM Address Summary1 All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a similar manner as the 8-bit control registers except that the data are twice as long. In addition, one additional READ cycle is required during READ operations to accommodate the one-deep pipeline architecture. (See "4.16. SPI Control Interface" on page 50 for more details). All internal RAM addresses are assigned a default value of zero during initialization and following a system reset. Unless otherwise noted, all RAM addresses use a 2s complement, MSB first data format (ordered alphabetically by mnemonic). RAM Addr Mnemonic Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Ex. Hex Ex. Dec Unit Battery Selection and VOC Tracking 31 BATHTH High Battery Switch Threshold Battery Tracking Filter Coeff Low Battery Switch Threshold RING Voltage Filter Coeff BATHTH[14:7]2 Init 0E54 18 V 34 BATLPF BATLPF[15:3] Init 0A08 10 32 BATLTH BATLTH[14:7]2 Init 0D88 17 V 33 BSWLPF BSWLPF[15:3] Speedup Init 0A08 10 36 CMHITH Speedup Threshold— High Byte Speedup Threshold— Low Byte CMHITH[15:0] Init 0001 1 V 35 CMLOTH CMLOTH[15:0] Init 07F5 10 V SLIC Diagnostics Filter 53 DIAGAC SLIC Diags AC Detector Threshold SLIC Diags AC Filter Coeff SLIC Diags dc Output SLIC Diags dc Filter Coeff SLIC Diags Peak Detector DIAGAC[15:0] Diag V 54 51 52 55 DIAGACCO DIAGDC DIAGDCCO DIAGPK DIAGACCO[15:3] DIAGDC[15:0] DIAGDCCO[15:3] DIAGPK[15:0] Diag Diag Diag Diag 7FF8 127.3 Hz V 0A08 10 Hz V Loop Currents 9 ILONG Longitudinal Current Sense Value Loop Current Sense Value Q5 Current Measurement Q3 Current Measurement Q2 Current Measurement Q6 Current Measurement Q4 Current Measurement Q1 Current Measurement ILONG[15:0]2 DIag mA 8 18 16 15 19 17 14 ILOOP IRING IRINGN IRINGP ITIP ITIPN ITIPP ILOOP[15:0]2 IRING[15:0] IRINGN[15:0] IRINGP[15:0] ITIP[15:0] ITIPN[15:0] ITIPP[15:0] Loop Closure Detection Diag Diag Diag Diag Diag Diag Diag mA mA mA mA mA mA mA 24 LCRDBI Loop Closure Detection Debounce Interval Loop Closure Filter Coeff LCRDBI[15:0]2 Init 000C 15 ms 25 Notes: 1. 2. LCRLPF LCRLPF[15:3] Init 0A10 10 RAM values are 2’s complement unless otherwise noted. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. 90 Preliminary Rev. 0.96 S i3232 RAM Addr 26 Mnemonic LCRMASK Description Loop Closure Mask Interval Coeff LCR Mask During Polarity Reversal Off-Hook Detect Threshold On-Hook Detect Threshold Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Init Ex. Hex 0040 Ex. Dec 80 Unit ms LCRMASK[15:0]2 166 LCRMSKPR LCRMSKPR[15:0] Init 0040 80 ms 22 23 LCROFFHK LCRONHK LCROFFHK[15:0]2 LCRONHK[15:0]2 Longitudinal Current Detection Init Init 0C0C 0DE0 10 11 mA mA 29 LONGDBI Ground Key Detection Debounce Interval Ground Key Detection Threshold Ground Key Removal Detection Threshold Ground Key Filter Coeff LONGDBI[15:0]2 Init ms 27 LONGHITH LONGHITH[15:0]2 Init 08D4 7 mA 28 LONGLOTH LONGLOTH[15:0]2 Init 0A17 8 mA 30 LONGLPF LONGLPF[15:3] Power Filter Coefficients Init 0A08 10 40 PLPF12 Q1/Q2 Thermal Low-pass Filter Coeff Q3/Q4 Thermal Low-pass Filter Coeff Q5/Q6 Thermal Low-pass Filter Coeff PLPF12[15:3] Init 0008 .3 s 41 PLPF34 PLPF34[15:3] Init 0008 .3 s 42 PLPF56 PLPF56[15:3] Init 0008 .3 s Pulse Metering 68 70 PMAMPL PMAMPTH Pulse Metering Amplitude Pulse Metering AGC Amplitude Threshold Pulse Metering Frequency Pulse Metering Ramp Rate PMAMPL[15:0] PMAMPTH[15:0] Init Init 4000 00C8 65536 798 V V 67 PMFREQ PMFREQ[15:3] Init 0000 0 Hz 69 PMRAMP PMRAMP[15:0] Power Calculations Init 008A 550 s 44 45 46 47 48 49 50 37 38 39 43 PQ1DH PQ2DH PQ3DH PQ4DH PQ5DH PQ6DH PSUM PTH12 PTH34 PTH56 RB56 Q1 Calculated Power Q2 Calculated Power Q3 Calculated Power Q4 Calculated Power Q5 Calculated Power Q6 Calculated Power Total Calculated Power Q1/Q2 Power Threshold Q3/Q4 Power Threshold Q5/Q6 Power Threshold Q5/Q6 Base Resistor PQ1DH[15:0] PQ2DH[15:0] PQ3DH[15:0] PQ4DH[15:0] PQ5DH[15:0] PQ6DH[15:0] PSUM[15:0] PTH12[15:0] PTH34[15:0] PTH56[15:0] RB56[15:0] Ringing 2 2 2 Diag Diag Diag Diag Diag Diag Diag Init Init Init Init 0007 003C 002A .22 17 1.28 W W W W W W W W W W Ω 59 Notes: 1. 2. RINGAMP Ringing Amplitude RINGAMP[15:0] Init 00D5 47 Vrms RAM values are 2’s complement unless otherwise noted. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. Preliminary Rev. 0.96 91 S i3232 RAM Addr 57 Mnemonic RINGFRHI Description Ringing Frequency— High Byte Ringing Frequency— Low Byte Ringing Waveform dc Offset Ringing Oscillator Initial Phase Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Init Ex. Hex 3F78 Ex. Dec 20 Unit Hz RINGFRHI[14:0] 58 RINGFRLO RINGFRLO[14:3] Init 6CE8 20 Hz 56 RINGOF RINGOF[14:0] Init 0000 0 V 60 RINGPHAS RINGPHAS[15:3] Init 0000 Ring Trip Detection 66 RTACDB AC Ring Trip Debounce Interval AC Ring Trip Detect Threshold DC Ring Trip Debounce Interval DC Ring Trip Detect Threshold Ring Trip Low-pass Filter Coeff Period RTACDB[15:0] Init 0003 75 ms 64 RTACTH RTACTH[15:0] Init 1086 mA 65 RTDCDB RTDCDB[15:0] Init 0003 75 ms 62 RTDCTH RTDCTH[15:0] Init 7FFF mA 63 RTPER RTPER[15:0] Init 0028 40 DC Speedup 168 169 SPEEDUP SPEEDUPR DC Speedup Timer Ring Speedup Timer SPEEDUP[15:0] SPEEDUPR[15:0]2 Loop Voltages 13 VBAT Scaled Battery Voltage Measurement Common Mode Voltage Loop Voltage Open Circuit Voltage VOC Delta for Off-Hook VOC Delta Upper Threshold VOC Delta Lower Threshold Battery Tracking Open Circuit Voltage Overhead Voltage Ringing Overhead Voltage Scaled RING Voltage Measurement Scaled TIP Voltage Measurement VBAT[15:0] Diag V Init Init 0000 0000 60 60 ms ms 4 7 0 1 3 VCM VLOOP VOC VOCDELTA VOCHTH VCM[15:0]2 VLOOP[15:0]2 VOC[15:0]2 VOCDELTA[15:0]2 VOCHTH[15:0]2 Init Diag Init Init Init 0268 3 V V 2668 059A 0198 48 7 2 V V V 2 VOCLTH VOCLTH[15:0] Init F9A2 –8 V 10 VOCTRACK VOCTRACK[15:0]2 Diag V 5 6 VOV VOVRING VOV[15:0]2 VOVRING[14:0] 2 Init Init 0334 0000 4 0 V V 12 VRING VRING[15:0] Diag V 11 VTIP VTIP[15:0] Diag V Notes: 1. 2. RAM values are 2’s complement unless otherwise noted. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses. 92 Preliminary Rev. 0.96 S i3232 8. 16-Bit Control Descriptions BATHTH: High Battery Switch Threshold (RAM Address 31) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BATHTH[14:7] R/W Reset settings = 0x00 Bit Name Function High Battery Switch Threshold. Programs the voltage threshold for selecting the high battery supply (VBATH). Threshold is compared to the RING lead voltage (normal ACTIVE mode) plus the VOV value. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution. 14:7 BATHTH[14:7] BATLPF: Battery Tracking Filter Coefficient (RAM Address 34) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BATLPF[15:3] R/W Reset settings = 0x00 Bit Name Function Battery Tracking Filter Coefficient. Programs the digital low-pass filter block that filters the voltage measured on the RING lead when battery tracking is enabled. 15:3 BATLPF[15:3] BATLTH: Low Battery Switch Threshold (RAM Address 32) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BATLTH[14:7] R/W Reset settings = 0x00 Bit Name Function Low Battery Switch Threshold. Programs the voltage threshold for selecting the low battery supply (VBATL). Threshold is compared to the RING lead voltage (normal ACTIVE mode) plus the VOV value. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution. 14:7 BATLTH[14:7] Preliminary Rev. 0.96 93 S i3232 BSWLPF: RING Voltage Filter Coefficient (RAM Address 33) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BSWLPF[15:3] R/W Reset settings = 0x00 Bit Name Function RING Voltage Filter Coefficient. Programs the digital low-pass filter block that filters the voltage measured on the RING lead used to determine battery switching threshold. 15:3 BSWLPF[15:3] CMHITH: Speedup Threshold—High Byte (RAM Address 36) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CMHITH[15:0] R/W Reset settings = 0x00 Bit Name Function Speedup Threshold—High Byte. Programs the upper byte of the threshold at which speedup mode in enabled. The CMLOTH RAM location holds the lower byte of this value. 15:0 CMHITH[15:0] CMLOTH: Speedup Threshold—Low Byte (RAM Address 35) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CMLOTH[15:0] R/W Reset settings = 0x00 Bit Name Function Speedup Threshold—Low Byte. Programs the lower byte of the threshold at which speedup mode in enabled. The CMHITH RAM location holds the upper byte of this value. 15:0 CMLOTH[15:0] 94 Preliminary Rev. 0.96 S i3232 DIAGAC: SLIC Diagnostics AC Output (RAM Address 53) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIAGAC[15:0] R/W Reset settings = 0x00 Bit Name Function SLIC Diagnostic AC Output. Provides a filtered value that reflects the ac rms value from the output of the monitor ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13). The DIAGACCO RAM location determines the rms filter coefficient used. This register is used for frequencies < 300 Hz. 15:0 DIAGAC[15:0] DIAGACCO: SLIC Diagnostics AC Filter Coefficient (RAM Address 54) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIAGACCO[15:3] R/W Reset settings = 0x00 Bit Name Function SLIC Diagnostics AC Filter Coefficient. Programs the rms filter coefficient used in the ac measurement result from the monitor ADC. 15:3 DIAGACCO[15:3] DIAGDC: SLIC Diagnostics dc Output (RAM Address 51) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIAGDC[15:0] R/W Reset settings = 0x00 Bit Name Function SLIC Diagnostic DC Output. Provides a low-pass filtered value that reflects the dc value from the output of the monitor ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13). The DIAGDCCO RAM location determines the low-pass filter coefficient used. 15:0 DIAGDC[15:0] Preliminary Rev. 0.96 95 S i3232 DIAGDCCO: SLIC Diagnostics dc Filter Coefficient (RAM Address 52) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIAGDCCO[15:3] R/W Reset settings = 0x00 Bit Name Function SLIC Diagnostics dc Filter Coefficient. Programs the low-pass filter coefficient used in the dc measurement result from the monitor ADC. 15:3 DIAGDCCO[15:3] DIAGPK: SLIC Diagnostics Peak Detector (RAM Address 55) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DIAGPK[15:0] R/W Reset settings = 0x00 Bit Name Function SLIC Diagnostic Peak Detector. Provides filtered value that reflects the peak amplitude from the output of the monitor ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13). 15:0 DIAGPK[15:0] ILONG: Longitudinal Current Sense Value (RAM Address 9) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ILONG[15:0] R/W Reset settings = 0x00 Bit Name Function Longitudinal Current Sense Value. Holds the realtime measured longitudinal current. 0 to 101.09 mA measurement range, 3.097 µA/LSB, 500 µA effective resolution. Updated at an 800 Hz rate, signed/magnitude. 15:0 ILONG[15:0] 96 Preliminary Rev. 0.96 S i3232 ILOOP: Loop Current Sense Value (RAM Address 8) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ILOOP[15:0] R/W Reset settings = 0x00 Bit Name Function Loop Current Sense Value. Holds the realtime measured loop current. 0 to 101.09 mA measurement range, 3.097 µA/LSB, 500 µA effective resolution. 800 Hz update rate, signed/magnitude. 15:0 ILOOP[15:0] IRING: (Transistor Q5) Current Measurement (RAM Address 18) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IRING[15:0] R/W Reset settings = 0x00 Bit Name Function IRING (Transistor Q5) Current Measurement. Reflects the current flowing into the IRING pin of the Si3200 (transistor Q5 of a discrete circuit). 3.097 µA/LSB, 2’s complement. 15:0 IRING[15:0] IRINGN: (Transistor Q3) Current Measurement (RAM Address 16) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IRINGN[15:0] R/W Reset settings = 0x00 Bit Name Function IRINGN (Transistor Q3) Current Measurement. Reflects the current flowing into the IRINGN pin of the Si3200 (transistor Q3 of a discrete circuit). 195.3 nA/LSB, 2’s complement. 15:0 IRINGN[15:0] Preliminary Rev. 0.96 97 S i3232 IRINGP: (Transistor Q2) Current Measurement (RAM Address 15) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IRINGP[15:0] R/W Reset settings = 0x00 Bit Name Function IRINGP (Transistor Q2) Current Measurement. Reflects the current flowing into the IRINGP pin of the Si3200 (transistor Q2 of a discrete circuit). 3.097 µA/LSB, 2’s complement. 15:0 IRINGP[15:0] ITIP: (Transistor Q6) Current Measurement (RAM Address 19) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ITIP[15:0] R/W Reset settings = 0x00 Bit Name Function ITIP (Transistor Q6) Current Measurement. Reflects the current flowing into the ITIP pin of the Si3200 (transistor Q6 of a discrete circuit). 3.097 µA/LSB, 2’s complement. 15:0 ITIP[15:0] ITIPN: (Transistor Q4) Current Measurement (RAM Address 17) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ITIPN[15:0] R/W Reset settings = 0x00 Bit Name Function ITIPN (Transistor Q4) Current Measurement. Reflects the current flowing into the ITIPN pin of the Si3200 (transistor Q4 of a discrete circuit). 195.3 nA/LSB, 2’s complement. 15:0 ITIPN[15:0] 98 Preliminary Rev. 0.96 S i3232 ITIPP: (Transistor Q1) Current Measurement (RAM Address 14) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ITIPP[15:0] R/W Reset settings = 0x00 Bit Name Function ITIPP (Transistor Q1) Current Measurement. Reflects the current flowing into the ITIPP pin of the Si3200 (transistor Q1 of a discrete circuit). 3.097 µA/LSB, 2’s complement. 15:0 ITIPP[15:0] LCRDBI: Loop Closure Detection Debounce Interval (RAM Address 24) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCRDBI[15:0] R/W Reset settings = 0x00 Bit Name Function Loop Closure Detection Debounce Interval. Programs the debounce interval during the loop closure detection process. Programmable range is 0 to 40.96 s, 1.25 ms/LSB. 15:0 LCRDBI[15:0] LCRLPF: Loop Closure Filter Coefficient (RAM Address 25) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCRLPF[15:3] R/W Reset settings = 0x00 Bit Name Function Loop Closure Filter Coefficient. Programs the digital low-pass filter block in the loop closure detection circuit. Refer to "4.5.1. Loop Closure Detection" on page 32 for calculation. 15:3 LCRLPF[15:3] Preliminary Rev. 0.96 99 S i3232 LCRMASK: Loop Closure Mask Interval Coefficient (RAM Address 26) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCRMASK[15:0] R/W Reset settings = 0x00 Bit Name Function Loop Closure Mask Interval Coefficient. Programs the loop closure detection mask interval. Programmable range is 0 to 40.96 s, 1.25 µs/LSB 15:0 LCRMASK[15:0] LCRMSKPR: LCR Mask During Polarity Reversal (RAM Address 166) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCRMSKPR[15:0] R/W Reset settings = 0x00 Bit Name Function LCR Mask During Polarity Reversal. Programs the loop closure detection mask interval during a polarity reversal. Programmable range is 0 to 40.96 s, 1.25 µs/LSB 15:0 LCRMSKPR[15:0] LCROFFHK: Loop Closure Detection Threshold—On-Hook to Off-Hook Transition (RAM Address 22) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCROFFHK[15:0] R/W Reset settings = 0x00 Bit Name Function Loop Closure Detection Threshold—On-Hook to Off-Hook Transition. Programs the loop current threshold at which a valid loop closure is detected when transitioning from on-hook to off-hook. Hysteresis is provided by programming the ONHKTH RAM location to a different value that detects the off-hook to on-hook transition threshold. 0 to 101.09 mA programmable range, 3.097 µA/LSB, 396.4 µA effective resolution. Usable range is 0 to 61 mA. 15:0 LCROFFHK[15:0] 100 Preliminary Rev. 0.96 S i3232 LCRONHK: Loop Closure Detection Threshold—Off-Hook to On-Hook Transition (RAM Address 23) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCRONHK[15:0] R/W Reset settings = 0x00 Bit Name Function Loop Closure Detection Threshold—Off-Hook to On-Hook Transition. Programs the loop current threshold at which a valid loop closure event has been terminated (the off-hook to on-hook transition). The OFFHKTH RAM location determines the loop current threshold for detecting the off-hook to on-hook transition. 0 to 101.09 mA programmable range, 3.097 µA/LSB, 396.4 µA effective resolution. Usable range is 0 to 61 mA. 15:0 LCRONHK[15:0] LONGDBI: Ground Key Detection Debounce Interval (RAM Address 29) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LONGDBI[15:0] R/W Reset settings = 0x00 Bit Name Function Ground Key Detection Debounce Interval. Programs the debounce interval during the ground key detection process. Programmable range is 0 to 40.96 s, 1.25 ms/LSB. 15:0 LONGDBI[15:0] LONGHITH: Ground Key Detection Threshold (RAM Address 27) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LONGHITH[15:0] R/W Reset settings = 0x00 Bit 15:0 Name LONGHITH[15:0] Function Ground Key Detection Threshold. Programs the longitudinal current threshold at which a valid ground key event is detected. Hysteresis is provided by programming the LONGLOTH RAM location to a different value that detects the removal of a ground key event. 0 to 101.09 mA programmable range, 3.097 µA/LSB, 396.4 µA effective resolution. Usable range is 0 to 16 mA. Preliminary Rev. 0.96 101 S i3232 LONGLOTH: Ground Key Removal Detection Threshold (RAM Address 28) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LONGLOTH[15:0] R/W Reset settings = 0x00 Bit 15:0 Name LONGLOTH[15:0] Function Ground Key Removal Detection Threshold. Programs the longitudinal current threshold at which it is determined that a ground key event has been terminated. 0 to 101.09 mA programmable range, 3.097 µA/ LSB, 396.4 µA effective resolution. Usable range is 0 to 16 mA. LONGLPF: Ground Key Filter Coefficient (RAM Address 30) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LONGLPF[15:3] R/W Reset settings = 0x00 Bit Name Function Ground Key Filter Coefficient. Programs the digital low-pass filter block in the ground key detection circuit. Refer to "4.5.2. Ground Key Detection" on page 34 for calculation. 15:3 LONGLPF[15:3] PLPF12: Q1/Q2 Thermal Low-pass Filter Coefficient (RAM Address 40) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PLPF12[15:3] R/W Reset settings = 0x00 Bit Name Function Q1/Q2 Thermal Low-pass Filter Coefficient. Programs the thermal low-pass filter value used to calculate the power in transistors Q1 and Q2. Also used to set thermal IPF when using Si3200. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. 15:3 PLPF12[15:3] 102 Preliminary Rev. 0.96 S i3232 PLPF34: Q3/Q4 Thermal Low-pass Filter Coefficient (RAM Address 41) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PLPF34[15:3] R/W Reset settings = 0x00 Bit Name Function Q3/Q4 Thermal Low-pass Filter Coefficient. Programs the thermal low-pass filter value used to calculate the power in transistors Q3 and Q4. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. 15:3 PLPF34[15:3] PLPF56: Q5/Q6 Thermal Low-pass Filter Coefficient (RAM Address 42) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PLPF56[15:3] R/W Reset settings = 0x00 Bit Name Function Q5/Q6 Thermal Low-pass Filter Coefficient. Programs the thermal low-pass filter value used to calculate the power in transistors Q5 and Q6. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. 15:3 PLPF56[15:3] PMAMPL: Pulse Metering Amplitude (RAM Address 68) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PMAMPL[15:0] R/W Reset settings = 0x00 Bit Name Function Pulse Metering Amplitude. Programs the voltage amplitude of the pulse metering signal. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use. 15:0 PMAMPL[15:0] Preliminary Rev. 0.96 103 S i3232 PMAMPTH: Pulse Metering AGC Amplitude Threshold (RAM Address 70) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PMAMPTH[15:0] R/W Reset settings = 0x00 Bit Name Function Pulse Metering AGC Amplitude Threshold. Programs the voltage threshold for the automatic gain control (AGC) stage in the transmit audio path. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use. 15:0 PMAMPTH[15:0] PMFREQ: Pulse Metering Frequency (RAM Address 67) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PMFREQ[15:3] R/W Reset settings = 0x00 Bit Name Function Pulse Metering Frequency. Programs the frequency of the pulse metering signal. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use. 15:3 PMFREQ[15:3] PMRAMP: Pulse Metering Ramp Rate (RAM Address 69) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PMRAMP[15:0] R/W Reset settings = 0x00 Bit Name Function Pulse Metering Ramp Rate. Programs the attack and decay rate of the pulse metering signal. Programmable range is 0 to 4.0965 at 0.125 ms/LSB (15 bit). Refer to "4.13.2. Pulse Metering Generation" on page 46 for use. 15:0 PMRAMP[15:0] 104 Preliminary Rev. 0.96 S i3232 PQ1DH: Q1 Calculated Power (RAM Address 44) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PQ1DH[15:0] R/W Reset settings = 0x00 Bit Name Function Q1 Calculated Power. Provides the calculated power in transistor Q1 when used with discrete linefeed circuitry. 0 to 16.319 W range, 498 µW/LSB. 15:0 PQ1DH[15:0] PQ2DH: Q2 Calculated Power (RAM Address 45) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PQ2DH[15:0] R/W Reset settings = 0x00 Bit Name Function Q2 Calculated Power. Provides the calculated power in transistor Q2. Used with discrete linefeed circuitry. 0 to 16.319 W range, 498 µW/LSB. 15:0 PQ2DH[15:0] PQ3DH: Q3 Calculated Power (RAM Address 46) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PQ3DH[15:0] R/W Reset settings = 0x00 Bit Name Function Q3 Calculated Power. Provides the calculated power in transistor Q3. Used with discrete linefeed circuitry. 0 to 1.03 W range, 31.4 µW/LSB. 15:0 PQ3DH[15:0] Preliminary Rev. 0.96 105 S i3232 PQ4DH: Q4 Calculated Power (RAM Address 47) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PQ4DH[15:0] R/W Reset settings = 0x00 Bit Name Function Q4 Calculated Power. Provides the calculated power in transistor Q4. Used with discrete linefeed circuitry. 0 to 1.03 W range, 31.4 µW/LSB. 15:0 PQ4DH[15:0] PQ5DH: Q5 Calculated Power (RAM Address 48) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PQ5DH[15:0] R/W Reset settings = 0x00 Bit Name Function Q5 Calculated Power. Provides the calculated power in transistor Q5. Used with discrete linefeed circuitry. 0 to 16.319 W range, 498 µW/LSB. 15:0 PQ5DH[15:0] PQ6DH: Q6 Calculated Power (RAM Address 49) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PQ6DH[15:0] R/W Reset settings = 0x00 Bit Name Function Q6 Calculated Power. Provides the calculated power in transistor Q6. Used with discrete linefeed circuitry. 0 to 16.319 W range, 498 µW/LSB. 15:0 PQ6DH[15:0] 106 Preliminary Rev. 0.96 S i3232 PSUM: Total Calculated Power (RAM Address 50) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PSUM[15:0] R/W Reset settings = 0x00 Bit Name Function Total Calculated Power. Provides the total calculated power in transistors Q1 through Q6. Using the Si3200, this RAM location reflects the total power dissipated in the Si3200 package. 0 to 34.72 W range, 1059.6 µW/LSB 15:0 PSUM[15:0] PTH12: Q1/Q2 Power Alarm Threshold (RAM Address 37) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PTH12[15:0] R/W Reset settings = 0x00 Bit Name Function Q1/Q2 Power Alarm Threshold. Programs the power threshold in transistors Q1 and Q2 at which a power alarm is triggered. Also programs the total power threshold when using Si3200. 0 to 16.319 W programmable range, 498 µW/LSB (0 to 34.72 W range, 1059.6 µW/LSB in Si3200 mode). Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. 15:0 PTH12[15:0] Preliminary Rev. 0.96 107 S i3232 PTH34: Q3/Q4 Power Alarm Threshold (RAM Address 38) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PTH34[15:0] R/W Reset settings = 0x00 Bit Name Function Q3/Q4 Power Alarm Threshold. Programs the power threshold in transistors Q3 and Q4 at which a power alarm is triggered. 0 to 1.03 W programmable range, 31.4 µW/LSB. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. 15:0 PTH34[15:0] PTH56: Q5/Q6 Power Alarm Threshold (RAM Address 39) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PTH56[15:0] R/W Reset settings = 0x00 Bit Name Function Q5/Q6 Power Alarm Threshold. Programs the power threshold in transistors Q5 and Q6 at which a power alarm is triggered. 0 to 16.319 W programmable range, 498 µW/LSB. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use. 15:0 PTH56[15:0] RB56: Q5/Q6 Base Resistance (RAM Address 43) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RB56[15:0] R/W Reset settings = 0x00 Bit Name Function Q5/Q6 Base Resistance. Programs the base resistance feeding transistors, Q5 and Q6. 15:0 RB56[15:0] 108 Preliminary Rev. 0.96 S i3232 RINGAMP: Ringing Amplitude (RAM Address 59) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RINGAMP[15:0] R/W Reset settings = 0x00 Bit Name Function Ringing Amplitude. This RAM location programs the peak ringing amplitude. Refer to "4.6. Ringing Generation" on page 37 for use. 15:0 RINGAMP[15:0] Reset settings = 0x00 RINGFRHI: Ringing Frequency High Byte (RAM Address 57) Bit Name Type Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RINGFRHI[14:0] R/W Function Ringing Frequency High Byte. This RAM location programs the upper byte of the ringing frequency coefficient. The RINGFRLO RAM location holds the lower byte. Refer to "4.6. Ringing Generation" on page 37 for use. 14:0 RINGFRHI[14:0] RINGFRLO: Ringing Frequency Low Byte (RAM Address 58) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RINGFRLO[15:3] R/W Reset settings = 0x00 Bit Name Function Ringing Frequency Low Byte. This RAM location programs the lower byte of the ringing frequency coefficient. The RINGFRHI RAM location holds the upper byte. Refer to "4.6. Ringing Generation" on page 37 for use. 15:3 RINGFRLO[15:3] Preliminary Rev. 0.96 109 S i3232 RINGOF: Ringing Waveform dc Offset (RAM Address 56) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RINGOF[14:0] R/W Reset settings = 0x00 Bit Name Function Ringing Waveform dc Offset. Programs the amount of dc offset that is added to the ringing waveform during ringing mode. 0 to 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolution. 14:0 RINGOF[14:0] RINGPHAS: Ringing Oscillator Initial Phase (RAM Address 60) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RINGPHAS[15:3] R/W Reset settings = 0x00 Bit Name Function RInging Oscillator Initial Phase. Programs the initial phase of the ringing oscillator. 0 to 1.024 s range, 31.25 µs/LSB for trapezoidal ringing. 15:3 RINGPHAS[15:3] RTACDB: AC Ring Trip Debounce Interval (RAM Address 66) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RTACDB[15:0] R/W Reset settings = 0x00 Bit Name Function AC Ring Trip Debounce Interval. Programs the debounce interval for the ac loop current detection circuit. Refer to "4.8. Ring Trip Detection" on page 41 for recommended values. 15:0 RTACDB[15:0] 110 Preliminary Rev. 0.96 S i3232 RTACTH: AC Ring Trip Detect Threshold (RAM Address 64) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RTACTH[15:0] R/W Reset settings = 0x00 Bit Name Function AC Ring Trip Detect Threshold. Programs the ac loop current threshold value above which a valid ring trip event is detected. See "4.8. Ring Trip Detection" on page 41 for recommended values. 15:0 RTACTH[15:0] RTDCDB: DC Ring Trip Debounce Interval (RAM Address 65) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RTDCDB[15:0] R/W Function DC Ring Trip Debounce Interval. Programs the debounce interval for the dc loop current detection circuit. 0 to 40.96 s programmable range, 1.25 µs/LSB. Refer to "4.8. Ring Trip Detection" on page 41 for recommended values. Reset settings = 0x00 Bit Name 15:0 RTDCDB[15:0] RTDCTH: DC Ring Trip Detect Threshold (RAM Address 62) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RTDCTH[15:0] R/W Reset settings = 0x00 Bit Name Function DC Ring Trip Detect Threshold. Programs the dc loop current threshold value above which a valid ring trip event is detected. See “4.8. Ring Trip Detection” for recommended values. 15:0 RTDCTH[15:0] Preliminary Rev. 0.96 111 S i3232 RTPER: Ring Trip Low-pass Filter Coefficient (RAM Address 63) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RTPER[15:0] R/W Reset settings = 0x00 Bit Name Function Ring Trip Low-pass Filter Coefficient. Programs the low-pass filter coefficient used in the ring trip detection circuit. See “4.8. Ring Trip Detection” for recommended values. 15:0 RTPER[15:0] SPEEDUP: DC Settling Speedup Timer (RAM Address 168) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SPEEDUP[15:0] R/W Reset settings = 0x00 Bit Name Function DC Settling Speedup Timer. Programs the dc speedup timer that allows quicker settling during loop transitions. This timer is invoked by the common-mode threshold detectors, CMHITH and CMLOTH. 1.25 ms/LSB, exception: 0x0000 = 60 ms (default). 15:0 SPEEDUP[15:0] SPEEDUPR: Ringing Speedup Timer (RAM Address 169) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SPEEDUPR[15:0] R/W Reset settings = 0x00 Bit Name Function Ringing Speedup Timer. Programs the dc speedup timer that allows quicker settling following ringing bursts. This timer is invoked by any mode change from the ringing state. 40.96 s range, 1.25 ms/LSB, exception: 0x0000 = 60 ms (default). 15:0 SPEEDUPR[15:0] 112 Preliminary Rev. 0.96 S i3232 VBAT: Scaled Battery Voltage Measurement (RAM Address 13) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VBAT[15:0] R/W Reset settings = 0x00 Bit Name Function Scaled Battery Voltage Measurement. Reflects the battery voltage measured through the monitor ADC. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution. (251 mV effective resolution for VBAT < 64.07 V). 15:0 VBAT[15:0] VCM: Common Mode Voltage (RAM Address 4) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCM[14:0] R/W Reset settings = 0x00 Bit Name Function Common Mode Voltage. Programs the common mode voltage between the TIP lead and ground in normal polarity (between RING and ground in reverse polarity). The recommended value is 3 V, but can be programmed between 0 and 63.3 V. 4.907 mV/LSB, 1.005 V effective resolution, 14:0 VCM[14:0] VLOOP: Loop Voltage Sense Value (RAM Address 7) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VLOOP[15:0] R/W Reset settings = 0x00 Bit Name Function Loop Voltage Sense Value. Holds the realtime measured loop voltage across TIP-RING. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VLOOP < 64.07 V. 15:0 VLOOP[15:0] Preliminary Rev. 0.96 113 S i3232 VOC: Open Circuit Voltage (RAM Address 0) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOC[14:0] R/W Reset settings = 0x00 Bit Name Function Open Circuit Voltage. Programs the TIP-RING voltage during on-hook conditions. The recommended value is 48 V but can be programmed between 0 and 63.3 V. 4.907 mV/LSB, 1.005 V effective resolution. 14:0 VOC[14:0] VOCDELTA: Open Circuit Off-Hook Offset Voltage (RAM Address 1) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOCDELTA[14:0] R/W Reset settings = 0x00 Bit Name Function 14:0 VOCDELTA[14:0] Open Circuit Off-Hook Offset Voltage. Programs the amount of offset that is added to the VOC RAM value when the device transitions to off-hook. The recommended value is 7 V. 0 to 63.3 V range, 4.907 mV/ LSB, 1.005 V effective resolution. VOCHTH: VOC Delta Upper Threshold (RAM Address 3) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOCHTH[15:0] R/W Reset settings = 0x00 Bit Name Function VOC Delta Upper Threshold. 15:0 VOCHTH[15:0] Programs the voltage delta above the VOC value at which the VOCDELTA offset voltage is removed. This threshold is only applicable during the off-hook to on-hook transition, and the VOCTHDL RAM location determines the threshold voltage during the onhook to off-hook transition. Default value is 2 V. 0 to 63.3 V range, 4.907 mV/LSB, 1.005 V effective resolution. 114 Preliminary Rev. 0.96 S i3232 VOCLTH: VOC Delta Lower Threshold (RAM Address 2) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOCLTH[15:0] R/W Reset settings = 0x00 Bit Name Function VOC Delta Lower Threshold. 15:0 VOCLTH[15:0] Programs the voltage delta below the VOC value at which the VOCDELTA offset voltage is added. This threshold is only applicable during the on-hook to off-hook transition, and the VOCTHDH RAM location determines the threshold voltage during the off-hook to on-hook transition. Default value is –8 V. 0 to 63.3 V range, 4.907 mV/LSB, 1.005 V effective resolution. VOCTRACK: Battery Tracking Open Circuit Voltage (RAM Address 10) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOCTRACK[15:0] R/W Reset settings = 0x00 Bit Name Function 15:0 VOCTRACK[15:0] Battery Tracking Open Circuit Voltage. Reflects the TIP-RING voltage during on-hook conditions when the battery supply has dropped below the point where the VOC setting cannot be maintained. 0 to 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolution. VOV: Overhead Voltage (RAM Address 5) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOV[14:0] R/W Reset settings = 0x00 Bit 14:0 Name VOV[14:0] Function Overhead Voltage. Programs the overhead voltage between the RING lead and the voltage on the VBAT pin in normal polarity (between TIP and ground in reverse polarity). This value increases or decreases as the battery voltage changes to maintain a constant open circuit voltage, but maintains its user-defined setting to ensure sufficient overhead for audio transmission when the battery voltage decreases. 0 to 63.3 V programmable range, 4.907 mV/ LSB, 1.005 V effective resolution. Preliminary Rev. 0.96 115 S i3232 VOVRING: Ringing Overhead Voltage (RAM Address 6) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VOVRING[14:0] R/W Reset settings = 0x00 Bit Name Function 14:0 VOVRING[14:0] Ringing Overhead Voltage. Programs the overhead voltage between the peak negative ringing level and VBATH. This value increases or decreases as the battery voltage changes in order to maintain a constant open circuit voltage but maintains its user-defined setting to ensure sufficient overhead for audio transmission when the battery voltage decreases. 0 to 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolution. VRING: Scaled RING Voltage Measurement (RAM Address 12) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VRING[15:0] R/W Reset settings = 0x00 Bit Name Function Scaled RING Voltage Measurement. Reflects the RING-to-ground voltage measured through the monitor ADC. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VRING < 64.07 V). Updated at 800 Hz rate, 2’s complement. 15:0 VRING[15:0] VTIP: Scaled TIP Voltage Measurement (RAM Address 11) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VTIP[15:0] R/W Reset settings = 0x00 Bit Name Function Scaled TIP Voltage Measurement. Reflects the TIP to ground voltage measured through the monitor ADC. 4.92 mV/LSB, 2’s complement. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VTIP < 64.07 V). Updated at 800 Hz rate, 2’s complement. 15:0 VTIP[15:0] 116 Preliminary Rev. 0.96 S i3232 9. Pin Descriptions: Si3232 SRINGDCa SRINGACa SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 BATSELa STIPDCa STIPACa THERMa IRINGNa IRINGPa VRXNa VRXPa VTXNa VTXPa ITIPNa ITIPPa GND1 VDD1 GPOa CS SDITHRU SDI SDO SCLK VDD4 GND4 INT PCLK GND3 VDD3 GPOb BATSELb FSYNC RESET 10 11 12 13 14 15 Si3232 64-Lead TQFP (epad) 43 42 41 40 39 38 37 36 35 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 THERMb SRINGDCb ITIPNb ITIPPb IRINGPb VCM STIPACb VTXPb STIPDCb SRINGACb IRINGNb VRXPb VRXNb VTXNb GND2 VDD2 Pin #(s) Symbol Input/ Description Output 1, 16 2, 15 3, 14 4, 13 5, 12 6, 11 7, 10 8 9 SVBATa, SVBATb RPOa, RPOb RPIa, RPIb RNIa, RNIb RNOa, RNOb CAPPa, CAPPb CAPMa, CAPMb QGND IREF I O I I O Battery Sensing Input—Analog current input used to sense battery voltage. Transconductance Amplifier Resistor Input Connection. Transconductance Amplifier Resistor Output Connection. Transconductance Amplifier Resistor Output Connection. Transconductance Amplifier Resistor Input Connection. Differential Capacitor—Capacitor used in low-pass filter to stabilize SLIC feedback loops. Common Mode Capacitor—Capacitor used in low-pass filter to stabilize SLIC feedback loops. Component Reference Ground—Return path for differential and common-mode capacitors. Do not connect to system ground. I IREF Current Reference—Connects to an external resistor used to provide a high-accuracy reference current. Return path for IREF resistor. Should be routed to QGND pin. TIP Sense—Analog current input used to sense dc voltage on TIP side of subscriber loop. TIP Transmit Input—Analog input used to sense ac voltage on TIP side of subscriber loop. 17, 64 18, 63 STIPDCb, STIPDCa STIPACb, STIPACa I I Preliminary Rev. 0.96 117 S i3232 Pin #(s) Symbol Input/ Description Output 19, 62 20, 61 21, 60 22, 59 23, 58 SRINGACb, SRINGACa SRINGDCb, SRINGDCa ITIPNb, ITIPNa IRINGNb, IRINGNa ITIPPb, ITIPPa I I O O O RING Transmit Input—Analog input used to sense ac voltage on RING side of subscriber loop. RING Sense—Analog current input used to sense dc voltage on RING side of subscriber loop. Negative TIP Current Control—Analog current output providing dc current return path to VBAT from TIP side of the loop. Negative RING Current Control—Analog current output providing dc current return path to VBAT from RING side of loop. Positive TIP Current Control—Analog current output driving dc current onto TIP side of subscriber loop in normal polarity. Also modulates ac current onto TIP side of loop. Supply Voltage—Power supply for internal analog and digital circuitry. Connect all VDD pins to the same supply and decouple to adjacent GND pins as close to the pins as possible. Ground—Ground connection for internal analog and digital circuitry. Connect all pins to low-impedance ground plane. 24, 37, 42, 57 25, 38, 41, 56 26, 55 VDD2, VDD3, VDD4, VDD1 GND2, GND3 GND4, GND1 IRINGPb, IRINGPa O Positive RING Current Control—Analog current output driving dc current onto RING side of subscriber loop in reverse polarity. Also modulates ac current onto RING side of loop. Temperature Sensor—Used to sense the internal temperature of the Si3200. Connect to THERM pin of Si3200 or to VDD when using discrete linefeed circuit. Common Mode Voltage Input—Connect to external common mode voltage source. Differential Analog Receive Input for SLIC Channel b. Differential Analog Transmit Output for SLIC Channel b. Reset—Active low. Hardware reset used to place all control registers in known state. An internal pulldown resistor asserts this pin low when it is not driven externally. Frame Sync—8 kHz frame synchronization signal for internal timing. May be short or long pulse format. Battery Voltage Select Pin—Used to switch between high and low external battery supplies. General Purpose Driver Output—Used to drive test relays for connecting loop test equipment or as a second battery select pin. PCM System Clock—Master clock input. Interrupt—Maskable interrupt output. Open drain output for wireORed operation. Serial Port Bit Clock Input—Controls serial data on SDO and latches data on SDI. Serial Port Data Out—Serial port control data output. Serial Port Data In—Serial port control data input. 27, 54 THERMb, THERMa I 28 29, 30 31, 32 33 VCM VRXPb, VRXNb VTXPb, VTXNb RESET I I O I 34 35, 49 36, 48 39 40 43 44 45 FSYNC BATSELb, BATSELa GPOb, GPOa PCLK INT SCLK SDO SDI I O O I O I O I 118 Preliminary Rev. 0.96 S i3232 Pin #(s) Symbol Input/ Description Output 46 SDITHRU O Serial Daisy Chain—Enables up to 16 devices to use a single CS for serial port control. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high during idle periods. Chip Select—Active low. When inactive, SCLK and SDIO are ignored. When active, serial port is operational. Differential Analog Transmit Output for SLIC Channel a. Differential Analog Receive Input for SLIC Channel a. Exposed Die Paddle Ground. Connect to a low-impedance ground plane via topside PCB pad directly under the part. See "12. Package Outline: 64-Pin eTQFP" on page 123 for PCB pad dimensions. 47 50, 51 52, 53 epad CS VTXNa, VTXPa VRXNa, VRXPa GND I O I Preliminary Rev. 0.96 119 S i3232 10. Pin Descriptions: Si3200 Si3200 16-Lead SOIC (epad) TIP NC RING VBAT VBATH VBATL GND VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL Pin #(s) Symbol Input/ Output Description TIP Output—Connect to the TIP lead of the subscriber loop. No Internal Connection—Do not connect to any electrical signal. 1 2 3 4 TIP NC RING VBAT I/O I/O RING Output—Connect to the RING lead of the subscriber loop. Operating Battery Voltage—Si3200 internal system battery supply. Connect SVBATa/b pin from Si3232 and decouple with a 0.1 µF/100 V filter capacitor. High Battery Voltage—Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V filter capacitor. 5 6 VBATH VBATL — Low Battery Voltage—Connect to lowest system battery for off-hook operation driving short loops. An internal diode prevents leakage current when operating from VBATH. Ground—Connect to a low-impedance ground plane. Supply Voltage—Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 µF/10 V capacitor. 7 8 9 10 11 12 13 14 GND VDD BATSEL NC NC IRINGN IRINGP THERM I I O I Battery Voltage Select—Connect to the BATSEL pin of the Si3232 through an external resistor to enable automatic battery switching. No Internal Connection—Do not connect to any electrical signal. No Internal Connection—Do not connect to any electrical signal. Negative RING Current Control—Connect to the IRINGN lead of the Si3232. Positive RING Current Drive—Connect to the IRINGP lead of the Si3232. Thermal Sensor—Connection to internal temperature-sensing circuit. Connect to THERM pin of Si3232. 120 Preliminary Rev. 0.96 S i3232 Pin #(s) Symbol Input/ Output Description Negative TIP Current Control—Connect to the ITIPN lead of the Si3232. Positive TIP Current Control—Connect to the ITIPP lead of the Si3232. Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be soldered to a PCB pad that is connected to low-impedance inner and/or backside ground planes using multiple vias. See "13. Package Outline: 16-Pin ESOIC" on page 124 for PCB pad dimensions. 15 16 epad ITIPN ITIPP GND I I Preliminary Rev. 0.96 121 S i3232 11. Ordering Guide Part Number Package Lead Free Temp Range Si3232-X-FQ Si3232-X-GQ Si3200-X-FS Si3200-X-GS Si3200-KS Si3200-BS TQFP-64 TQFP-64 SOIC-16 SOIC-16 SOIC-16 SOIC-16 Yes Yes Yes Yes No No 0 to 70 °C –40 to 85 °C 0 to 70 °C –40 to 85 °C 0 to 70 °C –40 to 85 °C Notes: 1. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 2. “X” denotes product revision. 122 Preliminary Rev. 0.96 S i3232 12. Package Outline: 64-Pin eTQFP Figure 39 illustrates the package details for the Si3232. Table 33 lists the values for the dimensions shown in the illustration. Figure 39. 64-Pin Thin Quad Flat Package (TQFP) Table 33. 64-Pin Package Diagram Dimensions Symbol Min Millimeters Nom Max Symbol Min Millimeters Nom Max A A1 A2 b c D D1 D2 e — 0.05 0.95 0.17 0.09 — — 1.00 0.22 — 12.00 BSC. 10.00 BSC. 4.50 0.50 BSC. 1.20 0.15 1.05 0.27 0.20 E E1 E2 L aaa bbb ccc ddd Θ 4.35 0.45 — — — — 0° 12.00 BSC. 10.00 BSC. 4.50 0.60 — — — — 3.5° 4.65 0.75 0.20 0.20 0.08 0.08 7° 4.35 4.65 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. This package outline conforms to JEDEC MS-026, variant ACD-HD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body Components. Preliminary Rev. 0.96 123 S i3232 13. Package Outline: 16-Pin ESOIC Figure 40 illustrates the package details for the Si3201. Table 34 lists the values for the dimensions shown in the illustration. 16 9 h E H –B– .25 M B M θ x45° 1 B 8 Bottom Side Exposed Pad 2.3 x 3.6 mm L Detail F .25 M C A M B S –A– D C –C– A See Detail F e A1 Seating Plane γ Weight: Approximate device weight is 0.15 grams. Figure 40. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 34. Package Diagram Dimensions Millimeters Symbol Min Max A A1 B C D E e H h L γ θ 1.35 0 .33 .19 9.80 3.80 5.80 .25 .40 — 0º 1.75 0.15 .51 .25 10.00 4.00 6.20 .50 1.27 0.10 8º 1.27 BSC 124 Preliminary Rev. 0.96 S i3232 SUPPORT DOCUMENTATION AN55: Dual ProSLIC User Guide AN63: Si322x Coefficient Generator User's Guide AN64: Dual ProSLIC LINC User Guide AN68: 8-Bit Microcontroller Board Hardware Reference Guide AN71: Si3220/Si3225 GR-909 testing AN74: SiLINKPS-EVB User's Guide AN86: Ringing/Ringtrip Operation and Architecture on the Si3220/Si3225 Si3232PPT0-EVB Data Sheet Note: Refer to www.silabs.com for a current list of support documents for this chipset. Preliminary Rev. 0.96 125 S i3232 DOCUMENT CHANGE LIST Revision 0.95 to Revision 0.96 The following changes are specific to Rev G of the Si3232 silicon: "4.5.2. Ground Key Detection" on page 34 Added descriptive text and ILONG equation. Register , “ID: Chip Identification (Register Address 0),” on page 67 Added register value for Silicon Rev. G. The following changes are corrections to Rev 0.96. Table 34 on page 124. Corrected 16-pin ESOIC dimension A1. "4.5.1. Loop Closure Detection" on page 32 Added descriptive text and ILOOP equation. "4.16. SPI Control Interface" on page 50 Added pulldown resistor description Added description for current limiting resistors on VBATH and VDD connected to the Si3200 on page 19. Revised "2. Typical Application Schematic" on page 17. Added pulldown resistor to SDO pin. Added R20–R23, C23, C24, C32, and C33 to VBATH and VDD of Si3200. Updated "11. Ordering Guide" on page 122. Updated 64-pin eTQFP drawing on page 123. 126 Preliminary Rev. 0.96 S i3232 NOTES: Preliminary Rev. 0.96 127 S i3232 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 128 Preliminary Rev. 0.96

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