SI4312

Si4312 315/433.92 MH Z O O K R ECEIVER Features       Single chip receiver with only six external components Selectable 315/433.92 MHz carrier frequency Supports OOK modulation High sensitivity (–110 dBm @ 1.0 kbps) Frequency scanning Excellent interference rejection      Data rates up to 10 kbps NRZ (5 kbps Manchester) Direct battery operation with onchip low drop out (LDO) voltage regulator 16 MHz crystal oscillator support 3x3x0.85 mm 20L QFN package (RoHS compliant) –40 to +85 °C temperature range Applications   Ordering Information: See page 15. Satellite set-top box receivers Remote controls, IR replacement/extension  Garage and gate door openers  Home automation and security   Remote keyless entry After market alarms  Telemetry  Wireless point of sale  Toys Pin Assignments Si4312 (Top View) TH0 17 10 XTL2 TH1 16 15 BT0 14 BT1 13 DOUT 12 GND 7 GND 8 VDD 9 XTL1 11 VDD NC NC 19 NC 18 Description The Si4312 is a fully-integrated OOK CMOS RF receiver that operates in the unlicensed 315 and 433.92 MHz ultra high frequency (UHF) bands. It is designed for high-volume, cost-sensitive RF receiver applications, such as set-top box RF receivers, remote controls, garage door openers, home automation, security, remote keyless entry systems, wireless POS, and telemetry. The Si4312 offers industry-leading RF performance, high integration, flexibility, low BOM, small board area, and ease of design. No production alignment is necessary as all RF functions are integrated into the device. VDD 1 RFGND 2 RX_IN 3 RST 4 RATIO 5 6 315/434 20 GND PAD Functional Block Diagram Patents pending Antenna RX_IN LNA AGC 2.7 – 3.6 V VDD GND LDO FREQ SCAN XTAL OSC PGA ADC ADC DSP MCU BASEBAND PROCESSOR SQUELCH Si4312 DOUT RATIO 315/434 TH[1:0] BT[1:0] RST 16 MHz Rev. 0.5 3/10 Copyright © 2010 by Silicon Laboratories Si4312 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i4312 2 Rev. 0.5 S i4312 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Typical Application Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2. Receiver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3. Carrier Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4. Bit Time BT[1:0] Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5. RATIO Selection Used for the Slicer Threshold Calculation Window . . . . . . . . . . . . 10 3.6. Frequency Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.7. Threshold Hold Time Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8. Low Noise Amplifier Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.10. Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Pin Descriptions: Si4312-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1. Si4312 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. Package Outline: Si4312-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. PCB Land Pattern: Si4312-B10-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rev. 0.5 3 S i4312 1. Electrical Specifications Table 1. Recommended Operating Conditions* Parameter Supply Voltage Supply Voltage Powerup Rise Time Ambient Temperature Symbol VDD VDD-RISE TA Test Condition Min 2.7 10 –40 Typ 3.3 — 25 Max 3.6 — 85 Unit V μs °C *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Supply Voltage Input Current 3 Symbol VDD IIN VIN TOP TSTG Value –0.5 to 3.9 10 –0.3 to (VDD + 0.3) –45 to 95 –55 to 150 0.4 Unit V mA V C C VPK Input Voltage3 Operating Temperature Storage Temperature RF Input Level 4 Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4312 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For input pins 315/434, RATIO, BT[1:0], TH[1:0]. 4. At RF input pin RX_IN. 4 Rev. 0.5 S i4312 Table 3. DC Characteristics (TA = 25 °C, VDD = 3.3 V, Rs = 50 Ω, FRF = 433.92 MHz unless otherwise noted) Parameter Supply Current Reset Supply Current High Level Input Voltage 1 Symbol IVDD IRST VIH VIL IIH IIL VOH VOL Test Condition Min — Typ 20 2 — — — — — — Max TBD TBD VDD + 0.3 0.3 x VDD 10 10 — 0.2 x VDD Unit mA µA V V µA µA V V Reset asserted — 0.7 x VDD –0.3 Low Level Input Voltage1 High Level Input Current 1 VIN = VDD = 3.6 V VIN = 0 V, VDD = 3.6 V IOUT = 500 µA IOUT = –500 µA –10 –10 0.8 x VDD — Low Level Input Current1 High Level Output Voltage2 Low Level Output Voltage2 Notes: 1. For input pins OOK, 315/434, RATIO, BT[1:0], TH[1:0]. 2. For output pin DOUT. Table 4. Reset Timing Characteristics (VDD = 3.3 V, TA = 25 °C) Parameter RST Pulse Width Symbol tSRST Min 100 Typ — Max — Unit µs tSRST RST 70% 30% Figure 1. Reset Timing Rev. 0.5 5 S i4312 Table 5. Si4312 Receiver Characteristics (TA = 25 °C, VDD = 3.3 V, Rs = 50 Ω, FRF = 433.92 MHz unless otherwise noted) Parameter Symbol Test Condition 1.0 kbps, 315 MHz (Note2) (Note2) (Note2) Min — — — TBD — Typ –110 –103 –106 –101 — Max — — — — 10 Unit dBm dBm dBm dBm kbps Sensitivity @ BER = 10–3 (Note 1) 10 kbps, 315 MHz 1.0 kbps, 433.92 MHz NRZ 10 kbps, 433.92 MHz Data Rate 3 Adjacent Channel Rejection ±200 kHz (Note 1) Desired signal is 3 dB above sensitivity (BER = 10–3), unmodulated interferer is at ±200 kHz, rejection measured as TBD difference between desired signal and interferer level in dB when BER = 10–3 Desired signal is 3 dB above sensitivity (BER = 10–3), unmodulated interferer is at ±400 kHz, rejection measured as difference between desired signal and interferer level in dB when BER = 10–3 ±2 MHz, 1.0 kbps, desired signal is 3 dB above sensitivity, CW interferer level is increased until BER = 10–3 ±10 MHz, 1.0 kbps, desired signal is 3 dB above sensitivity, CW interferer level is increased until BER = 10–3 | f2 – f1 | = 5 MHz, high gain mode, desired signal is 3 dB above sensitivity, CW interference levels are increased until BER = 10–3 4 35 — dB Alternate Channel Rejection ±400 kHz1,2 Image Rejection, IF = 128 kHz1,2 — 55 — dB — — 23 65 — — dB dB Blocking1,2 — — — — — 70 8 –10 7 160 500 — — — — — — dB dBm dBm pF kHz ms Maximum RF Input Power 1,2 Input IP33 LNA Input Capacitance3 Receiver Channel Bandwidth RX Boot Time3 From reset — Notes: 1. 1.0 kbps, Manchester encoded, RATIO = 0, TH[1:0] = 00, xtal = ±20 ppm. 2. Guaranteed by characterization. 3. Guaranteed by design. 4. The frequency scanning (see section “3.6. Frequency Scanning”) extends this to 420 kHz. Table 6. Crystal Characteristics (VDD = 3.3 V, TA = 25 °C) Parameter Crystal Oscillator Frequency Crystal ESR XTL1, XTL2 Input Capacitance Symbol Test Condition Min — — — Typ 16 — 11 Max — 100 — Unit MHz  pF 6 Rev. 0.5 S i4312 2. Typical Application Schematic TH0 TH1 BT0 BT1 BT0 15 BT1 14 DOUT 13 GND 12 VDD 11 L1 C3 C2 1 uF 1 VDD 2 RFGND 3 U1 RX_IN Si4312-GM 4 RST 5 RATIO GND PAD NC NC NC TH0 TH1 RX ANTENNA VDD 20 19 18 17 16 DOUT VDD C1 22 nF VBATTERY 2.7 to 3.6 V R1 20 k RATIO X1 (16 MHz) Figure 2. Si4312 OOK 433.92 MHz Application Schematic 2.1. Typical Application Bill of Materials Table 7. Si4312 Typical Application Bill of Materials Component(s) C1 C2 C3 L1 R1 X1 U1 Value/Description Supply bypass capacitor, 22 nF, 20%, Z5U/X7R Time constant capacitor, 1 µF Antenna matching capacitor, 15 pF Antenna matching inductor, 33 nH for 433.92 MHz and 62 nH for 315 MHz Time constant resistor, 20 k 16 MHz crystal Si4312 315/433.92 MHz OOK receiver Supplier(s) Murata Murata Murata Murata Murata Hosonic Silicon Laboratories 6 7 8 9 10 Rev. 0.5 434 GND VDD XTL1 XTL2 7 S i4312 3. Functional Description 3.1. Overview Antenna RX_IN LNA AGC 2.7 – 3.6 V VDD GND LDO FREQ SCAN XTAL OSC PGA ADC ADC Si4312 DOUT DSP MCU BASEBAND PROCESSOR SQUELCH RATIO 315/434 TH[1:0] BT[1:0] RST 16 MHz Figure 3. Functional Block Diagram The Si4312 is a fully-integrated OOK CMOS RF receiver that operates in the unlicensed 315 and 433.92 MHz ultra high frequency (UHF) bands. It is designed for high-volume, cost-sensitive RF receiver applications. The chip operates at a carrier frequency of 315 or 433.92 MHz and supports OOK digital modulation with data rates of up to 10 kbps NRZ or 5 kbps Manchester coded. The Si4312 has selectable data filters to optimize the sensitivity of the receiver for a given data rate. The Si4312 employs a frequency scanning algorithm to improve the sensitivity of the receiver with a small IF bandwidth while still maintaining the ability to accommodate large transmit frequency offsets. The integrated on-chip squelch circuit prevents false output data when the RF input signal is absent or below sensitivity. The device leverages Silicon Labs’ patented and proven digital low-IF architecture and offers superior sensitivity and interference rejection. The Si4312 can achieve superior sensitivity in the presence of large interference due to its high dynamic range ADCs and digital filters. The digital low-IF architecture also enables superior blocking ability and low intermodulation distortion for robust reception in the presence of wide-band interference. Digital integration reduces the number of required external components compared to traditional offerings, resulting in a solution that only requires a 16 MHz crystal and passive components allowing a small and compact printed circuit board (PCB) implementation area. The high integration of the Si4312 improves the system manufacturing reliability, improves quality, eases design-in, and minimizes costs. 3.2. Receiver Description The RF input signal is amplified by a low-noise amplifier (LNA) and down-converts to a low intermediate frequency with a quadrature image-reject mixer. The mixer output is amplified by a programmable gain amplifier (PGA), filtered, and digitized with a highresolution analog-to-digital converter (ADC). All RF functions are integrated into the device eliminating any production alignment issues associated with external components, such as SAW and ceramic IF filters. Silicon Labs’ advanced digital low-IF architecture achieves superior performance by using the DSP to perform channel filtering, demodulation, automatic gain control (AGC), automatic frequency control (AFC), and other baseband processing. DSP implementation of the channel filters provides better repeatability and control of the bandwidth and frequency response of the filter compared to analog implementations. No off-chip ceramic filters are needed with the Si4312 as all IF channel filtering is performed in the digital domain. 8 Rev. 0.5 S i4312 3.3. Carrier Frequency Selection The Si4312 can be tuned to either 315 or 433.92 MHz by driving Pin 6 (315/434) to VDD or GND. The 315 MHz operation is chosen by driving Pin 6 (315/434) to VDD, and 433.92 MHz operation is chosen by driving Pin 6 (315/434) to GND. Table 8. Carrier Frequency Selection Pin 6 (315/434) 0 1 Frequency [MHz] 433.92 315 3.4. Bit Time BT[1:0] Selection The Si4312 can operate with data rates of up to 10 kbps non-return to zero (NRZ) data or 5 kbps Manchester encoded data. However, OOK modulation uses other encoding schemes such as pulse width modulation (PWM) and pulse position modulation (PPM) where a bit can be encoded into a pulse with a certain duty cycle or pulse width as shown in Figure 4. Digital Data NRZ Encoding Manchester Encoding PPM Encoding “1” “0” “1” “1” 100 us 1000 us Figure 4. Example Data Waveforms In order to set the data filter bandwidth correctly, the shortest pulse width of the transmitted encoded data should be chosen as the bit time. In the PPM example shown in Figure 4, the shortest pulse width is 100 µs; so, the bit time is chosen as BT = 100 µs even though the actual data rate is 1 kbps (1000 µs). After finding BT, Table 9 can be used to find the bit settings for pins 14 and 15, BT[1:0]. In this PPM example, BT[1:0] is set as logic BT1 = 1 and BT0 = 1 or BT[1:0] = (1,1) since BT = 100 µs. Table 9. How to Choose BT[1:0] Based on the Bit Time Bit Time [µs] BT ≥ 1000 1000 < BT < 500 500 < BT < 200 200 < BT < 100 Filter Bandwidth [kHz] 1.5 3.0 7.5 15 BT1 (pin 14) 0 0 1 1 BT0 (pin 15) 0 1 0 1 Rev. 0.5 9 S i4312 3.5. RATIO Selection Used for the Slicer Threshold Calculation Window In OOK modulation, many different encoding schemes exist, which can result in variable ON and OFF times as seen in the example data waveforms shown in Figure 4. In order to determine the proper slicer threshold used for demodulating the OOK signal into digital data, the Si4312 must sample an "ON" and "OFF" event in a time window called the threshold calculation window. The samples during the "ON" time will determine the ON voltage, and the samples during the "OFF" time will determine the OFF voltage. These voltages are used to determine the slicer threshold voltage as follows: SlicerThreshold =  Max_ON_Voltage + Min_OFF_Voltage  ---------------------------------------------------------------------------------------------------------2 Defining the BT variable from the last section as the ON time and RATIO = OFF ----------ON then, the threshold calculation window is calculated as follows: Threshold Calculation Window = 1.25   ON + OFF  = 1.25   BT + BT  RATIO  = 1.25  BT  RATIO + 1  The threshold calculation window is 1.25 times longer than the ON plus OFF times for margin to allow sampling of both ON and OFF times. Figure 5 shows a graph of the threshold calculation window. Digital Data PPM Encoding “1” “0” “1” 100 us “1” 1000 us ON voltage OOK Waveform OFF voltage Threshold Calculation Window Figure 5. Example of the Threshold Calculation Ratio is a unit-less multiplier that relates the OFF time to the ON time. The Si4312 defines two constants for RATIO as shown in Table 10 based on the logic level of pin 5. Table 10. RATIO Constants Based on Logic Level of Pin 5 Pin 5 0 1 RATIO 5 10 10 Rev. 0.5 S i4312 Since the OFF time = RATIO x BT and the values for RATIO are either 5 or 10, RATIO should be chosen such that either the value of 5 or 10 x the BT[1:0] setting is just larger than the OFF time. For the PPM example shown in Figure 4, BT[1:0] = (1,1) since BT = 100 µs. The actual OFF time is 900 µs; so, we would set pin 5 = 1 to get a RATIO of 10 such that the calculated OFF time is BT[1:0] x RATIO = 100 µs x 10 = 1000 µs, which is greater than the actual OFF time of 900 µs. An alternative approach to choosing the RATIO bit (pin 5) is to choose the RATIO parameter such that the threshold calculation window is greater than the actual ON plus OFF times using Table 11 and the values chosen for BT[1:0]. Table 11. Threshold Calculation Window Times Based on RATIO and BT[1:0] Settings RATIO 0 0 0 0 1 1 1 1 BT1 0 0 1 1 0 0 1 1 BT0 0 1 0 1 0 1 0 1 Threshold Calculation Window (ms) 7.500 3.750 1.500 0.750 13.750 6.875 2.750 1.375 3.6. Frequency Scanning The channel bandwidth directly affects the sensitivity of any wireless receiver. Typical analog OOK receivers use an external ceramic filter with a large bandwidth to accommodate the data rate, crystal tolerances, and transmit carrier frequency offsets, which leads to unnecessary amounts of noise and lower sensitivity levels. The Si4312 uses a narrow channel bandwidth of 160 kHz and frequency scanning to obtain excellent sensitivity levels (–110 dBm at data rate of 1 kbps at 315 MHz) while still accommodating up to ±210 kHz of scan bandwidth from its operating frequency. The frequency scan algorithm works by breaking the scan bandwidth (420 kHz) into three frequency bins approximately 140 kHz wide and checking for transmit signal energy in each bin. Because the received signal power can vary by large orders of magnitude depending on how close the transmitter is to the receiver, the frequency algorithm may have to re-scan the frequency bins if the received power level saturates the receiver. Three gain settings are used in the frequency scan algorithm denoted as high-, medium-, and low-gain. The chip begins scanning the frequency in the highest receiver gain setting to find signals that have a receive signal strength indicator (RSSI) level from sensitivity to about –70 dBm. If energy is detected in only one of these frequency bands, it is double-checked again and deemed as the correct operating frequency band. Therefore, the frequency scan algorithm takes at least two searches to find the correct frequency band. The scan time per frequency bin search is equal to the threshold calculation window time as chosen by the RATIO and BT[1:0] settings given in Table 11. Therefore, the best case frequency scan time is equal to two times the threshold calculation window time. In case the input signal is large while the gain is also large, the receiver could be overloaded; therefore, the frequency scan algorithm follows a series of frequency and gain level settings based on measured RSSI as shown in Figure 6. In the worst case, there are a total of nine frequency bin searches (three frequency bins times three gain settings) plus one additional frequency re-scan because we don't know when the signal starts or for double checking. Thus, the worst-case scan time is equal to 10 times the threshold calculation window time. Figure 6 shows the frequency scan algorithm broken into three frequency bins of 140 kHz and three gain settings. Rev. 0.5 11 S i4312 Low Gain: Input RSSI in the range of -45dBm ~ -15dBm Medium Gain: Input RSSI in the range of -75dBm to -40dBm High Gain: Input RSSI in the range of Sensitivity to -70dBm Fc Freq Bin 2 Scan Directions Freq Bin 1 Freq Bin 3 Figure 6. Frequency Scan Algorithm Depicting 3 Frequency Bins of 140 kHz and 3 Gain Settings Frequency scanning is always enabled to find the transmitted signal. The scanning process stops after the correct frequency band is found for the transmitted signal and is held throughout the duration of the packet plus a time of no RF signal activity. This dead time is called “threshold hold time” and is described in section 3.7. Theshold hold time allows a frequency found in the first packet of transmission to be held for any subsequent retransmissions of packets if the retransmissions occur before the threshold hold time. This held frequency ensures all bits of the second and subsequent packets are recovered completely. Frequency scanning resumes after the time of no RF signal activity exceeds the threshold hold time. 3.7. Threshold Hold Time Selection The threshold hold time is defined as the length of time the Si4312 keeps its slicer threshold voltage level when no signals are present. If a signal does not appear after this time interval, the Si4312 will re-start the frequency scan process and look for the signal in one of its three frequency bins. The threshold hold times are determined by the bit settings chosen on pins 16 and 17 as shown in Table 12. Table 12. Threshold Time Settings Based on TH[1:0] Logic Levels TH1 (Pin 16) 0 0 1 1 TH0 (Pin 17) 0 1 0 1 Threshold Hold Time (ms) 70 100 300 500 3.8. Low Noise Amplifier Input Circuit Figure 2 shows the typical application circuit with 50  matching. Components C3 and L1 are used to transform the input impedance of the LNA. C3 is equal to 15 pF and L1 is equal to 33 nH at 433.92 MHz and 62 nH at 315 MHz for 50  matching. 12 Rev. 0.5 S i4312 3.9. Crystal Oscillator An on-board crystal oscillator is used to generate a 16 MHz reference clock for the Si4312. This reference frequency is required for proper operation of the Si4312 and is used for calibration of the on-chip VCO and other timing references. No external load capacitors are required to set the 16 MHz reference frequency if the recommended crystal load capacitor is around 14 pF, assuming the effective board capacitance between pins XTL1 and XTL2 is 3 pF and the chip input capacitance on pins XTL1 or XTL2 is 11 pF. Refer to Table 6, “Crystal Characteristics,” on page 6 for board capacitance and frequency tolerance information. The frequency tolerance of the crystal should be chosen such that the received signal is within the IF bandwidth of the Si4312 receiver. Additionally, the Si4312 can be driven by an external 16 MHz reference clock. The clock signal can be applied to either the XTL1 or XTL2 inputs. When the 16 MHz reference clock is applied to one of the inputs, the other crystal input pin must be floating. 3.10. Reset Pin Driving the RST pin (pin 4) low will disable the Si4312 and place the device into reset mode. All active blocks in the device are powered off in this mode, bringing the current consumption to less than 10 uA. The Si4312 is enabled by driving the RST pin (pin 4) to VDD. Refer to Table 4 "Reset Timing Characteristics" for the reset timing requirements. The chip requires about 500 ms to go from reset to active mode. The Si4312 can output invalid data during the 500 ms turn-on time. Rev. 0.5 13 S i4312 4. Pin Descriptions: Si4312-B10-GM TH0 17 10 XTL2 VDD 1 20 19 18 RFGND 2 RX_IN 3 RST 4 RATIO 5 6 315/434 7 GND 8 VDD 9 XTL1 GND PAD Pin Number(s) 1, 8, 11 2 3 4 5 6 7, 12, GND PAD 9 10 13 14, 15 16, 17 18,19,20 Name VDD RFGND RX_IN RST RATIO 315/434 GND XTL1 XTL2 DOUT BT[1:0] TH[1:0] NC Description Supply voltage, may connect to external battery. RF ground. Connect to ground plane on PCB. RF receiver input. Device reset, active low input. Constant used to determine threshold calculation window, input pin. Selectable logic input for 315 or 433.92 MHz operation. Ground. Connect to ground plane on PCB. Crystal input. Crystal input. Data output. Bit time selection input pins. Threshold hold time selection input pins. No connect. Leave floating. 14 Rev. 0.5 TH1 16 15 BT0 14 BT1 13 DOUT 12 GND 11 VDD NC NC NC S i4312 5. Ordering Guide Part Number* Si4312-B10-GM Description 315/433.92 MHz OOK Receiver Package Type QFN Pb-free Operating Temperature –40 to 85 °C *Note: Add an “(R)” at the end of the device part number to denote tape and reel option. Rev. 0.5 15 S i4312 6. Package Markings (Top Marks) 6.1. Si4312 Top Mark 1210 RTTT YWW Figure 7. Si4312 Top Mark Example 6.2. Top Mark Explanation Mark Method: Line 1 Marking: Line 2 Marking: Line 3 Marking: YAG Laser Part Number Firmware Revision Die Revision TTT = Internal Code 12 = Si4312 10 = Firmware Revision 1.0 B = Revision B Die Internal tracking code Circle = 0.5 mm Diameter Pin 1 Identifier (Bottom-Left Justified) YWW = Date Code Assigned by the Assembly House. Corresponds to the last digit of the current year (Y) and the workweek (WW) of the mold date. 16 Rev. 0.5 S i4312 7. Package Outline: Si4312-B10-GM Figure 8 illustrates the package details for the Si4312-B10-GM. Table 13 lists the values for the dimensions shown in the illustration. Figure 8. 20-Pin Quad Flat No-Lead (QFN) Table 13. Package Dimensions Symbol Min A A1 b c D D2 e E E2 1.65 1.65 0.80 0.00 0.20 0.27 Millimeters Nom 0.85 0.02 0.25 0.32 3.00 BSC 1.70 0.50 BSC 3.00 BSC 1.70 1.75 1.75 Max 0.90 0.05 0.30 0.37 f L L1 aaa bbb ccc ddd eee 0.30 0.00 — — — — — Symbol Min Millimeters Nom 2.53 BSC 0.35 — — — — — — 0.40 0.10 0.05 0.05 0.08 0.10 0.10 Max Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. Rev. 0.5 17 S i4312 8. PCB Land Pattern: Si4312-B10-GM Figure 9 illustrates the PCB land pattern details for the Si4312-B10-GM. Table 14 lists the values for the dimensions shown in the illustration. Figure 9. PCB Land Pattern 18 Rev. 0.5 S i4312 Table 14. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 e E E2 f GD 1.60 Max GE W X Y ZE ZD — — — 1.80 Symbol Millimeters Min 2.10 — — Max — 0.34 0.28 0.61 REF 3.31 3.31 2.71 REF 0.50 BSC 2.71 REF 1.60 2.10 1.80 2.53 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification. 3. This land pattern design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a fabrication allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component standoff. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Rev. 0.5 19 S i4312 NOTES: 20 Rev. 0.5 S i4312 DOCUMENT CHANGE LIST Revision 0.1 to 0.2  Updated sensitivity and supply current. Revision 0.2 to 0.5  Removed IVDD current spec when input = –30 dBm from Table 3 "DC Characteristics"  Updated sensitivity specs and test conditions in Table 5 "Si4312 Receiver Characteristics"  Updated frequency scanning description in section “3.6. Frequency Scanning”  Added reference clock drive capability to section “3.9. Crystal Oscillator” Rev. 0.5 21 S i4312 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: wireless@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Rev. 0.5