SI4432-V2-FM

Si4432 Si4432 ISM T RANSCEIVER Features           Frequency Range = 240–930 MHz Sensitivity = –118 dBm +20 dBm Max Output Power Configurable +11 to +20 dBm Low Power Consumption 18.5 mA receive 27 mA @ +11 dBm transmit Data Rate = 1 to 128 kbps Power Supply = 1.8 to 3.6 V Ultra low power shutdown mode Digital RSSI Wake-on-radio Auto-frequency calibration (AFC)               Antenna diversity and TR switch control Configurable packet structure Preamble detector TX and RX 64 byte FIFOs Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning 20-Pin QFN package FSK, GFSK, and OOK modulation Low BOM Power-on-reset (POR) Ordering Information: See page 156. Pin Assignments Silicon Laboratories’ Si4432 highly integrated, single chip wireless ISM transceiver is part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. The Si4432 offers advanced radio features including continuous frequency coverage from 240–930 MHz and adjustable output power of up to +20 dBm. The Si4432’s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (–118 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, poweron-reset (POR), and GPIOs further reduce overall system cost and size. The Si4432’s digital receive architecture features a high-performance ADC and DSP based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. This digital architecture simplifies system design while allowing for the use of lower-end MCUs. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with FCC and ETSI regulations. Copyright © 2009 by Silicon Laboratories nIRQ nSEL 15 SCLK TX 2 14 SDI RXp 3 13 SDO RXn 4 12 VDD_DIG VR_IF 5 11 NC 7 8 9 10 VDR 6 GPIO_2 1 Metal Paddle Description Preliminary Rev. 0.4 6/09 20 19 18 17 16 VDD_RF GPIO_1 Remote meter reading Remote keyless entry Home automation Industrial control Sensor networks Health monitors Tag readers XOUT SDN        NC Remote control Home security & alarm Telemetry Personal data logging Toy control Tire Pressure monitoring Wireless PC peripherals GPIO_0        XIN Si4432 Applications Patents pending Si4432 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si4432 nSEL Xin VDD_DIG RC 32K OSC RF LDO Xout VDD_RF SDN Functional Block Diagram PLL LDO VCO LDO VCO LPF CP 30M XTAL OSC PFD LBD TX PA Temp Sensor PA_RAMP PWR_CTRL N 8Bit ADC Delta Sigma Modulator ANTDIV TXRXSW PA_RAMP PWR_CTRL TXMOD Digital Logic SCLK SDI SDO VDD_DIG SPI, & Controller Digital Modem AGC Control Low Power Digital LDO Digital LDO RFp ADC RFn POR LNA BIAS GPIO_0 GPIO_1 GPIO_2 IF LDO PGA VR_IF 2 Preliminary Rev. 0.4 VR_DIG Mixers Si4432 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.4. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.5. PN9 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.6. Synchronous vs. Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.7. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.8. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.9. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 6.4. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 6.5. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.6. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.7. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.8. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.9. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Preliminary Rev. 0.4 3 Si4432 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 8.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.9. Antenna-Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.10. TX/RX Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.11. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.3. Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13. Pin Descriptions: Si4432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 16. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 4 Preliminary Rev. 0.4 Si4432 L I S T OF F IGURES Figure 1. +20 dBm Application with Antenna Diversity and FHSS............................................ 17 Figure 2. SPI Timing.................................................................................................................. 19 Figure 3. SPI Timing—READ Mode ..........................................................................................20 Figure 4. SPI Timing—Burst Write Mode .................................................................................. 20 Figure 5. SPI Timing—Burst Read Mode .................................................................................. 20 Figure 6. State Machine Diagram.............................................................................................. 21 Figure 7. TX Timing................................................................................................................... 25 Figure 8. RX Timing .................................................................................................................. 26 Figure 9. Frequency Deviation .................................................................................................. 30 Figure 10. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................31 Figure 11. FSK vs GFSK Spectrums......................................................................................... 34 Figure 12. Direct Synchronous Mode Example......................................................................... 36 Figure 13. Direct Asynchronous Mode Example ....................................................................... 36 Figure 14. FIFO Mode Example ................................................................................................ 37 Figure 15. PLL Synthesizer Block Diagram............................................................................... 39 Figure 16. FIFO Thresholds ...................................................................................................... 42 Figure 17. Packet Structure....................................................................................................... 43 Figure 18. Multiple Packets in TX Packet Handler .................................................................... 44 Figure 19. Required RX Packet Structure with Packet Handler Disabled ................................. 44 Figure 20. Multiple Packets in RX Packet Handler.................................................................... 44 Figure 21. Multiple Packets in RX with CRC or Header Error ................................................... 45 Figure 22. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 47 Figure 23. POR Glitch Parameters............................................................................................ 55 Figure 24. General Purpose ADC Architecture ......................................................................... 57 Figure 25. ADC Differential Input Example—Bridge Sensor ..................................................... 58 Figure 26. ADC Differential Input Offset for Sensor Offset Coarse Compensation................... 59 Figure 27. Temperature Ranges using ADC8 ........................................................................... 61 Figure 28. WUT Interrupt and WUT Operation.......................................................................... 64 Figure 29. Low Duty Cycle Mode .............................................................................................. 65 Figure 30. GPIO Usage Examples ............................................................................................ 67 Figure 31. RSSI Value vs. Input Power..................................................................................... 69 Figure 32. Split RF I/Os with Separated TX and RX Connectors—Schematic ......................... 70 Figure 33. Common TX/RX Connector with RF Switch—Schematic ........................................ 72 Figure 34. Antenna Diversity Reference Design—Schematic................................................... 74 Figure 35. Sensitivity vs. Data Rate ..........................................................................................76 Figure 36. Receiver Selectivity.................................................................................................. 77 Figure 37. TX Output Power vs. VDD Voltage .......................................................................... 78 Figure 38. TX Output Power vs Temperature ........................................................................... 78 Figure 39. TX Modulation (40 kbps, 20 kHz Deviation)............................................................. 79 Figure 40. TX Unmodulated Spectrum (917 MHz) .................................................................... 79 Figure 41. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) ................. 80 Figure 42. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ........................... 80 Figure 43. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 81 Preliminary Rev. 0.4 5 Si4432 Figure 44. RX LNA Matching..................................................................................................... 83 Figure 45. TX Matching and Filtering for Different Bands ......................................................... 84 Figure 46. QFN-20 Package ................................................................................................... 157 Figure 47. PCB Land Pattern .................................................................................................. 158 6 Preliminary Rev. 0.4 Si4432 L I S T OF TABLES Table 1. DC Characteristics1 ................................................................................................................................8 Table 2. Synthesizer AC Electrical Characteristics1 ....................................................................................9 Table 3. Receiver AC Electrical Characteristics1 .....................................................................10 Table 4. Transmitter AC Electrical Characteristics1 ................................................................................... 11 Table 5. Auxiliary Block Specifications1 ..........................................................................................................12 Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 13 Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 13 Table 8. Absolute Maximum Ratings ........................................................................................ 14 Table 9. Operating Modes ........................................................................................................18 Table 10. Serial Interface Timing Parameters .......................................................................... 19 Table 11. Operating Modes ...................................................................................................... 21 Table 12. Frequency Band Selection ....................................................................................... 28 Table 13. RX Packet Handler Configuration ............................................................................45 Table 14. Packet Handler Registers ......................................................................................... 46 Table 15. Minimum Receiver Settling Time .............................................................................. 48 Table 16. RX Modem Configurations for FSK and GFSK ........................................................ 49 Table 17. Filter Bandwidth Parameters .................................................................................... 51 Table 18. Channel Filter Bandwidth Settings ........................................................................... 52 Table 19. ndec[2:0] Settings ..................................................................................................... 53 Table 20. RX Modem Configuration for OOK with Manchester Disabled ................................. 54 Table 21. RX Modem Configuration for OOK with Manchester Enabled ................................. 54 Table 22. POR Parameters ...................................................................................................... 55 Table 23. Temperature Sensor Range ..................................................................................... 60 Table 24. Antenna Diversity Control ......................................................................................... 68 Table 25. Split RF I/Os Bill of Materials .................................................................................... 71 Table 26. Common TX/RX Connector Bill of Materials ............................................................ 73 Table 27. Antenna Diversity Bill of Materials ............................................................................75 Table 28. Recommended Crystal Parameters ......................................................................... 82 Table 29. RX Matching for Different Bands .............................................................................. 83 Table 30. Register Descriptions ............................................................................................... 85 Table 31. Interrupt or Status 1 Bit Set/Clear Description ......................................................... 90 Table 32. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? ............. 90 Table 33. Interrupt or Status 2 Bit Set/Clear Description ........................................................ 92 Table 34. Detailed Description of Status Registers when not Enabled as Interrupts ............... 92 Table 35. Internal Analog Signals Available on the Analog Test Bus .................................... 129 Table 36. Internal Digital Signals Available on the Digital Test Bus .......................................130 Table 37. Package Dimensions .............................................................................................. 157 Table 38. PCB Land Pattern Dimensions ............................................................................... 158 Preliminary Rev. 0.4 7 Si4432 1. Electrical Specifications Table 1. DC Characteristics1 Parameter Symbol Conditions Min Typ Max Units 1.8 3.0 3.6 V Supply Voltage Range Vdd Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 — 10 — nA IStandby Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF — 400 — nA ISleep RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF — 800 — nA ISensor-LBD Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA ISensor-TS Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled1 — 600 — µA ITune Synthesizer and regulators enabled — 9.5 — mA — 18.5 — mA TUNE Mode Current RX Mode Current IRX TX Mode Current ITX_+20 txpow[1:0] = 11 (+20 dBm), VDD = 3.3 V — 80 — mA ITX_+11 txpow[1:0] = 00 (+11 dBm), VDD = 3.3 V — 27 — mA Notes: 1. All specifications guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 8 Preliminary Rev. 0.4 Si4432 Table 2. Synthesizer AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units FSYNTH-LB Low Band 240 — 480 MHz FSYNTH-HB High Band 480 — 930 MHz FRES-LB Low Band — 156.25 — Hz FRES-HB High Band — 312.5 — Hz Reference Frequency fREF fcrystal / 3 — 10 — MHz Reference Frequency Input Level2 fREF_LV When using reference frequency instead of crystal. Measured peak-to-peak (VPP) 0.7 — 1.6 V Synthesizer Settling Time2 tLOCK Measured from leaving Ready mode with XOSC running to any frequency including VCO Calibration — 200 — µs Residual FM2 FRMS Integrated over 250 kHz bandwidth (500 Hz lower bound of integration) — 2 4 kHzRMS Phase Noise2 L(fM) F = 10 kHz — –80 — dBc/Hz F = 100 kHz — –90 — dBc/Hz F = 1 MHz — –115 — dBc/Hz F = 10 MHz — –130 — dBc/Hz Synthesizer Frequency Range Synthesizer Frequency Resolution2 Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. Preliminary Rev. 0.4 9 Si4432 Table 3. Receiver AC Electrical Characteristics1 Parameter RX Frequency Range RX Sensitivity Symbol Conditions Min Typ Max Units FSYNTH-LB Low Band 240 — 480 MHz FSYNTH-HB High Band 480 — 930 MHz PRX_2 (BER < 0.1%) (2 kbps, GFSK, BT = 0.5, f = 5 kHz)2 — –118 — dBm PRX_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, f = 20 kHz)2 — –107 — dBm PRX_100 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, f = 50 kHz)2 — –103 — dBm PRX_125 (BER < 0.1%) (125 kbps, GFSK, BT = 0.5, f = 62.5 kHz)1 — –101 — dBm PRX_OOK (BER < 0.1%) (4.8 kbps, 350 kHz BW, OOK)2 — –110 — dBm (BER < 0.1%) (40 kbps, 400 kHz BW, OOK)1 — –102 — dBm 2.6 — 620 kHz RX Bandwidth2 BW Residual BER Performance2 PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm Input Intercept Point, 3rd Order2 IIP3RX — –20 — dBm LNA Input Impedance2 (Unmatched, measured differentially across RX input pins) f1 = 915 MHz, f2 = 915 MHz, P1 = P2 = –40 dBm RIN-RX 915 MHz — 40–55j —  868 MHz — 44–58j — 433 MHz — 79–110j — 315 MHz — 96–134j — — ±0.5 — dB — –31 — dB — –35 — dB — –40 — dB RSSI Resolution Selectivity2 RESRSSI 1-Ch Offset (BER < 0.1%) C/I1-CH 2-Ch Offset Selectivity2 (BER < 0.1%) C/I2-CH  3-Ch Offset Selectivity2 (BER < 0.1%) C/I3-CH Blocking at 1 MHz2 1MBLOCK Blocking at 4 MHz 2 4MBLOCK Blocking at 8 MHz 2 8MBLOCK Image Rejection2 Spurious Emissions2 Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5 — –52 — dB — –56 — dB — –63 — dB ImREJ IF=937 kHz — –30 — dB POB_RX1 Measured at RX pins (LO feed through) — — –54 dBm Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 10 Preliminary Rev. 0.4 Si4432 Table 4. Transmitter AC Electrical Characteristics1 Parameter TX Frequency Range 2 Symbol Conditions Min Typ Max Units FSYNTH-LB Low Band 240 — 480 MHz FSYNTH-HB High Band 480 — 930 MHz FSK Modulation Data Rate DRFSK 1 — 128 kbps OOK Modulation Data Rate2 DROOK 1.2 — 40 kbps Modulation Deviation Δf ±320 kHz Modulation Deviation Resolution ΔfRES Output Power Range PTX TX RF Output Steps2 TX RF Output Level Variation vs. Voltage2 Production tests maximum limit of 320 kHz ±0.625 — 0.625 — kHz Power control by txpow[1:0] Register Production test at txpow[1:0] = 11 Tested at 915 MHz +11 — +20 dBm PRF_OUT controlled by txpow[1:0] Register — 3 — dB PRF_V Measured from VDD=3.6 V to VDD=1.8 V — 2 — dB TX RF Output Level2 Variation vs. Temperature PRF_TEMP –40 to +85 C — 2 — dB TX RF Output Level Variation vs. Frequency2 PRF_FREQ Measured across any one frequency band — 1 — dB Transmit Modulation Filtering2 B*T Gaussian Filtering Bandwith Time Product — 0.5 — Spurious Emissions2 POB-TX1 POUT = 11 dBm, Frequencies