SI50122-A1-GMR

Si50122-A1/A2 C R YS TA L - L E S S PCI- EXPRESS G EN 1 D U A L O UTPUT C L O C K G ENERATOR Features        Crystal-less clock generator with  integrated CMEMS PCI-Express Gen 1 compliant Two PCIe 100 MHz differential HCSL   outputs One 25 MHz single-ended LVCMOS  output Supports Serial (ATA) at 100 MHz  Low power differential output buffers No termination resistors required for  differential output clocks Triangular spread spectrum profile for maximum EMI reduction (Si50122-A2) Industrial Temperature –40 to 85 °C 2.5 V, 3.3 V Power supply Small package 10-pin TDFN (2.0 x 2.5 mm) Si50122-A1 does not support spread spectrum outputs Si50122-A2 supports 0.5% down spread outputs Ordering Information: See page 10 Applications Pin Assignments   Network Attached Storage  Multi-function Printer  Digital TV  Set top box Solid State Drives (SSD)  Wireless Access Point  Home Gateway  Digital Video Camera Si50 122-A1 /A2 Description Si50122-A1/A2 is a high-performance, crystal-less PCIe clock generator that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS clock outputs. The differential clock outputs are compliant to PCIe Gen1 specifications. The ultrasmall footprint (2.0 x 2.5 mm) and industry leading low-power consumption makes Si50122-A1/A2 the ideal clock solution for consumer and embedded applications where board space is limited and low power is needed. VSS 1 10 VDD REFOUT 2 9 VDD NC 3 8 DIFF2 DIFF1 4 7 DIFF2 DIFF1 5 6 VSS Patents pending Functional Block Diagram VDD REFOUT DIFF1 CMEMS PLL  (SSC) Divider DIFF2 VSS Rev 0.7 9/14 Copyright © 2014 by Silicon Laboratories Si50122-A1/A2 Si50122-A1/A2 2 Rev 0.7 Si50122-A1/A2 TABLE O F C ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Rev 0.7 3 Si50122-A1/A2 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage (3.3 V Supply) VDD 3.3 V ± 10% 2.97 3.3 3.63 V Supply Voltage (2.5 V Supply) VDD 2.5 V ± 10% 2.25 2.5 2.75 V Symbol Test Condition Min Typ Max Unit Operating Voltage (VDD = 3.3 V) VDD 3.3 V ± 10% 2.97 3.30 3.63 V Operating Voltage (VDD = 2.5 V) VDD 2.5 V ± 10% 2.25 2.5 2.75 V Operating Supply Current IDD Full Active; 3.3 V ± 10% — 20 23 mA Full Active; 2.5 V ± 10% — 18 21 mA CIN Input Pin Capacitance — 3 5 pF COUT Output Pin Capacitance — — 5 pF Table 2. DC Electrical Specifications Parameter Input Pin Capacitance Output Pin Capacitance 4 Rev 0.7 Si50122-A1/A2 Table 3. AC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit TDC Measured at 0 V differential 45 — 55 % TSKEW Measured at 0 V differential — — 100 ps Output Frequency FOUT VDD = 3.3 V — 100 — MHz Frequency Accuracy FACC All output clocks — — 100 ppm tr/f2 Measured differentially from ±150 mV 0.6 — 5.0 V/ns DIFF Clocks Duty Cycle Skew Slew rate PCIe Gen1 Pk-Pk Jitter Pk-PkGEN1 PCIe Gen 1, VDD = 3.3 V ±10% — 20.7 35 ps PCIe Gen1 Pk-Pk Jitter Pk-PkGEN1 PCIe Gen 1, VDD = 2.5 V ±10% — 25 40 ps VOX 300 — 550 mV Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V Spread Range SRNG Down Spread, –A2 only — — –0.5 % Modulation Frequency FMOD –A2 only 30 31.5 33 kHz TDC Measurement at 1.5 V 45 — 55 % Output Rise Time tr CL = 10 pF, 20% to 80% — 1.2 3.0 ns Output Fall Time tf CL = 10 pF, 20% to 80% — 1.2 3.0 ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 250 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm TSTABLE First power up to first output — — 10 ms Crossing Point Voltage at 0.7 V Swing 25 MHz at 3.3 V Duty Cycle Powerup Time Clock Stabilization from Powerup *Note: Visit www.pcisig.com for complete PCIe specifications. Rev 0.7 5 Si50122-A1/A2 Table 4. Thermal Conditions Parameter Symbol Test Condition Min Temperature, Storage TS Non-functional Temperature, Operating Ambient TA Temperature, Junction Typ Max Unit –65 150 °C Functional –40 85 °C TJ Functional — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — 38.3 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — 90.4 °C/W Test Condition Min Max Unit — 4.6 V Table 5. Absolute Maximum Conditions Parameter Main Supply Voltage Input Voltage ESD Protection (Human Body Model) Flammability Rating Symbol VDD_3.3 V Typ VIN Relative to VSS –0.5 4.6 VDC ESDHBM JEDEC (JESD 22 - A114) 2000 — V UL-94 UL (Class) V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup. Power supply sequencing is not required. 6 Rev 0.7 Si50122-A1/A2 2. Test and Measurement Setup Figure 1–Figure 3 show the test load configuration for the differential clock signals. M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" M e a su re m e n t P o in t L1 O U T- 5 0 2 pF Figure 1. 0.7 V Differential Load Configuration Figure 2. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) Rev 0.7 7 Si50122-A1/A2 Figure 3. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) L1 = 0.5", L2 = 5" 50 REF Measurement Point L1 L2 33  10 pF Figure 4. Single-ended Clocks with Single Load Configuration Figure 5. Single-ended Output Signal (for AC Parameter Measurement) 8 Rev 0.7 Si50122-A1/A2 3. Pin Descriptions VSS 1 10 VDD REFO UT 2 9 VDD NC 3 8 D IF F 2 D IF F 1 4 7 D IF F 2 D IF F 1 5 6 VSS Figure 6. 10-Pin TDFN Table 6. Si50122-Ax-GM 10-Pin TDFN Descriptions Pin # Name Type Description 1 VSS GND Connect to Ground 2 REFOUT O, SE 25 MHz LVCMOS clock output 3 NC NC 4 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output 5 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output 6 VSS GND 7 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output 8 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output 9 VDD PWR Power supply 10 VDD PWR Power supply No Connect; do not connect this pin to anything. Connect to Ground Rev 0.7 9 Si50122-A1/A2 4. Ordering Guide Part Number Spread Option Package Type Temperature Si50122-A1-GM No Spread 10-pin TDFN Industrial, –40 to 85 C Si50122-A1-GMR No Spread 10-pin TDFN—Tape and Reel Industrial, –40 to 85 C Si50122-A2-GM –0.5% Spread 10-pin TDFN Industrial, –40 to 85 C Si50122-A2-GMR –0.5% Spread 10-pin TDFN—Tape and Reel Industrial, –40 to 85 C Si50122 Si52112 Ax Bx Base part number A: Product Revision A x=1: non-spread outputs x=2: -0.5% spread outputs GMR GM2R Operating Temp Range: G: -40 to +85 °C M:10-TDFN M :10-TDFNPackage, Package,ROHS6, ROHS6,Pb-free Pb-free R: Tape & Reel (blank) = Tubes Figure 7. Ordering Information 10 Rev 0.7 Si50122-A1/A2 5. Package Outlines Figure 8. 10-Pin TDFN Package Drawing Rev 0.7 11 Si50122-A1/A2 Table 7. Package Diagram Dimensions Symbol Min Nom Max A 0.80 0.85 0.90 A1 0.00 — 0.05 A3 b 0.203 REF. 0.20 0.25 D 2.00 BSC. e 0.50 BSC E 2.50 BSC. L 0.35 0.4 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 0.30 0.45 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerances per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. This drawing conforms to the JEDEC Solid State Outline MO-229. 12 Rev 0.7 Si50122-A1/A2 6. Recommended Design Guideline 3.3V / 2.5V FB VDD 4.7uF 0.1uF Si50122 Figure 9. Recommended Application Schematic Note: FB Specifications: DC resistance 0.1–0.3 , Impedance at 100 MHz > 1000  Rev 0.7 13 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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