SI52147

Si52147 PCI-E XPRESS G EN 1, G EN 2 , & G EN 3 N IN E O UTPUT C L O C K G ENERATOR Features       PCI-Express Gen 1, Gen 2, &  Gen 3 compliant Low power push-pull type  differential output buffers Integrated resistors on differential  clocks Output enable pin for all clocks Hardware selectable spread control  Nine PCI-Express clocks 25 MHz crystal input or clock input I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Industrial temperature: –40 to 85 oC  3.3 V power supply  48-pin QFN package Ordering Information: See page 20. Applications   Pin Assignments VSS_PCI VSS_CORE VDD_CORE Network attached storage Multi-function printer   Wireless access point Routers VDD 1 2 3 4 5 6 7 8 9 10 11 12 VDD OE0 1 OE1 1 CKPWRGD_PDB1 SDATA 38 48 47 46 45 44 43 42 41 XOUT XIN NC NC NC NC 40 39 37 36 35 34 33 32 31 DIFF8 DIFF8 VDD DIFF7 DIFF7 DIFF6 DIFF6 VDD DIFF5 DIFF5 DIFF4 Description The Si52147 is a spread-controlled PCIe clock generator that can source nine PCIe clocks simultaneously. The device has six hardware output enable control inputs for enabling the respective differential outputs on the fly while powered on along with the hardware spread control for EMI reduction. SSON 2 VSS_PLL3 VSS_PLL4 OE2 1 OE3 1 OE[4:5] 1 OE[6:8] 1 VDD 49 GND SCLK 30 29 28 27 26 25 DIFF4 24 13 14 15 16 17 18 19 20 21 22 23 VDD VDD VSS DIFF0 DIFF0 DIFF1 DIFF1 DIFF2 DIFF2 DIFF3 Functional Block Diagram Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Patents pending DIFF0 XIN/CLKIN XOUT DIFF2 DIFF3 DIFF1 PLL1 (SSC) Divider DIFF4 DIFF5 DIFF6 SCLK SDATA CKPWRGD/PDB OE [8:0] SSON Control & Memory DIFF7 Control RAM DIFF8 Preliminary Rev. 0.1 12/11 Copyright © 2011 by Silicon Laboratories DIFF3 VSS Si52147 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i52147 2 Preliminary Rev. 0.1 S i52147 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. CKPWRGD_PDB (Power down) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. PDB (Power down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.8. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Preliminary Rev. 0.1 3 S i52147 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter 3.3 V Operating Voltage 3.3 V Input High Voltage 3.3 V Input Low Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current 3.3 V Output High Voltage (SE) 3.3 V Output Low Voltage (SE) High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Power Down Current Dynamic Supply Current Symbol VDD core VIH VIL VIHI2C VILI2C IIH IIL VOH VOL IOZ CIN COUT LIN IDD_PD IDD_3.3V All outputs enabled. Differential clocks with 5” traces and 2 pF load. Test Condition 3.3 ±5% Control input pins Control input pins SDATA, SCLK SDATA, SCLK Except internal pull-down resistors, 0 < VIN < VDD Except internal pull-up resistors, 0 < VIN < VDD IOH = –1 mA IOL = 1 mA Min 3.135 2.0 VSS – 0.3 2.2 — — –5 2.4 — –10 1.5 — — — — Typ 3.3 — — — — — — — — — — — — — — Max 3.465 VDD + 0.3 0.8 — 1.0 5 — — 0.4 10 5 6 7 1 85 Unit V V V V V A A V V A pF pF nH mA mA 4 Preliminary Rev. 0.1 S i52147 Table 2. AC Electrical Specifications Parameter Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle CLKIN Rise and Fall Times CLKIN Cycle to Cycle Jitter CLKIN Long Term Jitter Input High Voltage Input Low Voltage Input High Current Input Low Current DIFF at 0.7 V DIFF Duty Cycle Symbol LACC TDC TR/TF TCCJ TLTJ VIH VIL IIH IIL TDC Condition Measured at VDD/2 differential Measured at VDD/2 Measured between 0.2 VDD and 0.8 VDD Measured at VDD/2 Measured at VDD/2 XIN/CLKIN pin XIN/CLKIN pin XIN/CLKIN pin, VIN = VDD XIN/CLKIN pin, 0 < VIN