SI5310

Si5310 PRECISION CLOCK MULTIPLIER/REGENERATOR IC Features Complete precision clock multiplier and clock regenerator device: Performs clock multiplication to one of two frequency ranges: 150–167 MHz or 600–668 MHz Jitter generation as low as 0.5 psrms for 622 MHz output Accepts input clock from 9.4–668 MHz Regenerates a “clean”, jitterattenuated version of input clock DSPLL™ technology provides superior jitter performance Small footprint: 4 x 4 mm Low power: 310 mW typical ROHS-compliant Pb-free packaging option available Ordering Information: See page 21. Applications SONET/SDH systems Terabit routers Digital cross connects Optical transceiver modules Gigabit Ethernet systems Fibre channel Pin Assignments Si5310 MULTOUT+ MULTOUT– 15 MULTSEL Description REXT 1 2 3 4 5 20 19 18 17 16 PWRDN VDD CLKOUT+ CLKOUT– VDD The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. The clock regenerator operates simultaneously, creating a “clean” version of the input clock by using the clock synthesis phase-locked loop (PLL) to remove unwanted jitter and square up the input clock’s rising and falling edges. The Si5310 uses Silicon Laboratories patented DSPLL® architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs with a digital signal-processing algorithm. The Si5310 represents a new standard in low jitter, small size, low power, and ease-of-use for clock devices. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C). VDD GND REFCLK+ REFCLK– GND NC GND Pad 14 13 12 11 6 LOL 7 VDD 8 GND 9 CLKIN+ 10 CLKIN– Functional Block Diagram Regeneration BUF 2 CLKOUT+ CLKOUT– CLKIN+ CLKIN– 2 BUF DSPLL® Phase-Locked Loop Calibration 2 PWRDN/CAL MULTOUT+ MULTOUT– LOL BUF 2 Bias Gen REFCLK+ REFCLK– MULTSEL REXT Rev. 1.2 8/06 Copyright © 2006 by Silicon Laboratories Si5310 S i5310 2 Rev. 1.2 S i5310 TA B L E O F C O N T E N TS Section Page 1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2. Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3. 1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4. Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.6. DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8. Device Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.10. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.11. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.12. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.13. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Pin Descriptions: Si5310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 8. Package Outline: Si5310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 9. 4x4 mm 20L MLP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Rev. 1.2 3 S i5310 1. Detailed Block Diagram Regen Retime CLKOUT+ CLKOUT– c CLKIN+ CLKIN– Phase Detector A/D DSP n VCO CLK Divider MULTOUT+ c MULTOUT– REFCLK+ REFCLK– Lock Detector LOL MULTSEL REXT Bias Generation Calibration PWRDN/CAL 4 Rev. 1.2 S i5310 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5310 Supply Voltage2 Symbol TA VDD Test Condition Min1 –40 2.375 Typ 25 2.5 Max1 85 2.625 Unit °C V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5310 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3. Typical Application Circuit" on page 11. V SIG NAL + Differential V ICM , V O CM SIG NAL – I/Os V IS (SIGNAL +) – (SIGNAL –) Differential Voltage Swing V ID ,V O D Differential Peak-to-Peak Voltage t Figure 1. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT) CLKIN MULTOUT tCI-M tM-CO 1/fMULT CLKOUT Figure 2. CLKIN to CLKOUT, MULTOUT Phase Relationship CLKIN, REFCLK, CLKOUT, MULTOUT 80% 20% tF tR Figure 3. Differential Clock Input and Output Rise/Fall Times Rev. 1.2 5 S i5310 Table 2. DC Characteristics, VDD = 2.5 V, 622 Mbps (MULTSEL = 0) (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter Supply Current MULTSEL = 0 MULTSEL = 1 Power Dissipation MULTSEL = 0 MULTSEL = 1 Common Mode Input Voltage (CLKIN, REFCLK) Input Voltage Range* (CLKIN+, CLKIN–, REFCLK+, REFCLK–) Differential Input Voltage Swing* (CLKIN, REFCLK) Input Impedance (CLKIN, REFCLK) Differential Output Voltage Swing (CLKOUT) Differential Output Voltage Swing (MULTOUT) Output Common Mode Voltage (CLKOUT, MULTOUT) Output Impedance (CLKOUT, MULTOUT) Output Short to GND (CLKOUT, MULTOUT) Output Short to VDD (CLKOUT, MULTOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Internal Pulldown Current Symbol IDD Test Condition Min — — — — Typ 117 124 293 310 .80 x VDD — — 100 970 970 VDD – 0.23 100 25 –14.5 — — — — — — — 25 Max 127 134 333 352 — 750 1500 116 1260 1260 — 116 31 — .8 — 10 10 0.4 — — 45 Unit mA PD mW V mV mVPP Ω mVPP mVPP V Ω mA mA V V µA µA V V kΩ µA VICM VIS VID RIN VOD VOD VOCM ROUT ISC(–) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN See Figure 1 See Figure 1 See Figure 1 Line-to-Line 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line Single-ended — 200 200 84 780 780 — 84 — –17.5 — 2.0 — — IO = 2 mA IO = 2 mA VPWRDN ≥ 0.8 V — 2.0 10 15 *Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN–, REFCLK+, or REFCLK–) must not exceed the specified maximum Input Voltage Range (VIS max). 6 Rev. 1.2 S i5310 Table 3. AC Characteristics (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter CLKIN Frequency Range* CLKIN Duty Cycle REFCLK Range * Symbol Test Condition Min 9.375 40 9.375 Typ — — — 50 — Max 668 60 167 60 100 Unit MHz % MHz % ppm REFCLK Duty Cycle REFCLK Frequency Tolerance MULTOUT Clock Rate MULTOUT = 0 MULTOUT = 1 Output Rise/Fall Time (differential) (CLKOUT, MULTOUT) Input Rise/Fall Time (differential) (CLKIN, REFCLK) CLKIN to MULTOUT Delay MULTSEL = 0 MULTSEL = 1 MULTOUT to CLKOUT Delay CDUTY CTOL fMULT 40 –100 600 150 Figure 3 — — — 80 668 167 110 MHz ps tR,tF tR,tF Figure 3 — — 50 ns tCI-M Figure 2 –670 2.4 Figure 2 1/fMULT + 100 1/fMULT + 140 1/fMULT + 180 960 870 780 100 kHz–1 GHz — 20 — ps ps dB 130 3.4 930 4.4 ps ns tM-CO MULTSEL = 0 MULTSEL = 1 Input Return Loss *Note: See Table 9. Rev. 1.2 7 S i5310 Table 4. AC Characteristics (PLL Performance Characteristics) (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter Jitter Tolerance (MULTSEL = 0, MULTOUT = 600 to 668 MHz) Jitter Tolerance (MULTSEL = 1, MULTOUT = 150 to 167 MHz) Jitter Generation (MULTOUT, CLKOUT) (MULTSEL = 0, MULTOUT = 600 to 668 MHz)* (measurement BW = 12kHz to 1MHz) Symbol JTOL(PP) Test Condition Min Typ Max Unit See Table 5 JTOL(PP) See Table 6 JGEN(rms) Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000 — — — — — — — — — — — — — — — 2.5 1.6 0.9 0.6 0.4 8.5 5.0 3.7 2.3 1.1 75 150 300 600 1200 5.4 3.1 1.6 1.3 0.8 34.0 19.7 15.2 15.2 3.0 105 210 420 840 1680 psrms psrms psrms psrms psrms psrms psrms psrms psrms psrms kHz kHz kHz kHz kHz Jitter Generation (MULTOUT, CLKOUT) (MULTSEL = 1, MULTOUT = 150 to 167 MHz)* (measurement BW = 12kHz to 1MHz) JGEN(rms) Clock Input (MHz) = 9.375 to 10.438 Clock Input (MHz) = 18.750 to 20.875 Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Jitter Transfer Bandwidth (MULTSEL = 0, MULTOUT = 600 to 668 MHz)* JBW Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000 *Note: See PLL Performance section of this document for test descriptions. 8 Rev. 1.2 S i5310 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter Jitter Transfer Bandwidth (MULTSEL = 1, MULTOUT = 150 to 167 MHz)* Symbol JBW Test Condition Clock Input (MHz) = 9.375 to 10.438 Clock Input (MHz) = 18.750 to 20.875 Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Min — — — — — — — — — — — — — — — 1.45 40 450 Typ 19 38 75 150 300 0.12 0.06 0.03 0.02 0.01 0.12 0.06 0.03 0.02 0.01 1.5 60 600 Max 26 53 105 210 420 0.4 0.2 0.1 0.066 0.033 0.4 0.2 0.1 0.066 0.033 1.7 150 750 Unit kHz kHz kHz kHz kHz dB dB dB dB dB dB dB dB dB dB ms µs ppm Jitter Transfer Peaking (MULTSEL = 0, MULTOUT = 600 to 668 MHz)* JP Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000 Jitter Transfer Peaking (MULTSEL = 1, MULTOUT = 150 to 167 MHz)* JP Clock Input (MHz) = 9.375 to 10.438 Clock Input (MHz) = 18.750 to 20.875 Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Acquisition Time TAQ After falling edge of PWRDN/CAL From the return of valid CLKIN Frequency Difference at which PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOL LOCK 150 300 450 ppm *Note: See PLL Performance section of this document for test descriptions. Rev. 1.2 9 S i5310 Table 5. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL = 0, MULTOUT = 600 to 668 MHz) Frequency (Hz) < 300 25K 250K > 1M 37.5–41.75 MHz Clock Input 25.0 1.6 1.6 0.3 75–83.5 MHz Clock Input 25.0 3.2 3.2 0.3 150–167 MHz Clock Input 25.0 6.5 3.0 0.5 300–334 MHz Clock Input 25.0 16 3.2 0.5 *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Table 6. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL = 1, MULTOUT = 150 to 167 MHz) Frequency (Hz) < 300 6.5K 65K 325K > 1M 9.375–10.438 MHz Clock Input 66.7 6.4 1.2 1.2 1.2 18.75–20.875 MHz Clock Input 66.7 13.0 1.9 1.9 1.9 37.5–41.75 MHz Clock Input 66.7 29.0 1.9 1.9 1.9 75–83.5 MHz Clock Input 66.7 33.3 4.8 2.6 1.9 *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Table 7. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) CLKIN+, CLKIN–, REFCLK+, REFCLK–, All other pins TJCT TSTG — — Symbol VDD VDIG VDIF Value –0.5 to 2.8 –0.3 to 3.6 –0.3 to (VDD+ 0.3) ±50 –55 to 150 –55 to 150 1 1.5 Unit V V V mA °C °C kV kV Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol ϕJA Test Condition Still Air Value 38 Unit °C/W 10 Rev. 1.2 S i5310 3. Typical Application Circuit LV TTL Control Inputs Loss -of-Loc k Indicator MULTSEL Cloc k Input CLKIN+ CLKIN– PWRDDN/CA L CLKOUT+ CLKOUT– LOL Regenerated Cloc k Si5310 Sy s tem Ref erenc e Cloc k REFCLK+ REFCLK– MULTOUT+ MULTOUT– Multiplied Cloc k REXT 10 k Ω (1% ) 0.1 µ F V DD 2200 pF 20 pF Rev. 1.2 GND V DD 11 S i5310 4. Functional Description The Si5310 is an integrated clock multiplier and clock regenerator device based on SIlicon Laboratories DSPLL™ technology. The DSPLL phase locks to the clock input signal (CLKIN) and generates a phaselocked output clock (MULTOUT) at a multiple of the input clock frequency. The DSPLL is also employed to regenerate an output clock (CLKOUT) that is a jitterattenuated version of the input clock with clean rising and falling edges. The MULTOUT output is configured to operate in either the 150–167 MHz or the 600–668 MHz frequency range using the MULTSEL control input. A reference clock input signal (REFCLK) is used by the DSPLL as a reference for determination of the PLL lock status. For convenience, REFCLK can be provided at any one of five frequencies, each a multiple of the CLKIN frequency. The REFCLK rate is automatically detected, so no control inputs are needed for configuration. The REFCLK input can be synchronous or asynchronous with respect to the CLKIN input. The operating ranges for the CLKIN, CLKOUT, MULTOUT, and REFCLK signals are indicated in Table 9. Typical values for several applications are presented in Table 10. Table 9. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges MULTSEL CLKIN Range (MHz) REFCLK = 2n x CLKIN ±100 ppm (See Note 1) n = –2, –1, 0, 1, 2 n = –3, –2, –1, 0, 1 n = –4, –3, –2, –1, 0 n = –5, –4, –3, –2, –1 n = –6, –5, –4, –3, –2 n = 0, 1, 2, 3, 4 n = –1, 0, 1, 2, 3 n = –2, –1, 0, 1, 2 n = –3, –2, –1, 0, 1 n = –4, –3, –2, –1, 0 CLKOUT MULTOUT 37.500–41.750 75.000–83.500 0 (MULTOUT = 600–668 MHz) 150.000–167.000 300.000–334.000 600.000–668.000 9.375–10.438 18.750–20.875 1 (MULTOUT = 150–167 MHz) 37.500–41.750 75.000–83.500 150.000–167.000 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN See Note 2 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN See Note 2 16xCLKIN 8xCLKIN 4xCLKIN 2xCLKIN 1xCLKIN 16xCLKIN 8xCLKIN 4xCLKIN 2xCLKIN 1xCLKIN Note: 1. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple. 2. The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.) 12 Rev. 1.2 S i5310 Table 10. Clock Values for Typical Applications CLKIN (MHz) SONET/SDH 9.72 19.44 38.88 77.76 155.52 311.04 622.08 Gigabit Ethernet 9.77 19.53 39.06 78.125 156.25 312.5 625 SONET/SDH FEC (15/14) 10.41 20.83 41.66 83.31 166.63 333.26 666.51 REFCLK Input (MHz) 9.72 19.44 38.88 77.76 155.52 9.72, 19.44, 38.88, 77.76, or 155.52 9.72, 19.44, 38.88, 77.76, or 155.52 9.77 19.53 39.06 78.125 156.25 9.77, 19.53, 39.06, 78.125, or 156.25 9.77, 19.53, 39.06, 78.125, or 156.25 10.41 20.83 41.66 83.31 166.63 10.41, 20.83, 41.66, 83.31, or 166.63 10.41, 20.83, 41.66, 83.31, or 166.63 MULTSEL 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 CLKOUT (MHz) 9.72 19.44 38.88 38.88 77.76 77.76 — 155.52 311.04 — 9.77 19.53 39.06 39.06 78.125 78.125 — 156.25 312.5 — 10.41 20.83 41.66 41.66 83.31 83.31 — 166.63 333.26 — MULTOUT output (MHz) 155.52 155.52 155.52 622.08 155.52 622.08 155.52 622.08 622.08 622.08 156.25 156.25 156.25 625 156.25 625 156.25 625 625 625.00 166.63 166.63 166.63 666.51 166.63 666.51 166.63 666.51 666.51 666.51 Rev. 1.2 13 S i5310 4.1. DSPLL® The PLL structure (shown in Figure 1 on page 5) utilizes Silicon Laboratories' DSPLL® technology to produce superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). The technology produces clocks with less jitter than is generated using traditional methods. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. CLKOUT output is a resampled version of the CLKIN input with all CLKOUT transitions occurring synchronously with the rising edges of the MULTOUT output. The rising edges of CLKOUT are insensitive to the location of the falling edges of the CLKIN input. Thus the period of CLKOUT, measured rising edge to rising edge, is not affected by the CLKIN duty cycle or by jitter on the falling edge of CLKIN. The falling edges of CLKOUT may be affected by the location of the CLKIN falling edges as follows: If the duty cycle error of CLKIN is significant relative to the period of MULTOUT, then 1. The CLKOUT duty cycle may deviate from 50% (the falling edge of CLKOUT will be time quantized to the nearest rising edge of MULTOUT.) 2. Jitter on the falling edges of CLKIN may result in a CLKOUT duty cycle that alternates between two discrete values. Note: When the Si5310 is configured as a 1:1 multiplier, the CLKOUT output is not valid. 4.2. Clock Multiplier The DSPLL phase locks to the clock input signal (CLKIN) and generates an output clock (MULTOUT) at a multiple of the input clock frequency. The MULTOUT output is configured to operate in either the 150– 167 MHz frequency range or in the 600–668 MHz frequency range using the MULTSEL control input as indicated in Table 9. Values for typical applications are given in Table 10. The amount of jitter present in the MULTOUT output is a function of the DSPLL jitter transfer function and jitter generation characteristic. Details are provided in the PLL Performance section of this document. (See Figures 4 and 5.) The amount of jitter that the DSPLL can tolerate on the CLKIN input is specified in Tables 5 and 6. The DSPLL implementation in the Si5310 is insensitive to the duty cycle of the CLKIN input. The MULTOUT output will continue to exhibit a very good duty cycle characteristic even when the CLKIN input duty cycle is degraded. 4.5. Reference Clock The Si5310 CMU requires an external reference clock applied to the REFCLK input for normal device operation. When REFCLK is absent, the LOL alarm will always be asserted when it has been determined that no activity exists on REFCLK, indicating the lock status of the PLL is unknown. Additionally, the reference clock input is used to center the DSPLL and also to act as a reference for determination of the PLL lock status. REFCLK is a multiple of the CLKIN frequency, and can be provided in any one of five frequency ranges (9.375– 10.438 MHz, 18.78–20.875 MHz, 37.500–41.750 MHz, 75.00–83.50 MHz, or 150–167.00 MHz). The REFCLK rate is automatically detected by the Si5310, so no control inputs are needed for REFCLK frequency selection. The REFCLK input may be synchronous or asynchronous with respect to the CLKIN input. The frequency relationship between REFCLK and CLKIN is indicated in Table 9. In many applications, it may be desirable to tie REFCLK and CLKIN together and drive them from the same clock source. The Si5310 is insensitive to the phase relationship between CLKIN and REFCLK, so these differential inputs may be driven in phase or 180° out of phase if this simplifies board layout. Values for typical applications are given in Table 10. 4.3. 1x Multiplication The Si5310 Clock Multiplier function may also be utilized as a 1x multiplier in order to provide jitter attenuation and duty cycle correction without multiplication of the input clock frequency. Note: When the Si5310 is configured as a 1:1 multiplier, the CLKOUT output is not valid. 4.4. Clock Regeneration The DSPLL is used to regenerate a jitter-attenuated version of the CLKIN input, resulting in a “clean” CLKOUT output with sharp rising and falling edges. The 4.6. DSPLL Lock Detection (Loss-of-Lock) The Si5310 provides lock-detect circuitry that indicates whether the DSPLL has achieved frequency lock with the incoming CLKIN signal. The circuit compares the frequency of a divided down version of the multiplier 14 Rev. 1.2 S i5310 output with the frequency of the supplied reference clock. If the divided multiplier output frequency deviates from that of the reference clock by the amount specified in Table 4 on page 8, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted high. In this state, the PLL will periodically try to reacquire lock with the input clock (CLKIN). During reacquisition, the multiplier output clock (MULTOUT) may drift over a ±600 ppm range relative to the applied reference clock and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the low noise and stability of the DSPLL, under the condition where the input clock is removed from the inputs, there is the possibility that the PLL will not drift enough to render an out-of-lock condition. If REFCLK is removed, the LOL output alarm will always be asserted when it has been determined that no activity exists on REFCLK, indicating the frequency lock status of the PLL is unknown. Note: LOL is not asserted during PWRDN/CAL. MULTSEL setting and the input clock rate. Higher input clock rates produce higher bandwidth transfer functions with lower jitter peaking. Table 4 gives the 3 dB bandwidth and peaking values for specified input clock rates and MULTSEL settings. Figures 4 and 5 show a family of jitter transfer curves for different input clock rates. 4.7.3. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of MULTSEL setting and input clock frequency. For clock multiplier applications, the higher the multiplier ratio desired, the larger the jitter generation. Table 4 gives the jitter generation values for specified MULTSEL settings and input clock rates. 4.8. Device Powerdown The Si5310 PWRDN/CAL input can be used to hold the device in a power-down state when not in use. When the PWRDN/CAL input is asserted (set high), the CLKOUT and MULTOUT output drivers are disabled and the positive and negative terminals of the CLKOUT and MULTOUT outputs are each tied to VDD through 100 Ω on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant clock sources. When PWRDN/CAL is released (set to low) the digital logic is reset to a known initial condition and the DSPLL circuitry is recalibrated and will begin to lock to the incoming clock. 4.7. PLL Performance The Si5310 DSPLL circuitry is designed to provide low jitter generation, high jitter tolerance, and a wellcontrolled jitter transfer function with low peaking. Each of these key performance parameters is described more fully in the following sections. 4.7.1. Jitter Tolerance Jitter tolerance for the Si5310 is defined as the maximum peak-to-peak sinusoidal jitter that can be added to the incoming clock before the PLL exceeds its allowable operating range and loses lock. The tolerance is a function of the jitter frequency, the incoming clock rate, and the MULTSEL setting. The jitter tolerance for specified jitter frequencies and input clock rates is given in Tables 5 and 6. 4.7.2. Jitter Transfer Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The jitter transfer characteristic determines the amount of input clock jitter that will be passed on to the Si5310 CLKOUT and MULTOUT outputs. The DSPLL technology used in the Si5310 provides a tightly controlled jitter transfer curve because many of the PLL gain parameters are determined by digital signal processing algorithms which do not vary over supply voltage, process, and temperature. In a system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board, providing more consistent system level jitter performance. The jitter transfer characteristic is a function of the 4.9. PLL Self-Calibration Si5310 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLL. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. For optimal jitter performance, the supply voltage should be stable at 2.5 V ±10% when calibration is initiated. The PWRDN/CAL signal should be held high for at least 1 µS after the supply has stabilized before transitioning low to initiate self-calibration. See Silicon Laboratories application note AN42 for suggested methods of generating the PWRDN/CAL signal for initiation of self-calibration. 4.10. Device Grounding The Si5310 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 11 and 12 for the ground (GND) pad location. 15 Rev. 1.2 S i5310 4.11. Bias Generation Circuitry The Si5310 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption compared with traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. 0 CLKIN=622MHz −1 coupling is possible, the 0.1 µF capacitors may be omitted. The CLKIN and REFCLK input amplifiers require input signals with minimum differential peak-topeak voltages as specified in Table 2 on page 6. 0 CLKIN=155MHz −1 −2 −3 −4 CLKIN=9.7MHz −2 −5 −3 −6 −4 CLKIN=39MHz −5 −7 −8 −6 −9 10 3 10 4 10 5 10 6 −7 −8 Figure 5. PLL Jitter Transfer Functions, MULTSEL = 1 (MULTOUT = 150–167 MHz) 10 3 −9 10 4 10 5 10 6 Figure 4. PLL Jitter Transfer Functions, MULTSEL = 0 (MULTOUT = 600–668 MHz) 4.13. Differential Output Circuitry The Si5310 utilizes a current mode logic (CML) architecture to output both the regenerated clock (CLKOUT) and the multiplied clock (MULTOUT). An example of output termination with ac coupling is shown in Figure 10. For applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML is listed in Table 2 on page 6. 4.12. Differential Input Circuitry The Si5310 provides differential inputs for both the input clock (CLKIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc 16 Rev. 1.2 S i5310 Clock source Si5310 VDD CLKIN +, RFCLK + 2.5 k Ω 0.1 µ F Zo = 50 Ω 10 k Ω 0.1 µ F Zo = 50 Ω CLKIN –, RFCLK – 2.5 k Ω 102 Ω 10 k Ω GND Figure 6. Input Termination for CLKIN and REFCLK (ac-coupled) Si5310 Clock source 0.1 µF Zo = 50 Ω REFCLK + 10 kΩ 100 Ω REFCLK – 10 kΩ 0.1 µF 2.5 kΩ VDD 2.5 kΩ 102 Ω GND Figure 7. Single-Ended Input Termination for REFCLK (ac-coupled) Si5310 Clock source 0.1 µF Zo = 50 Ω CLKIN + 10 kΩ 100 Ω CLKIN – 10 kΩ 0.1 µF 2.5 kΩ VDD 2.5 kΩ 102 Ω GND Figure 8. Single-Ended Input Termination for CLKIN (ac-coupled) Rev. 1.2 17 S i5310 Clock source or differential buffer/driver 2.5 kΩ 0.1 µF Zo = 50 Ω REFCLK + 10 kΩ 100 Ω REFCLK – Si5310 VDD 2.5 kΩ 102 Ω 10 kΩ 0.1 µF GND VDD 2.5 kΩ 0.1 µF Zo = 50 Ω CLKIN 10 kΩ 100 Ω CLKIN + 10 kΩ 0.1 µF 2.5 kΩ 102 Ω ( Example: REFCLK = CLKIN = 155.52MHz ) GND Figure 9. Single-Ended Input Termination for REFCLK & CLKIN (ac-coupled) Si5310 VDD 100 Ω VDD 50 Ω CLKOUT+, MULTOUT+ 0.1 µ F Zo = 50 Ω CLKOUT–, MULTOUT– 0.1 µ F Zo = 50 Ω 100 Ω VDD 50 Ω VDD Figure 10. Output Termination for CLKOUT and MULTOUT (ac-coupled) 18 Rev. 1.2 S i5310 5. Pin Descriptions: Si5310 MULTOUT+ MULTOUT– MULTSEL 20 19 18 REXT VDD GND REFCLK+ REFCLK– GND NC 17 16 15 PWRDN 14 VDD 1 2 3 4 5 6 LOL GND Pad 13 CLKOUT+ 12 CLKOUT– 11 VDD 7 VDD 8 GND 9 CLKIN+ 10 CLKIN– Top View Figure 11. Si5310 Pin Configuration Table 11. Si5310 Pin Descriptions Pin # 1 Pin Name REXT I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. 2.5 V GND Supply Voltage. Nominally 2.5 V. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 12) must be connected directly to supply ground. Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock regeneration and multiplication. Additionally, the reference clock is used as a reference in generation of the LOL output and to bound the frequency drift of MULTOUT when CLKIN is not present. Loss of Lock. This output is driven high when a divided version of the clock multiplier output deviates from the reference clock frequency by the amount specified in Table 4 on page 8. Differential Clock Input. Differential input clock from which MULTOUT is derived. 2, 7, 11, 14 3, 8, 18, and GND Pad VDD GND 4, 5 REFCLK+, REFCLK– I See Table 2 6 LOL O LVTTL 9, 10 CLKIN+, CLKIN– I See Table 2 Rev. 1.2 19 S i5310 Table 11. Si5310 Pin Descriptions (Continued) Pin # 12, 13 Pin Name CLKOUT–, CLKOUT+ I/O O Signal Level CML Description Differential Clock Output. The clock output signal is a regenerated version of the input clock signal present on CLKIN. It is phase aligned with MULTOUT and is updated on the rising edge of MULTOUT. Note: Connection of an improperly terminated transmission line to the CLKOUT output can cause reflections that may adversely affect the performance of the MULTOUT output. If the CLKOUT output is not used, these pins should be either tied to VDD (recommended), left unconnected, or connected to a properly terminated transmission line. 15 PWRDN/CAL I LVTTL Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a high-tolow transition on this pin. (See "4.9. PLL Self-Calibration" on page 15.) Note: This input has a weak internal pulldown. 16, 17 MULTOUT–, MULTOUT+ O CML Differential Multiplier Output. The multiplier output is generated from the signal present on CLKIN. In the absence of CLKIN, the REFCLK is used to bound the frequency of MULTOUT according to Table 4 on page 8. Note: Connection of an improperly terminated transmission line to the MULTOUT output can cause reflections that may adversely affect the CLKOUT output. If the MULTOUT output is not used, these pins should be either tied to VDD (recommended), left unconnected, or connected to a properly terminated transmission line. 19 MULTSEL I LVTTL Multiplier Rate Select. This pin configures the onboard PLL-based clock multiplier for clock generation at one of two user selectable clock rates. Note: This input has a weak internal pulldown. 20 NC No Connect. 20 Rev. 1.2 S i5310 6. Ordering Guide Part Number Si5310-BM Si5310-GM Package 20-pin MLP 20-pin MLP (Pb free) Temperature –40 to 85 °C –40 to 85 °C 7. Top Mark Silicon Labs Part Number Si5310-BM Si5310-GM Die Revision (R) C C Part Designator (Z) D G Rev. 1.2 21 S i5310 8. Package Outline: Si5310 Figure 12 illustrates the package details for the Si5310. Table 12 lists the values for the dimensions shown in the illustration. D D1 PIN1 ID 0.50 DIA. 20 A A1 A2 A3 b b 1 2 3 θ e e D2 L 20 1 2 3 E1 E E2 Top View Side View Bottom View Figure 12. 20-pin Micro Leadframe Package (MLP) Table 12. Package Dimensions Symbol Min A A1 A2 A3 b D, E 0.18 — 0.00 — Millimeters Nom 0.85 0.01 0.65 0.20 REF. 0.23 4.00 BSC 0.30 Max 0.90 0.05 0.70 D1, E1 D2, E2 e θ L — 0.50 1.95 Symbol Min Millimeters Nom 3.75 BSC 2.10 0.50 BSC — 0.60 12° 0.75 2.25 Max Notes: 1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 2. Package warpage MAX 0.05 mm. 3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP. 4. The package weight is approximately 42 mg. 5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28 minimum/54 typical. 6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification. 22 Rev. 1.2 S i5310 9. 4x4 mm 20L MLP Recommended PCB Layout See Note 8 Gnd Pin See Note 9 Gnd Pin Symbol A D e G R X Y Z Parameter Min Pad Row/Column Width/Length Thermal Pad Width/Height Pad Pitch Pad Row/Column Separation Pad Radius Pad Width Pad Length Pad Row/Column Extents 2.23 2.03 — 2.43 — 0.23 — 4.26 Gnd Pin Dimensions Nom 2.25 2.08 0.50 BSC 2.46 0.12 REF 0.25 0.94 REF 4.28 Max 2.28 2.13 — 2.48 — 0.28 — 4.31 Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad. 3. The center thermal pad is to be Solder Mask Defined (SMD). 4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent solder from flowing into the via hole. 5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a 0.65 mm pitch, should be used for the center thermal pad. 6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate paste release. 7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended. 8. Do not place any signal or power plane vias in these “keep out” regions. 9. Suggest four 0.38 mm (15 mil) vias to the ground plane. Rev. 1.2 23 S i5310 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Added "7. Top Mark" on page 21. Updated "8. Package Outline: Si5310" on page 22. Added "9. 4x4 mm 20L MLP Recommended PCB Layout" on page 23. Revision 1.1 to Revision 1.2 Added Pb-free packaging option in "6. Ordering Guide" on page 21. 24 Rev. 1.2 S i5310 NOTES: Rev. 1.2 25 S i5310 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 26 Rev. 1.2