SI5316

Si5316 P R E L I M I N A R Y D A TA S H E E T PRECISION CLOCK JITTER ATTENUATOR Description The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is ideal for providing jitter attenuation in high performance timing applications. Features Fixed frequency jitter attenuator with selectable clock ranges at 19, 38, 77, 155, 311, and 622 MHz (710 MHz max) Support for SONET, 10GbE, 10GFC, and corresponding FEC rates Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (100 Hz to 7.9 kHz) Meets OC-192 GR-253-CORE jitter specifications Dual clock inputs with integrated clock select mux One clock input can be 1x, 4x, or 32x the frequency of the second clock input Single clock output with selectable signal format: LVPECL, LVDS, CML, CMOS LOL, LOS alarm outputs Pin programmable settings On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation Small size (6 x 6 mm 36-lead QFN) Pb-free, RoHS compliant Applications Optical modules SONET/SDH OC-48/OC-192 line cards 10GbE, 10GFC line cards ITU G.709 line cards Wireless basestations Test and measurement Xtal or Refclock CK1DIV CKIN1 CK2DIV ÷ Signal Format DSPLL ® ÷ Signal Detect CKOUT Disable CKIN2 Loss of Signal VDD (1.8, 2.5, or 3.3 V) GND Clock Select Frequency Bandwidth Select Select Loss of Lock PLL Bypass Preliminary Rev. 0.24 3/07 Copyright © 2007 by Silicon Laboratories Si5316 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5316 Table 1. Performance Specifications (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol TA VDD Test Condition Min –40 2.97 2.25 1.62 Typ 25 3.3 2.5 1.8 217 194 TBD — — — — — — — — — — — — — — — — 230 — 0.3 Max 85 3.63 2.75 1.98 243 220 TBD 22.28 44.56 89.13 178.25 356.5 710.0 1.9 1.4 1.7 1.95 11 60 — VDD – 1.25 1.9 0.93 350 55 TBD Unit ºC V V V mA mA mA MHz Supply Current IDD fOUT = 622.08 MHz LVPECL format output fOUT = 19.44 MHz CMOS format output Tristate/Sleep Mode — — — 19.38 38.75 77.5 155.0 310.0 620.0 0.25 Input/Output Clock Frequency (CKIN1, CKIN2, CKOUT) CKF FRQSEL[1:0] = LL FRQSEL[1:0] = LM FRQSEL[1:0] = LH FRQSEL[1:0] = ML FRQSEL[1:0] = MM FRQSEL[1:0] = MH Input Clocks (CKIN1, CKIN2) Differential Voltage Swing Common Mode Voltage CKNDPP CKNVCM 1.8V ±10% 2.5V ±10% 3.3V ±10% Rise/Fall Time Duty Cycle Output Clock (CKOUT) Common Mode Differential Output Swing Single Ended Output Swing Rise/Fall Time Duty Cycle PLL Performance Jitter Generation JGEN fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz Jitter Transfer JPK — ps rms VOCM VOD VSE CKOTRF CKODC LVPECL 100 Ω load line-to-line 20–80% VDD – 1.42 1.1 0.5 — 45 V VPP V ps % CKNTRF CKNDC 20–80% Whichever is less VPP V V V ns % ns 0.9 1.0 1.1 — 40 50 — — 0.3 0.05 TBD 0.1 ps rms dB Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.24 S i5316 Table 1. Performance Specifications (Continued) (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter External Reference Jitter Transfer Phase Noise Symbol JPKEXTN CKOPN Test Condition Min — Typ TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD Unit dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset — — — — — — — Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient SPSUBH SPSPUR Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air θJA — 38 — ºC/W Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 3.6 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V ºC ºC kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.24 3 S i5316 155.52 MHz in, 622.08 MHz out 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Preliminary Rev. 0.24 S i5316 Figure 2. Si5316 Typical Application Circuit Preliminary Rev. 0.24 5 S i5316 1. Functional Description The Si5316 is a precision jitter attenuator for high-speed communication systems, including OC-48, OC-192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitterattenuated clock output at the same frequency. Within each of these clock ranges, the device can be tuned approximately 15% higher than nominal SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz range. The Si5316 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. For applications which require input clocks at different frequencies, the frequency of CKIN1 can be 1x, 4x, or 32x the frequency of CKIN2 as specified by the CK1DIV and CK2DIV inputs. The Si5316 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 100 Hz to 7.9 kHz. To calculate potential loop bandwidth values for a given input/output clock frequency, Silicon Laboratories offers a PC-based software utility, DSPLLsim, that calculates valid loop bandwidth settings automatically. This utility can be downloaded from www.silabs.com/timing. The Si5316 supports manual active input clock selection. The Si5316 monitors both input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on either input clock. Hitless switching is not supported by the Si5316. During a clock transition, the phase of the output clock will slew at a rate defined by the PLL loop bandwidth until the original input clock phase to output clock phase is restored. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5316 has one differential clock output. The electrical format of the clock output is programmable to support LVPECL, LVDS, CML, or CMOS loads. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. 1.1. External Reference An external, 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high-quality crystal from TXC (www.txc.com.tw), part number 7MA1400014. An external 38.88 MHz clock from a high quality OCXO or TCXO can also be used as a reference for the device. In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in digital hold will be tracked by the output of the device. Note that crystals can have temperature sensitivities. 1.2. Further Documentation Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5316. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing. 6 Preliminary Rev. 0.24 S i5316 2. Pin Descriptions: Si5316 CKOUT+ CKOUT– SFOUT0 GND SFOUT1 VDD NC NC NC 27 CK2DIV 26 CK1DIV 25 FRQSEL1 24 FRQSEL0 23 BWSEL1 22 BWSEL0 21 CS 20 NC 19 NC 10 11 12 13 14 15 16 17 18 CKIN2+ CKIN1+ CKIN2– CKIN1– VDD DBL_BY RATE LOL NC 36 35 34 33 32 31 30 29 28 RST NC C1B C2B VDD XA XB GND NC 1 2 3 4 5 6 7 8 9 GND Pad Pin assignments are preliminary and subject to change. Table 3. Si5316 Pin Descriptions Pin # 1 Pin Name RST I/O I Signal Level LVCMOS Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5316 will perform an internal self-calibration. This pin has a weak pull-up. No Connect. These pins must be left unconnected for normal operation. CKIN1 Loss of Signal. Active high Loss-of-signal indicator for CKIN1. Once triggered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present 1 = LOS on CKIN1 CKIN2 Loss of Signal. Active high Loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present 1 = LOS on CKIN2 Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should be placed as close to device as is practical. 2, 9, 11, 19, 20, 28, 29, 36 3 NC — — C1B O LVCMOS 4 C2B O LVCMOS 5, 10, 32 VDD VDD Supply Preliminary Rev. 0.24 7 S i5316 Table 3. Si5316 Pin Descriptions (Continued) Pin # 7 6 Pin Name XB XA I/O I Signal Level Analog Description External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. If external reference is used, apply reference clock to XA input and leave XB pin floating. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pin. Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. External Crystal or Reference Clock Rate. Three level input that selects the type and rate of external crystal or reference clock to be applied to the XA/XB port. L = 38.88 MHz external clock M = 114.285 MHz 3rd OT crystal H = Reserved Clock Input 2. Differential input clock. This input can also be driven with a singleended signal. Output Disable/Bypass Mode Control. Controls enable of CKOUT divider/output buffer path and PLL bypass mode. L = CKOUT enabled M = CKOUT disabled H = Bypass mode with CKOUT enabled Clock Input 1. Differential input clock. This input can also be driven with a singleended signal. PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator. 0 = PLL locked 1 = PLL unlocked Input Clock Select. This pin functions as the input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CKSEL input state. 0 = Select CKIN1 1 = Select CKIN2 Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. Frequency Select. Sets the output frequency of the device. When the frequency of CKIN1 is not equal to CKIN2, the lower frequency input clock must be equal to the output clock frequency. Preliminary Rev. 0.24 8, 31 GND GND Supply 15 RATE I 3-Level 12 13 14 CKIN2+ CKIN2– DBL_BY I Multi I 3-Level 16 17 18 CKIN1+ CKIN1– LOL I Multi O LVCMOS 21 CS I LVCMOS 23 22 BWSEL1 BWSEL0 I 3-Level 25 24 FRQSEL1 FRQSEL0 I 3-Level 8 S i5316 Table 3. Si5316 Pin Descriptions (Continued) Pin # 26 Pin Name CK1DIV I/O I Signal Level 3-Level Description Input Clock 1 Pre-Divider Select. Pre-divider on CKIN1. Used with CK2DIV to divide input clock frequencies to a common value. When the frequencies applied to CKIN1 and CKIN2 are equal, CK1DIV must be tied low. L = CKIN1 input divider set to 1. M = CKIN1 input divider set to 4. H = CKIN1 input divider set to 32. Input Clock 2 Pre-Divider Select. Pre-divider on CKIN2. Used with CK1DIV to divide input clock frequencies to a common value. When the frequencies applied to CKIN1 and CKIN2 are equal, CK2DIV must be tied low. L = CKIN2 input divider set to 1. M = CKIN2 input divider set to 4. H = CKIN2 input divider set to 32. Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for CKOUT. Valid settings include LVPECL, LVDS, and CML. Also includes selections for CMOS mode, tristate mode, and tristate/sleep mode. SFOUT[1:0] HH HM HL MH MM ML LH LM LL 34 35 CKOUT– CKOUT+ O Multi Signal Format Reserved Reserved CML LVPECL Reserved LVDS CMOS Tristate/Sleep Reserved 27 CK2DIV I 3-Level 33 30 SFOUT0 SFOUT1 I 3-Level Clock Output. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. GND PAD GND GND Supply Preliminary Rev. 0.24 9 S i5316 3. Ordering Guide Ordering Part Number Si5316-B-GM Package 36-Lead 6 x 6 mm QFN Temperature Range –40 to 85 °C 10 Preliminary Rev. 0.24 S i5316 4. Package Outline: 36-Lead QFN Figure 3 illustrates the package details for the Si5316. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 36-Pin Quad Flat No-lead (QFN) Table 4. Package Dimensions Symbol Min A A1 b D D2 e E E2 3.95 3.95 0.80 0.00 0.18 Millimeters Nom 0.85 0.01 0.23 6.00 BSC 4.10 0.50 BSC 6.00 BSC 4.10 4.25 4.25 Max 0.90 0.05 0.30 L θ aaa bbb ccc ddd eee Symbol Min 0.50 — — — — — — Millimeters Nom 0.60 — — — — — — Max 0.75 12º 0.10 0.10 0.05 0.10 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.24 11 S i5316 5. Recommended PCB Layout Figure 4. PCB Land Pattern Diagram 12 Preliminary Rev. 0.24 S i5316 Table 5. PCB Land Pattern Dimensions Dimension e E D E2 D2 GE GD X Y ZE ZD — — 4.00 4.00 4.53 4.53 — 0.89 REF. 6.31 6.31 MIN 0.50 BSC. 5.42 REF. 5.42 REF. 4.20 4.20 — — 0.28 MAX Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.24 13 S i5316 DOCUMENT CHANGE LIST Revision 0.23 to 0.24 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Added Figure 1, “Typical Phase Noise Plot,” on page 4. Showed preferred interface for an external reference clock in Figure 2, “Si5316 Typical Application Circuit,” on page 5. Updated 3. "Ordering Guide" on page 10. Added “5. Recommended PCB Layout”. 14 Preliminary Rev. 0.24 S i5316 NOTES: Preliminary Rev. 0.24 15 S i5316 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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