SI5322-C-GM

Si5322 P I N - P ROGRAMMABLE P R E C I S I O N C LOCK M U LT IP L I E R Features      Not recommended for new  designs. For alternatives, see the Si533x family of products. Selectable output frequencies  ranging from 19.44 to 1050 MHz Low jitter clock outputs with jitter  generation as low as 0.6 psRMS  (50 kHz–80 MHz)  Integrated loop filter with selectable loop bandwidth (150 kHz to 1.3 MHz)  Dual clock inputs with manual or automatically controlled  switching Dual clock outputs with selectable signal format: LVPECL, LVDS, CML, CMOS Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOS alarm output Pin-programmable settings On-chip voltage regulator for 1.8 V ±5%, 2.5 or 3.3 V ±10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, RoHS compliant Ordering Information: See page 18. Pin Assignments Applications SONET/SDH OC-48/STM-16  ITU G.709 line cards and OC-192/STM-64 line cards  Optical modules  GbE/10GbE, 1/2/4/8/10GFC line  Test and measurement cards CKOUT1– CKOUT1+ SFOUT1 GND SFOUT0 VDD CKOUT2– CKOUT2+ NC  36 35 34 33 32 31 30 29 28 RST 1 27 FRQSEL3 FRQTBL 2 26 FRQSEL2 Description C1B 3 25 FRQSEL1 C2B 4 The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two equal frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5322 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides anyfrequency synthesis in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for providing clock multiplication in high performance timing applications. VDD 5 GND 6 NC 7 GND 8 20 GND AUTOSEL 9 19 GND Rev. 1.0 9/14 Copyright © 2014 by Silicon Laboratories 24 FRQSEL0 GND Pad 23 BWSEL1 22 BWSEL0 21 CS_CA NC CKIN1– VDD CKIN1+ DBL2_BY CKIN2– CKIN2+ VDD VDD 10 11 12 13 14 15 16 17 18 Si5322 Si5322 Functional Block Diagram CKOUT1 CKIN1 DSPLL® Signal Format CKOUT2 CKIN2 Disable/BYPASS Loss of Signal Control Signal Detect VDD (1.8, 2.5, or 3.3 V) GND 2 Frequency Select Manual/Auto Switch Bandwidth Select Clock Select Rev. 1.0 Si5322 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2. Three-Level Input Pins (Example with External Resistors) . . . . . . . . . . . . . . . . . . . . .9 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. Pin Descriptions: Si5322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. Land Pattern: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1. Si5322 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Rev. 1.0 3 Si5322 1. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol Test Condition Min Typ Max Unit –40 25 85 ºC 3.3 V nominal 2.97 3.3 3.63 V 2.5 V nominal 2.25 2.5 2.75 V 1.8 V nominal 1.71 1.8 1.89 V TA VDD Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Supply Current (Supply current is independent of VDD) Symbol Test Condition Min Typ Max Unit IDD LVPECL Format 622.08 MHz Out All CKOUTs Enabled1 LVPECL Format 622.08 MHz Out Only 1 CKOUT Enabled1 CMOS Format 19.44 MHz Out All CKOUTs Enabled CMOS Format 19.44 MHz Out Only CKOUT1 Enabled — 251 279 mA — 217 243 mA — 204 234 mA — 194 220 mA 1.8 V ±5% 0.9 — 1.4 V 2.5 V ±10% 1.0 — 1.7 V 3.3 V ±10% 1.1 — 1.95 V CKIN Input Pins Input Common Mode Voltage (Input Threshold Voltage) VICM Input Resistance CKNRIN Single-ended 20 40 60 k Input Voltage Level Limits CKNVIN See Note 2 0 — VDD V VISE fCKIN < 212.5 MHz See Figure 2. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 2. 0.25 — — VPP Single-Ended Input Voltage Swing Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 4 Rev. 1.0 Si5322 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit VID fCKIN < 212.5 MHz See Figure 2. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 2. 0.25 — — VPP CKOVCM LVPECL 100  load line-to-line VDD – 1.42 — VDD – 1.25 V Differential Output Swing CKOVD LVPECL 100  load line-to-line 1.1 — 1.9 VPP Single-ended Output Swing CKOVSE LVPECL 100  load line-to-line 0.5 — 0.93 VPP Differential Output Voltage CKOVD CML 100  load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM CML 100  load line-to-line — VDD – 0.36 — V Differential Output Voltage CKOVD LVDS 100  load line-to-line 500 700 900 mVPP Low swing LVDS 100  load line-to-line 350 425 500 mVPP CKOVCM LVDS 100  load line-to-line 1.125 1.2 1.275 V CKORD CML, LVDS, LVPECL — 200 —  Output Voltage Low CKOVOLLH CMOS — — 0.4 V Output Voltage High CKOVOHLH VDD = 1.71 V CMOS 0.8 x VDD — — V Output Drive Current CKOIO CMOS Driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally. — — 7.5 32 — — mA mA Differential Input Voltage Swing Output Clocks (CKOUTn)1 Common Mode Common Mode Output Voltage Differential Output Resistance VDD = 1.8 V VDD = 3.3 V Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. Rev. 1.0 5 Si5322 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit VIL VDD = 1.71 V — — 0.5 V VDD = 2.25 V — — 0.7 V VDD = 2.97 V — — 0.8 V VDD = 1.89 V 1.4 — — V VDD = 2.25 V 1.8 — — V VDD = 3.63 V 2.5 — — V 2-Level LVCMOS Input Pins Input Voltage Low Input Voltage High VIH Input Low Current IIL — — 50 µA Input High Current IIH — — 50 µA Weak Internal Input Pull-up Resistor RPUP — 75 — k Weak Internal Input Pull-down Resistor RPDN — 75 — k Input Voltage Low VILL — — 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD — 0.55 x VDD V Input Voltage High VIHH 0.85 x VDD — — V Input Low Current IILL3 –20 — — µA Input Mid Current 3 –2 — 2 µA 3 — — 20 µA 3-Level Input Pins Input High Current IIMM IIHH Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 6 Rev. 1.0 Si5322 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit VOL IO = 2 mA VDD = 1.71 V — — 0.4 V IO = 2 mA VDD = 2.97 V — — 0.4 V IO = –2 mA VDD = 1.71 V VDD – 0.4 — — V IO = –2 mA VDD = 2.97 V VDD – 0.4 — — V RST = 0 –100 — 100 µA LVCMOS Output Pins Output Voltage Low Output Voltage High VOH Disabled Leakage Current IOZ Notes: 1. LVPECL outputs require nominal VDD > 2.5 V. 2. No overshoot or undershoot. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. V SIGNAL + Differential I/Os VICM , VOCM SIGNAL – VISE , VOSE (SIGNAL +) – (SIGNAL –) Differential Peak-to-Peak Voltage VID,VOD VICM, VOCM Single-Ended Peak-to-Peak Voltage t SIGNAL + VID = (SIGNAL+) – (SIGNAL–) SIGNAL – Figure 1. Voltage Characteristics 80% CKIN, CKOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics Rev. 1.0 7 Si5322 Table 3. AC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Units 19.44 — 707.35 MHz 40 — 60 % 2 — — ns — — 3 pF — — 11 ns 19.44 — 1050 MHz — — 212.5 MHz CMOS Output VDD = 1.71 Cload = 5 pF — — 8 ns CMOS Output VDD = 2.97 Cload = 5 pF — — 2 ns CKIN Input Pins Input Frequency Input Duty Cycle (Minimum Pulse Width) CKNF CKNDC Input Capacitance CKNCIN Input Rise/Fall Time CKNTRF Whichever is smaller (i.e., the 40%/60% limitation applies only to high clock frequencies) 20–80% See Figure 2 CKOUTn Output Pins Output Frequency (Output not configured for CMOS or disable) Maximum Output Frequency in CMOS Format CKOF CKOFMC Single-ended Output Rise/Fall (20–80%) CKOTRF Differential Output Rise/Fall Time CKOTRF 20 to 80 %, fOUT = 622.08 — 230 350 ps Output Duty Cycle Differential Uncertainty CKODC 100  Load Line to Line Measured at 50% Point (not for CMOS) — — ±40 ps tRSTMIN 1 — — µs CIN — — 3 pF — 25 — ns — 750 µs ps LVCMOS Input Pins Minimum Reset Pulse Width Input Capacitance LVCMOS Output Pins Rise/Fall Times LOSn Trigger Window tRF CLOAD = 20 pf See Figure 2 LOSTRIG From last CKIN to LOS tP_STEP After clock switch f3  128 kHz — 200 — — 0.05 0.1 dB JTOL BW determined by BWSEL[1:0] 5000/ BW — — ns pkpk SPSPUR Max spur @ n x f3 (n > 1, n x f3 < 100 MHz) — –93 –70 dBc tTEMP Max phase changes from – 40 to +85 ºC — 300 500 ps PLL Performance Output Clock Phase Change Closed Loop Jitter Peaking Jitter Tolerance Spurious Noise Phase Change due to Temperature Variation 8 JPK Rev. 1.0 Si5322 1.1. Three-Level (3L) Input Pins (No External Resistors) Si5322 VDD 75 k Iimm 75 k External Driver Figure 3. Three-Level Input Pins 1.2. Three-Level Input Pins (Example with External Resistors) V DD V DD Si5322 18 k 75 k 18 k 75 k 3L input current External Driver One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Figure 4. Three-Level Input Pins Table 4. Three-Level Input Pins1,2,3,4 Parameter Min Max Input Low Current –30 µA — Input Mid Current –11 µA –11 µA Input High Current — –30 µA Notes: 1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver using the external resistor values indicated in this example. In most designs, an external resistor voltage divider is recommended. 2. Resistor packs are only needed if the leakage current of the external driver exceeds the current specified in Table 2, Iimm. Any resistor pack may be used (e.g., Panasonic EXB-D10C183J). PCB layout is not critical. 3. If a pin is tied to ground or VDD, no resistors are needed. 4. If a pin is left open (no connect), no resistors are needed. Rev. 1.0 9 Si5322 Table 5. Performance Specifications1, 2, 3, 4 (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Jitter Generation fIN = fOUT = 622.08 MHz, LVPECL Output Format BW = 877 Hz JGEN 50 kHz–80 MHz — .47 — ps rms 12 kHz–20 MHz — .48 — ps rms 4 MHz–80 MHz — .23 — ps rms Phase Noise fIN = fOUT = 622.08 MHz LVPECL Output Format CKOPN 1 kHz offset — –90 — dBc/Hz 10 kHz offset — –113 — dBc/Hz 100 kHz offset — –118 — dBc/Hz 1 MHz offset — –132 — dBc/Hz Notes: 1. BWSEL [1:0] loop bandwidth settings provided in by DSPLLsim. 2. VDD = 3.3 V 3. TA = 85 °C 4. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-80%), LVPECL clock output. Table 6. Thermal Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air — 32 — ºC/W Thermal Resistance Junction to Case JC Still Air — 14 — ºC/W Parameter Table 7. Absolute Maximum Ratings Symbol Value Unit DC Supply Voltage VDD –0.5 to 3.8 V LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V CKNVIN 0 to VDD V Operating Junction Temperature TJCT –55 to 150 C Storage Temperature Range TSTG –55 to 150 C 2 kV ESD MM Tolerance; All pins except CKIN+/CKIN– 150 V ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN– 750 V ESD MM Tolerance; CKIN+/CKIN– 100 V Parameter CKINn Voltage Level Limits ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– Latch-Up Tolerance JESD78 Compliant Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 10 Rev. 1.0 Si5322 Phase Noise (dBc/Hz) 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 5. Typical Phase Noise Plot Table 8. Typical Jitter Data Jitter Bandwidth RMS Jitter (fs) OC-48, 12 kHz to 20 MHz 374 OC-192, 20 kHz to 80 MHz 388 OC-192, 4 MHz to 80 MHz 181 OC-192, 50 kHz to 80 MHz 377 Broadband, 800 Hz to 80 MHz 420 Rev. 1.0 11 Si5322 C4 1 µF System Power Supply C3 0.1 µF Ferrite Bead C2 0.1 µF VDD = 3.3 V CKIN1+ GND 130  VDD 130  C1 0.1 µF CKOUT1+ 0.1 µF + 100  CKIN1– 82  CKOUT1– 82  CKOUT2+ Input Clock Sources1 0.1 µF – Clock Outputs + 100  VDD = 3.3 V CKOUT2– 130  0.1 µF 0.1 µF – 130  CKIN2+ CKIN2– 82  82  Si5322 Manual/Automatic Clock Selection (L) 15 k VDD 15 k 15 k 15 k Clock Output 2 Disable/ Bypass Mode Control Reset CKIN_2 Loss of Signal FRQSEL[3:0]2 15 k VDD FRQTBL2 15 k VDD 15 k Signal Format Select C2B CS_CA3 VDD Frequency Select Bandwidth Select CKIN_1 Loss of Signal AUTOSEL2 Input Clock Select/ Active Clock Indicator Frequency Table Select C1B BWSEL[1:0]2 15 k SFOUT[1:0]2 VDD 15 k DBL2_BY2 15 k RST Notes: 1. Assumes differential LVEPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection. Figure 6. Si5322 Typical Application Circuit 12 Rev. 1.0 Si5322 2. Functional Description 2.1. Further Documentation The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, SDH STM-16/64 Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequencymultiplied clock outputs ranging from 19.44 to 1050 MHz. The two input clocks are at the same frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5322 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to look up valid Si5322 frequency translations. This utility can be downloaded from http://www.silabs.com/timing (click on Documentation). Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed information about the Si5322. Additional design support is available from Silicon Laboratories through your distributor. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from http://www.silabs.com/timing; click on Documentation. The Si5322 is recommended for applications in which the input clock is relatively low jitter and only clock multiplication is required. The Si5322 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5322 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 150 kHz to 1.5 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5322 monitors all input clocks for loss of signal and provides a LOS alarm when it detects a missing clock. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The Si5322 has two differential clock outputs. The electrical format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. Rev. 1.0 13 Si5322 CKOUT1– CKOUT1+ SFOUT1 VDD GND SFOUT0 CKOUT2– CKOUT2+ NC 3. Pin Descriptions: Si5322 36 35 34 33 32 31 30 29 28 RST 1 27 FRQSEL3 FRQTBL 2 26 FRQSEL2 C1B 3 25 FRQSEL1 C2B 4 VDD 5 GND 6 NC 7 GND 8 20 GND AUTOSEL 9 19 GND 24 FRQSEL0 GND Pad 23 BWSEL1 22 BWSEL0 21 CS_CA NC CKIN1– CKIN1+ VDD DBL2_BY CKIN2– CKIN2+ VDD VDD 10 11 12 13 14 15 16 17 18 Table 9. Si5322 Pin Descriptions Pin # 1 2 3 4 14 Pin Name RST FRQTBL C1B C2B I/O I I O O Signal Level Description LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5322 will perform an internal self-calibration. This pin has a weak pull-up. 3-Level Frequency Table Select. Selects SONET/SDH, datacom, or SONET/SDH to datacom frequency table. L = SONET/SDH. M = Datacom. H = SONET/SDH to Datacom. The pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. LVCMOS CKIN1 Loss of Signal. Active high loss-of-signal indicator for CKIN1. Once triggered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present. 1 = LOS on CKIN1. LVCMOS CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present. 1 = LOS on CKIN2. Rev. 1.0 Si5322 Table 9. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description 5, 10, 11, 15, 32 VDD VDD Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should be placed as close to device as is practical. 6, 8,19, 20, 31 GND GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. 3-Level Manual/Automatic Clock Selection. Three level input that selects the method of input clock selection to be used. L = Manual. M = Automatic non-revertive. H = Automatic revertive. The pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 9 12 13 14 16 17 AUTOSEL CKIN2+ CKIN2– DBL2_BY CKIN1+ CKIN1– I I I I Multi Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. 3-Level Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 enabled. M = CKOUT2 disabled. H = Bypass mode with CKOUT2 enabled. CMOS outputs do not support Bypass Mode. The pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Multi Clock Input 1. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. Rev. 1.0 15 Si5322 Table 9. Si5322 Pin Descriptions (Continued) Pin # 21 23 22 27 26 25 24 16 Pin Name CS_CA BWSEL1 BWSEL0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 I/O I/O I I Signal Level Description LVCMOS Input Clock Select/Active Clock Indicator. Input: If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CS input state. 0 = Select CKIN1. 1 = Select CKIN2. If configured as input, must be set high or low. Output: If automatic clock selection mode is chosen (AUTOSEL = M or H), this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both CKIN1 and CKIN2, indicating that the digital hold state has been entered, CA will indicate the last active clock that was used before entering the hold state. 0 = CKIN1 active input clock. 1 = CKIN2 active input clock. 3-Level Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and timing characteristics for these pins may be found in the Any-Frequency Precision Clock Family Reference Manual. These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 3-Level Multiplier Select. Three level inputs that select the input clock and clock multiplication ratio, depending on the FRQTBL setting. Consult the Any-Frequency Precision Clock Family Reference Manual or DSPLLsim configuration software for settings, both available for download at www.silabs.com/timing (click on Documentation). These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Rev. 1.0 Si5322 Table 9. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for both CKOUT1 and CKOUT2. Valid settings include LVPECL, LVDS, and CML. Also includes selections for CMOS mode, tristate mode, and tristate/sleep mode. SFOUT[1:0] 33 30 SFOUT0 SFOUT1 I 3-Level Signal Format HH Reserved HM LVDS HL CML MH LVPECL MM Reserved ML LVDS—Low Swing LH CMOS LM Disabled LL Reserved CMOS outputs do not support Bypass Mode. These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. 34 35 CKOUT2– CKOUT2+ O Multi Clock Output 2. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 29 28 CKOUT1– CKOUT1+ O Multi Clock Output 1. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 7, 18, 36 NC — — No Connect. These pins must be left unconnected for normal operation. Supply Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. GND PAD GND GND Rev. 1.0 17 Si5322 4. Ordering Guide Ordering Part Number Package ROHS6, Pb-Free Temperature Range Si5322-C-GM* 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C *Note: Not recommended for new designs. For alternatives, see the Si533x family. 18 Rev. 1.0 Si5322 5. Package Outline: 36-Pin QFN Figure 7 illustrates the package details for the Si5322. Table 10 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-lead (QFN) Table 10. Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05  — — 12º b 0.18 0.25 0.30 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 D D2 L 6.00 BSC 3.95 4.10 4.25 Min Nom Max 0.50 0.60 0.70 e 0.50 BSC ddd — — 0.10 E 6.00 BSC eee — — 0.05 E2 3.95 4.10 4.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.0 19 Si5322 6. Land Pattern: 36-Pin QFN Figure 8. 36-Pin QFN Land Pattern 20 Rev. 1.0 Si5322 Table 11. PCB Land Pattern Dimensions Dimension MIN MAX e 0.50 BSC. E 5.42 REF. D 5.42 REF. E2 4.00 4.20 D2 4.00 4.20 GE 4.53 — GD 4.53 — X — 0.28 Y 0.89 REF. ZE — 6.31 ZD — 6.31 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.0 21 Si5322 7. Top Marking 7.1. Si5322 Top Marking (QFN)   7.2. Top Marking Explanation Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5322 Customer Part Number See Ordering Guide for options Line 2 Marking: C-GM C = Product Revision G = Temperature Range –40 to 85 °C (RoHS6) M = QFN Package Line 3 Marking: YYWWRF YY = Year WW = Work Week R = Die Revision F = Internal code Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter Lower-Left Justified XXXX Internal Code 22 Rev. 1.0 Si5322 DOCUMENT CHANGE LIST Revision 0.44 to Revision 0.45  Condensed format. Revision 0.45 to Revision 0.46      Removed references to latency control, INC, and DEC in figures and text. Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 5. Added Figure 1, “Typical Phase Noise Plot,” on page 4. Updated “3. Pin Descriptions: Si5322”. Added “6. Land Pattern: 36-Pin QFN”. Revision 0.46 to Revision 0.47 Removed Figure 1. “Typical Phase Noise Plot.”  Changed pins 11 and 15 from NC to VDD in “3. Pin Descriptions: Si5322”.  Revision 0.47 to Revision 0.5         Changed 1.8 V operating range to ±5%. Updated Table 1 on page 4. Updated Table 2 on page 5. Updated Figure 6 on page 12 to add pull-up/pulldown resistors for 3-level inputs. Added figure and table on page 11. Updated "2. Functional Description" on page 13. Clarified "3. Pin Descriptions: Si5322" on page 14. Updated SFOUT values. Revision 0.5 to Revision 0.51        Changed “any-rate” to “any-frequency” throughout. Expanded spec tables 1 through 7. Updated Table 5 on page 10. Added "7. Top Marking" on page 22. Added clarification that CMOS output format is not available in PLL bypass mode. Updated "4. Ordering Guide" on page 18. Removed note from "3. Pin Descriptions: Si5322" on page 14. Revision 0.51 to Revision 1.0   Updated logo. Transitioned to full production. Rev. 1.0 23 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required, or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications. Trademark Information Silicon Laboratories Inc.®, Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri DMS, ZWave®, and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective holders. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA http://www.silabs.com