SI5325

Si5325 P R E L I M I N A R Y D A TA S H E E T µP-P R O G R A M M A B L E P R E C I S I O N C L O C K M U L T I P L I E R Description The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5325 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5325 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325 is ideal for providing clock multiplication in high performance timing applications. Features Generates any frequency from 10 to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 10 to 710 MHz Low jitter clock outputs w/jitter generation as low as 0.6 ps rms (30 kHz–1.3 MHz) Integrated loop filter with selectable loop bandwidth (150 kHz to 2 MHz) Dual clock inputs w/manual or automatically controlled hitless switching Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) LOS, FOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Optical modules Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement CKIN1 ÷ N31 ÷ NC1 CKOUT1 ® CKIN2 ÷ N32 DSPLL ÷ NC2 ÷ N2 CKOUT2 Alarms Signal Detect Control VDD (1.8, 2.5, or 3.3 V) GND I2C/SPI Port Device Interrupt Clock Select Preliminary Rev. 0.26 7/07 Copyright © 2007 by Silicon Laboratories Si5325 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5325 Table 1. Performance Specifications (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol TA VDD Test Condition Min –40 2.97 2.25 1.62 Typ 25 3.3 2.5 1.8 251 Max 85 3.63 2.75 1.98 279 Unit ºC V V V mA Supply Current IDD fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output CKOUT2 disabled fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output CKOUT2 disabled Tristate/Sleep Mode — — — 217 204 243 234 mA mA — — 10 10 970 1213 194 TBD — — — — 220 TBD 710 945 1134 1417 mA mA MHz MHz Input Clock Frequency (CKIN1, CKIN2) Output Clock Frequency (CKOUT1, CKOUT2) CKF CKOF Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult Silicon Laboratories configuration software DSPLLsim at www.silabs.com/timing to determine PLL divider settings for a given input frequency/clock multiplication ratio combination. Input Clocks (CKIN1, CKIN2) Differential Voltage Swing Common Mode Voltage CKNDPP CKNVCM 1.8 V ±10% 2.5 V ±10% 3.3 V ±10% Rise/Fall Time Duty Cycle CKNTRF CKNDC 20–80% Whichever is less 40 50 Output Clocks (CKOUT1, CKOUT2) Common Mode Differential Output Swing Single Ended Output Swing VOCM VOD VSE LVPECL 100 Ω load line-to-line VDD – 1.42 1.1 0.5 — — — VDD – 1.25 1.9 0.93 V V V 0.25 0.9 1.0 1.1 — — — — — — — 1.9 1.4 1.7 1.95 11 60 — VPP V V V ns % ns Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.26 S i5325 Table 1. Performance Specifications (Continued) (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Rise/Fall Time Duty Cycle PLL Performance Jitter Generation Symbol CKOTRF CKODC JGEN Test Condition 20–80% Min — 45 Typ 230 — 0.6 Max 350 55 TBD Unit ps % ps rms fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz 800 Hz–80 MHz — — — — — — — — — — — 0.6 TBD 0.05 TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD ps rms ps rms dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Jitter Transfer Phase Noise JPK CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient SPSUBH SPSPUR Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air θJA — 38 — ºC/W Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 3.6 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V C C kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.26 3 S i5325 C4 1 µF System Power Supply C3 0.1 µF Ferrite Bead C2 0.1 µF C1 0.1 µF VDD = 3.3 V GND VDD 130 Ω 130 Ω CKIN1+ CKIN1– CKOUT1+ 0.1 µF 100 Ω + CKOUT1– 0.1 µF – Clock Outputs 82 Ω 82 Ω CKOUT2+ 0.1 µF 100 Ω CKOUT2– 130 Ω CKIN2+ CKIN2– 0.1 µF – + Input Clock Sources* 130 Ω VDD = 3.3 V Si5325 INT_C1B C2B Interrupt/CKIN_1 Invalid Indicator CKIN_2 Invalid Indicator 82 Ω 82 Ω Control Mode (L) Reset CMODE RST A[2:0] SDA SCL Serial Port Address Serial Data Serial Clock I2C Interface *Note: Assumes differential LVPECL termination (3.3 V) on clock inputs. Figure 1. Si5325 Typical Application Circuit (I2C Control Mode) C4 1 µF System Power Supply C3 0.1 µF Ferrite Bead C2 0.1 µF C1 0.1 µF VDD = 3.3 V GND VDD 130 Ω 130 Ω CKIN1+ CKIN1– CKOUT1+ 0.1 µF 100 Ω + CKOUT1– 0.1 µF – Clock Outputs 82 Ω 82 Ω CKOUT2+ 0.1 µF 100 Ω CKOUT2– 130 Ω CKIN2+ CKIN2– 0.1 µF – + Input Clock Sources* 130 Ω VDD = 3.3 V Si5325 INT_C1B C2B Interrupt/CLKIN_1 Invalid Indicator CLKIN_2 Invalid Indicator 82 Ω 82 Ω Control Mode (H) Reset CMODE RST SS SDO SDI SCLK Slave Select Serial Data Out Serial Data In Serial Clock SPI Interface *Note: Assumes differential LVPECL termination (3.3 V) on clock inputs. Figure 2. Si5325 Typical Application Circuit (SPI Control Mode) 4 Preliminary Rev. 0.26 S i5325 1. Functional Description The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent, synchronous clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5325 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5325 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from www.silabs.com/timing. The Si5325 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5325 PLL loop bandwidth is digitally programmable and supports a range from 30 kHz to 1.3 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The Si5325 has two differential clock outputs. The electrical format of each clock output is independently programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. In addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. The resolution varies from 800 ps to 2.2 ns depending on the PLL divider settings. Consult the DSPLLsim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ratio combination. For systemlevel debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. 1.1. Further Documentation Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5325. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing. Preliminary Rev. 0.26 5 S i5325 2. Pin Descriptions: Si5325 CLKOUT1– CLKOUT2+ CMODE CLKOUT2– CLKOUT1+ 27 SDI 26 A2_SS 25 A1 24 A0 23 SDA_SDO 22 SCL 21 CS_CA 20 NC 19 NC 10 11 12 13 14 15 16 17 18 CLKIN2+ CLKIN1+ VDD VDD NC CLKIN2– VDD CLKIN1– NC VDD GND NC 36 35 34 33 32 31 30 29 28 RST NC INT_C1B C2B 1 2 3 4 VDD 5 GND NC GND 6 7 8 GND Pad NC 9 Pin numbers are preliminary and subject to change. Pin # 1 Pin Name RST I/O I Signal Level LVCMOS Table 3. Si5325 Pin Descriptions Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5325 will perform an internal self-calibration. This pin has a weak pull-up. No Connect. This pin must be left unconnected for normal operation. Interrupt/CKIN1 Invalid Indicator. This pin functions as a device interrupt output or an alarm output for CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. If used as an alarm output, the pin functions as a LOS (and optionally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and INT_PIN = 0. 0 = CKIN1 present. 1 = LOS (FOS) on CKIN1. The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates. 2, 7, 9, 14, 18, 19, 20, 30, 33 3 NC — — INT_C1B O LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. 6 Preliminary Rev. 0.26 NC S i5325 Table 3. Si5325 Pin Descriptions (Continued) Pin # 4 Pin Name C2B I/O O Signal Level LVCMOS Description CKIN2 Invalid Indicator. This pin functions as a LOS (and optionally FOS) alarm indicator for CKIN2 if CK2_BAD_PIN = 1. 0 = CKIN2 present. 1 = LOS (FOS) on CKIN2. The active polarity can be changed by CK_BAD_POL. If CK2_BAD_PIN = 0, the pin tristates. Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following Vdd pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should be placed as close to device as is practical. Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. Input frequency range is 10 to 710 MHz. Clock Input 1. Differential input clock. This input can also be driven with a single-ended signal. Input frequency range is 10 to 710 MHz. Input Clock Select/Active Clock Indicator. In manual clock selection mode, this pin functions as the manual input clock selector if the CKSEL_PIN is set to 1. 0 = Select CKIN1. 1 = Select CKIN2. If CKSEL_PIN = 0, the CKSEL_REG register bit controls this function and this input tristates. In automatic clock selection mode, this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both clocks, CA will indicate the last active clock that was used before entering the digital hold state. The CK_ACTV_PIN register bit must be set to 1 to reflect the active clock status to the CA output pin. 0 = CKIN1 active input clock. 1 = CKIN2 active input clock. If CK_ACTV_PIN = 0, this pin will tristate. The CA status will always be reflected in the CK_ACTV_REG read only register bit. 5, 10, 11, 15, 32 VDD VDD Supply 6, 8, 31 GND GND Supply 12 13 16 17 21 CKIN2+ CKIN2– CKIN1+ CKIN1– CS_CA I Multi I Multi I/O LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. Preliminary Rev. 0.26 7 S i5325 Table 3. Si5325 Pin Descriptions (Continued) Pin # 22 Pin Name SCL I/O I Signal Level LVCMOS Description Serial Clock/Serial Clock. This pin functions as the serial clock input for both SPI and I2C modes. Serial Data. In I2C control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output. Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. In SPI control mode (CMODE = 1), these pins are ignored. Serial Port Address/Slave Select. In I2C control mode (CMODE = 0), this pin functions as a hardware controlled address bit. In SPI control mode (CMODE = 1), this pin functions as the slave select input. Serial Data In. In I2C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. Output Clock 1. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Output Clock 2. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT2_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Control Mode. Selects I2C or SPI control mode for the Si5325. 0 = I2C Control Mode. 1 = SPI Control Mode. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. 23 SDA_SDO I/O LVCMOS 25 24 A1 A0 I LVCMOS 26 A2_SS I LVCMOS 27 SDI I LVCMOS 29 28 CKOUT1– CKOUT1+ O Multi 34 35 CKOUT2– CKOUT2+ O Multi 36 CMODE I LVCMOS GND PAD GND GND Supply Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. 8 Preliminary Rev. 0.26 S i5325 3. Ordering Guide Ordering Part Number Si5325A-B-GM Output Clock Frequency Range 10–945 MHz 970–1134 MHz 1.213–1.417 GHz 10–808 MHz 10–346 MHz Package 36-Lead 6 x 6 mm QFN Temperature Range –40 to 85 °C Si5325B-B-GM Si5325C-B-GM 36-Lead 6 x 6 mm QFN 36-Lead 6 x 6 mm QFN –40 to 85 °C –40 to 85 °C Preliminary Rev. 0.26 9 S i5325 4. Package Outline: 36-Pin QFN Figure 3 illustrates the package details for the Si5325. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 36-Pin Quad Flat No-lead (QFN) Table 4. Package Dimensions Symbol Min A A1 b D D2 e E E2 3.95 3.95 0.80 0.00 0.18 Millimeters Nom 0.85 0.01 0.23 6.00 BSC 4.10 0.50 BSC 6.00 BSC 4.10 4.25 4.25 Max 0.90 0.05 0.30 L θ aaa bbb ccc ddd eee Symbol Min 0.50 — — — — — — Millimeters Nom 0.60 — — — — — — Max 0.75 12º 0.10 0.10 0.05 0.10 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 10 Preliminary Rev. 0.26 S i5325 5. Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Preliminary Rev. 0.26 11 S i5325 Table 5. PCB Land Pattern Dimensions Dimension e E D E2 D2 GE GD X Y ZE ZD — — 4.00 4.00 4.53 4.53 — 0.89 REF. 6.31 6.31 MIN 0.50 BSC. 5.42 REF. 5.42 REF. 4.20 4.20 — — 0.28 MAX Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 12 Preliminary Rev. 0.26 S i5325 DOCUMENT CHANGE LIST Revision 0.23 to Revision 0.24 Clarified that the two outputs have a common, higher frequency source on page 1. Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Added Figure 1, “Typical Phase Noise Plot,” on page 4. Updated “2. Pin Descriptions: Si5325”. Removed references to latency control, INC, and DEC. Changed font for register names to underlined italics. Updated "3. Ordering Guide" on page 9. Added “5. Recommended PCB Layout”. Revision 0.24 to Revision 0.25 Updated Section "2. Pin Descriptions: Si5325" on page 6. Revision 0.25 to Revision 0.26 Removed Figure 1. “Typical Phase Noise Plot.” Changed pins 11 and 15 from NC to VDD in “2. Pin Descriptions: Si5325”. Preliminary Rev. 0.26 13 S i5325 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 14 Preliminary Rev. 0.26