SI823X

Si823x 0 . 5 A ND 4 . 0 A MP I S O D R I V E R S ( 2.5 A ND 5 K V RMS ) Features Pin Assignments      Two completely isolated drivers  60 ns maximum propagation in one package delay Up to 5 kVRMS input-to-output  Independent HS and LS inputs or PWM input versions isolation Up to 1500 VDC peak driver-to Transient immunity >30 kV/µs driver differential voltage  Overlap protection and HS/LS and dual driver versions programmable dead time Up to 8 MHz switching frequency  Operating temperature range 0.5 A peak output (Si8230/1/2) –40 to +125 °C 4.0 A peak output (Si8233/4/5/6)  UL/VDE/CSA approval  RoHS-compliant SOIC-16 (Wide) VIA VIB VDDI GNDI DISABLE DT NC VDDI 1 2 3 4 5 6 7 8 16 15 14 VDDA VOA GNDA NC NC VDDB VOB GNDB Si8230 Si8233 13 12 11 10 9 Applications  SOIC-16 (Narrow) VIA 1 2 3 4 5 6 7 8 16 15 14 VDDA VOA GNDA NC NC VDDB VOB GNDB Power delivery systems  Motor control systems  Isolated dc-dc power supplies  Lighting control systems  Plasma displays  Solar and industrial inverters VIB VDDI GNDI DISABLE Si8230 13 Si8233 12 11 10 9 Description The Si823x isolated driver family combines two independent, isolated drivers into a single package. The Si8230/1/3/4 are high-side/low-side drivers, and the Si8232/5/6 are dual drivers. Versions with peak output currents of 0.5 A (Si8230/1/2) and 4.0 A (Si8233/4/5/6) are available. All drivers operate with a maximum supply voltage of 24 V. The Si823x drivers utilize Silicon Labs' proprietary silicon isolation technology, which provides up to 5 kVRMS withstand voltage per UL1577, and fast 60 ns propagation times. Driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. The TTL level compatible inputs with >400 mV hysteresis are available in individual control input (Si8230/2/3/5/6) or PWM input (Si8231/4) configurations. High integration, low propagation delay, small installed size, flexibility, and cost-effectiveness make the Si823x family ideal for a wide range of isolated MOSFET/IGBT gate drive applications. DT NC VDDI LGA-14 (5 x 5 mm) GNDI VIA VIB VDDI DISABLE DT VDDI 1 2 3 4 5 6 7 14 13 12 VDDA VOA GNDA NC VDDB VOB GNDB Si8230 Si8233 11 10 7 8 Patents Pending Safety Approval   UL 1577 recognized Up  VDE certification conformity IEC EN to 5000 Vrms for 1 minute CSA component notice 5A approval IEC 60747-5-2 (VDE 0884 Part 2) 60950 (reinforced insulation) (Pending) 60950, 61010, 60601 (reinforced insulation) Rev. 0.3 4/10 Copyright © 2010 by Silicon Laboratories Si823x This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i823x Block Diagrams VIA VDDA PWM VDDA VIA VDDA Isolation Isolation DT VOA GNDA DT VOA GNDA Isolation VOA GNDA VDDI UVLO Overlap Protection, Programmable Dead Time, Control Gating VDDB VDDI UVLO Programmable Dead Time, Control Gating VDDB VDDI UVLO Control Gating VDDB Isolation Isolation DISABLE VIB GNDI VOB GNDB DISABLE VOB GNDB DISABLE Isolation VOB GNDB VIB GNDI GNDI Si8230/3 Si8231/4 Si8232/5/6 2 Rev. 0.3 S i823x TABLE O F C ONTENTS Section Page 1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.2. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1. Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.3. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5.5. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.7. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1. RF, Magnetic, and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . 28 7. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1. High-Side / Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .30 8. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 11. Land Pattern: Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12. Package Outline: Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13. Land Pattern: Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 14. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .48 17. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Rev. 0.3 3 S i823x 1. Top-Level Block Diagrams VDDI VIA ISOLATION VDDA VOA UVLO GNDA DT DT CONTROL & OVERLAP PROTECTION VDDI VDDI UVLO VDDI VDDB ISOLATION VOB UVLO GNDB DISABLE VIB GNDI Si8230/3 Figure 1. Si8230/3 Two-Input High-Side / Low-Side Isolated Drivers VDDI PWM LPWM ISOLATION VDDA VOA UVLO GNDA DT VDDI VDDI UVLO DT CONTROL & OVERLAP PROTECTION VDDI VDDB ISOLATION VOB UVLO GNDB DISABLE LPWM GNDI Si8231/4 Figure 2. Si8231/4 Single-Input High-Side / Low-Side Isolated Drivers 4 Rev. 0.3 S i823x VDDI VDDA ISOLATION VIA VOA UVLO GNDA VDDI VDDI UVLO VDDI VDDB ISOLATION DISABLE VOB UVLO GNDB VIB GNDI Si8232/5/6 Figure 3. Si8232/5/6 Dual Isolated Drivers Rev. 0.3 5 S i823x 2. Electrical Specifications Table 1. Electrical Characteristics1 4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter DC Specifications Input-side Power Supply Voltage Driver Supply Voltage Symbol Test Conditions Min Typ Max Units VDDI Voltage between VDDA and VDDA, VDDB GNDA, and VDDB and GNDB (See “9. Ordering Guide” ) Si8230/32/33/35/36 IDDI(Q) Si8231/34 IDDA(Q), IDDB(Q) IDDI IDDO IVIA, IVIB, IPWM IDISABLE VIH VIL VIHYST VOAH, VOBH VOAL, VOBL IOA(SCL), IOB(SCL) IOA(SCH), IOB(SCH) RON(SINK) IOA, IOB = –1 mA IOA, IOB = 1 mA Si8230/1/2, Figure 4 Si8233/4/5/6, Figure 4 Si8230/1/2, Figure 5 Si8233/4/5/6, Figure 5 Si8230/1/2 Current per channel PWM freq = 500 kHz PWM freq = 500 kHz 4.5 — 5.5 V 6.5 — — — — — –10 –10 2.0 — 400 (VDDA /VDDB) — 0.04 — — — — — — — — — — 2 2 — 2.5 3.6 — — — — 450 — — 0.5 4.0 0.25 2.0 5.0 1.0 15 2.7 24 3 3 3.0 — — +10 +10 — 0.8 — — 0.04 — — V mA mA mA mA mA µA dc µA dc V V mV V V Input Supply Quiescent Current Output Supply Quiescent Current Input Supply Active Current Output Supply Active Current Input Pin Leakage Current Input Pin Leakage Current Logic High Input Threshold Logic Low Input Threshold Input Hysteresis Logic High Output Voltage Logic Low Output Voltage Output Short-circuit Pulsed Sink Current Output Short-circuit Pulsed Source Current Output Sink Resistance A — — — — — —  Si8233/4/5/6 Si8230/1/2 Output Source Resistance RON(SOURCE) Si8233/4/5/6 Notes: 1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices. 2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only). 3. The largest RDT resistor that can be used is 220 k. 6 Rev. 0.3 S i823x Table 1. Electrical Characteristics1 (Continued) 4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter VDDI Undervoltage Threshold VDDI Undervoltage Threshold VDDI Lockout Hysteresis VDDA, VDDB Undervoltage Threshold 5 V threshold 8 V threshold 10 V threshold 12.5 V threshold VDDA, VDDB Undervoltage Threshold 5 V threshold 8 V threshold 10 V threshold 12.5 V threshold VDDA, VDDB Lockout hysteresis VDDA, VDDB Lockout hysteresis VDDA, VDDB Lockout hysteresis AC Specifications Symbol VDDIUV+ VDDIUV– VDDIHYS VDDAUV+, VDDBUV+ Test Conditions VDDI rising VDDI falling Min 3.60 3.30 — Typ 4.0 3.70 250 Max 4.45 4.15 — Units V V mV VDDA, VDDB rising See Figure 36 on page 25. See Figure 37 on page 25. See Figure 38 on page 25. See Figure 39 on page 25. 5.20 7.50 9.60 12.4 5.80 8.60 11.1 13.8 6.30 9.40 12.2 14.8 V V V V VDDAUV–, VDDBUV– VDDA, VDDB falling See Figure 36 on page 25. See Figure 37 on page 25. See Figure 38 on page 25. See Figure 39 on page 25. 4.90 7.20 9.40 11.6 — — — 5.52 8.10 10.1 12.8 280 600 1000 6.0 8.70 10.9 13.8 — — — V V V V mV mV mV VDDAHYS, VDDBHYS VDDAHYS, VDDBHYS VDDAHYS, VDDBHYS UVLO voltage = 5 V UVLO voltage = 8 V UVLO voltage = 10 V or 12.5 V Minimum Pulse Width Propagation Delay tPHL, tPLH CL = 200 pF — — 10 30 — 60 ns ns Pulse Width Distortion |tPLH - tPHL| Minimum Overlap Time2 Programmed Dead Time3 PWD TDD DT Figure 41, RDT = 6 k tR,tF CL = 200 pF (Si8230/1/2) CL = 200 pF (Si8233/4/5/6) DT = VDDI, No-Connect Figure 41, RDT = 100 k — — — — — — — 0.4 900 70 — — 5.60 — — — 12 20 ns ns ns ns ns ns Output Rise and Fall Time Notes: 1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices. 2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only). 3. The largest RDT resistor that can be used is 220 k. Rev. 0.3 7 S i823x Table 1. Electrical Characteristics1 (Continued) 4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C Parameter Shutdown Time from Disable True Restart Time from Disable False Device Start-up Time Common Mode Transient Immunity Symbol tSD tRESTART tSTART CMTI Test Conditions Min — — Typ — — 5 50 Max 60 60 7 — Units ns ns µs kV/µs Time from VDD_ = VDD_UV+ to VOA, VOB = VIA, VIB VIA, VIB, PWM = VDDI or 0 V — 30 Notes: 1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices. 2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only). 3. The largest RDT resistor that can be used is 220 k. 8 Rev. 0.3 S i823x 2.1. Test Circuits Figures 4 and 5 depict sink current and source current test circuits. VDDA = VDDB = 15 V VDDI (5 V) INPUT IN_ VDD Si823x OUT_ SCHOTTKY VSS 1 µF 100 µF 5V 10 + _ Measure 50 ns 1 µF CER 10 µF EL RSNS 0.1 VDDI GND 200 ns INPUT WAVEFORM Figure 4. Sink Current Test Circuit VDDA = VDDB = 15 V VDDI (5 V) INPUT IN_ VDD Si823x OUT_ SCHOTTKY VSS 1 µF 100 µF 5V 10 + _ Measure 50 ns 1 µF CER 10 µF EL RSNS 0.1 VDDI GND 200 ns INPUT WAVEFORM Figure 5. Source Current Test Circuit Rev. 0.3 9 S i823x Table 2. Absolute Maximum Ratings1 Parameter Storage Temperature2 Ambient Temperature under Bias Input-side Supply Voltage Driver-side Supply Voltage Voltage on any pin with respect to ground Output Drive Current per channel Lead Solder Temperature (10 sec.) Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 Maximum Isolation (Output to Output) (1 sec) WB SOIC-16 Maximum Isolation (Input to Output) (1 sec) NB SOIC-16 Maximum Isolation (Output to Output) (1 sec) NB SOIC-16 Maximum Isolation (Input to Output) (1 sec) 14 LD LGA without thermal pad Maximum Isolation (Output to Output) (1 sec) 14 LD LGA without thermal pad Maximum Isolation (Input to Output) (1 sec) 14 LD LGA with thermal pad Maximum Isolation (Output to Output) (1 sec) 14 LD LGA with thermal pad Symbol TSTG TA VDDI VDDA, VDDB VIN IO Min –65 –40 –0.6 –0.6 –0.5 — — — — — — — — — — Typ — — — — — — — — — — — — — — — Max +150 +125 6.0 30 VDD + 0.5 10 260 6500 2500 4250 2500 3850 650 1850 0 Units °C °C V V V mA °C VRMS VRMS VRMS VRMS VRMS VRMS VRMS VRMS Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VDE certifies storage temperature from –40 to 150 °C. Table 3. Regulatory Information* CSA The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. VDE The Si823x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si823x is certified under UL1577 component recognition program. For more details, see File E257455. *Note: Regulatory Certifications apply to 1.5 kVRMS rated devices which are production tested to 1.8 kVRMS for 1 sec. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. For more information, see "9.Ordering Guide" on page 37. 10 Rev. 0.3 S i823x Table 4. Insulation and Safety-Related Specifications Value Parameter Symbol Test Condition 14 LD NBSOIC-16 14 LD WBSOIC-16 LGA w/ Unit LGA WBSOIC-16 5 kVRMS Pad 2.5 kVRMS 2.5 kVRMS 1.5 kVRMS 8.0 8.0 0.014 DIN IEC 60112/VDE 0303 Part 1 4.01 4.01 0.014 3.5 3.5 0.014 1.75 1.75 0.014 mm mm mm Nominal Air Gap (Clearance)1 Nominal External Tracking (Creepage)1 Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Resistance (Input-Output)2 Capacitance (Input-Output)2 Input Capacitance3 L(1O1) L(1O2) CTI >175 1012 >175 1012 1.4 4.0 >175 1012 1.4 4.0 >175 1012 1.4 4.0 V  pF pF RIO CIO CI f = 1 MHz 1.4 4.0 Notes: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in “10. Package Outline: 16-Pin Wide Body SOIC” , “12. Package Outline: Narrow Body SOIC” , “14. Package Outline: 14 LD LGA (5 x 5 mm)” , and “16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)” . VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC 16 and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1-7, 14 LD LGA) are shorted together to form the first terminal and pins 9–16 (8-14, 14 LD LGA) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Table 5. IEC 60664-1 (VDE 0884 Part 2) Ratings Specification Parameter Test Conditions WB SOIC-16 IIIa I-IV I-IV I-III I-III NB SOIC-16 IIIa I-IV I-III I-II I-II 14 LD LGA IIIa I-IV I-III I-II I-II 14 LD LGA w/ Pad IIIa I-IV I-III I-II I-I Basic Isolation Group Material Group Rated Mains Voltages < 150 VRMS Installation Classification Rated Mains Voltages < 300 VRMS Rated Mains Voltages < 400 VRMS Rated Mains Voltages < 600 VRMS Rev. 0.3 11 S i823x Table 6. IEC 60747-5-2 Insulation Characteristics* Characteristic Parameter Maximum Working Insulation Voltage Symbol Test Condition WB SOIC-16 891 Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Method b1 (VIORM x 1.875 = V PR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS VTR NB SOIC-16 14 LD LGA 14 LD LGA w/ Pad 560 373 Unit VIORM V peak 1590 896 597 Input to Output Test Voltage VPR 1375 1050 700 V peak 1018 672 448 6000 2 >109 4000 2 >109 2650 2 >109 V peak  *Note: The Si823x is suitable for basic electrical isolation within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si823x provides a climate classification of 40/125/21. 12 Rev. 0.3 S i823x Table 7. IEC Safety Limiting Values1 Parameter Case Temperature Symbol TS JA = 100 °C/W (WB SOIC-16), 105 °C/W (NB SOIC-16, 14 LD LGA), 50 °C/W (14 LD LGA w/ Pad) VDDI = 5.5 V, VDDA = VDDB= 24 V, TJ = 150 °C, TA = 25 °C Test Condition WB SOIC-16 150 NB SOIC-16 150 14 LD LGA 150 14 LD LGA w/ Pad 150 Unit °C Safety Input Current IS 50 50 50 100 mA Device Power Dissipation2 PD 1.2 1.2 1.2 1.2 W Notes: 1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 6. 2. The Si823x is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square wave. Rev. 0.3 13 S i823x Table 8. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Symbol JA WB SOIC-16 100 NB SOIC-16 105 14 LD LGA 105 14 LD LGA w/ Pad 50 Unit °C/W Safety-Limiting Current (mA) 60 50 40 30 20 10 0 0 50 100 150 Case Temperature (ºC) 200 VDDI = 5.5 V VDDA, VDDB = 24 V Figure 6. WB SOIC-16, NB SOIC-16, 14 LD LGA Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 120 100 80 60 40 20 0 0 50 100 150 Case Temperature (ºC) 200 VDDI = 5.5 V VDDA, VDDB = 24 V Figure 7. 14 LD LGA with Pad Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 14 Rev. 0.3 S i823x 2.2. Theory of Operation The operation of an Si823x channel is analogous to that of an opto coupler and gate driver, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si823x channel is shown in Figure 8. Transmitter RF OSCILLATOR Receiver Driver VDD A Dead time control MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR 0.5 to 4 A peak B Gnd Figure 8. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 9 for more details. Input Signal Modulation Signal Output Signal Figure 9. Modulation Scheme Rev. 0.3 15 S i823x 3. Typical Operating Characteristics (0.5 Amp) The typical performance characteristics depicted in Figures 10 through 21 are for information purposes only. Refer to Table 1 on page 6 for actual specification limits. 10 8 Rise/Fall Time (ns) VDDA Supply Current (mA) 7 6 5 4 3 2 1 0 9 14 19 24 VDDA Supply Voltage (V) 50 kHz Duty Cycle = 50% CL = 100 pF 1 Channel Switching 1MHz 500kHz 100kHz Tfall 6 4 2 0 9 12 15 18 21 24 VDDA Supply (V) Trise VDD=12V, 25°C CL = 100 pF Figure 10. Rise/Fall Time vs. Supply Voltage 30 Figure 13. Supply Current vs. Supply Voltage 5 Propagation Delay (ns) 25 H-L 20 L-H 15 VDD=12V, 25°C CL = 100 pF 10 9 12 15 18 21 24 VDDA Supply (V) Supply Current (mA) 4 3 2 1 -50 0 50 Temperature (°C) 100 VDDA = 15V, f = 250kHz, CL = 0 pF Duty Cycle = 50% 2 Channels Switching Figure 11. Propagation Delay vs. Supply Voltage Figure 14. Supply Current vs. Temperature 40 35 Trise 4 VDDA Supply Current (mA) 3.5 3 2.5 2 1.5 Duty Cycle = 50% CL = 0 pF 1 Channel Switching Rise/Fall Time (ns) 30 25 20 15 10 5 0 0.0 0.5 1MHz Tfall 500kHz 100kHz 50 kHz VDD=12V, 25°C 1.0 Load (nF) 1.5 2.0 1 9 14 19 24 VDDA Supply Voltage (V) Figure 15. Rise/Fall Time vs. Load Figure 12. Supply Current vs. Supply Voltage 16 Rev. 0.3 S i823x 50 45 Propagation Delay (ns) 4 3.75 Source Current (A) 3.5 3.25 3 2.75 2.5 2.25 VDD=12V, Vout=VDD-5V 10 15 20 25 40 35 30 25 20 15 10 0.0 0.5 VDD=12V, 25°C 1.0 Load (nF) 1.5 2.0 L-H H-L 2 Supply Voltage (V) Figure 16. Propagation Delay vs. Load 30 Figure 19. Output Source Current vs. Supply Voltage 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 -40 Propagation Delay (ns) 25 L-H 20 Sink Current (A) H-L 15 VDD=12V, Load = 200pF -40 -20 0 20 40 60 80 100 120 10 VDD=12V, Vout=5V -10 20 50 80 110 Temperature (°C) Figure 17. Propagation Delay vs. Temperature 9 3.5 8 Sink Current (A) 7 6 5 VDD=12V, Vout=5V 4 10 12 14 16 18 20 22 24 Supply Voltage (V) Source Current (A) 3.25 3 2.75 2.5 2.25 2 -40 Temperature (°C) Figure 20. Output Sink Current vs. Temperature VDD=12V, Vout=VDD-5V -10 20 50 80 110 Figure 18. Output Sink Current vs. Supply Voltage Temperature (°C) Figure 21. Output Source Current vs. Temperature Rev. 0.3 17 S i823x 4. Typical Operating Characteristics (4.0 Amp) The typical performance characteristics depicted in Figures 22 through 33 are for information purposes only. Refer to Table 1 on page 6 for actual specification limits. 10 8 Rise/Fall Time (ns) Tfall 6 Trise 4 2 0 9 12 15 18 21 24 VDDA Supply (V) Supply Current (mA) VDDA Supply Current (mA) 14 12 10 8 6 4 2 0 9 Duty Cycle = 50% CL = 100 pF 1 Channel Switching 1MHz 500kHz 100kHz 50 kHz 14 19 24 VDD=12V, 25°C CL = 100 pF VDDA Supply Voltage (V) Figure 25. Supply Current vs. Supply Voltage 10 8 6 4 2 0 -50 0 50 Temperature (°C) 100 VDDA = 15V, f = 250kHz, CL = 0 pF Duty Cycle = 50% 2 Channels Switching Figure 22. Rise/Fall Time vs. Supply Voltage 30 Propagation Delay (ns) 25 L-H 20 H-L 15 VDD=12V, 25°C CL = 100 pF 10 9 12 15 18 21 24 VDDA Supply (V) Figure 26. Supply Current vs. Temperature 40 35 Rise/Fall Time (ns) 30 25 20 15 10 5 0 0 100kHz 50 kHz Trise Figure 23. Propagation Delay vs. Supply Voltage 14 12 10 8 6 4 2 0 9 14 19 VDDA Supply Voltage (V) 24 500kHz Duty Cycle = 50% CL = 0 pF 1 Channel Switching Tfall VDDA Supply Current (mA) 1MHz VDD=12V, 25°C 1 2 3 4 5 Load (nF) 6 7 8 9 10 Figure 27. Rise/Fall Time vs. Load Figure 24. Supply Current vs. Supply Voltage 18 Rev. 0.3 S i823x 50 45 Propagation Delay (ns) 40 35 30 25 20 15 10 0 1 2 3 4 VDD=12V, 25°C 5 Load (nF) 6 7 8 9 10 L-H H-L Source Current (A) 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 10 15 20 25 Supply Voltage (V) VDD=12V, Vout=VDD-5V Figure 28. Propagation Delay vs. Load 30 Figure 31. Output Source Current vs. Supply Voltage 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 -40 Propagation Delay (ns) 25 H-L L-H Sink Current (A) 20 15 VDD=12V, Load = 200pF -40 -20 0 20 40 60 80 100 120 VDD=12V, Vout=5V -10 20 50 80 110 10 Temperature (°C) Temperature (°C) Figure 29. Propagation Delay vs. Temperature 9 8 Figure 32. Output Sink Current vs. Temperature 3.5 3.25 Source Current (A) 3 2.75 2.5 2.25 Sink Current (A) 7 6 5 VDD=12V, Vout=5V 4 10 12 14 16 18 20 22 24 Supply Voltage (V) 2 -40 VDD=12V, Vout=VDD-5V -10 20 50 80 110 Temperature (°C) Figure 30. Output Sink Current vs. Supply Voltage Figure 33. Output Source Current vs. Temperature Rev. 0.3 19 S i823x 5. Application Information The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations. 5.1. Products Table 9 shows the configuration and functional overview for each product in this family. Table 9. Si823x Family Overview Part Number Si8230 Si8231 Si8232 Si8233 Si8234 Si8235/6 Configuration High-Side/Low-Side High-Side/Low-Side Dual Driver High-Side/Low-Side High-Side/Low-Side Dual Driver Overlap Protection   —   — Programmable Dead Time   —   — Inputs VIA, VIB PWM VIA, VIB VIA, VIB PWM VIA, VIB Peak Output Current (A) 0.5 0.5 0.5 4.0 4.0 4.0 5.2. Device Behavior Table 10 contains truth tables for the Si8230/3, Si8231/4, and Si8232/5/6 families. Table 10. Si823x Family Truth Table* Si8230/3 (High-Side/Low-Side) Truth Table Inputs VIA L L H H X X VIB L H L H X X VDDI State Disable Powered Powered Powered Powered Unpowered Powered L L L L X H Output VOA L L H L L L Output VOA H L L L VOB L H L L VOB L H L L L L Notes Output transition occurs after internal dead time expires. Output transition occurs after internal dead time expires. Output transition occurs after internal dead time expires. Invalid state. Output transition occurs after internal dead time expires. Output returns to input state within 7 µs of VDDI power restoration. Device is disabled. Si8231/4 (PWM Input High-Side/Low-Side) Truth Table PWM Input H L X X VDDI State Disable Powered Powered Unpowered Powered L L X H Notes Output transition occurs after internal dead time expires. Output transition occurs after internal dead time expires. Output returns to input state within 7 µs of VDDI power restoration. Device is disabled. *Note: This truth table assumes VDDA and VDDB are powered. If VDDA or VDDB power is lost, the respective output state (VOA or VOB) is undetermined. 20 Rev. 0.3 S i823x Table 10. Si823x Family Truth Table* (Continued) Si8232/5/6 (Dual Driver) Truth Table Inputs VIA L L H H X X VIB L H L H X X VDDI State Disable Powered Powered Powered Powered Unpowered Powered L L L L X H Output VOA L L H H L L VOB L H L H L L Notes Output transition occurs immediately (no internal dead time). Output transition occurs immediately (no internal dead time). Output transition occurs immediately (no internal dead time). Output transition occurs immediately (no internal dead time). Output returns to input state within 7 µs of VDDI power restoration. Device is disabled. *Note: This truth table assumes VDDA and VDDB are powered. If VDDA or VDDB power is lost, the respective output state (VOA or VOB) is undetermined. Rev. 0.3 21 S i823x 5.3. Power Supply Connections Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum, are recommended. 5.4. Power Dissipation Considerations Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range. The Si823x total power dissipation is the sum of the power dissipated by bias supply current, internal switching losses, and power delivered to the load. Equation 1 shows total Si823x power dissipation. In a non-overlapping system, such as a high-side/low-side driver, n = 1. For a dual driver with each driver having an independent load, n can have a maximum value of 2, corresponding to a 100% overlap between the two outputs. P D = V DDI I DDI + 2  V DDO I QOUT + C int V DDO F  + 2n  C L V DDO F  where: P D is the total Si823x device power dissipation (W) I DDI is the input-side maximum bias current (3 mA) I QOUT is the driver die maximum bias current (2.5 mA) C int is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver) V DDI is the input-side VDD supply voltage (4.5 to 5.5 V) V DDO is the driver-side supply voltage (10 to 24 V) F is the switching frequency (Hz) n is the overlap constant (max value = 2) 2 2 Equation 1. The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in Equation 2: T jmax – T A P Dmax  -------------------------- ja where: P Dmax = Maximum Si823x power dissipation (W) T jmax = Si823x maximum junction temperature (145 °C) T A = Ambient temperature (°C)  ja = Si823x junction-to-air thermal resistance (105 °C/W) F = Si823x switching frequency (Hz) Equation 2. Substituting values for PDMAX TjMAX, TA, and ja into Equation 2 results in a maximum allowable total power dissipation of 1.1 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet values from Table 1 on page 6 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V. 1.4  10 – 11 C L(MAX) = ------------------------- – 7.5  10 F –3 Equation 3. 1.4  10 – 10 C L(MAX) = ------------------------- – 3.7  10 F –3 Equation 4. 22 Rev. 0.3 S i823x Equation 1 and Equation 2 are graphed in Figure 34 where the points along the load line represent the package dissipation-limited value of CL for the corresponding switching frequency. 1 6 ,0 0 0 1 4 ,0 0 0 0 .5 A D r i ve r ( p F ) 4 A D r i ve r ( p F ) 1 2 ,0 0 0 1 0 ,0 0 0 Max Load (pF) 8 ,0 0 0 6 ,0 0 0 4 ,0 0 0 2 ,0 0 0 0 100 150 200 250 300 350 400 450 500 550 600 650 700 F re q u e n c y (K h z ) Figure 34. Max Load vs. Switching Frequency Rev. 0.3 23 S i823x 5.5. Layout Considerations It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to minimize parasitic inductance in these paths by locating the Si823x as close to the device it is driving as possible. In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise performance. 5.6. Device Operation Device behavior during start-up, normal operation and shutdown is shown in Figure 35, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low when input side power supply (VDDI) is not present. 5.6.1. Device Startup Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs VIA and VIB. 5.6.2. Under Voltage Lockout Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own under voltage lockout monitors. The Si823x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and VOB, remain low when the input side of the Si823x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above VDDAUV+. UVLO+ UVLO- VDD HYS VDDI UVLO+ UVLO- VDD HYS VDDA VIA DISABLE tSTART tSD tSTART tSTART tSD tRESTART tPHL tPLH VOA Figure 35. Device Behavior during Normal Operation and Shutdown 24 Rev. 0.3 S i823x 5.6.3. Under Voltage Lockout (UVLO) The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 36 through 39, upon power up, the Si823x is maintained in UVLO until VDD rises above VDDUV+. During power down, the Si823x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS). V DDUV+ (Typ) V DDUV+ ( Typ) Output Voltage (VO) 10.5 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 Output Voltage (VO) 10.5 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 Supply Voltage (V DD - V SS) (V) Supply Voltage (V DD - V SS) (V) Figure 36. Si823x UVLO Response (5 V) V DDUV+ (Typ) Figure 38. Si823x UVLO Response (10 V) V DDUV+ ( Typ) Output Voltage (VO) 10.5 Output Voltage (VO) 10.5 11.3 11.8 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 12.3 12.8 13.3 13.8 14.3 14.8 15.3 Supply Voltage (V DD - V SS) (V) Supply Voltage (V DD - V SS) (V) Figure 37. Si823x UVLO Response (8 V) Figure 39. Si823x UVLO Response (12.5 V) Rev. 0.3 25 S i823x 5.6.4. Control Inputs VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when the PWM input is high, and VOA is low and VOB is high when the PWM input is low. 5.6.5. Disable Input When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after DISABLE = VIL. The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low). 5.7. Programmable Dead Time and Overlap Protection All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and VOB from being high at the same time. These devices also include programmable dead time, which adds a userprogrammable delay between transitions of VOA and VOB (Figure 26.A). When enabled, dead time is present on all transitions, even after overlap recovery (Figure 26.B). The amount of dead time delay (DT) is programmed by a single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps. DT  10  RDT where: DT = dead time (ns) and RDT = dead time programming resistor (k   Equation 5. The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection. Input/output timing waveforms for the two-input drivers are shown in Figure 40, and dead time waveforms are shown in Figure 41. Ref VIA Description Normal operation: VIA high, VIB low. Normal operation: VIB high, VIA low. Contention: VIA = VIB = high. Recovery from contention: VIA transitions low. Normal operation: VIA = VIB = low. Normal operation: VIA high, VIB low. Contention: VIA = VIB = high. Recovery from contention: VIB transitions low. Normal operation: VIB transitions high. A ` B C D E VIB VOA F G H A B C D E F G H I VOB I Figure 40. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers 26 Rev. 0.3 S i823x OVERLAP OVERLAP VOB VIA VIA 50% VIB DT DT VIB DT DT 90% 10% DT DT 90% VOA VOA VOB 10% VOB B. Dead Time Operation During Overlap A. Typical Dead Time Operation Figure 41. Dead Time Waveforms for High-Side/Low-Side Two-Input Drivers Rev. 0.3 27 S i823x 6. RF Radiated Emissions The Si823x family uses a RF carrier frequency of approximately 700 MHz. This results in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC but, rather, is due to a small amount of RF energy driving the isolated ground planes which can act as a dipole antenna. The unshielded Si8230 evaluation board passes FCC Class B (Part 15) requirements. Table 11 shows measured emissions compared to FCC requirements. Note that the data reflects worst-case conditions where all inputs are tied to logic 1 and the RF transmitters are fully active. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna. Table 11. Radiated Emissions Frequency Measured (MHz) (dBµV/m) 712 1424 2136 2848 4272 4984 5696 29 39 42 43 44 44 44 FCC Spec (dBµV/m) 37 54 54 54 54 54 54 Compared to Spec (dB) –8 –15 –12 –11 –10 –10 –10 6.1. RF, Magnetic, and Common Mode Transient Immunity The Si823x families have very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures at 30 kV/µs (minimum). During a high surge event, the output may glitch low for up to 20–30 ns, but the output corrects immediately after the surge event. The Si823x families pass the industrial requirements of CISPR24 for RF immunity of 10 V/m using an unshielded evaluation board. As shown in Figure 20, the isolated ground planes form a parasitic dipole antenna. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded. The Si823x digital isolator can be used in close proximity to large motors and various other magnetic-field producing equipment. In theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. However, in actual use, the Si823x devices provide extremely high immunity to external magnetic fields and have been independently evaluated to withstand magnetic fields of at least 1000 A/m according to the IEC 61000-4-8 and IEC 61000-4-9 specifications. GND1 Isolator GND2 Dipole Antenna Figure 42. Dipole Antenna 28 Rev. 0.3 S i823x 7. Applications The following examples illustrate typical circuit configurations using the Si823x. 7.1. High-Side / Low-Side Driver Figure 43A shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure 43B shows the Si8231/4 controlled by a single PWM signal. VDDI VDDI C1 1uF VDD2 C2 1 µF D1 VDDI VDDI 1500 V max C1 1uF VDD2 C2 1 µF D1 1500 V max GNDI VDDA CB GNDI VDDA CB OUT1 OUT2 VIA VIB DT VOA Q1 PWMOUT PWM VOA Q1 GNDA DT GNDA CONTROLLER RDT Si8230/3 VDDB VDDB C3 10uF CONTROLLER RDT Si8231/4 VDDB VDDB C3 10uF I/O DISABLE GNDB I/O DISABLE GNDB VOB Q2 VOB Q2 A Figure 43. Si823x in Half-Bridge Application B For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V, while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will depend on the CB cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the Si823x should be located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors be used to reduce high frequency noise and maximize performance. Rev. 0.3 29 S i823x 7.2. Dual Driver Figure 44 shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a common ground or to different grounds with as much as 1500 V dc between them. VDDI VDDI C1 10 µF GNDI VDDA PH1 PH2 VIA VIB GNDA CONTROLLER VDDA C2 10 µF VOA Q1 S i8235/6 VDDB VDDB C3 10 µF GNDB I/O DISABLE VOB Q2 Figure 44. Si8235 in a Dual Driver Application 7.3. Dual Driver with Thermally Enhanced Package (Si8236) The thermal pad of the Si8236 must be connected to a heat spreader to lower thermal resistance. Generally, the larger the thermal shield’s area, the lower the thermal resistance. It is recommended that a thermal vias also be used to add mass to the shield. Vias generally have much more mass than the shield alone and consume less space, thus reducing thermal resistance more effectively. While the heat spreader is not generally a circuit ground, it is a good reference plane for the Si8236 and is also useful as a shield layer for EMI reduction. With a 10mm2 thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the Si8236 was measured at 50 °C/W. This is a significant improvement over the Si835 which does not include a thermal pad. The Si8235’s thermal resistance was measured at 105 °C /W. 30 Rev. 0.3 S i823x 8. Pin Descriptions SOIC-16 (Wide) VIA VIB VDDI GNDI DISABLE DT NC VDDI 1 2 3 4 5 6 7 8 16 15 14 SOIC-16 (Narrow) VDDA VOA GNDA NC NC VDDB VOB GNDB VIA VIB VDDI GNDI DISABLE DT NC VDDI 1 2 3 4 5 6 7 8 16 15 14 VDDA VOA GNDA NC NC VDDB VOB GNDB Si8230 Si8233 13 12 11 10 9 Si8230 13 Si8233 12 11 10 9 Table 12. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16) Pin 1 2 3 4 5 Name VIA VIB VDDI GNDI Description Non-inverting logic input terminal for Driver A. Non-inverting logic input terminal for Driver B. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Input-side ground terminal. DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. DT Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on page 26). No connection. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Ground terminal for Driver B. Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. No connection. No connection. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. 6 7 8 9 10 11 12 13 14 15 16 NC VDDI GNDB VOB VDDB NC NC GNDA VOA VDDA Rev. 0.3 31 S i823x SOIC-16 (Wide) PWM NC VDDI GNDI DISABLE DT NC VDDI 1 2 3 4 5 6 7 8 16 15 14 SOIC-16 (Narrow) VDDA VOA GNDA NC NC VDDB VOB GNDB PWM NC VDDI GNDI DISABLE DT NC VDDI 1 2 3 4 5 6 7 8 16 15 14 VDDA VOA GNDA NC NC VDDB VOB GNDB Si8231 Si8234 13 12 11 10 9 Si8231 13 Si8234 12 11 10 9 Table 13. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16) Pin 1 2 3 4 5 Name PWM NC VDDI GNDI PWM input. No connection. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Input-side ground terminal. Description DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. DT Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on page 26). No connection. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Ground terminal for VOB driver output. Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. No connection. No connection. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. 6 7 8 9 10 11 12 13 14 15 16 NC VDDI GNDB VOB VDDB NC NC GNDA VOA VDDA 32 Rev. 0.3 S i823x SOIC-16 (Wide) VIA VIB VDDI GNDI DISABLE NC NC VDDI 1 2 3 4 5 6 7 8 16 15 14 SOIC-16 (Narrow) VDDA VOA GNDA NC NC VDDB VOB GNDB VIA VIB VDDI GNDI DISABLE NC NC VDDI 1 2 3 4 5 6 7 8 16 15 14 VDDA VOA GNDA NC NC VDDB VOB GNDB Si8232 Si8235 13 12 11 10 9 Si8232 13 Si8235 12 11 10 9 Table 14. Si8232/5 Dual Isolated Driver (SOIC-16) Pin 1 2 3 4 5 Name VIA VIB VDDI GNDI Description Non-inverting logic input terminal for Driver A. Non-inverting logic input terminal for Driver B. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Input-side ground terminal. DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. NC NC VDDI GNDB VOB VDDB NC NC GNDA VOA VDDA No connection. No connection. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Ground terminal for VOB driver output. Driver B output. Driver output VOB power supply voltage terminal; connect to a source of 6.5 to 24 V. No connection. No connection. Ground terminal for Driver A. Driver B output. Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. 6 7 8 9 10 11 12 13 14 15 16 Rev. 0.3 33 S i823x LGA-14 (5 x 5 mm) GNDI VIA VIB VDDI DISABLE DT VDDI 1 2 3 4 5 6 7 14 13 12 VDDA VOA GNDA NC VDDB VOB GNDB Si8233 11 10 7 8 Table 15. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA) Pin GNDI VIA VIB VDDI DISABLE Name 1 2 3 4 5 Input-side ground terminal. Non-inverting logic input terminal for Driver A. Non-inverting logic input terminal for Driver B. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see"5.7.Programmable Dead Time and Overlap Protection" on page 26). Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Ground terminal for Driver B. Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. No connection. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Description DT 6 VDDI GNDB VOB VDDB NC GNDA VOA VDDA 7 8 9 10 11 12 13 14 34 Rev. 0.3 S i823x LGA-14 (5 x 5 mm) GNDI PWM NC VDDI DISABLE DT VDDI 1 2 3 4 5 6 7 14 13 12 VDDA VOA GNDA NC VDDB VOB GNDB Si8234 11 10 7 8 Table 16. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA) Pin GNDI PWM NC VDDI DISABLE Name 1 2 3 4 5 Input-side ground terminal. PWM input. No connection. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when connected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on page 26). Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Ground terminal for Driver B. Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. No connection. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Description DT 6 VDDI GNDB VOB VDDB NC GNDA VOA VDDA 7 8 9 10 11 12 13 14 Rev. 0.3 35 S i823x LGA-14 (5 x 5 mm) GNDI VIA VIB VDDI DISABLE NC VDDI 1 2 3 4 5 6 7 14 13 12 VDDA VOA GNDA NC VDDB VOB GNDB Si8235 Si8236 11 10 7 8 Table 17. Si8235/6 Dual Isolated Driver (14 LD LGA) Pin GNDI VIA VIB VDDI DISABLE Name 1 2 3 4 5 Input-side ground terminal. Non-inverting logic input terminal for Driver A. Non-inverting logic input terminal for Driver B. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling. No connection. Input-side power supply terminal; connect to a source of 4.5 to 5.5 V. Ground terminal for Driver B. Driver B output (low-side driver). Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V. No connection. Ground terminal for Driver A. Driver A output (high-side driver). Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V. Description NC VDDI GNDB VOB VDDB NC GNDA VOA VDDA 6 7 8 9 10 11 12 13 14 36 Rev. 0.3 S i823x 9. Ordering Guide The ordering part number (OPN) naming convention is described in Figure 45. The currently available OPNs are listed in Table 18. The part number convention is not intended to imply that all possible device configuration options and their corresponding ordering part numbers (OPN) will be available or are included in the ordering guide table. However, if there is a specific device configuration of interest that is currently not listed in the ordering guide table, contact your local Silicon Labs sales representative, or go to the Silicon Labs Technical Support web page at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a request for your specific device configuration and OPN. Ordering part number options for 10 V and 12.5 V UVLO will be made available only by request. Si823YUV-R-TPn ISOdriver Product Peak Output Current (0,1,2=0.5A, 3,4,5=4A) UVLO* level (A=5V, B=8V, C=10V, D=12.5V) Insulation Rating (A=1.5kV,B=2.5kV,C=3.75kV,D=5kV) Product Revision Temp Range (I=-40 to +125C) Package Type (S=SOIC, M=LGA) Package Extension (1=Narrow Body) Note: UVLO = Under Voltage Lock Out for VDDA, VDDB. Figure 45. ISODriver OPN Naming Convention Rev. 0.3 37 S i823x Table 18. Ordering Part Numbers Legacy Ordering Part Number (OPN) 2.5 kV Only Ordering Part Number (OPN) Inputs Peak UVLO Configuration Current Voltage Isolation Rating Temperature Range Package Type Wide Body (WB) Package Options Si8230BB-B-IS Si8231BB-B-IS Si8232BB-B-IS Si8233BB-C-IS Si8234BB-C-IS Si8235BB-C-IS VIA, VIB PWM VIA,VIB VIA,VIB PWM VIA,VIB High Side/ Low Side High Side/ Low Side Dual Driver 2.5 kVrms High Side/ Low Side High Side/ Low Side Dual Driver 4.0 A 8V –40 to +125 °C 0.5 A 8V Si8230-A-IS Si8231-A-IS SOIC-16 Wide Body Si8232-A-IS Si8233-B-IS Si8234-B-IS Si8235-B-IS Narrow Body (NB) Package Options Si8230BB-B-IS1 Si8231BB-B-IS1 Si8232BB-B-IS1 Si8233BB-C-IS1 Si8234BB-C-IS1 Si8235BB-C-IS1 VIA,VIB PWM VIA,VIB VIA,VIB PWM VIA,VIB High Side/ Low Side High Side/ Low Side Dual Driver 2.5 kVrms High Side/ Low Side High Side/ Low Side Dual Driver 4.0 A 8V –40 to +125 °C 0.5 A 8V SOIC-16 Narrow Body N/A Note: All packages are RoHS-compliant. Moisture sensitivity level is MSL3 for wide-body SOIC-16 and 14-LD LGA packages and MSL2A for narrow-body SOIC-16 packages with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 38 Rev. 0.3 S i823x Table 18. Ordering Part Numbers (Continued) Legacy Ordering Part Number (OPN) 2.5 kV Only Ordering Part Number (OPN) Inputs Peak UVLO Configuration Current Voltage Isolation Rating Temperature Range Package Type LGA Package Options Si8233BB-C-IM Si8234BB-C-IM Si8235BB-C-IM Si8235AB-C-IM Si8236BA-C-IM Si8236AA-C-IM VIA,VIB PWM VIA,VIB VIA,VIB VIA, VIB VIA,VIB High Side/ Low Side High Side/ Low Side Dual Driver Dual Driver Dual Driver Dual Driver 4.0 A 5V 8V 5V 1.5 kVrms LGA-14 5x5 mm with Thermal Pad 8V 2.5 kVrms –40 to +125 °C LGA-14 5x5 mm Si8233-B-IM Si8234-B-IM Si8235-B-IM N/A Si8236-B-IM 5 kV Ordering Options Si8230BD-B-IS Si8231BD-B-IS Si8232BD-B-IS Si8233BD-C-IS Si8234BD-C-IS Si8235BD-C-IS VIA, VIB PWM VIA, VIB VIA, VIB PWM VIA, VIB High Side/ Low Side High Side/ Low Side Dual Driver 8V High Side/ Low Side High Side/ Low Side Dual Driver 4.0 A 5.0 kVrms –40 to +125 °C 0.5 A SOIC-16 Wide Body N/A Note: All packages are RoHS-compliant. Moisture sensitivity level is MSL3 for wide-body SOIC-16 and 14-LD LGA packages and MSL2A for narrow-body SOIC-16 packages with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. Rev. 0.3 39 S i823x 10. Package Outline: 16-Pin Wide Body SOIC Figure 46 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table 19 lists the values for the dimensions shown in the illustration. Figure 46. 16-Pin Wide Body SOIC Table 19. Package Diagram Dimensions Millimeters Symbol A A1 D E E1 b c e h L  Min — 0.1 Max 2.65 0.3 10.3 BSC 10.3 BSC 7.5 BSC 0.31 0.20 0.25 0.4 0° 0.51 0.33 0.75 1.27 7° 1.27 BSC 40 Rev. 0.3 S i823x 11. Land Pattern: Wide-Body SOIC Figure 47 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-body SOIC. Table 20 lists the values for the dimensions shown in the illustration. Figure 47. 16-Pin SOIC Land Pattern Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension C1 E X1 Y1 Feature Pad Column Spacing Pad Row Pitch Pad Width Pad Length (mm) 9.40 1.27 0.60 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. Rev. 0.3 41 S i823x 12. Package Outline: Narrow Body SOIC Figure 48 illustrates the package details for the Si823x in a 16-pin narrow-body SOIC (SO-16). Table 21 lists the values for the dimensions shown in the illustration. Figure 48. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 21. Package Diagram Dimensions Dimension A A1 A2 b c D E E1 e L L2 0.40 0.25 BSC Min — 0.10 1.25 0.31 0.17 9.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 1.27 Max 1.75 0.25 — 0.51 0.25 42 Rev. 0.3 S i823x Table 21. Package Diagram Dimensions (Continued) h θ aaa bbb ccc ddd 0.25 0° 0.10 0.20 0.10 0.25 0.50 8° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC JSTD-020C specification for Small Body Components. Rev. 0.3 43 S i823x 13. Land Pattern: Narrow Body SOIC Figure 49 illustrates the recommended land pattern details for the Si823x in a 16-pin narrow-body SOIC. Table 22 lists the values for the dimensions shown in the illustration. Figure 49. 16-Pin Narrow Body SOIC PCB Land Pattern Table 22. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension C1 E X1 Y1 Feature Pad Column Spacing Pad Row Pitch Pad Width Pad Length (mm) 5.40 1.27 0.60 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 44 Rev. 0.3 S i823x 14. Package Outline: 14 LD LGA (5 x 5 mm) Figure 50 illustrates the package details for the Si823x in an LGA outline. Table 23 lists the values for the dimensions shown in the illustration. Figure 50. Si823x LGA Outline Table 23. Package Diagram Dimensions Dimension A b D D1 e E E1 L L1 aaa bbb ccc ddd eee 0.70 0.05 — — — — — MIN 0.74 0.25 NOM 0.84 0.30 5.00 BSC 4.15 BSC 0.65 BSC 5.00 BSC 3.90 BSC 0.75 0.10 — — — — — 0.80 0.15 0.10 0.10 0.08 0.15 0.08 MAX 0.94 0.35 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Rev. 0.3 45 S i823x 15. Land Pattern: 14 LD LGA Figure 51 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA. Table 24 lists the values for the dimensions shown in the illustration. Figure 51. 14-Pin LGA Land Pattern 46 Rev. 0.3 S i823x Table 24. 14-Pin LGA Land Pattern Dimensions Dimension C1 E X1 Y1 (mm) 4.20 0.65 0.80 0.40 Notes: General: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design: 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design: 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly: 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD020D specification for Small Body Components. Rev. 0.3 47 S i823x 16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) Figure 52 illustrates the package details for the Si8236 ISOdriver in an LGA outline. Table 25 lists the values for the dimensions shown in the illustration. Figure 52. Si823x LGA Outline with Thermal Pad Table 25. Package Diagram Dimensions Dimension A b D D1 e E E1 L L1 P1 P2 aaa bbb ccc ddd eee 0.70 0.05 1.40 4.15 — — — — — MIN 0.74 0.25 NOM 0.84 0.30 5.00 BSC 4.15 BSC 0.65 BSC 5.00 BSC 3.90 BSC 0.75 0.10 1.45 4.20 — — — — — 0.80 0.15 1.50 4.25 0.10 0.10 0.08 0.15 0.08 MAX 0.94 0.35 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 48 Rev. 0.3 S i823x 17. Land Pattern: 14 LD LGA with Thermal Pad Figure 53 illustrates the recommended land pattern details for the Si8236 in a 14-pin LGA with thermal pad. Table 26 lists the values for the dimensions shown in the illustration. Figure 53. 14-Pin LGA with Thermal Pad Land Pattern Rev. 0.3 49 S i823x Table 26. 14-Pin LGA with Thermal Pad Land Pattern Dimensions Dimension C1 C2 D2 E X1 Y1 (mm) 4.20 1.50 4.25 0.65 0.80 0.40 Notes: General: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design: 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design: 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly: 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD020D specification for Small Body Components. 50 Rev. 0.3 S i823x DOCUMENT CHANGE LIST Revision 0.11 to Revision 0.2       Updated all specs to reflect latest silicon revision. Updated Table 1 on page 6 to include new UVLO options. Updated Table 2 on page 10 to reflect new maximum package isolation ratings Added Figures 34, 35, and 36. Updated Ordering Guide to reflect new package offerings. Added "5.6.3.Under Voltage Lockout (UVLO)" on page 25 to describe UVLO operation. Revision 0.2 to Revision 0.3  Moved Sections 2, 3, and 4 to after Section 5.  Updated Tables 15, 16, and 17. Removed Si8230, Si8231, and Si8232 from pinout and from title.  Updated and added Ordering Guide footnotes.  Updated UVLO specifications in Table 1 on page 6.  Added PWD and Output Supply Active Current specifications in Table 1.  Updated and added typical operating condition graphs in "3.Typical Operating Characteristics (0.5 Amp)" on page 16 and "4.Typical Operating Characteristics (4.0 Amp)" on page 18. Rev. 0.3 51 S i823x CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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