Si864x Data Sheet
Low-Power Quad-Channel Digital Isolators
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Enable inputs provide a single point control for enabling and disabling
output drive. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and 5
kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products >1 kV are safety certified by UL, CSA, VDE, and CQC, and
products in wide-body packages support reinforced insulation withstanding up to 5
kVRMS.
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robustness and low defectivity required for automotive applications.
Industrial Applications
• Industrial automation systems
• Medical electronics
• Isolated switch mode supplies
• Isolated ADC, DAC
• Motor control
• Power inverters
• Communications systems
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 62368-1, 60601-1 (reinforced insulation)
• VDE certification conformity
• Si864xxT options certified to reinforced VDE 0884-10
• All other options certified to basic
VDE 0884-10 and reinforced 60950-1
• CQC certification approval
• GB4943.1
Automotive Applications
• On-board chargers
• Battery management systems
• Charging stations
• Traction inverters
• Hybrid Electric Vehicles
• Battery Electric Vehicles
KEY FEATURES
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 VRMS isolation
• Reinforced VDE 0884-10, 10 kV surgecapable (Si864xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
2.5 V Operation
• 1.5 mA per channel at 1 Mbps
• 3.5 mA per channel at 100 Mbps
• Tri-state outputs with ENABLE
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Precise timing (typical)
• 10 ns propagation delay
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C
• RoHS-compliant packages
• SOIC-16 wide body
• SOIC-16 narrow body
• QSOP-16
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• IMDS and CAMDS listing support
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Rev. 2.15
Si864x Data Sheet
Ordering Guide
1. Ordering Guide
Industrial and Automotive Grade OPNs
Industrial-grade devices (part numbers having an “-I” in their suffix) are built using well-controlled, high-quality manufacturing flows to
ensure robustness and reliability. Qualifications are compliant with JEDEC, and defect reduction methodologies are used throughout
definition, design, evaluation, qualification, and mass production steps.
Automotive-grade devices (part numbers having an “-A” in their suffix) are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and low defectivity. These devices are supported with AIAG-compliant Production Part Approval
Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material Data System
(CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass production steps.
Table 1.1. Ordering Guide for Valid OPNs1, 2, 5
Ordering Part Number
(OPN)
Automotive OPNs6, 7
Number Number
of Inputs of Inputs Max Data
Rate
VDD2
VDD1
(Mbps)
Side
Side
Default
Output
State
Isolation
Rating
(kV)
Package
QSOP-16 Packages
Si8640BA-B-IU
Si8640BA-AU
4
0
150
Low
1.0
QSOP-16
Si8640BB-B-IU
Si8640BB-AU
4
0
150
Low
2.5
QSOP-16
Si8640EB-B-IU
Si8640EB-AU
4
0
150
High
2.5
QSOP-16
Si8641BA-B-IU
Si8641BA-AU
3
1
150
Low
1.0
QSOP-16
Si8641BA-C-IU
Si8641BA-AU
3
1
150
Low
1.0
QSOP-16
Si8641BB-B-IU
Si8641BB-AU
3
1
150
Low
2.5
QSOP-16
Si8641EB-B-IU
Si8641EB-AU
3
1
150
High
2.5
QSOP-16
Si8642BA-B-IU
Si8642BA-AU
2
2
150
Low
1.0
QSOP-16
Si8642BA-C-IU
Si8642BA-AU
2
2
150
Low
1.0
QSOP-16
Si8642BB-B-IU
Si8642BB-AU
2
2
150
Low
2.5
QSOP-16
Si8642EA-B-IU
Si8642EA-AU
2
2
150
High
1.0
QSOP-16
Si8642EB-B-IU
Si8642EB-AU
2
2
150
High
2.5
QSOP-16
Si8645BA-B-IU
Si8645BA-AU
4
0
150
Low
1.0
QSOP-16
Si8645BA-C-IU
Si8645BA-AU
4
0
150
Low
1.0
QSOP-16
Si8645BB-B-IU
Si8645BB-AU
4
0
150
Low
2.5
QSOP-16
Si8640BB-B-IS1
Si8640BB-AS1
4
0
150
Low
2.5
NB SOIC-16
Si8640BB-B-IS
Si8640BB-AS
4
0
150
Low
2.5
WB SOIC-16
Si8640BC-B-IS1
Si8640BC-AS1
4
0
150
Low
3.75
NB SOIC-16
Si8640BD-B-IS2
Si8640BD-AS2
4
0
150
Low
5.0
WB SOIC-16
(8 mm creepage)4
Si8640BD-B-IS
Si8640BD-AS
4
0
150
Low
5.0
WB SOIC-16
Si8640EC-B-IS1
Si8640EC-AS1
4
0
150
High
3.75
NB SOIC-16
Si8640ED-B-IS2
Si8640ED-AS2
4
0
150
High
5.0
WB SOIC-16
(8 mm creepage)4
SOIC-16 Packages
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Rev. 2.15 | 2
Si864x Data Sheet
Ordering Guide
Number Number
of Inputs of Inputs Max Data
Rate
VDD2
VDD1
(Mbps)
Side
Side
Default
Output
State
Isolation
Rating
(kV)
Package
150
High
5.0
WB SOIC-16
1
150
Low
2.5
NB SOIC-16
3
1
150
Low
2.5
WB SOIC-16
Si8641BC-AS1
3
1
150
Low
3.75
NB SOIC-16
Si8641BD-B-IS2
Si8641BD-AS2
3
1
150
Low
5.0
WB SOIC-16
(8 mm creepage)4
Si8641BD-B-IS
Si8641BD-AS
3
1
150
Low
5.0
WB SOIC-16
Si8641EC-B-IS1
Si8641EC-AS1
3
1
150
High
3.75
NB SOIC-16
Si8641ED-B-IS2
Si8641ED-AS2
3
1
150
High
5.0
WB SOIC-16
(8 mm creepage)4
Si8641ED-B-IS
Si8641ED-AS
3
1
150
High
5.0
WB SOIC-16
Si8642BB-B-IS1
Si8642BB-AS1
2
2
150
Low
2.5
NB SOIC-16
Si8642BB-B-IS
Si8642BB-AS
2
2
150
Low
2.5
WB SOIC-16
Si8642BC-B-IS1
Si8642BC-AS1
2
2
150
Low
3.75
NB SOIC-16
Si8642BD-B-IS2
Si8642BD-AS2
2
2
150
Low
5.0
WB SOIC-16
(8 mm creepage)4
Si8642BD-B-IS
Si8642BD-AS
2
2
150
Low
5.0
WB SOIC-16
Si8642EC-B-IS1
Si8642EC-AS1
2
2
150
High
3.75
NB SOIC-16
Si8642ED-B-IS2
Si8642ED-AS2
2
2
150
High
5.0
WB SOIC-16
(8 mm creepage)4
Si8642ED-B-IS
Si8642ED-AS
2
2
150
High
5.0
WB SOIC-16
Si8645BB-B-IS1
Si8645BB-AS1
4
0
150
Low
2.5
NB SOIC-16
Si8645BB-B-IS
Si8645BB-AS
4
0
150
Low
2.5
WB SOIC-16
Si8645BC-B-IS1
Si8645BC-AS1
4
0
150
Low
3.75
NB SOIC-16
Si8645BD-B-IS
Si8645BD-AS
4
0
150
Low
5.0
WB SOIC-16
Ordering Part Number
(OPN)
Automotive OPNs6, 7
Si8640ED-B-IS
Si8640ED-AS
4
0
Si8641BB-B-IS1
Si8641BB-AS1
3
Si8641BB-B-IS
Si8641BB-AS
Si8641BC-B-IS1
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8640BT-IS
Si8640BT-AS
4
0
150
Low
5.0
WB SOIC-16
Si8640ET-IS
Si8640ET-AS
4
0
150
High
5.0
WB SOIC-16
Si8641BT-IS
Si8641BT-AS
3
1
150
Low
5.0
WB SOIC-16
Si8641ET-IS
Si8641ET-AS
3
1
150
High
5.0
WB SOIC-16
Si8642BT-IS
Si8642BT-AS
2
2
150
Low
5.0
WB SOIC-16
Si8642ET-IS
Si8642ET-AS
2
2
150
High
5.0
WB SOIC-16
Si8645BT-IS
Si8645BT-AS
4
0
150
Low
5.0
WB SOIC-16
Si8645ET-IS
Si8645ET-AS
4
0
150
High
5.0
WB SOIC-16
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Rev. 2.15 | 3
Si864x Data Sheet
Ordering Guide
Ordering Part Number
(OPN)
Automotive OPNs6, 7
Number Number
of Inputs of Inputs Max Data
Rate
VDD2
VDD1
(Mbps)
Side
Side
Default
Output
State
Isolation
Rating
(kV)
Package
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. The package designated IS2 has a design that eliminates tie bars, thus allowing for extra creepage distance while maintaining
standard WB SOIC-16 package dimensions and land pattern.
5. Temperature range is –40 to 125 °C.
6. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with an "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is included on shipping labels.
7. In the top markings of each device, the Manufacturing Code represented by either “RTTTTT” or “TTTTTT” contains as its first
character a letter in the range N through Z to indicate Automotive-Grade.
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Rev. 2.15 | 4
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Theory of Operation .
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2.2 Eye Diagram.
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3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Device Startup .
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.10
3.2 Undervoltage Lockout
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.10
3.3 Layout Recommendations .
3.3.1 Supply Bypass . . .
3.3.2 Output Pin Termination.
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3.4 Fail-Safe Operating Mode .
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3.5 Typical Performance Characteristics.
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.11
4. Electrical Specifications
5. Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . 12
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6. Package Outline (16-Pin Wide Body SOIC)
. . . . . . . . . . . . . . . . . . . 29
7. Land Pattern (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . .
8. Package Outline (16-Pin Narrow Body SOIC)
31
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9. Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . 34
10. Package Outline (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . 35
11. Land Pattern (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . 37
12. Top Marking (16-Pin Wide Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
14. Top Marking (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . 38
. . . . . . . . . . . . . . . . . . .39
. . . . . . . . . . . . . . . . . . . . . . . . 40
15. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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41
Rev. 2.15 | 5
Si864x Data Sheet
Functional Description
2. Functional Description
2.1 Theory of Operation
The operation of an Si864x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si864x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si864x Data Sheet
Functional Description
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8640. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8640 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Rev. 2.15 | 7
Si864x Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 10, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following tables to
determine outputs when power supply (VDD) is not present and for logic conditions when enable pins are used.
Table 3.1. Si86xx Logic Operation
VI Input1, 2 EN Input1, 2, 3, 4
VDDI State1, 5, 6
VDDO State1, 5, 6
VO Output1, 2
H
H or NC
P
P
H
L
H or NC
P
P
L
X7
L
P
P
Hi-Z8
X7
H or NC
UP
P
L9
H9
X7
L
UP
P
X7
X7
P
UP
Hi-Z8
Comments
Enabled, normal operation.
Disabled.
Upon transition of VDDI from unpowered to
powered, VO returns to the same state as VI
in less than 1 µs.
Disabled.
Undetermined Upon transition of VDDO from unpowered to
powered, VO returns to the same state as VI
within 1 µs, if EN is in either the H or NC
state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1
µs if EN is L.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the
enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy
environments.
4. No Connect (NC) replaces EN1 on Si8640/45. No Connect replaces EN2 on the Si8645. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
9. See 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default
output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/
outputs.
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Rev. 2.15 | 8
Si864x Data Sheet
Device Operation
Table 3.2. Enable Input Truth
Part Number
EN11, 2
EN21, 2
Si8640
—
H
Outputs B1, B2, B3, B4 are enabled and follow the input state.
—
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
H
X
Output A4 enabled and follows the input state.
L
X
Output A4 disabled and in high impedance state.3
X
H
Outputs B1, B2, B3 are enabled and follow the input state.
X
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
H
X
Outputs A3 and A4 are enabled and follow the input state.
L
X
Outputs A3 and A4 are disabled and in high impedance state.3
X
H
Outputs B1 and B2 are enabled and follow the input state.
X
L
Outputs B1 and B2 are disabled and in high impedance state.3
—
—
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Si8641
Si8642
Si8645
Operation
Note:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic operation is
summarized for each isolator product in Table 2. These inputs are internally pulled-up to local VDD allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2
if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the
Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
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Si864x Data Sheet
Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low-voltage circuits (SELV is a circuit with 109
>109
>109
VIORM
Method b1
Input to Output Test Voltage
VPR
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
VIOTM
t = 60 sec
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
Surge Voltage
VIOSM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO
= 500 V
RS
Vpeak
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. VDE 0884-10 Safety Limiting Values 1
Parameter
Case Temperature
Symbol
Test Condition
TS
Max
WB SOIC-16 NB SOIC-16
QSOP-16
Unit
150
150
150
°C
220
210
210
mA
275
275
275
mW
θJA = 100 °C/W (WB SOIC-16)
Safety Input, Output, or Supply
Current
IS
105 °C/W (NB SOIC-16, QSOP-16)
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Device Power Dissipation 2
PD
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 26 and Figure 4.5 (NB
SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10
on page 26.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Rev. 2.15 | 25
Si864x Data Sheet
Electrical Specifications
Table 4.10. Thermal Characteristics
Parameter
IC Junction-to-Air Thermal Resistance
Symbol
WB SOIC-16
NB SOIC-16/QSOP-16
Unit
θJA
100
105
°C/W
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE
0884-10
Figure 4.5. (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per VDE 0884-10
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Si864x Data Sheet
Electrical Specifications
Table 4.11. Absolute Maximum Ratings 1
Parameter
Symbol
Min
Max
Unit
Storage Temperature 2
TSTG
–65
150
°C
Operating Temperature
TA
–40
125
°C
Junction Temperature
TJ
—
150
°C
VDD1, VDD2
–0.5
7.0
V
Input Voltage
VI
–0.5
VDD + 0.5
V
Output Voltage
VO
–0.5
VDD + 0.5
V
Output Current Drive Channel
IO
—
10
mA
Lead Solder Temperature (10 s)
—
260
°C
Maximum Isolation (Input to Output) (1 sec)
—
4500
VRMS
—
6500
VRMS
Supply Voltage
NB SOIC-16, QSOP-16
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded periods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
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Si864x Data Sheet
Pin Descriptions
5. Pin Descriptions
VDD1
VDD2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
XMITR
I
s
o
l
a
t
i
o
n
GND2
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
RCVR
B4
VDD1
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
RCVR
I
s
o
l
a
t
i
o
n
EN2/NC
NC
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
XMITR
B4
GND2
Si8640/45
VDD2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
RCVR
A4
RF
RCVR
GND1
GND1
Si8641
I
s
o
l
a
t
i
o
n
GND2
RF
RCVR
B1
RF
RCVR
B2
RF
RF
XMITR
RCVR
B3
RF
XMITR
B4
EN2
EN1
EN2
EN1
GND1
VDD1
VDD2
GND2
Si8642
GND2
Name
SOIC-16 Pin#
Type
Description
VDD1
1
Supply
Side 1 power supply.
GND1
21
Ground
Side 1 ground.
A1
3
Digital Input
Side 1 digital input.
A2
4
Digital Input
Side 1 digital input.
A3
5
Digital I/O
Side 1 digital input or output.
A4
6
Digital I/O
Side 1 digital input or output.
EN1/NC2
7
Digital Input
GND1
81
Ground
Side 1 ground.
GND2
91
Ground
Side 2 ground.
EN2/NC2
10
Digital Input
B4
11
Digital I/O
Side 2 digital input or output.
B3
12
Digital I/O
Side 2 digital input or output.
B2
13
Digital Output
Side 2 digital output.
B1
14
Digital Output
Side 2 digital output.
GND2
151
Ground
Side 2 ground.
VDD2
16
Supply
Side 2 power supply.
Side 1 active high enable. NC on Si8640/45.
Side 2 active high enable. NC on Si8645.
Note:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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Rev. 2.15 | 28
Si864x Data Sheet
Package Outline (16-Pin Wide Body SOIC)
6. Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the the Si86xx digital isolator in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
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Si864x Data Sheet
Package Outline (16-Pin Wide Body SOIC)
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
θ
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Si864x Data Sheet
Land Pattern (16-Pin Wide Body SOIC)
7. Land Pattern (16-Pin Wide Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC PCB Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si864x Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
8. Package Outline (16-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC package. The table lists the values for the
dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
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Rev. 2.15 | 32
Si864x Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si864x Data Sheet
Land Pattern (16-Pin Narrow Body SOIC)
9. Land Pattern (16-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 9.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.15 | 34
Si864x Data Sheet
Package Outline (16-Pin QSOP)
10. Package Outline (16-Pin QSOP)
The figure below illustrates the package details for the Si86xx in a 16-pin QSOP package. The table lists the values for the dimensions
shown in the illustration.
Figure 10.1. 16-Pin QSOP Package
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Rev. 2.15 | 35
Si864x Data Sheet
Package Outline (16-Pin QSOP)
Table 10.1. 16-Pin QSOP Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.20
0.30
c
0.17
0.25
D
4.89 BSC
E
6.00 BSC
E1
3.90 BSC
e
0.635 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 2.15 | 36
Si864x Data Sheet
Land Pattern (16-Pin QSOP)
11. Land Pattern (16-Pin QSOP)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin QSOP package. The table lists the values
for the dimensions shown in the illustration.
Figure 11.1. 16-Pin QSOP PCB Land Pattern
Table 11.1. 16-Pin QSOP Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
0.635
X1
Pad Width
0.40
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si864x Data Sheet
Top Marking (16-Pin Wide Body SOIC)
12. Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
e4
TW
Figure 12.1. 16-Pin Wide Body SOIC Top Marking
Table 12.1. 16-Pin Wide Body SOIC Top Marking Explanation
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4)
Base Part Number
Line 1 Marking: Ordering Options
(See 1. Ordering Guide for more information).
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with
10 kV surge capability.
YY = Year
Line 2 Marking:
WW = Workweek
RTTTTT = Mfg Code
Circle = 1.7 mm Diameter
Line 3Marking:
(Center-Justified)
Country of Origin ISO Code Abbreviation
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
Manufacturing code from assembly house.
“R” indicates revision.
“e4” Pb-Free Symbol.
TW = Taiwan as shown, TH = Thailand
Note:
1. Si8645 has 0 reverse channels.
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Si864x Data Sheet
Top Marking (16-Pin Narrow Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
e3
Si86XYSV
YYWWRTTTTT
Figure 13.1. 16-Pin Narrow Body SOIC Top Marking
Table 13.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4)
Base Part Number
Line 1 Marking: Ordering Options
(See 1. Ordering Guide for more information).
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
Assigned by the assembly subcontractor. Corresponds to the
year and work week of the mold date.
Line 2 Marking: WW = Work Week
RTTTTT = Mfg Code
Manufacturing code from assembly house.
“R” indicates revision.
Note:
1. Si8645 has 0 reverse channels.
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Si864x Data Sheet
Top Marking (16-Pin QSOP)
14. Top Marking (16-Pin QSOP)
Figure 14.1. 16-Pin QSOP Top Marking
Table 14.1. 16-Pin QSOP Top Marking Explanation
86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4)
Base Part Number
Line 1 Marking: Ordering Options
(See 1. Ordering Guide for more information.)
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating.
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: RTTTTT = Mfg Code
Line 3 Marking:
YY = Year
WW = Work Week
Manufacturing code from assembly house.
“R” indicates revision.
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
Note:
1. Si8645 has 0 reverse channels.
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Rev. 2.15 | 40
Si864x Data Sheet
Revision History
15. Revision History
Revision 2.15
September 2019
• Updated Ordering Guide.
Revision 2.14
February 2019
• Updated Ordering Guide.
Revision 2.13
September 2018
• Added SI8640BB-AS, SI8641BC-AS1, and SI8642ED-AS to Ordering Guide for Automotive-Grade OPN options
Revision 2.12
February 2018
• Added SI8641BD-AS to Ordering Guide for Automotive-Grade OPN options
Revision 2.11
November 2017
• Added new table to Ordering Guide for Automotive-Grade OPN options
Revision 2.1
October 18, 2017
• Added new OPNs in Ordering Guide for IU (QSOP) and IS2 (8 mm creepage WB SOIC) package options.
• Added 62368-1 references throughout.
• Removed 61010-1 references throughout.
Revision 2.0
November 30, 2016
• Added note to Table 1.1 Ordering Guide for Valid OPNs1, 2, 5 on page 2 for denoting tape and reel marking.
Revision 1.9
November 18, 2015
• Deleted duplicate Si8641BB-B-IU OPN listing and corrected Si8645BB-B-IU listing in 1. Ordering Guide.
• Added QSOP-16 information to Table 4.7 IEC 60664-1 Ratings on page 24.
• Added QSOP-16 information to Table 4.8 VDE 0884-10 Insulation Characteristics for Si86xxxx 1 on page 25.
• Added QSOP-16 information to Table 4.9 VDE 0884-10 Safety Limiting Values 1 on page 25.
• Added QSOP-16 reference to Figure 4.5 (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE 0884-10 on page 26.
Revision 1.8
October 29, 2015
• Added product options Si8641BB-B-IU, Si8645BB-B-IU and Si864xxT in 1. Ordering Guide.
• Added spec line items for Input and Enable Leakage Currents pertaining to Si864xxT in Electrical Specifications.
• Added new spec for tSD in 4. Electrical Specifications.
• Updated IEC 60747-5-2 to IEC 60747-5-5 throughout document.
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Rev. 2.15 | 41
Si864x Data Sheet
Revision History
Revision 1.7
June 18, 2015
• Updated Table 5 on page 14.
• Added CQC certificate numbers.
• Updated "4. Ordering Guide" on page 10.
• Added Si8640BA OPN.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Revision 1.6
September 25, 2013
• Added Figure 3, “Common Mode Transient Immunity Test Circuit,” on page 7.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated "4. Ordering Guide" on page 10.
• Updated "11.1. Top Marking (16-Pin Wide Body SOIC)" on page 20.
Revision 1.5
October 3, 2012
• Updated "4. Ordering Guide" on page 10.
• Updated "11.5. Top Marking (16-Pin QSOP)" on page 22.
Revision 1.4
June 26, 2012
• Updated Table 11 on page 18.
• Added junction temperature spec.
• Updated "2.3.1. Supply Bypass" on page 7.
• Removed “3.3.2 Pin Connections” on page 23.
• Updated "3. Pin Descriptions" on page 9.
• Updated table notes.
• Updated "4. Ordering Guide" on page 10.
• Removed Rev A devices.
• Updated "5. Package Outline: 16-Pin Wide Body SOIC" on page 12.
• Updated Top Marks.
• Added revision description.
Revision 1.3
March 21, 2012
• Updated "4. Ordering Guide" on page 10 to include MSL2A.
Revision 1.2
February 15, 2012
• Updated Table 3, “Ordering Guide for Valid OPNs” on page 10.
• Updated Note 1 with MSL2A.
• Updated Current Revision Devices.
Revision 1.1
September 14, 2011
• Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 8.
• Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 11.
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Rev. 2.15 | 42
Si864x Data Sheet
Revision History
Revision 1.0
July 14, 2011
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
Revision 0.2
March 31, 2011
• Added chip graphics on page 1.
• Moved Tables 1 and 11 to page 18.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 15.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 16.
• Moved Table 1 to page 4.
• Moved Table 2 to page 5.
• Moved “Typical Performance Characteristics” to page 8.
• Updated "3. Pin Descriptions" on page 9.
• Updated "4. Ordering Guide" on page 10.
Revision 0.1
September 15, 2010
• Initial release.
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Rev. 2.15 | 43
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Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
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