SL28504-2
Clock Generator for Intel®Eaglelake Chipset
Features
• 25MHz Free run for WOL
• Selectable 25MHz/24.576MHz output
• Compliant to Intel® CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I2C support with readback capabilities
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clocks with selectable frequency
• 3.3V Power supply
• 100 MHz Differential SRC clocks
• 56-pin TSSOP packages
• 96 MHz Differential DOT clock
• 48 MHz USB clocks
• 33 MHz PCI clock
Block Diagram
Xin
Xout
SRC
PCI
REF
DOT96
USB_48
24.576M
25M
x8/x11
x6
x2
x1
x1
x1
x2
Pin Configuration
14.318MHz
Crystal
REF0
PLL Reference
CPU[1:0]
PLL1
Divider
SRC8/CPU2_ITP
PCI[4:0]; PCIF0
PLL3
Divider
SRC
SRC_SATA
25M0_F
PLL4
Divider
25M1_24.576M
PLL2
DOT96/SRC0
Divider
USB_48
SATA_SEL
CK_PWRGD/PD#
SDATA
SCLK
CPU
x2 / x3
Control Logic
PCI_0/ CR#_A
VDD_PCI
PCI_1/ CR#_B
PCI_2
PCI_3
PCI_4 / SRC5_EN
PCIF_0 / ITP_EN
VSS_PCI
VDD_48
USB_48 / FSA
VSS_48
VDD_IO
SRC0 / DOT96
SRC0# / DOT96#
VSS_IO
VDD_PLL3
SRC1/25M0_F
SRC1#/25M1_24.576M
VSS_PLL3
VDD_PLL3_IO
SRC2_SATA
SRC2#_SATA#
VSS_SRC
SRC3/ CR#_C
SRC3#/ CR#_D
VDD_SRC_IO
SRC4
SRC4#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SL28504-2
PCI_STOP#
CPU_STOP#
FSC:A]
SEL_24.576M
........................ DOC #: SP-AP-0051 (Rev. AA) Page 1 of 27
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FSB / TEST_MODE
CK_PWRGD / PWRDWN#
VDD_CPU
CPU0
CPU0#
VSS_CPU
CPU1
CPU1#
VDD_CPU_IO
*SEL_24.576M
SRC8 / CPU2_ITP
SRC8# / CPU2_ITP#
VDD_SRC_IO
SRC7/ CR#_F
SRC7#/ CR#_E
VSS_SRC
SRC6
SRC6#
VDD_SRC
SRC5/ PCI_STOP#
SRC5#/ CPU_STOP#
* Internal Pull-Down
1+(512) 416-9669
www.silabs.com
SL28504-2
56-TSSOP Pin Definitions
Pin No.
Name
1
PCI_0/ CR#_A
Type
Description
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI_0
2
VDD_PCI
3
PCI_1/ CR#_B
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI_1.
PWR
4
PCI_2
O, SE 33 MHz clock.
5
PCI_3
O, SE, 33 MHz clock.
6
PCI4 /SRC5_EN
I/O, SE 33 MHz clock output/3.3V-tolerant input for SRC enable
(Sampled on CKPWRGD assertion)
1 = SRC5, 0 =CPU_STOP#/PCI_STOP#
7
PCIF_0/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND
Ground for outputs.
9
VDD_48
PWR
3.3V Power supply for outputs and PLL.
10
USB_48/FSA
11
VSS_48
12
VDD_IO
13
SRC0/DOT96T
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
14
SRC0#/DOT96#
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
15
VSS_IO
16
17
I/O
3.3V Power supply for PCI PLL.
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer
to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
GND
Ground for outputs.
PWR
3.3V-1.05V Power supply for outputs.
GND
Ground for PLL2.
VDD_PLL3
PWR
3.3V Power supply for PLL3
SRC1/25M0_F
O, SE 100 MHz Differential serial reference clocks/ Free run 25MHz clock output
18
SRC1#/25M1_24.576M
O, SE 100 MHz Differential serial reference clocks/ 25MHz clock output/24.576MHz clock
output
19
VSS_PLL3
GND
Ground for PLL3.
20
VDD_PLL3_IO
PWR
3.3V-1.05V power supply for PLL3
21
SRC2_SATA
O, DIF 100 MHz Differential serial reference clocks.
22
SRC2#_SATA#
O, DIF 100 MHz Differential serial reference clocks.
23
VSS_SRC
24
SRC3/ CR#_C
I/O,
Dif
100-MHz Differential serial reference clocks / 3.3V CR#_C, input, mappable via
I2C to control either SRC 0 or SRC 2. Default SRC3
25
SRC3#/ CR#_D
I/O,
Dif
100-MHz Differential serial reference clocks / 3.3V CR#_D input, mappable via I2C
to control either SRC 1 or SRC 4. Default SRC3
26
VDD_SRC_IO
GND
PWR
Ground for outputs.
3.3V-1.05V power supply for SRC outputs.
27
SRC4
O, DIF 100 MHz Differential serial reference clocks.
28
SRC4#
O, DIF 100 MHz Differential serial reference clocks.
29
CPU_STOP#/SRC5#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference
clocks. The option is selected by SRC5_EN
30
PCI_STOP#/SRC5
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs./100 MHz Differential serial
reference clocks.The option is selected by SRC5_EN
31
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
........................ DOC #: SP-AP-0051 (Rev. AA) Page 2 of 27
SL28504-2
56-TSSOP Pin Definitions
Pin No.
32
SRC6#
Name
Type
Description
O, DIF 100 MHz Differential serial reference clocks.
33
SRC6
34
VSS_SRC
35
SRC7#/ CR#_E
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V CR#_E Input controlling SRC6.
Default SRC7.
36
SRC7/ CR#_F
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
Default SRC7.
37
VDD_SRC_IO
38
SRC8#/CPUC2_ITP#
O, DIF 100 MHz Differential serial reference clocks.
GND
PWR
Ground for outputs.
3.3V-1.05V power supply for SRC outputs.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
39
SRC8/CPUT2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
40
SEL_24.576M
I, PD
Select 25M1_24.576M output and SRC1
0 = 25M1, M= SRC1, 1 = 24.576M
PWR
3.3V-1.05V power supply for CPU outputs.
41
VDD_CPU_IO
42
CPU1#
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
43
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
44
VSS_CPU
45
CPU0#
O, DIF Differential CPU clock outputs.
46
CPU0
O, DIF Differential CPU clock outputs.
on the configuration set in Byte 11 Bit3:2.
on the configuration set in Byte 11 Bit3:2.
GND
PWR
Ground for outputs.
47
VDD_CPU
48
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
49
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
50
VSS_REF
GND
51
XTAL_OUT
O, SE 14.318 MHz Crystal output.
52
XTAL_IN
53
VDD_REF
54
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH. Refer to DC
Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
55
SMB_DATA
I/O
SMBus compatible SDATA.
56
SMB_CLK
I
I
PWR
3.3V Power supply for CPU PLL.
Ground for outputs.
14.318 MHz Crystal input.
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
SMBus compatible SCLOCK.
........................ DOC #: SP-AP-0051 (Rev. AA) Page 3 of 27
SL28504-2
Frequency Select Pin (FSA, FSB and FSC)
FSC
FSB
FSA
CPU
0
0
0
266 MHz
0
0
1
133 MHz
0
1
0
200 MHz
0
1
1
166 MHz
1
0
0
333 MHz
1
0
1
100 MHz
1
1
0
400 MHz
1
1
1
Reserved
SRC
PCIF/PCI
REF
DOT96
USB
100 MHz
33 MHz
14.318 MHz
96 MHz
48 MHz
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
Reserved
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
Table 1. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Block Read Protocol
Bit
1
8:2
9
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
Acknowledge from slave
27:21
Slave address–7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
........................ DOC #: SP-AP-0051 (Rev. AA) Page 4 of 27
37:30
Byte Count from slave–8 bits
SL28504-2
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
46
Description
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
Block Read Protocol
Bit
38
46:39
47
....
Acknowledge from slave
....
Stop
55:48
Description
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
Byte Read Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
28
Acknowledge from slave
29
Stop
18:11
19
20
27:21
Acknowledge from slave
Repeated start
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
........................ DOC #: SP-AP-0051 (Rev. AA) Page 5 of 27
Command Code–8 bits
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
SL28504-2
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
HW
FS_C
CPU Frequency Select Bit, set by HW
6
HW
FS_B
CPU Frequency Select Bit, set by HW
5
HW
FS_A
4
0
iAMT_EN
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
3
0
Reserved
Reserved
2
0
Reserved
1
0
SATA_SEL
Select source of SATA clock
0 =PLL3, 1= PLL4
0
1
PD_Restore
Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
CPU Frequency Select Bit, set by HW
Reserved
Byte 1: Control Register 1
Bit
@Pup
Name
7
0
SRC0_SEL
Description
6
0
PLL1_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
5
0
PLL3_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
1
Reserved
Reserved
0
1
PCI_SEL
Select source of PCI clocks
0=PLL1, 1=PLL3
Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
REF0_OE
Output enable for REF0
0 = Output Disabled, 1 = Output Enabled
6
1
USB48_OE
Output enable for USB48
0 = Output Disabled, 1 = Output Enabled
5
1
PCIF0_OE
Output enable for PCIF5
0 = Output Disabled, 1 = Output Enabled
4
1
PCI4_OE
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
3
1
PCI3_OE
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
2
1
PCI2_OE
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
1
1
PCI1_OE
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
0
1
PCI0_OE
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
........................ DOC #: SP-AP-0051 (Rev. AA) Page 6 of 27
SL28504-2
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
Reserved
Reserved
Description
6
1
Reserved
Reserved
5
1
Reserved
Reserved
4
1
SRC8/CPU2_ITP_OE
Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
3
1
SRC7_OE
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
2
1
SRC6_OE
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1
1
RESERVED
0
1
SRC4_OE
RESERVED
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
SRC3_OE
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6
1
SRC2_SATA_OE
Output enable for SRC2_SATA
0 = Output Disabled, 1 = Output Enabled
5
1
SRC1_OE
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
4
1
SRC0/DOT96_OE
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
3
1
CPU1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1
1
PLL1_SS_EN
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0
1
PLL3_SS_EN
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
CR#_A_EN
Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
6
0
CR#_A_SEL
Set CR#_A SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
5
0
CR#_B_EN
Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
4
0
CR#_B_SEL
Set CR#_B SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
3
0
CR#_C_EN
Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
2
0
CR#_C_SEL
Set CR#_C SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
........................ DOC #: SP-AP-0051 (Rev. AA) Page 7 of 27
SL28504-2
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
1
0
CR#_D_EN
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
0
0
CR#_D_EN
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
CR#_E_EN
Enable CR#_E (clk req) SRC6
0 = Disabled, 1 = Enabled
6
0
CR#_F_EN
Enable CR#_F (clk req) SRC8
0 = Disabled, 1 = Enabled
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
SRC_STP_CTRL
Allows control of SRC with assertion of PCI_STOP#
0 = Free running SRC 1 = Stopped with PCI_STOP#
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Rev Code Bit 3
Revision Code Bit 3
6
0
Rev Code Bit 2
Revision Code Bit 2
5
0
Rev Code Bit 1
Revision Code Bit 1
4
1
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
7
0
Device_ID3
6
0
Device_ID2
5
0
Device_ID1
4
0
Device_ID0
3
0
Reserved
Description
0000 = 56-TSSOP
0001 = 64-TSSOP
0010 = Reserved
0011 = 56-QFN
0100 = 64-QFN
0101 = Reserved
0110 = Reserved
0111 = 56-SSOP
1000 = Reserved
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Reserved
........................ DOC #: SP-AP-0051 (Rev. AA) Page 8 of 27
SL28504-2
Byte 8: Control Register 8 (continued)
Bit
@Pup
Name
Description
2
0
Reserved
1
1
25M0_F_OE
Output enable for 25M0_F
0 = Output Disabled, 1 = Output Enabled
0
1
25M1_24.576M_OE
Output enable for 25M1_24.576M
0 = Output Disabled, 1 = Output Enabled
Reserved
Byte 9: Control Register 9
Bit
@Pup
Name
7
0
PCIF5_STP_CTRL
6
0
Reserved
Reserved
5
1
REF Bit1
REF drive strength Setting 1 of 3 (see Byte 13 and 14 for more settings)
0 = Low, 1 = High
4
0
Reserved
3
0
TEST_MODE_ENTRY
2
1
I2C_VOUT
1
0
I2C_VOUT
0
1
I2C_VOUT
Description
Allows control of PCIF5 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
Reserved
Allows entry into test mode
0 = Normal Operation, 1 = Enter test mode(s)
I2C_VOUT[2:0]
000 = 0.30V
001 = 0.40V
010 = 0.50V
011 = 060V
100 = 0.70V
101 = 0.80V (default)
110 = 0.90V
111 = 1.00V
Byte 10: Control Register 10
Bit
@Pup
Name
7
HW
SRC5_EN
SRC5_EN latche status
0= CPU_STP#/PCI_STP#; 1= SRC5
Description
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
1
CPU1_STP_CTRL
Enable CPU_STOP# control of CPU1
0 = Free running, 1= Stoppable
0
1
CPU0_STP_CTRL
Enable CPU_STOP# control of CPU0
0 = Free running, 1= Stoppable
Byte 11: Control Register 11
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
1
25M0_F
25M0_F Output Enabled applies to Powerdown / M1
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
4
0
Reserved
Reserved
........................ DOC #: SP-AP-0051 (Rev. AA) Page 9 of 27
SL28504-2
Byte 11: Control Register 11 (continued)
3
0
CPU2_iAMT_EN
2
1
CPU1_iAMT_EN
1
0
Reserved
0
1
CPU2_STP_CRTL
PCIF5/ITP_EN
A MT_EN
CPU2_A MT_EN
CPU1_A MT_EN
x
1
0
0
Description
Reserved
x
1
0
1
CPU1 = M1 Clock
1
1
1
0
CPU2 - M1 Clock
1
1
1
1
CPU1 and CPU2 = M1 Clock
Reserved
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
Byte 12: Byte Count
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
BC5
Byte count
4
1
BC4
Byte count
3
0
BC3
Byte count
2
0
BC2
Byte count
1
1
BC1
Byte count
0
1
BC0
Byte count
Byte 13: Control Register 13
Bit
@Pup
Name
7
0
PCIF/PCI Bit 2
Description
6
1
PCIF/PCI Bit 1
5
0
PCIF/PCI Bit 0
Bit 2
Bit 1
Bit 0
4
0
USB Bit 2
(Various Bytes)
(Various Bytes)
(Various Bytes)
Buffer
Strength
3
1
USB Bit 1
1
1
1
Strongest
1
1
0
2
0
USB Bit 0
1
0
1
1
0
REF Bit 2
1
0
0
0
1
1
0
0
REF Bit 0
0
1
0
0
0
1
0
0
0
Drive Strength Control - Bit[2:0]
Note: REF Bit 1 is located in Byte 9 Bit 5
Default
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
25M_24.576M Bit 2
25M_24.576M Bit 2 drive strength
0 = Low, 1 = High
6
1
25M_24.576M Bit 1
25M_24.576M SE1/SE2 Bit 1 drive strength
0 = Low, 1 = High
5
0
25M_24.576M Bit 0
25M_24.576M Bit 0 drive strength
0 = Low, 1 = High
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
1
SATA_SS_EN
Enable SATA spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
...................... DOC #: SP-AP-0051 (Rev. AA) Page 10 of 27
Weakest
SL28504-2
Bit
@Pup
Name
Description
1
1
EN_CFG0_SET
By defalult CFG0 pin strap sets the SMBus initial values to select the HW
mode. When this bit is written0, subsequent SMBus accesses is the Lathes
Open state, can overwrite the CFG0 pin setting into the SMBus bits and set
the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5
0
1
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are
resumed in a synchronous manner with no short pulses.
Name
Description
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
Byte 15: Control Register 15
Bit
@Pup
7
0
CPU_DAF_N7
6
0
CPU_DAF_N6
5
0
CPU_DAF_N5
4
0
CPU_DAF_N4
3
0
CPU_DAF_N3
2
0
CPU_DAF_N2
1
0
CPU_DAF_N1
0
0
CPU_DAF_N0
Byte 16: Control Register 16
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
See Byte 14 for description
6
0
CPU_DAF_M6
5
0
CPU_DAF_M5
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
1
0
CPU_DAF_M1
0
0
CPU_DAF_M0
Byte 17: Control Register 17
Bit
@Pup
Name
7
0
PCI-E_N7
PCI-E Dial-A-Frequency® Bit N7
Description
6
0
PCI-E_N6
PCI-E Dial-A-Frequency Bit N6
5
0
PCI-E_N5
PCI-E Dial-A-Frequency Bit N5
4
0
PCI-E_N4
PCI-E Dial-A-Frequency Bit N4
3
0
PCI-E_N3
PCI-E Dial-A-Frequency Bit N3
2
0
PCI-E_N2
PCI-E Dial-A-Frequency Bit N2
1
0
PCI-E_N1
PCI-E Dial-A-Frequency Bit N1
0
0
PCI-E_N0
PCI-E Dial-A-Frequency Bit N0
Byte 18: Control Register 18
Bit
@Pup
Name
...................... DOC #: SP-AP-0051 (Rev. AA) Page 11 of 27
Description
SL28504-2
Byte 18: Control Register 18 (continued)
7
0
SMSW_EN
Enable Smooth Switching
0 = Disabled, 1= Enabled
6
0
SMSW_SEL
Smooth switch select
0 = PLL1, 1 = PLL3
5
0
Prog_PCI-E_EN
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
4
0
Prog_CPU_EN
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Table 4. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The SL28504-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the SL28504-2 to
operate at the wrong frequency and violates the ppm specification. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
C lo c k C h ip
C i2
C i1
P in
3 to 6 p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive
loading (CL).
X2
X1
C s1
C s2
T ra c e
2 .8 p F
XTAL
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
Ce1
Ce2
T r im
33pF
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
Figure 1. Crystal Capacitive Clarification
=
1
1
( Ce1 + Cs1
+ Ci1
+
1
Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
...................... DOC #: SP-AP-0051 (Rev. AA) Page 12 of 27
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
SL28504-2
Dial-A-Frequency® (CPU and PCIEX)
switch circuit is less than 1 MHz/0.667 s. The frequency
overshoot and undershoot is less than 2%.
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table ,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table , Frequency Select Table.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
PD_RESTORE
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the SL28504-2 initiates a full reset. The result of this is
that the clock chip emulates a cold power on start and goes to
the “Latches Open” state. If the PD_RESTORE bit is set to a
‘1’ then the configuration is stored upon PWRDWN# asserted
LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then
the PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PWRDWN# reset is not allowed.
Associated Register Bits
PWRDWN# (Power down) Clarification
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table , Frequency Select Table.
• CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table ,
Frequency Select Table
• SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
• SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table , Frequency Select Table.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
...................... DOC #: SP-AP-0051 (Rev. AA) Page 13 of 27
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD# is also an asynchronous input for powering
up the system. When PD# is asserted LOW, clocks are driven
to a LOW value and held before turning off the VCOs and the
crystal oscillator.
PWRDWN# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
PWRDWN# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 4 is an example showing the relationship of
clocks coming up.
SL28504-2
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power down Assertion Timing Waveform
Ts ta b le
< 1 .8 m s
PD#
C P U T , 1 3 3 MH z
C P U C , 1 3 3 MH z
S R C T 1 0 0 MH z
S R C C 1 0 0 MH z
U S B , 4 8 MH z
D OT 9 6 T
D OT 9 6 C
P C I, 3 3 MH z
REF
Td r iv e _ PW R D N #
2 00m V
Figure 4. Power down Deassertion Timing Waveform
Figure 5. CK_PWRGD Timing Diagram
...................... DOC #: SP-AP-0051 (Rev. AA) Page 14 of 27
SL28504-2
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
...................... DOC #: SP-AP-0051 (Rev. AA) Page 15 of 27
SL28504-2
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
PCI_STP# Assertion
.
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
T su
PC I_STP#
PC I_F
PC I
SR C 100M H z
Figure 10. PCI_STP# Assertion Waveform
.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transitions to a HIGH level.
T su
T d rive _S R C
P C I_S T P #
P C I_F
PC I
S R C 10 0M H z
Figure 11. PCI_STP# Deassertion Waveform
...................... DOC #: SP-AP-0051 (Rev. AA) Page 16 of 27
SL28504-2
.
Table 5. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
Single-ended Clocks Stoppable
Differential Clocks
CPU_STOP# Asserted
Driven low
Running
Non stoppable
Running
Running
Stoppable
Clock driven high
Clock driven high
Clock# driven low
Clock# driven low
Running
Running
Non stoppable
SMBus OE Disabled
Driven low
Clock driven Low or 20K
pulldown
Table 6. Output Driver Status
All Single-ended Clocks
w/o Strap
All Differential Clocks except
CPU1
w/ Strap
Clock
Clock#
CPU1
Clock
Clock#
Latches Open State
Low
Hi-z
Low or 20K pulldown Low
Low or 20K pulldown Low
Powerdown
Low
Hi-z
Low or 20K pulldown Low
Low or 20K pulldown Low
M1
Low
Hi-z
Low or 20K pulldown Low
Running
.
Figure 12. Clock Generator Power up/Run State Diagram
...................... DOC #: SP-AP-0051 (Rev. AA) Page 17 of 27
Running
SL28504-2
C l o c k O f f t o M1
3.3V
Vcc
2.0V
FSC
T_delay t
CPU_STOP#
FSB
FSA
PCI_STOP#
CKPWRGD/PWRDWN
Off
CK505 SMBUS
CK505 State
Latches Open
Off
M1
BSEL[0..2]
CK505 Core Logic
Off
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 13. BSEL Serial Latching
...................... DOC #: SP-AP-0051 (Rev. AA) Page 18 of 27
SL28504-2
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–
4.6
V
VDD_A
Analog Supply Voltage
–
4.6
V
VDD_IO
IO Supply Voltage
1.5
V
VIN
Input Voltage
Relative to VSS
–0.5
4.6
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating
Ambient
Functional
-40
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-STD-883E Method 1012.1
–
20
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
°C/
W
ESDHBM
ESD Protection (Human Body
Model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
At 1/8 in.
MSL
Moisture Sensitivity Level
Max.
Unit
3.135
3.465
V
2.0
VDD + 0.3
V
VSS – 0.3
0.8
V
2.2
–
V
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
VDD core
3.3V Operating Voltage
VIH
3.3V Input High Voltage (SE)
Condition
3.3 ± 5%
Min.
VIL
3.3V Input Low Voltage (SE)
VIHI2C
Input High Voltage
SDATA, SCLK
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIH_FS
FS_[A,B] Input High Voltage
0.7
1.5
V
VIL_FS
FS_[A,B] Input Low Voltage
VSS – 0.3
0.35
V
VIHFS_C_TEST
FS_C, SEL_24.576M Input
High Voltage
2
VDD + 0.3
V
0.7
2
V
VSS – 0.3
0.35
V
–
5
A
VIMFS_C_NORMAL FS_C, SEL_24.576M Input
Middle Voltage
VILFS_C_NORMAL
FS_C, SEL_24.576M Input Low
Voltage
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
SEL_24.576M_HI SEL_24.576M Input High
Voltage
GH
Typ. 2.75V
2.40
VDD
V
SEL_24.576M_MI SEL_24.576M Input Mid
Voltage
D
Typ. 1.65V
1.30
2.00
V
SEL_24.576M_LO SEL_24.576M Input Low
Voltage
W
Typ. 0.550V
0
0.900
V
–5
–
A
2.4
–
V
V
IIL
Input Low Leakage Current
VOH
Except internal pull-up resistors, 0 < VIN < VDD
VOL
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
–
0.4
VDD IO
Low Voltage IO Supply Voltage
1
3.465
VOH
3.3V Input High Voltage (DIFF)
0.70
0.90
V
VOL
3.3V Input Low Voltage (DIFF)
0.40
V
...................... DOC #: SP-AP-0051 (Rev. AA) Page 19 of 27
SL28504-2
DC Electrical Specifications
Min.
Max.
Unit
IOZ
Parameter
High-impedance Output
Current
Description
Condition
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Pin Inductance
–
7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
IDD3.3V
Dynamic Supply Current
–
250
mA
...................... DOC #: SP-AP-0051 (Rev. AA) Page 20 of 27
SL28504-2
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
TPERIOD
XIN Period
When XIN is driven from an external
clock source
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–
10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-s duration
–
500
ps
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential at 0.1s
45
55
%
TPERIOD
100 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
9.99900
10.0100
ns
TPERIOD
133 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
7.49925
7.50075
ns
TPERIOD
166 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
5.99940
6.00060
ns
TPERIOD
200 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
4.99950
5.00050
ns
TPERIOD
266 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
3.74963
3.75038
ns
TPERIOD
333 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
2.99970
3.00030
ns
TPERIOD
400 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
2.49975
2.50025
ns
TPERIODSS
100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODSS
133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
7.51804
7.51955
ns
TPERIODSS
166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
6.01444
6.01564
ns
TPERIODSS
200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
5.01203
5.01303
ns
TPERIODSS
266 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
3.75902
3.75978
ns
TPERIODSS
333 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
3.00722
3.00782
ns
TPERIODSS
400 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
2.50601
2.50652
ns
TPERIODAbs
100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
9.91400
10.0860
ns
TPERIODAbs
133 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
7.41425
7.58575
ns
TPERIODAbs
166 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
5.91440
6.08560
ns
TPERIODAbs
200 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
4.91450
5.08550
ns
TPERIODAbs
266 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
3.66463
3.83538
ns
TPERIODAbs
333 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
2.91470
3.08530
ns
TPERIODAbs
400 MHz CPUT and CPUC Absolute
period
Measured at 0V differential @ 1 clock
2.41475
2.58525
ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
9.91406
10.1362
ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
7.41430
7.62340
ns
TPERIODSSAbs 166 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
5.91444
6.11572
ns
TPERIODSSAbs 200 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
4.91453
5.11060
ns
TPERIODSSAbs 266 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
3.66465
3.85420
ns
CPU at 0.7V
...................... DOC #: SP-AP-0051 (Rev. AA) Page 21 of 27
SL28504-2
AC Electrical Specifications (continued)
Min.
Max.
Unit
TPERIODSSAbs 333 MHz CPUT and CPUC Absolute
period, SSC
Parameter
Description
Measured at 0V differential @ 1 clock
Condition
2.91472
3.10036
ns
TPERIODSSAbs 400 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
2.41477
2.59780
ns
–
85
ps
TCCJ
CPU Cycle to Cycle Jitter
Measured at 0V differential
TCCJ2
CPU2_ITP Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
TSKEW
CPU0 to CPU1 Clock Skew
Measured at 0V differential
–
100
ps
TSKEW2
CPU2_ITP to CPU0 Clock Skew
Measured at 0V differential
–
150
ps
T R / TF
CPU Rising/Falling Slew rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential @ 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
Measured at 0V differential @ 1 clock
9.87406
10.1762
ns
–
3.0
ns
–
125
ps
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential
bank to the latest bank
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
LACC
SRC Long Term Accuracy
Measured at 0V differential
–
100
ppm
T R / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
DOT96 at 0.7V
TDC
DOT96 Duty Cycle
Measured at 0V differential
45
55
%
10.4177
ns
ns
TPERIOD
DOT96 Period
Measured at 0V differential at 0.1s
10.4156
TPERIODAbs
DOT96 Absolute Period
Measured at 0V differential at 0.1s
10.1656
10.6677
TCCJ
DOT96 Cycle to Cycle Jitter
Measured at 0V differential at 1 clock
–
250
ps
LACC
DOT96 Long Term Accuracy
Measured at 0V differential at 1 clock
–
100
ppm
T R / TF
DOT96 Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
VLOW
Voltage Low
VOX
Crossing Point Voltage at 0.7V Swing
TRFM
Rise/Fall Matching
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
Measured single-endedly from ±75 mV
PCI/PCIF at 3.3V
...................... DOC #: SP-AP-0051 (Rev. AA) Page 22 of 27
1.15
V
–0.3
–
V
300
550
mV
–
20
%
SL28504-2
AC Electrical Specifications (continued)
Parameter
Description
TDC
PCI Duty Cycle
Min.
Max.
Unit
Measurement at 1.5V
Condition
45
55
%
TPERIOD
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.99700
30.00300
ns
TPERIODSS
Spread Enabled PCIF/PCI Period
Measurement at 1.5V
30.08421
30.23459
ns
TPERIODAbs
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
29.49700
30.50300
ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period
Measurement at 1.5V
29.56617
30.58421
ns
THIGH
Spread Enabled PCIF and PCI high time Measurement at 2V
12.27095
16.27995
ns
TLOW
Spread Enabled PCIF and PCI low time Measurement at 0.8V
11.87095
16.07995
ns
THIGH
Spread Disabled PCIF and PCI high
time
12.27365
16.27665
ns
TLOW
Spread Disabled PCIF and PCI low time Measurement at 0.8V
11.87365
16.07665
ns
TR / TF
PCIF/PCI Rising/Falling Slew Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
Any PCI clock to Any PCI clock Skew
Measurement at 1.5V
–
1000
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
LACC
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
–
100
ppm
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.83125
20.83542
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125
21.18542
ns
THIGH
48_M High time
Measurement at 2V
8.216563
11.15198
ns
TLOW
48_M Low time
Measurement at 0.8V
7.816563
10.95198
ns
TR / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
LACC
48M Long Term Accuracy
Measurement at 1.5V
–
100
ppm
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
39.996
40.004
ns
TR/TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
500
ps
LACC
25M Long Term Accuracy
Measurement at 1.5V
–
50
ppm
%
Measurement at 2.V
48_M at 3.3V
25_M
1394A - 24.576M
TDC
Duty Cycle
Measurement at 1.5V
45
55
TPERIOD
Period
Measurement at 1.5V
40.686
40.694
ns
TR/TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
200
ps
LACC
24M Long Term Accuracy
Measurement at 1.5V
–30
30
ppm
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.82033
69.86224
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.83429
70.84826
ns
THIGH
REF High time
Measurement at 2V
29.97543
38.46654
ns
TLOW
REF Low time
Measurement at 0.8V
29.57543
38.26654
ns
TR / TF
REF Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
REF Clock to REF Clock
Measurement at 1.5V
–
500
ps
REF
...................... DOC #: SP-AP-0051 (Rev. AA) Page 23 of 27
SL28504-2
AC Electrical Specifications (continued)
Min.
Max.
Unit
TCCJ
Parameter
REF Cycle to Cycle Jitter
Description
Measurement at 1.5V
Condition
–
1000
ps
LACC
Long Term Accuracy
Measurement at 1.5V
–
100
ppm
–
1.8
ms
10.0
–
ns
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
L1
22
50
PCI/USB
Measurement
Point
L2
L1 = 0.5", L2 = 8"
4 pF
Measurement
Point
50
22
L1
L2
4 pF
Figure 14. Single-ended PCI and USB Double Load Configuration
L1
15
L2
50
REF
Measurement
Point
4 pF
L1
15
L2
50
Measurement
Point
4 pF
L1
15
L2
50
Measurement
Point
4 pF
Figure 15. Single-ended REF Triple Load Configuration
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
For CPU, SRC, and DOT96 Signals and Reference
This diagram shows the test load configuration for the differential CPU and SRC outputs
...................... DOC #: SP-AP-0051 (Rev. AA) Page 24 of 27
SL28504-2
Figure 17. 0.7V Differential Load Configuration
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0V
0.0V
Clck-Clck#
Rise
Edge
Rate
Fall
Edge
Rate
VIH = +150V
VIH = +150V
0.0V
0.0V
VIL = -150V
VIL = -150V
Clock-Clock#
Figure 18. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
V M A X = 1 .1 5 V
V M A X = 1 .1 5 V
CLK#
V c ro s s M A X = 5 5 0 m V
V c ro s s M A X = 5 5 0 m V
V c ro s s M IN = 3 0 0 m V
V c ro s s M IN = 3 0 0 m V
CLK
V M IN = 0 .3 0 V
V M IN = 0 .3 0 V
CLK#
V c ro s s d e lta = 1 4 0 m V
V c ro s s d e lta = 1 4 0 m V
CLK#
V c ro s s m e d ia n + 7 5 m V
V c ro s s m e d ia n
V c ro s s m e d ia n -7 5 m V
CLK
ise
Tr
V c ro s s m e d ia n
T
fa
ll
CLK#
CLK
Figure 19. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
...................... DOC #: SP-AP-0051 (Rev. AA) Page 25 of 27
SL28504-2
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
SL28504BZC-2
56-pin TSSOP
Commercial, 0 to 85C
SL28504BZC-2T
56-pin TSSOP–Tape and Reel
Commercial, 0 to 85C
SL28504BZI-2
56-pin TSSOP
Commercial, -40 to 85C
SL28504BZI-2T
56-pin TSSOP–Tape and Reel
Commercial, -40 to 85C
SL 28 504 B Z C 2 T
Packaging Designator for Tape and Reel
Derivatives of a Generic Part
Temperature Designator
C : Commercial spec; I: Industrial Spec
Package Designator
Z : TSSOP;
Revision Number
A = 1st revision; B = 2nd revision......
Generic Part Number
Designated Family Number
Company Initials
Package Diagrams
56-Lead Thin Shrunk Small Outline Package Type II (6 mm x 12 mm) Z56
51-85153-*A
...................... DOC #: SP-AP-0051 (Rev. AA) Page 26 of 27
SL28504-2
Document History Page
Document Title: SL28504-2 Clock Generator for Intel®Eaglelake Chipset
DOC #: SP-AP-0051 (Rev. AA)
Issue Date
Orig. of
Change
1.0
10/5/07
BSHEN
Initial Release
1.1
10/16/07
BSHEN
Add SRC1 to pin 17/18. and tri-level trigger at 24.576M
1.2
01/21/08
BSHEN
1. Change Revision ID Byte7[7:4] to be 0001
2. Updated block diagram
3. Change Byte10[6:2] and Byte11[4] to be reserved
1.3
07/26/09
BSHEN
1. Updated Package Dimensions to compliant to SLI POD specification
2. Updated the CR# pin & register
3. Remove PCIE Gen II compliant on Feature
04/29/09
BSHEN
1. Correct VDD_IO pin description
2. Updated Industrial ordering information
3. Change document format for ISO complaint
REV.
AA
ECR#
1575
Description of Change
...................... DOC #: SP-AP-0051 (Rev. AA) Page 27 of 27
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