SL28506-2
Clock Generator for Intel® Eaglelake Chipset
Features
• 25 MHz Video clocks
• Intel® CK505 Rev. 1.0 Compliant
• Low power push-pull type differential output buffers
• PCI-Express Gen 2 Compliant SRC clocks (exclude
SRC0 and SRC1)
• 8-step programmable drive strength for single-ended
clocks
• 1396 Firewire clock
• Buffered Reference Clock 14.318 MHz
• 14.318 MHz Crystal Input or Clock Input
• Low-voltage frequency select input
• I2C support with readback capabilities
• Differential CPU clocks with selectable frequency
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 100 MHz Differential SRC clocks
• Industrial Temperature -40°C to 85°C
• 100 MHz Differential LCD clock
• 3.3V Power supply
• 96 MHz Differential DOT clock
• 56-pin TSSOP packages
• 48 MHz USB clock
• 33 MHz PCI clocks
• 27MHz non-spread Video clock
CPU
SRC
x2 / x3
x4/9
Block Diagram
PCI REF DOT96 USB_48 LCD
x6
x1
x1
x1
x1
Pin Configuration
* 100K-ohm Internal Pull Down
......................... DOC #: SP-AP-0021 (Rev AB) Page 1 of 27
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SE
x2
SL28506-2
56 TSSOP Pin Definition
Pin No.
Name
1
PCI0/OE#_0/2_A
Type
Description
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or
SRC2. (Default PCI0, 33MHz clock)
2
VDD_PCI
3
PCI1/OE#_1/4_B
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or
SRC4. (Default PCI1, 33MHz clock)
PWR
4
PCI2/TME
I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
5
PCI3/CFG0
I/O, SE, 3.3V tolerant input for CPU frequency selection/3.3V 33MHz clock.
PD
(Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and
Vih_PCI3/CFG0 specifications).
6
PCI4/SRC5_EN
I/O, SE 3.3V tolerant input to enable SRC5/3.3V, 33MHz clock.
(Sampled on the CKPWRGD assertion)
1 = SRC5, 0 = CPU_STP#
7
PCIF/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/3.3V, 33MHz clock.
(Sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND
9
VDD_48
PWR
10
USB_48/FSA
11
VSS_48
I/O
3.3V Power supply for PCI PLL.
Ground for outputs.
3.3V Power supply for outputs and PLL.
3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
GND
Ground for outputs.
PWR
0.7V Power supply for outputs.
12
VDD_IO
13
SRC0/DOT96
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
14
SRC0#/DOT96#
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
15
VSS_IO
GND
Ground for PLL2.
PWR
3.3V Power supply for PLL3
16
VDD_PLL3
17
SRC1/LCD100/SE1
O, DIF, 100MHz Differential serial reference clocks/100MHz LCD video clock/SE1 clocks.
SE
(Default SRC1, 100MHz clock)
18
SRC1#/LCD100#/SE2
O, DIF, 100MHz Differential serial reference clocks/100MHz LCD video clock/SE2 clocks.
SE
(Default SRC1, 100MHz clock)
19
VSS_PLL3
20
21
GND
Ground for PLL3.
VDD_PLL3_IO
PWR
IO Power supply for PLL3 outputs.
SRC2/SATA
O, DIF 100MHz Differential serial reference clocks.
22
SRC2#/SATA#
O, DIF 100MHz Differential serial reference clocks.
23
VSS_SRC
24
SRC3/OE#_0/2_B
I/O,
Dif
100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable
via I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)
25
SRC3#OE#_1/4_B
I/O,
Dif
100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable
via I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)
GND
Ground for outputs.
.........................DOC #: SP-AP-0021 (Rev AB) Page 2 of 27
SL28506-2
56 TSSOP Pin Definition (continued)
Pin No.
Name
26
VDD_SRC_IO
Type
PWR
27
SRC4
O, DIF 100MHz Differential serial reference clocks.
28
SRC4#
O, DIF 100MHz Differential serial reference clocks.
29
SRC5#CPU_STP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs/100MHz Differential serial reference
clocks.
30
SRC5/PCI_STP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs/100MHz Differential serial
reference clocks.
31
VDD_SRC
32
SRC6#
O, DIF 100MHz Differential serial reference clocks.
33
SRC6
O, DIF 100MHz Differential serial reference clocks.
34
VSS_SRC
35
SRC7#/OE#_6
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
36
SRC7/OE#_8
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
37
VDD_SRC_IO
PWR
38
SRC8#/CPU2#_ITP#
PWR
GND
Description
IO power supply for SRC outputs.
3.3V Power supply for SRC PLL.
Ground for outputs.
0.7V power supply for SRC outputs.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
39
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
40
IO_VOUT
PWR
Integrated Linear Regulator Control.
PWR
IO Power supply for CPU outputs.
41
VDD_CPU_IO
42
CPU1#
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
43
CPU1
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
44
VSS_CPU
45
CPU#0
O, DIF Differential CPU clock outputs.
46
CPU0
O, DIF Differential CPU clock outputs.
47
VDD_CPU
48
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
49
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
50
VSS_REF
GND
51
XOUT
O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
52
XIN/CLKIN
I
53
VDD_REF
PWR
on the configuration set in Byte 11 Bit3:2)
on the configuration set in Byte 11 Bit3:2)
GND
PWR
Ground for outputs.
3.3V Power supply for CPU PLL.
Ground for outputs.
14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
.........................DOC #: SP-AP-0021 (Rev AB) Page 3 of 27
SL28506-2
56 TSSOP Pin Definition (continued)
Pin No.
Name
54
REF0/FSC/TEST_SEL
Type
I/O
55
SMB_DATA
I/O
56
SMB_CLK
I
Description
3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer
to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
SMBus compatible SDATA.
SMBus compatible SCLOCK.
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
FSB
FSA
CPU
0
0
0
266MHz
0
0
1
133MHz
0
1
0
200MHz
0
1
1
166MHz
1
0
0
333MHz
1
0
1
100MHz
1
1
0
400MHz
1
1
1
200MHz
SRC
PCIF/PCI
27MHz
REF
DOT96
USB
100MHz
33MHz
27MHz
14.318MHz
96MHz
48MHz
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CKPWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CKPWRGD and indicates that VTT voltage is stable then FSA,
FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CKPWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
Table 2. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
Block Read Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
.........................DOC #: SP-AP-0021 (Rev AB) Page 4 of 27
SL28506-2
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
18:11
19
27:20
28
36:29
37
45:38
Description
Command Code–8 bits
Block Read Protocol
Bit
18:11
Description
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
20
Repeat start
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
27:21
Read = 1
29
Acknowledge from slave
37:30
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
Slave address–7 bits
28
38
46:39
47
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Byte Read Protocol
Bit
1
8:2
9
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
28
29
37:30
.........................DOC #: SP-AP-0021 (Rev AB) Page 5 of 27
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
SL28506-2
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
HW
FS_C
CPU Frequency Select Bit, set by HW
6
HW
FS_B
CPU Frequency Select Bit, set by HW
5
HW
FS_A
4
0
iAMT_EN
3
0
RESERVED
2
0
SRC_MAIN_SEL
1
0
SATA_SEL
Select source of SATA clock
0 = SATA SRC_MAIN, 1= SATA PLL2
0
1
PD_Restore
Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
CPU Frequency Select Bit, set by HW
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled, Sticky 1
RESERVED
Select source for SRC clock,
0 = SRC_MAIN = PLL1, PLL3_CFB Table applies
1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply
Byte 1: Control Register 1
Bit
@Pup
Name
7
0
SRC0_SEL
Description
6
0
PLL1_SS_DC
Select for down or center SS,
0 = Down spread, 1 = Center spread
5
0
PLL3_SS_DC
Select for down or center SS,
0 = Down spread, 1 = Center spread
4
0
PLL3_CFB3
Bit 4:1 only apply when SRC_SEL=0
3
0
PLL3_CFB2
2
0
PLL3_CFB1
1
1
PLL3_CFB0
Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96
0000 = PLL3 Disable Default
PLL3 OFF, SRC1 = SRC_MAIN
0001 = 100 MHz 0.5% SSC Stby PLL3 ON, SRC1 = SRC_MAIN
0010 = 100 MHz 0.5% SSC
Only SRC1 sourced from PLL3
0011 = 100 MHz 1.0% SSC
Only SRC1 sourced from PLL3
0100 = 100 MHz 1.5% SSC
Only SRC1 sourced from PLL3
0101 = 100 MHz 2.0% SSC
Only SRC1 sourced from PLL3
0110 = RESERVED
Note: SE clocks required to be
0111 = RESERVED
enabled through Byte 8 Bit[1:0]
1000 = 1394A(24.576M) on SE1 and SE2
1001 = 1394A(24.576M) on SE1 and 1394B (98.304M) on SE2
1010 = 1394B on SE1 and SE2
1011 = 27MHz_NSS on SE1 and SE2
1100 = 25MHz on SE1 and SE2
1101 = 25MHz on SE1 and SE2 Disabled (set whenPCI3/CFB0 is set high to
config to HW mode 3)
1110 = RESERVED
1111 = RESERVED
0
1
PCI_SEL
Select PCI Clock source from PLL1 or SRC_MAIN
0 = PLL1, 1 = SRC_MAIN
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
REF_OE
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
Description
6
1
USB_OE
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
.........................DOC #: SP-AP-0021 (Rev AB) Page 6 of 27
SL28506-2
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
5
1
PCIF0_OE
Output enable for PCIF0
0 = Output Disabled, 1 = Output Enabled
4
1
PCI4_OE
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
3
1
PCI3_OE
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
2
1
PCI2_OE
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
1
1
PCI1_OE
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
0
1
PCI0_OE
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
RESERVED
RESERVED
6
1
RESERVED
RESERVED
5
1
RESERVED
RESERVED
4
1
SRC8/ITP_OE
3
1
SRC7_OE
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
2
1
SRC6_OE
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1
1
SRC5_OE
Output enable for SRC5
0 = Output Disabled, 1 = Output Enabled
0
1
SRC4_OE
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
7
1
SRC3_OE
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
Description
6
1
SRC2/SATA_OE
Output enable for SATA/SRC2
0 = Output Disabled, 1 = Output Enabled
5
1
SRC1_OE
Output enable for SRC
0 = Output Disabled, 1 = Output Enabled
4
1
SRC0/DOT96_OE
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
3
1
CPU1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1
1
PLL1_SS_EN
Enable PLL1’s spread modulation,
0 = Spread Disabled 1 = Spread Enabled
0
1
PLL3_SS_EN
Enable PLL3’s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
.........................DOC #: SP-AP-0021 (Rev AB) Page 7 of 27
SL28506-2
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
OE#_0/2_EN_A
Enable OE#_0/2 (clk req)
0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2,
Description
6
0
OE#_0/2_SEL_A
Set OE#_0/2 SRC0 or SRC2
0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2
5
0
OE#_1/4_EN_A
Enable OE#_1/4 (clk req)
0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,
4
0
OE#_1/4_SEL_A
Set OE#_1/4 SRC1 or SRC4
0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4
3
0
OE#_0/2_EN_B
Enable OE#_0/2 (clk req)
0 = Disabled OE#_0/2 1 = Enabled OE#_0/2
2
0
OE#_0/2_SEL_B
Set OE#_0/2 SRC0 or SRC2
0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2
1
0
OE#_1/4_EN_B
Enable OE#_1/4 (clk req)
0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,
0
0
OE#_1/4_SEL_B
Set OE#_1/4 SRC1 or SRC4
0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4
Byte 6: Control Register 6
Bit
@Pup
Name
7
0
OE#_6_EN
Enable OE#_6 (clk req) SRC6
Description
6
0
OE#_8_EN
Enable OE#_8 (clk req) SRC8
5
0
OE#_9_EN
Enable OE#_9 (clk req) SRC9
4
0
OE#_10_EN
Enable OE#_10 (clk req) SRC10
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
LCD_100_STP_CTRL
0
0
SRC_STP_CTRL
Allows control of LCD_100 with assertion of PCI_STP#
0 = Free runningLCD_100, 1 = Stopped with PCI_STP#
Allows control of SRC with assertion of PCI_STP#
0 = Free running SRC 1 = Stopped with PCI_STP#
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Rev Code Bit 3
Revision Code Bit 3
6
0
Rev Code Bit 2
Revision Code Bit 2
5
0
Rev Code Bit 1
Revision Code Bit 1
4
1
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
.........................DOC #: SP-AP-0021 (Rev AB) Page 8 of 27
SL28506-2
Byte 8: Control Register 8
Bit
@Pup
Name
7
0
Device_ID3
Description
6
0
Device_ID2
5
0
Device_ID1
4
0
Device_ID0
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
SE1_OE
SE1 Output enable 0 = Output Disabled, 1 = Output Enabled
0
0
SE2_OE
SE2 Output enable 0 = Output Disabled, 1 = Output Enabled
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
0010 = CK505 Yellow Cover Device, 48-pin QFN (reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN (reserved)
0101 = CK505 Yellow Cover Device, 72-pin QFN (reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (reserved)
0111 = CK505 Yellow Cover Device, 56-pin SSOP (reserved)
1000 = Reserved
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Byte 9: Control Register 9
Bit
@Pup
Name
7
0
PCIF0_STP_CTRL
6
HW
TME_STRAP
5
1
REF_Bit1
4
0
TEST_MODE_SEL
3
0
TEST_MODE_ENTRY
2
1
IO_VOUT2
1
0
IO_VOUT1
0
1
IO_VOUT0
Description
Allows control of PCIF0 with assertion of PCI_STP#
0 = Free running PCIF, 1 = Stopped with PCI_STP#
Trusted mode enable strap status, 0 = normal, 1 = no overclocking
REF drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
Allow entry into test mode
0=Normal operation, 1=Enter test mode
IO_VOUT[2,1,0]
000 = 0.3V
001 = 0.4V
010 = 0.5V
011 = 0.6V
100 = 0.7V
101 = 0.8V, Default
110 = 0.9V
111 = 1.0V
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
HW
SRC5_EN_STRAP
6
1
PLL3_EN
PLL3 Enabled
0 = PLL3 disabled, 1 = PLL3 enabled
5
1
PLL2_EN
PLL2 Enabled
0 = PLL2 disabled, 1 = PLL2 enabled
4
1
SRC_DIV_EN
Read only bit for SRC5_EN_STRAP
0 = CPU/PCI_STP enabled, 1 = SRC5 pair enabled
SRC Divider Enabled
0 = SRC Divider disabled, 1 = SRC Divider enabled
.........................DOC #: SP-AP-0021 (Rev AB) Page 9 of 27
SL28506-2
Byte 10: Control Register 10 (continued)
Bit
@Pup
Name
Description
3
1
PCI_DIV_EN
PCI Divider Enabled
0 = PCI Divider disabled, 1 = PCI Divider enabled
2
1
CPU_DIV_EN
CPU Divider Enabled
0 = CPU Divider disabled, 1 = CPU Divider enabled
1
1
CPU1_STP_CRTL
Allow control of CPU1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU0_STP_CRTL
Allow control of CPU0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 11: Control Register 11
Bit
@Pup
Name
7
HW
PCI3_CFG1
6
HW
PCI3_CFG0
5
0
25MHz_EN_SE1
Description
CFG
[1:0]
PCI2/T PCI3/
ME CGF0
PLL1
PLL2
Mode
Output
SSC
Output
SSC
00
x
Low
0 -Def
CPU / SRC / PCI33
Dow n
USB
NA
01
x
Mid
1
CPU
Dow n
USB
NA
10
0
High
2
CPU
Center
USB
NA
25MHz Output Enabled applies to Powerdown / M1
(Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3)
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
4
1
RESERVED
3
0
CPU2_AMT_EN
2
1
CPU1_AMT_EN
1
1
PCI-E_GEN2
0
1
CPU2_STP_CRTL
RESERVED
PCIF0/ITP_EN
AMT_EN
CPU2_AMT_EN
CPU1_AMT_EN
x
1
0
0
Description
Reserved
x
1
0
1
CPU1 = M1 Clock
1
1
1
0
CPU2 - M1 Clock
1
1
1
1
CPU1 and CPU2 = M1 Clock
PCI-E_Gen2 Compliant (Read Only bit)
0 = non Gen2, 1= Gen2 Compliant
Allow control of CPU2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 12: Byte Count
Bit
@Pup
Name
7
0
RESERVED
Description
6
0
RESERVED
5
0
BC5
Byte count
4
0
BC4
Byte count
3
1
BC3
Byte count
2
1
BC2
Byte count
1
0
BC1
Byte count
0
1
BC0
Byte count
RESERVED
RESERVED
.......................DOC #: SP-AP-0021 (Rev AB) Page 10 of 27
SL28506-2
Byte 13: Control Register 13
Bit
@Pup
Name
7
1
USB_Bit1
USB drive strength control, See Byte 18 for more setting
0 = Low, 1= High
Description
6
1
PCI/PCIF_Bit1
PCI drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
5
0
PLL1_Spread
Select percentage of spread for PLL1
0 = 0.5%, 1=0.45%
4
0
SATA_SS_EN
Enable SATA spread modulation,
0 = Spread Disabled 1 = Spread Enabled
3
1
EN_CFG0_SET
2
1
SE1/SE2_Bit1
1
1
RESERVED
0
1
SW_PCI
By defalult CFG0 pin strap sets the SMBus initial values to select the HW
mode. When this bit is written0, subsequent SMBus accesses is the Lathes
Open state, can overwrite the CFG0 pin setting into the SMBus bits and set
the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5
SE1 and SE2 drive strength control, See Byte 18 for more setting
0 = Low, 1 = High
RESERVED
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
CPU_DAF_N7
6
0
CPU_DAF_N6
5
0
CPU_DAF_N5
4
0
CPU_DAF_N4
3
0
CPU_DAF_N3
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The
setting of the FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[C:A] register will be used. When it is set, the frequency ratio
stated in the FSEL[2:0] register will be used
2
0
CPU_DAF_N2
1
0
CPU_DAF_N1
0
0
CPU_DAF_N0
Byte 15: Control Register 15
Bit
@Pup
Name
Description
7
0
CPU_DAF_N8
See Byte 14 for description
6
0
CPU_DAF_M6
5
0
CPU_DAF_M5
4
0
CPU_DAF_M4
3
0
CPU_DAF_M3
2
0
CPU_DAF_M2
If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency. The setting of the FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared, the same
frequency ratio stated in the Latched FS[C:A] register will be used. When it
is set, the frequency ratio stated in the FSEL[2:0] register will be used
1
0
CPU_DAF_M1
0
0
CPU_DAF_M0
Byte 16: Control Register 16
Bit
@Pup
Name
....................... DOC #: SP-AP-0021 (Rev AB) Page 11 of 27
Description
SL28506-2
Byte 16: Control Register 16
7
0
PCI-E_N7
6
0
PCI-E_N6
5
0
PCI-E_N5
4
0
PCI-E_N4
3
0
PCI-E_N3
2
0
PCI-E_N2
1
0
PCI-E_N1
0
0
PCI-E_N0
If Prog_SRC_EN is set, the values programmed in SRC_DAF_N[7:0] will
be used to determine the SRC output frequency.
Byte 17: Control Register 17
Bit
@Pup
Name
7
0
SMSW_EN
6
0
SMSW_SEL
Smooth switch select, 0 = CPU_PLL, 1 = SRC_PLL
5
0
RESERVED
RESERVED
4
0
Prog_PCI-E_EN
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
3
0
Prog_CPU_EN
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 18: Control Register 18
Bit
@Pup
Description
Enable Smooth Switching, 0 = Disabled, 1= Enabled
Name
Description
7
0
PCIF/PCI_Bit2
6
1
PCIF/PCI_Bit0
5
0
USB_Bit2
4
0
USB_Bit0
3
0
Drive Strength Control - Bit[2:0]
Bit 2
(Byte18)
1
(Vario us B ytes)
1
Bit 0
(Byte 18)
1
1
1
0
1
0
1
1
0
0
Def ault PCI
0
1
1
Def ault REF/Usb
0
1
0
0
0
1
0
0
0
SE1/SE2_Bit2
2
0
SE1/SE2_Bit0
1
0
REF_Bit2
0
0
REF_Bit0
Bit 1
Buf f er
Strength
Strongest
Weakest
Table 5. Output Driver Status during PCI-STP# and CPU-STP#
PCI_STP# Asserted
Single-ended Clocks Stoppable
Differential Clocks
CPU_STP# Asserted
Driven low
Running
Non stoppable
Running
Running
Stoppable
Clock driven high
Clock driven high
Clock# driven low
Clock# driven low
Running
Running
Non stoppable
.......................DOC #: SP-AP-0021 (Rev AB) Page 12 of 27
SMBus OE Disabled
Driven low
Clock driven Low or 20K
pulldown
SL28506-2
Table 6. Output Driver Status
All Single-ended Clocks
w/o Strap
All Differential Clocks except
CPU1
w/ Strap
Clock
Clock#
CPU1
Clock
Clock#
Latches Open State
Low
Hi-z
Low or 20K pulldown Low
Low or 20K pulldown Low
Powerdown
Low
Hi-z
Low or 20K pulldown Low
Low or 20K pulldown Low
M1
Low
Hi-z
Low or 20K pulldown Low
Running
Running
Table 7. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The SL28506-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the SL28506-2 to
operate at the wrong frequency and violates the ppm specification. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance
Figure 1. Crystal Capacitive Clarification
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
.......................DOC #: SP-AP-0021 (Rev AB) Page 13 of 27
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
Dial-A-Frequency® (CPU andSRC)
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
SL28506-2
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
Associated Register Bits
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
• CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table 1,
Frequency Select Table
• SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
• SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 s. The frequency
overshoot and undershoot is less than 2%.
.......................DOC #: SP-AP-0021 (Rev AB) Page 14 of 27
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PD# LOW,
the SL28506-2 initiates a full reset. The result of this is that the
clock chip emulates a cold power on start and goes to the
“Latches Open” state. If the PD_RESTORE bit is set to a ‘1’
then the configuration is stored upon PD# asserted LOW. Note
that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the
PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PD# reset is not allowed.
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 4 is an example showing the relationship of
clocks coming up.
SL28506-2
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power down Assertion Timing Waveform
Ts ta b le
< 1 .8 m s
PD#
C P U T , 1 3 3 MH z
C P U C , 1 3 3 MH z
S R C T 1 0 0 MH z
S R C C 1 0 0 MH z
U S B , 4 8 MH z
D OT 9 6 T
D OT 9 6 C
P C I, 3 3 MH z
Td r iv e _ PW R D N #
2 00m V
REF
Figure 4. Power down Deassertion Timing Waveform
FS _A, FS _B ,FS_C ,FS _D
CKPWRGD
P W R G D _V R M
0.2-0.3 m s
D elay
V D D C lock G en
C lock S tate
C lock O utputs
C lock V C O
S tate 0
W ait for
V TT_PW R G D #
S tate 1
D evice is not affected,
V TT_P W R G D # is ignored
S am ple S els
State 2
O ff
State 3
On
On
O ff
Figure 5. CKPWRGD Timing Diagram
.......................DOC #: SP-AP-0021 (Rev AB) Page 15 of 27
SL28506-2
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
PCI_STP# Assertion
.
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 8.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
T su
PC I_STP#
PC I_F
PC I
SR C 100M H z
Figure 8. PCI_STP# Assertion Waveform
.......................DOC #: SP-AP-0021 (Rev AB) Page 16 of 27
SL28506-2
.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transitions to a HIGH level.
T su
T drive_ S R C
P C I_S T P #
P C I_F
PCI
SR C 100 M H z
Figure 9. PCI_STP# Deassertion Waveform
.
.
Figure 10. Clock Generator Power up/Run State Diagram
.......................DOC #: SP-AP-0021 (Rev AB) Page 17 of 27
SL28506-2
Clock Off to M 1
3.3V
Vcc
2.0V
FSC
T_delay t
CPU_STP#
FSB
FSA
PCI_STP#
CKPWRGD/PD#
Off
CK505 SMBUS
Latches Open
Off
CK505 State
M1
BSEL[0..2]
CK505 Core Logic
Off
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 11. BSEL Serial Latching
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
–
4.6
V
1.5
V
VDD_3.3V
Supply Voltage
Functional
VDD_IO
IO Supply Voltage
Functional
VIN
Input Voltage
Relative to VSS
–0.5
4.6
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Commercial Temperature,
Operating Ambient
Functional
0
85
°C
-40
+85
°C
Industrial Temperature,
Operating Ambient
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
JEDEC (JESD 51)
–
20
°C/W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
°C/
W
ESDHBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22-A114)
2000
–
V
UL-94
Flammability Rating
UL (CLASS)
MSL
Moisture Sensitivity Level
V–0
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
.......................DOC #: SP-AP-0021 (Rev AB) Page 18 of 27
SL28506-2
DC Electrical Specifications
Parameter
Description
Condition
3.3 ± 5%
Min.
Max.
Unit
3.135
3.465
V
2.0
VDD + 0.3
V
VSS – 0.3
0.8
V
2.2
–
V
VDD core
3.3V Operating Voltage
VIH
3.3V Input High Voltage (SE)
VIL
3.3V Input Low Voltage (SE)
VIHI2C
Input High Voltage
SDATA, SCLK
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIH_FS
FS_[A,B] Input High Voltage
0.7
1.5
V
VIL_FS
FS_[A,B] Input Low Voltage
VSS – 0.3
0.35
V
VIHFS_C_TEST
FS_C Input High Voltage
2
VDD + 0.3
V
VIMFS_C_NORMAL FS_C Input Middle Voltage
VILFS_C_NORMAL FS_C Input Low Voltage
0.7
1.5
V
VSS – 0.3
0.35
V
PCI3/CFG0_HIGH PCI3/CFG0 Input High Voltage Typ. 2.75V
2.40
VDD
V
PCI3/CFG0_MID PCI3/CFG0 Input Mid Voltage
Typ. 1.65V
1.30
2.00
V
PCI3/CFG0_LOW PCI3/CFG0 Input Low Voltage
Typ. 0.550V
0
0.900
V
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
–
5
A
Except internal pull-up resistors, 0 < VIN < VDD
–5
–
A
2.4
–
V
IIL
Input Low Leakage Current
VOH
3.3V Output High Voltage (SE) IOH = –1 mA
VOL
3.3V Output Low Voltage (SE)
VDD IO
Low Voltage IO Supply Voltage
IOZ
IOL = 1 mA
–
0.4
V
1
1.5
V
High-impedance Output
Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Pin Inductance
–
7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
IDDPWRDWN
Power Down Current
1
mA
IDD3.3V
Dynamic Supply Current
–
250
mA
Min.
Max.
Unit
–
300
ppm
AC Electrical Specifications
Parameter
Description
Condition
Crystal
LACC
Long-term Accuracy
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
–
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
–
350
ps
VIL
Input Low Voltage
XIN / CLKIN pin
–
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN
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