SP3281EB

® SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers ■ Operates over entire Li+ Battery range ■ Interoperable with EIA/TIA-232-F and adheres to EIA/TIA-562 down to a +2.35V power supply ■ AUTO ON-LINE® circuitry automatically wakes up from a 1µA shutdown ■ Minimum 250Kbps data rate ■ Regulated charge pump yields stable RS-232 outputs regardless of VCC variations ■ Unique VL for low logic compatibility regardless of VCC ■ Enhanced ESD Specifications: +15kV Human Body Model +15kV IEC1000-4-2 Air Discharge +8kV IEC1000-4-2 Contact Discharge ■ Enhanced battery life as the VCC drops below 3.1V C2+ 1 GND 2 C2- 3 V- 4 28 C1+ 27 V+ 26 VCC 25 C1- T1OUT 5 T2OUT 6 T3OUT 7 R1IN 8 R2IN 9 SP3281EB 24 T1IN 23 T2IN 22 T3IN 21 R1OUT 20 R2OUT 19 T4IN 18 T4OUT 10 R3IN 11 R3OUT T5IN VL T5OUT 12 ONLINE 13 SHUTDOWN 14 17 16 15 STATUS APPLICATIONS ■ Cell phone data cables ■ PDAs, PDA cradles ■ Hand held equipment ■ Peripherals DESCRIPTION The SP3281EB device is an RS-232 transceiver solution intended for portable or hand-held applications such as notebook and palmtop computers, PDAs, cell phones and their data cables and cradles. The SP3281EB is compatible with low voltage logic down to 1.8V using a logic select pin (VL) which conditions the logic inputs and outputs to be compatible with system logic. The SP3281EB uses an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3281EB device to deliver compliant RS-232 performance from a single +3.3V to +5.5Vpower supply and additionally adhere to EIA/TIA-562 driver outputs levels down to a power supply voltage of 2.35V. The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1µA. TABLE 1 Device SP3281EB Power Supplies 2.35V to 5.5V RS-232 Drivers 5 RS232 Receivers 3 External AUTO ON-LINE® Components Circuitry 4 yes Data No. of Rate Pins 250kbps 28 Applicable U.S. Patents - 5,306,954; and 6,378,026. Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC......................................................-0.3V to +6.0V V+ (note 1).........................................-0.3V to +7.0V V- (note 1)..........................................+0.3V to -7.0V V+ + |V-| (note 1).............................................+13V ICC (DC VCC or GND current).........................+100mA Input Voltages VL........................................................-0.3V to +6.0V TxIN, ONLINE, SHUTDOWN, .............0.3V to +6.0V RxIN..................................................................+25V Output Voltages TxOUT............................................................+13.2V RxOUT, STATUS.......................-0.3V to (VL + 0.3V) Short-Circuit Duration TxOUT.....................................................Continuous Storage Temperature......................-65°C to +150°C Power Dissipation per package 28-pin SSOP (derate 11.2mW/oC above +70oC)............900mW 28-pin TSSOP (derate 13.2mW/oC above +70oC).........1100mW ELECTRICAL CHARACTERISTICS VCC = +2.35 to +5.5V, VL=+1.8 to +5.5V, C1 - C4 = 0.22µF. TA=TMIN to TMAX, unless otherwise noted. Typical values are at VCC=VL=+3.3V, and TA = +25°C.) PARAMETER SUPPLY CURRENT Supply Current, AUTO ON-LINE® Supply Current, Shutdown MIN. TYP. 1.0 MAX. 10 UNITS µA CONDITIONS All RxIN open, all TxIN at VLor GND, VCC=VL=+3.3V, TA=25°C ONLINE = GND, SHUTDOWN = VL, All RxIN open, all TxIN at VL or GND VCC=VL=+3.3V, TA=25°C ONLINE = VL or GND, SHUTDOWN = GND All TxIN at VL or GND, ONLINE = VL, VCC=VL=+3.3V, TA=25°C SHUTDOWN = VL,no load TxIN, ONLINE, SHUTDOWN VL = +3.3V or +5.0V VL = +2.5V VL = +1.8V TxIN, ONLINE, SHUTDOWN VL = +5.0V VL = +3.3V VL = +2.5V VL = +1.8V TxIN, ONLINE, SHUTDOWN, T A = 2 5° C RxOUT, Receivers disabled IOUT = +1.6mA, VL=2.5V, 3.3V, or 5.0V IOUT = +0.8mA, VL=1.8V IOUT = -1.0mA, VL=2.5V, 3.3V, 5.0V IOUT = -0.5mA, VL=1.8V TxOUT=±5.0V to ±3.7V TxOUT=±3.7V to ±5.0V 1.0 10 µA Supply Current, AUTO ON-LINE® Disabled 0.3 1.0 mA LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW 0.8 0.6 0.4 Input Logic Threshold HIGH 2.4 2.0 1.4 0.9 Transmitter Input Hysteresis Input Leakage Current Output Leakage Current Output Voltage LOW Output Voltage HIGH DRIVER OUTPUTS VCC Mode Switch Point (VCC is Falling) VCC Mode Switch Point (VCC is Rising) VCC Mode Switch Point Hysteresis 2.95 3.3 3.1 3.5 400 3.25 3.7 V V mV VL - 0.6 VL - 0.6 VL - 0.1 VL - 0.1 0.3 ±0.01 ±0.05 ±1.0 ±10 0.4 0.4 V µA µA V V V V Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation 2 ELECTRICAL CHARACTERISTICS: Continued VCC = +2.35 to +5.5V, VL=+1.8 to +5.5V, C1 - C4 = 0.22µF. TA=TMIN to TMAX, unless otherwise noted. Typical values are at VCC=VL=+3.3V, and TA = +25°C.) PARAMETER Output Voltage Swing MIN. TYP. MAX. UNITS CONDITIONS All driver outputs loaded with 3KΩ to GND, TA=25°C VCC=3.25V to 5.5V, VCC=2.35 to 2.95V, VCC = V+ = V- = 0V, VTXOUT = ±2V VTXOUT = GND VTXOUT=+/-12V, transmitter disabled, VCC=0V or 2.35V to 5.5V ±5.0 +/-3.7 Output Resistance Output Short-Circuit Current Ouput Leakage Current RECEIVER INPUTS Input Voltage Range Input Threshold LOW -25 0.3 0.6 0.8 300 ±5.4 V Ω ±35 ±60 +/-25 mA µA 25 0.8 1.2 1.5 1.0 1.5 1.8 0.3 1.8 2.4 2.4 7 V V VL=1.8V, TA=25°C VL=2.5V or 3.3V, TA=25°C VL=5.0V, TA=25°C VL=1.8V, TA=25°C VL=2.5V or 3.3V, TA=25°C VL=5.0V, TA=25°C TA=25°C HIGH V Input Hysteresis Input Resistance STATUS Output Voltage LOW HIGH Receiver Threshold to Drivers Enabled (tONLINE) Receiver +/- Threshold to Status HIGH (tSTSH) to Status LOW (tSTSL) AC Characteristics Maximum Data Rate Receiver Propagation Delay t PHL t PLH Receiver Output Enable Time Receiver Output Disable Time Time to Exit Shutdown Driver Skew |tPHL-tPLH| Receiver Skew |tPHL-tPLH| Transition-Region Slew Rate 250 VL - 0.6 3 V kΩ 5 AUTO ON-LINE® CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = VCC) 0.4 VL-0.1 200 µs V IOUT = 1.6mA, VL=2.5V, 3.3V, 5.0V or IOUT = +0.8mA, VL=1.8V IOUT = -1.0mA, VL=2.5V, 3.3V, 5.0V or IOUT = -0.5mA, VL=1.8V 20 20 µs µs kbps SP3281EB: RL = 3kΩ, CL = 1000pF, one driver switching Receiver input to output, CL = 150pF 0.15 0.15 200 200 100 100 50 µs ns ns µs ns ns Normal operation Normal operation |VTXOUT|>3.7V, VCC=3.3V Measured at zero crossover Measured at zero crossover VCC = 3.3V, RL = 3kΩ to 7kΩ , TA = 25°C, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V CL = 150pF to 1000pF 30 V/µs Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation 3 PIN DESCRIPTION NAME C2+ GND C2VT1OUT T2OUT T3OUT R1IN R2IN T4OUT R3IN T5OUT ONLINE SHUTDOWN STATUS VL T5IN R3OUT T4IN R2OUT R1OUT T3IN T2IN T1IN C1VCC V+ C1+ FUNCTION Positive terminal of the symmetrical charge-pump capacitor C2. Ground. Negative terminal of the symmetrical charge-pump capacitor C2. Regulated -4.0V or -5.5V output generated by the charge pump. RS-232 driver output. RS-232 driver output. RS-232 driver output. RS-232 receiver input. RS-232 receiver input. RS-232 driver output. RS-232 receiver input. RS-232 driver output. Apply logic HIGH to override AUTO ON-LINE® circuitry keeping drivers active (SHUTDOWN must also be logic HIGH, refer to Table 2). Apply logic LOW to shut down drivers and charge pump. This overrides all AUTO ON-LINE® circuitry and ONLINE (refer to Table 2). TTL/CMOS Output indicating if a RS-232 signal is present on any Rx input. Logic level supply voltage selection TTL/CMOS driver input. TTL/CMOS receiver output. TTL/CMOS driver input. TTL/CMOS receiver output. TTL/CMOS receiver output. TTL/CMOS driver input. TTL/CMOS driver input. TTL/CMOS driver input. Negative terminal of the symmetrical charge-pump capacitor C1. +2.35V to +5.5V supply voltage. Regulated +4.0V or +5.5V output generated by the charge pump. Positive terminal of the symmetrical charge-pump capacitor C1 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 13 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 Table 2. Device Pin Description Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation 4 TYPICAL PERFOMANCE CHARACTERISTICS Unless otherwise noted, the following perfomance characteristics apply for VCC = +4.2V, 250kbps data rate, all drivers loaded with 3kΩ, 0.22µF charge pump capacitors, and TAMB = +25°C. VCC + 26 VCC 28 C1+ 0.1µF 25 C11 C2+ C2 + 0.1µF 3 C224 T1IN 23 T2IN TTL/CMOS INPUTS 22 T3IN 19 T4IN 17 T5IN T1OUT 5 T2OUT 6 T3OUT 7 T4OUT 10 T5OUT 12 C5 0.1µF C2+ 1 GND 2 C2- 3 V- 4 T1OUT 5 T2OUT 6 T3OUT 7 R1IN 8 R2IN 9 T4OUT 10 R3IN 11 T5OUT 12 ONLINE 13 SHUTDOWN 14 SP3281EB 28 C1+ 27 26 25 V+ VCC C1C1 + V+ 27 C3 + 0.1µF SP3281EB V- 4 C4 + 0.1µF 24 T1IN 23 T2IN 22 T3IN 21 R1OUT 20 R2OUT RS-232 OUTPUTS 19 T4IN 18 17 16 R3OUT T5IN VL 21 R1OUT TTL/CMOS OUTPUTS 5kΩ 20 R2OUT 5kΩ 18 R3OUT VCC R1IN R2IN R3IN 8 9 11 RS-232 INPUTS 5kΩ 14 13 SHUTDOWN ONLINE 15 STATUS Logic Level Select 16 V L GND 2 Figure 2. SP3281EB Pinout Configuration Figure 3. SP3281EB Application Diagram VCC C5 + 0.1µF 26 VCC 28 C1+ V+ C1 + 0.1µF 25 C11 + C2 0.1µF C2+ C2- 27 C3 + SP3281EB V- 0.1µF 3 4 C4 + 21 R1OUT 5kΩ 20 R2OUT 5kΩ 18 R3OUT 5kΩ 24 T1IN 23 T2IN 22 T3IN 19 T4IN 17 T5IN VCC 0.1µF R1IN R2IN R3IN 8 9 11 T1OUT T2OUT T3OUT T4OUT T5OUT 5 6 7 10 12 14 13 DB-9 Connector 6 7 8 9 1 2 3 4 5 SHUTDOWN ONLINE VL 16 To µP Supervisor Circuit 15 STATUS GND 2 DB-9 Connector Pins: 1. Received Line Signal Detector 2. Received Data 3. Transmitted Data 4. Data Terminal Ready 5. Signal Ground (Common) 6. DCE Ready 7. Request to Send 8. Clear to Send 9. Ring Indicator Figure 4. Circuit for the connectivity of the SP3281EB with a DB-9 connector Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation 5 DESCRIPTION The SP3281EB device meets the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3281EB device features Sipex's proprietary and patented (U.S. #5,306,954) on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.3V to +5.5V power supply. The SP3281EB will adhere to EIA/TIA-562 voltage levels with VCC as low as 2.35V. The SP3281EB device is an ideal choice for power sensitive designs. The SP3281EB device features AUTO ON-LINE® circuitry which reduces the power supply drain to a 1µA supply current. In many portable or hand-held applications, an RS232 cable can be disconnected or a connected peripheral can be turned off. Under these conditions, the internal charge pump and the drivers will be shut down. Otherwise, the system automatically comes online. This feature allows design engineers to address power saving concerns without major design changes. THEORY OF OPERATION The SP3281EB device is made up of four basic circuit blocks: 1. Drivers, 2. Receivers, 3. The Sipex proprietary charge pump, and 4. AUTO ON-LINE® circuitry. Drivers The drivers are inverting level transmitters that , when VCC is between +3.3V and +5.5V, convert TTL or CMOS logic levels to 5.0V EIA/TIA-232 levels with an inverted sense relative to the input logic levels . Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. The driver outputs will adhere to EIA/ TIA-562 when VCC is as low as 2.35V. The SP3281EB drivers can guarantee a data rate of 250 kbps fully loaded with 3kΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. All unused driver inputs must be connected to VL or GND. Figure 6 shows a loopback test circuit used to test the SP3281EB RS-232 drivers. Figure 7 shows the test results of the loopback circuit with all five drivers active at 120kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 8 shows the test results where one driver was active at 250kbps and all five drivers loaded with an RS232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120kbps provides compatibility with many designs in personal computer peripherals and LAN applications. Receivers The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Receivers are not active when in shutdown. If there is no activity present at the receivers for a period longer than 100µs during AUTO ONLINE® mode or when SHUTDOWN is enabled, the device goes into a standby mode where the circuit draws 1µA. The truth table logic of the driver and receiver outputs can be found in Table 3. VCC + 0.1µF 28 C1+ 0.1µF 25 C11 C2+ C2 + 0.1µF 3 C224 T1IN 23 T2IN 22 T3IN 19 T4IN 17 T5IN T1OUT 5 T2OUT 6 T3OUT 7 T4OUT 10 T5OUT 12 C5 26 VCC V+ 27 C3 + 0.1µF C1 + SP3281EB V- 4 C4 + 0.1µF RxD CTS DSR DCD RI RS-232 OUTPUTS UART or Serial µC TxD RTS DTR VCC 21 R1OUT 5kΩ 20 R2OUT 5kΩ 18 R3OUT 5kΩ 14 13 15 SHUTDOWN ONLINE STATUS R1IN 8 R2IN 9 RS-232 INPUTS R3IN 11 VL 16 GND 2 RESET µP Supervisor IC VIN Figure 5. Interface Circuitry Being Controlled by Microprocessor Supervisory Circuit Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation 6 VCC + C5 0.1µF C1+ 0.1µF C1C2+ VCC V+ C3 + 0.1µF C1 + SP3281EB Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump is a Sipex–patented design (U.S. #5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump uses a four–phase voltage shifting technique to attain symmetrical ±5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages ±5.5V regardless of the input voltage (VCC) over the +3.3V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. The charge pump will provide output voltage levels of ±4.0V when the input voltage (VCC) is from +3.1V to +2.35V. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V ( VCC > 3.3V ) and 4.0V (VCC < 3.1V), the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V (VCC > 3.3V) and 4.0V (VCC < 3.1V), the charge pump is disabled. This oscillator controls the four phases of the voltage shifting (Figure 10). A description of each phase follows. Phase 1 (Figure 11) C2 + VC4 + 0.1µF 0.1µF C2- LOGIC INPUTS LOGIC OUTPUTS VCC TxIN TxOUT 1000pF RxOUT 5kΩ ONLINE SHUTDOWN GND RxIN Figure 6. Loopback Test Circuit for RS-232 Driver Data Transmission Rates Figure 7. Loopback Test Circuit Result at 120kbps (All Drivers Fully Loaded) [ T ] +6V a) C2+ 1 2 2 T 0V 0V b) C2T -6V Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V Figure 8. Loopback Test Circuit result at 250kbps (All Drivers Fully Loaded) Rev. 6/19/03 Figure 10. Charge Pump Waveforms © Copyright 2003 Sipex Corporation SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers 7 — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1– is transferred to C2– . Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC. Phase 2 (Figure 12) — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C 3 . This generated voltage is regulated to a minimum voltage of -5.5V (VCC > 3.3V) and -4.0V (VCC < 3.1V). Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. Phase 3 (Figure 13) — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. Phase 4 (Figure 14) — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V (V CC>3.3V) and +4.0V(VCC