SP505
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
68 DM(a)
69 DM(b)
70 RD(a)
71 RD(b)
72 GND
73 VCC
74 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
80 CTS
• +5V Only Operation
• Seven (7) Drivers and Seven (7) Receivers
• Driver and Receiver Tri-state Control
• Internal Transceiver Termination Resistors for
V.11 and V.35 Protocols
• Loopback Self-Test Mode
• Software Selectable Protocol Selection
• Interface Modes Supported:
• RS-232 (V.28)
• X.21/RS-422 (V.11)
• EIA-530 (V.10 & V.11) • EIA-530A (V.10 & V.11)
• RS-449 (V.10 & V.11) • V.35 (V.35 & V.28)
• V.36 (V.10 & V.11)
• RS-485 (un-terminated V.11)
• Improved ESD Tolerance for Analog I/Os
• High Differential Transmission Rates
• SP505A - 10Mbps
• SP505B - over 16Mbps
• Compliant to NET1/2 and TBR2 Physical Layer
Requirements
(TUV Test Report NET2/052101/98)
79 SCT
WAN Multi-Mode Serial Transceiver
RxD 1
60 GND
SDEN 2
59 SD(b)
TREN 3
58 TR(a)
RSEN 4
57 GND
LLEN 5
56 TR(b)
TTEN 6
55 VCC
SCTEN7
54 RS(a)
LATCH 8
53 GND
SP505
DEC3 9
DEC2 10
DEC1 11
DEC0 12
52 RS(b)
51 LL(a)
50 GND
49 LL(b)
(TUV Test Report CTR2/052101/98)
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
2
VCC 33
41 VCC
VSS 32
42 ST(a)
RxC 20
GND 29
C1– 30
C – 31
43 GND
DCD 19
VDD 27
C2+ 28
44 ST(b)
RLEN 18
VCC 25
C1+ 26
45 RL(b)
RL 17
LL 24
46 GND
RTS 16
RI 21
47 RL(a)
TxC 15
ST 22
48 VCC
TxD 14
STEN 23
DTR 13
DESCRIPTION
The SP505 is a monolithic device that supports eight (8) popular serial interface standards for DTE
to DCE connectivity. The SP505 is fabricated using a low power BiCMOS process technology, and
incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Seven (7)
drivers and seven (7) receivers can be configured via software for any of the above interface modes
at any time. The SP505 requires no additional external components for compliant operation for all
of the eight (8) modes of operation. All necessary termination is integrated within the SP505 and is
switchable when V.35 drivers, V.35 receivers, and V.11 receivers are used. The SP505 can operate
as either a DTE or DCE.
Additional features with the SP505 include internal loopback that can be initiated in either single-ended
or differential modes. While in loopback mode, driver outputs are internally connected to receiver
inputs creating an internal signal path convenient for diagnostic testing. This eliminates the need for
an external loopback plug. The SP505 also includes a latch enable pin with the driver and receiver
address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit
word into the address decoder. Seven (7) drivers and one (1) receiver in the SP505 include separate
enable pins for added convenience. The SP505 is ideal for WAN serial ports in networking equipment
such as routers, switches, DSU/CSU's, and other access devices.
V.35
EIA-530
WAN
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
STORAGE CONSIDERATIONS
Due to the relatively large package size of the 80-pin
quad flat-pack, storage in a low humidity environment
is preferred. Large high density plastic packages
are moisture sensitive and should be stored in Dry
Vapor Barrier Bags. Prior to usage, the parts should
remain bagged and stored below 40°C and 60%RH.
If the parts are removed from the bag, they should be
used within 48 hours or stored in an environment at
or below 20%RH. If the above conditions cannot be
followed, the parts should be baked for four hours at
125°C in order remove moisture prior to soldering.
Exar ships the 80-pin QFP in Dry Vapor Barrier Bags
with a humidity indicator card and desiccant pack. The
humidity indicator should be below 30%RH.
VCC.......................................................................+7V
Input Voltages:
Logic............................-0.3V to (VCC+0.5V)
Drivers.........................-0.3V to (VCC+0.5V)
Receivers........................................±15.5V
Output Voltages:
Logic............................-0.3V to (VCC+0.5V)
Drivers................................................±15V
Receivers.....................-0.3V to (VCC+0.5V)
Storage Temperature.......................-65˚C to +150˚C
Power Dissipation.........................................2000mW
Package Derating:
øJA.................................................46 °C/W
øJC.................................................16 °C/W
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
PARAMETER
MIN
TYP
ELECTRICAL CHARACTERISTICS
MAX
UNITS
0.8
Volts
CONDITIONS
LOGIC INPUTS
VIL
VIH
2.0
Volts
LOGIC OUTPUTS
VOL
VOH
0.4
Volts
IOUT = -3.2mA
Volts
IOUT = 1.0mA
+/-15
Volts
Per Figure 1
+/-15
Volts
Per Figure 2
+/-100
mA
Per Figure 4
Ω
Per Figure 5
2.4
V.28 DRIVER OUTPUT DC PARAMETERS
Open Circuit Voltage
Loaded Voltage
+/-5.0
Short-Circuit Current
Power-Off Impedance
300
V.28 DRIVER OUTPUT AC PARAMETERS (Vcc = +5V for AC Parameters)
Transition Time
1.5
µs
Instantaneous Slew Rate
30
V/ µs
Propagation Delay tPHL
0.5
1
5
µs
Propagation Delay tPLH
0.5
1
5
µs
Max. Transmission Rate
120
230
Per Figure 6; +3V to -3V
Per Figure 3
kbps
V.28 RecEIver Input DC parameters
Input impedance
3
Open-Circuit Bias
HIGH Threshold
LOW Threshold
1.7
0.8
7
kΩ
Per Figure 7
+2.0
Volts
Per Figure 8
3.0
Volts
1.2
Volts
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
ELECTRICAL CHARACTERISTICS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
Parameter
MIN.
TYP.
MAX.
Units
Conditions
V.28 RecEIver AC Parameters (Vcc = +5V for AC Parameters)
Propagation Delay tPHL
50
100
500
ns
Propagation Delay tPLH
50
100
500
ns
Max Transmission Rate
120
230
kbps
V.10 Driver Output DC Parameters
Open Circuit Voltage
+/-4.0
Test Terminated Voltage
0.9Vcc
+/-6.0
Volts
Per Figure 9
Volts
Per Figure 10
Short-Circuit Current
+/-150
mA
Per Figure 11
Power-Off Current
+/-100
mA
Per Figure 12
V.10 Driver AC Parameters (Vcc = +5V for AC Parameters)
Transition Time
200
ns
50
100
500
ns
Propagation Delay tPLH
50
100
500
Max Transmission Rate
120
230
Propagation Delay tPHL
Per Figure 13; 10% to 90%
ns
kbps
V.10 RECEIVER INPUT DC Parameters
Input Current
Input Impedance
-3.25
+3.25
4
mA
Per Figures 14 and 15
kΩ
Sensitivity
+/-0.3
Volts
V.10 RECEIVER AC Parameters (Vcc = +5V for AC Parameters)
Propagation Delay tPHL
50
120
250
ns
Propagation Delay tPLH
50
120
250
ns
Max Transmission Rate
120
kbps
V.11 Driver Output DC Parameters
Open Circuit Voltage
Volts
Per Figure 16
Volts
Per Figure 17
0.67VOC
Volts
Per Figure 17
+/-0.4
Volts
Per Figure 17
+3.0
Volts
Per Figure 17
Short-Circuit Current
+/-150
mA
Per Figure 18
Power-Off Current
+/-100
µA
Per Figure 19
Test Terminated Voltage
+/-5.0
+/-2.0
0.5VOC
Balance
Offset
V.11 Driver OUTPUT AC Parameters (Vcc = +5V for AC Parameters)
Transition Time
20
ns
Per Figures 21 and 36; 10% to 90%
Propagation Delay tPHL
50
85
110
ns
Per Figures 33 and 36; CL = 50pF
Propagation Delay tPLH
50
85
110
ns
Per Figures 33 and 36; CL = 50pF
10
20
ns
Per Figures 33 and 36; CL = 50pF
Differential Skew
Max. Transmission Rate
SP505ACM-L
10
12
Mbps
Per Figure 33; CL = 50pF,
fIN = 5MHz
Max. Transmission Rate
SP505BCM-L
16.4
18
Mbps
Per Figure 33; CL = 50pF,
fIN = 8.2MHz
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
ELECTRICAL CHARACTERISTICS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
V.11 ReceIver Input DC Parameters
Common Mode Range
-7
Sensitivity
Input Current
-3.25
Current w/ 100Ω Termination
Input Impedance
+7
Volts
+/-0.3
Volts
+3.25
mA
Per Figures 20 and 22
+/-60.75
mA
Per Figures 23 and 24
4
kΩ
V.11 RecEiver Input AC Parameters (Vcc = +5V for AC Parameters)
Propagation Delay tPHL
80
110
130
ns
Per Figures 33 and 38; CL = 50pF
Propagation Delay tPLH
80
110
130
Differential Skew
ns
Per Figures 33 and 38; CL = 50pF
20
ns
Per Figures 33; CL = 50pF
Max. Transmission Rate
SP505ACM-L
10
12
Mbps
Per Figure 33; CL = 50pF,
fIN = 5MHz
Max. Transmission Rate
SP505BCM-L
16.4
18
Mbps
Per Figure 33; CL = 50pF,
fIN = 8.2MHz
+/-1.20
Volts
Per Figure 16
+/-0.66
Volts
Per Figure 25
Per Figure 25
V.35 Driver Output DC Parameters
Open Circuit Voltage
Test Terminated Voltage
+/-0.44
Offset
+/-0.6
Volts
Source Impedance
50
150
Ω
Per Figure 27; ZS = V2/V1 x 50 Ω
Short Circuit Impedance
135
165
Ω
Per Figure 28
V.35 Driver Output AC Parameters (Vcc = +5V for AC Parameters)
Transition Time
30
40
ns
Per Figure 29; 10% to 90%
Propagation Delay tPHL
50
90
110
ns
Per Figures 33 and 36; CL = 20pF
Propagation Delay tPLH
50
90
110
ns
Per Figures 33 and 36; CL = 20pF
20
30
ns
Per Figure 33; CL = 20pF
Differential Skew
Max. Transmission Rate
SP505ACM-L
10
12
Mbps
Per Figure 33; CL = 20pF,
fIN = 5MHz
Max. Transmission Rate
SP505BCM-L
16.4
18
Mbps
Per Figure 33; CL = 20pF,
fIN = 8.2MHz
V.35 RECEIVER INPUT DC PARAMETERS
Sensitivity
+/-80
mV
Source Impedance
90
110
Ω
Per Figure 30; ZS = V2/V1 x 50 Ω
Short Circuit Impedance
135
165
Ω
Per Figure 31
V.35 RECEIVER INPUT AC PARAMETERS (Vcc = +5V for AC Parameters)
Propagation Delay tPHL
80
110
130
ns
Per Figures 33 and 38; CL = 20pF
Propagation Delay tPLH
80
110
130
ns
Per Figures 33 and 38; CL = 20pF
20
ns
Per Figures 33; CL = 20pF
Differential Skew
Max. Transmission Rate
SP505ACM-L
10
12
Mbps
Per Figure 33; CL = 20pF,
fIN = 5MHz
Max. Transmission Rate
SP505BCM-L
16.4
18
Mbps
Per Figure 33; CL = 20pF,
fIN = 8.2MHz
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
ELECTRICAL CHARACTERISTICS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
Parameter
MIN.
TYP.
MAX.
Units
Conditions
100
500
µA
Per Figure 32; Drivers disabled
1
10
µA
DECX = 0000, 0.4V ≤ VO ≤ 2.4V
TRANSCEIVER LEAKAGE CURRENTS
Driver Output 3-state Current
Receiver Output 3-state
Current
AC Characteristics
TA = +25°C and VCC = +5.0V unless otherwise noted.
Parameter
MIN.
TYP.
MAX.
Units
Conditions
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
0.70
5.0
µs
CL = 100pF, Fig. 34 & 40; S1 closed
tPZH; Tri-state to Output HIGH
0.40
2.0
µs
CL = 100pF, Fig. 34 & 40; S2 closed
tPLZ; Output LOW to Tri-state
0.20
2.0
µs
CL = 100pF, Fig. 34 & 40; S1 closed
tPHZ; Output HIGH to Tri-state
0.40
2.0
µs
CL = 100pF, Fig. 34 & 40; S2 closed
0.15
2.0
µs
CL = 100pF, Fig. 34 & 40; S1 closed
tPZH; Tri-state to Output HIGH
0.20
2.0
µs
CL = 100pF, Fig. 34 & 40; S2 closed
tPLZ; Output LOW to Tri-state
0.20
2.0
µs
CL = 100pF, Fig. 34 & 40; S1 closed
tPHZ; Output HIGH to Tri-state
0.15
2.0
µs
CL = 100pF, Fig. 34 & 40; S2 closed
tPZL; Tri-state to Output LOW
2.80
10.0
µs
CL = 100pF, Fig. 34 & 37; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 34 & 37; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 34 & 37; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 34 & 37; S2 closed
tPZL; Tri-state to Output LOW
2.60
10.0
µs
CL = 100pF, Fig. 34 & 37; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 34 & 37; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 34 & 37; S1 closed
tPHZ; Output HIGH to Tri-state
0.15
2.0
µs
CL = 15pF, Fig. 34 & 37; S2 closed
RS-423/V.10
tPZL; Tri-state to Output LOW
RS-422/V.11
V.35
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
0.12
2.0
µs
CL = 100pF, Fig. 35 & 38; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S2 closed
RS-423/V.10
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 100pF, Fig. 35 & 38; S2 closed
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
AC Characteristics
TA = +25°C and VCC = +5.0V unless otherwise noted.
Parameter
MIN.
TYP.
MAX.
Units
Conditions
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE (Continued)
RS-422/V.11
tPZL; Tri-state to Output LOW
0.10
2.0
µs
CL = 100pF, Fig. 35 & 39; S1 closed
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 35 & 39; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 35 & 39; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 35 & 39; S2 closed
0.10
2.0
µs
CL = 100pF, Fig. 35 & 39; S1 closed
V.35
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
0.10
2.0
µs
CL = 100pF, Fig. 35 & 39; S2 closed
tPLZ; Output LOW to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 35 & 39; S1 closed
tPHZ; Output HIGH to Tri-state
0.10
2.0
µs
CL = 15pF, Fig. 35 & 39; S2 closed
TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 33, 36 and 38)
V.28 Driver
100
ns
| (tPHL)Tx1 - (tPHL)Tx6,7 |
V.28 Driver
100
ns
| (tPLH)Tx1 - (tPLH)Tx6,7 |
V.28 Receiver
20
ns
| (tPHL)Rx1 - (tPHL)Rx2,7 |
V.28 Receiver
20
ns
| (tPLH)Rx1 - (tPLH)Rx2,7 |
V.11 Driver
2
ns
| (tPHL)Tx1 - (tPHL)Tx6,7 |
V.11 Driver
2
ns
| (tPLH)Tx1 - (tPLH)Tx6,7 |
V.11 Receiver
3
ns
| (tPHL)Rx1 - (tPHL)Rx2,7 |
V.11 Receiver
3
ns
| (tPLH)Rx1 - (tPLH)Rx2,7 |
V.10 Driver
5
ns
| (tPHL)Tx2 - (tPHL)Tx3,4,5 |
V.10 Driver
5
ns
| (tPLH)Tx2 - (tPLH)Tx3,4,5 |
V.10 Receiver
5
ns
| (tPHL)Rx2 - (tPHL)Rx3,4,5 |
V.10 Receiver
5
ns
| (tPLH)Rx2 - (tPLH)Rx3,4,5 |
V.35 Driver
4
ns
| (tPHL)Tx1 - (tPHL)Tx6,7 |
V.35 Driver
4
ns
| (tPLH)Tx1 - (tPLH)Tx6,7 |
V.35 Receiver
6
ns
| (tPHL)Rx1 - (tPHL)Rx2,7 |
V.35 Receiver
6
ns
| (tPLH)Rx1 - (tPLH)Rx2,7 |
Power REQUIREMENTS
Parameter
MIN.
TYP.
MAX.
UNITS
VCC
4.75
5.00
5.25
Volts
ICC (No Mode Selected)
30
mA
ICC (V.28/RS-232)
60
mA
ICC (V.11/RS-422)
300
mA
ICC (RS-449)
250
mA
ICC (V.35)
105
mA
ICC (EIA-530)
260
mA
ICC (EIA-530A)
250
mA
ICC (V.36)
65
mA
CONDITIONS
All ICC values are with Vcc = +5V,
T = 25°C, all drivers loaded to their
specified maximum load and all
drivers are active at their maximum
specified data transmission rates
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
Test Circuits
A
A
VOC
VT
3kΩ
C
C
Figure 1. V.28 Driver Output Open Circuit Voltage
Figure 2. V.28 Driver Output Loaded Voltage
A
A
VT
7kΩ
Is c
O scilloscope
C
C
Scope used f or sle w rate
measurement.
Figure 4. V.28 Driver Output Short-Circuit Current
Figure 3. V.28 Driver Output Slew Rate
V C C = 0V
A
A
Ix
3kΩ
2500pF
O scilloscope
±2V
C
C
Figure 6. V.28 Driver Output Rise/Fall Times
Figure 5. V.28 Driver Output Power-Off Impedance
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
A
A
I ia
±15V
V oc
C
C
Figure 7. V.28 Receiver Input Impedance
Figure 8. V.28 Receiver Input Open Circuit Bias
A
A
3.9kΩ
VOC
Vt
450Ω
C
C
Figure 9. V.10 Driver Output Open-Circuit Voltage
Figure 10. V.10 Driver Output Test Terminated Voltage
V C C = 0V
A
A
Ix
±0 .2 5V
Is c
C
C
Figure 11. V.10 Driver Output Short-Circuit Current
Figure 12. V.10 Driver Output Power-Off Current
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
A
A
Iia
±10V
O scilloscope
450Ω
C
C
Figure 13. V.10 Driver Output Transition Time
Figure 14. V.10 Receiver Input Current
V.10 R E CE IVE R
+3.25mA
A
V
–10V
OCA
VOC
3.9kΩ
V OCB
–3V
+3V
B
+10V
Maximum Input C urrent
versus Voltage
C
–3. 25mA
Figure 15. V.10 Receiver Input IV Graph
Figure 16. V.11 and V.35 Driver Output Open-Circuit Voltage
A
Is a
A
50Ω
VT
50Ω
Is b
B
B
V OS
C
C
Figure 17. V.11 Driver Output Test Terminated Voltage
Figure 18. V.11 Driver Output Short-Circuit Current
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
SP505_100_081308
V C C = 0V
A
A
Iia
Ixa
±10V
±0.25V
B
B
C
C
V C C = 0V
A
A
±0.25V
±10V
Ixb
B
B
C
Iib
C
Figure 20. V.11 Receiver Input Current
Figure 19. V.11 Driver Output Power-Off Current
V.11 R E CE IVE R
+3.25mA
A
50Ω
Oscilloscope
–10V
50Ω
B
50Ω
–3V
VE
+3V
+10V
Maximum Input C urrent
versus Voltage
C
–3. 25mA
Figure 21. V.11 Driver Output Rise/Fall Time
Figure 22. V.11 Receiver Input IV Graph
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
10
SP505_100_081308
V.11 R E CE IVE R
A
w/ Option al Cable Termination
(100Ω to 150Ω)
i [mA] = V [V] / 0.1
Iia
i [mA] = (V [V] – 3) / 4.0
±6V
100Ω to
150Ω
–6V
–3V
+3V
B
+6V
i [mA] = (V [V] – 3) / 4.0
C
Maximum Input C urrent
versus Voltage
i [mA] = V [V] / 0.1
Figure 24. V.11 Receiver Input Graph w/ Termination
A
A
±6V
50Ω
100Ω to
150Ω
VT
50Ω
Iib
B
V OS
B
C
C
Figure 23. V.11 Receiver Input Current w/ Termination
Figure 25. V.35 Driver Output Test Terminated Voltage
V1
A
A
50Ω
24kHz, 550mV p-p
S ine Wave
50Ω
V2
VT
50Ω
B
VOS
B
C
C
Figure 26. V.35 Driver Output Offset Voltage
Figure 27. V.35 Driver Output Source Impedance
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SP505_100_081308
A
A
50Ω
Oscilloscope
50Ω
ISC
B
B
50Ω
±2V
C
C
Figure 28. V.35 Driver Output Short-Circuit Impedance
Figure 29. V.35 Driver Output Rise/Fall Time
A
V1
A
50Ω
24kHz, 550mV p-p
S ine Wa ve
V2
Isc
B
B
±2V
C
C
Figure 30. V.35 Receiver Input Source Impedance
Figure 31. V.35 Receiver Input Short-Circuit Impedance
Any one of the two conditions for dis abling the driver.
V CC = +5V
DEC
V CC
0
0
3
DEC
0
2
DEC
0
1
DEC
0
A
IZS C
TIN
±15V
CL1
A
B
fIN (50% Duty Cycle, 2.5V
L ogic “1”
CL2
A
ROUT
B
15pF
)
P-P
B
Figure 33. Driver/Receiver Timing Test Circuit
Figure 32. Driver Output Leakage Current Test
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SP505_100_081308
Output
Under
Test
VCC
S1
500Ω
1K Ω
S2
S2
Figure 35. Receiver Timing Test Load Circuit
Figure 34. Driver Timing Test Load Circuit
DRIVER
INPUT
DRIVER
OUTPUT
VCC
S1
CR L
CL
1K Ω
Test P oint
R eceiver
Output
f ≥ 5MHz; tR ≤ 10ns; tF ≤ 10ns
+3V
1.5V
0V
1.5V
tPLH
A
VO
B
tPHL
1/2VO
1/2VO
tDPLH
DIFFERENTIAL VO+
OUTPUT 0V
VA - VB VO–
tDPHL
tF
tR
tSKEW = │tDPLH - tDPHL │
Figure 36. Driver Propagation Delays
f = 1MHz; tR ≤ 10ns; tF ≤ 10ns
TXENABLE +3V
A, B
A, B
1.5V
0V
DECX
1.5V
tZL
5V
2.3V
VOL
VOH
2.3V
0V
tLZ
Output normally LOW
0.5V
Output normally HIGH
0.5V
tZH
tHZ
Figure 37. Driver Enable and Disable Times
A–B
R E C E IVE R O UT
f > 5MHz; tR < 10ns ; tF < 10ns
V 0D2 +
0V
V 0D2 –
O UT P UT
V OH
V OL
0V
INP UT
(V OH - V OL )/2
(V OH - V OL )/2
tPLH
tPHL
tSKEW = | tPHL - tPLH |
Figure 38. Receiver Propagation Delays
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SP505_100_081308
f = 1MHz; tR ≤ 10ns; tF ≤ 10ns
DE C X +3V
R C V R ENABLE
1.5V
0V
1.5V
tZL
5V
R E C E IVE R O UT
V IL
tLZ
1.5V
V IH
R E C E IVE R O UT
0V
1.5V
O utput norma lly L O W
0.5V
O utput norma lly HIG H
0.5V
tZH
tHZ
Figure 39. Receiver Enable and Disable Times
+3V
DE C X or Tx_Enable
0V
0V
T OUT
V OL
+3V
DE C X or Tx_Enable
0V
T OUT
V OH
f = 60kH z; tR < 10ns; tF < 10ns
1.5V
1.5V
tLZ
tZL
V OL – .5V
Output LOW
V OL – .5V
f = 60kH z; tR < 10ns; tF < 10ns
1.5V
1.5V
tZH
Output HIG H
V OH – .5V
tHZ
V OH – .5V
0V
Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times
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SP505_100_081308
INPUT
OUTPUT
Figure 42. Typical V.10 Driver Output Waveform
Figure 41. Typical V.28 Driver Output Waveform
INPUT
AOUT
BOUT
DIFFOUT
Figure 44. Typical V.35 Driver Output Waveform
Figure 43. Typical V.11 Driver Output Waveform
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SP505_100_081308
Pin 61 — SD(a) — Analog Out — Send
data, inverted; sourced from TxD.
Pin 63 — TT(a) — Analog Out — Terminal
Timing, inverted; sourced from TxC
61 SD(a)
62 VCC
63 TT(a)
64 GND
65 TT(b)
66 CS(a)
67 CS(b)
68 DM(a)
69 DM(b)
70 RD(a)
71 RD(b)
72 GND
73 VCC
74 VCC
75 GND
76 SCT(a)
77 SCT(b)
78 DSR
79 SCT
80 CTS
PINOUT…
RxD 1
Pin 65 — TT(b) — Analog Out — Terminal
Timing, non–inverted; sourced from TxC.
60 GND
SDEN 2
59 SD(b)
TREN 3
58 TR(a)
RSEN 4
57 GND
LLEN 5
56 TR(b)
TTEN 6
55 VCC
SCTEN7
Pin 70 — RD(a) — Receive Data, analog
input; inverted; source for RxD.
54 RS(a)
LATCH 8
53 GND
SP505
DEC3 9
DEC2 10
DEC1 11
DEC0 12
51 LL(a)
50 GND
49 LL(b)
DTR 13
48 VCC
TxD 14
47 RL(a)
TxC 15
46 GND
RTS 16
45 RL(b)
RL 17
44 ST(b)
Pin 76 — SCT(a) — Serial Clock Transmit;
analog input, inverted; source for SCT.
Pin 77 — SCT(b) — Serial Clock Transmit:
analog input, non–inverted; source for
SCT
IC(b) 40
IC(a) 39
RT(b) 38
RT(a) 37
RR(b) 36
RR(a) 35
GND 34
VCC 33
VSS 32
C2– 31
1
GND 29
C – 30
1
VDD 27
C2+ 28
41 VCC
VCC 25
C + 26
42 ST(a)
RxC 20
LL 24
DCD 19
RI 21
43 GND
ST 22
RLEN 18
STEN 23
Pin 71 — RD(b) — Receive Data; analog
input; non-inverted; source for RxD.
52 RS(b)
Pin 79 — SCT — Serial Clock Transmit; TTL
output; sources from SCT(a) and SCT(b)
inputs.
PIN ASSIGNMENTS…
CLOCK AND DATA GROUP
Pin 1 — RxD — Receive Data; TTL output,
sourced from RD(a) and RD(b) inputs.
CONTROL LINE GROUP
Pin 13 — DTR — Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.
Pin 14 — TxD — TTL input ; transmit data
source for SD(a) and SD(b) outputs.
Pin 16 — RTS — Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.
Pin 15 — TxC — Transmit Clock; TTL input
for TT driver outputs.
Pin 17 — RL — Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.
Pin 20 — RxC — Receive Clock; TTL output
sourced from RT(a) and RT(b) inputs.
Pin 19 — DCD— Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b)
inputs.
Pin 22 — ST — Send Timing; TTL input;
source for ST(a) and ST(b) outputs.
Pin 21 — RI — Ring In; TTL output; sourced
from IC(a) and IC(b) inputs.
Pin 37 — RT(a) — Receive Timing; analog
input, inverted; source for RxC.
Pin 24 — LL — Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.
Pin 38 — RT(b) — Receive Timing; analog
input, non-inverted; source for RxC.
Pin 35 — RR(a)— Receiver Ready; analog
input, inverted; source for DCD.
Pin 42 — ST(a) — Send Timing; analog
output, inverted; sourced from ST.
Pin 36 — RR(b)— Receiver Ready; analog
input, non-inverted; source for DCD.
Pin 44 — ST(b) — Send Timing; analog
output, non-inverted; sourced from ST.
Pin 39 — IC(a)— Incoming Call; analog
input, inverted; source for RI.
Pin 59 — SD(b) — Analog Out — Send data,
non-inverted; sourced from TxD.
Pin 40 — IC(b)— Incoming Call; analog
input,non-inverted; source for RI.
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SP505_100_081308
Pin 45 — RL(b) — Remote Loopback; analog
output, non-inverted; sourced from RL.
Pin 7 — SCTEN — Enables SCT receiver;
active high; TTL input.
Pin 47 — RL(a) — Remote Loopback; analog
output inverted; sourced from RL.
Pin 8 — LATCH — Latch control for decoder
bits (pins 9-12), active low. Logic high input
will make decoder transparent.
Pin 49— LL(b) — Local Loopback; analog
output, non-inverted; sourced from LL.
Pins 12–9 — DEC0 – DEC3 — Transmitter and
receiver decode register; configures transmitter and receiver modes; TTL inputs.
Pin 51 — LL(a) — Local Loopback; analog
output, inverted; sourced from LL.
Pin 18 — RLEN — Enables RL driver; active
low; TTL input.
Pin 52 — RS(b) — Ready To Send; analog
output, non-inverted; sourced from RTS.
Pin 23 — STEN — Enables ST driver; active
low; TTL input.
Pin 54 — RS(a) — Ready To Send; analog
output, inverted; sourced from RTS.
Pin 56 — TR(b) — Terminal Ready; analog
output, non-inverted; sourced from DTR.
POWER SUPPLIES
Pins 25, 33, 41, 48, 55, 62, 73, 74 — VCC
— +5V input.
Pin 58 — TR(a) — Terminal Ready; analog
output, inverted; sourced from DTR.
Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72,
75 — GND — Ground.
Pin 66 — CS(a)— Clear To Send; analog
input, inverted; source for CTS.
Pin 27 — VDD +10V Charge Pump Capacitor
— Connects from VDD to VCC. Suggested
capacitor size is 22µF, 16V.
Pin 67 — CS(b)— Clear To Send; analog
input, non-inverted; source for CTS.
Pin 68 — DM(a)— Data Mode; analog input,
inverted; source for DSR.
Pin 32 — VSS –10V Charge Pump Capacitor
— Connects from ground to VSS. Suggested
capacitor size is 22µF, 16V.
Pin 69 — DM(b)— Data Mode; analog input,
non-inverted; source for DSR
Pins 26 and 30 — C1+ and C1– — Charge
Pump Capacitor — Connects from C1+ to C1–.
Suggested capacitor size is 22µF, 16V.
Pin 78 — DSR— Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.
Pins 28 and 31 — C2+ and C2– — Charge
Pump Capacitor — Connects from C2+ to C2–.
Suggested capacitor size is 22µF, 16V.
Pin 80 — CTS— Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.
CONTROL REGISTERS
Pins 2 — SDEN — Enables TxD driver,
active low; TTL input.
Pins 3 — TREN — Enables DTR driver,
active low; TTL input.
Pins 4 — RSEN — Enables RTS driver,
active low; TTL input.
Pins 5 — LLEN — Enables LL driver, active
low; TTL input.
Pin 6 — TTEN — Enables TT driver, active
low; TTL input.
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SP505_100_081308
FEATURES…
The SP505 is a highly integrated serial
transceiver that allows software control of
its interface modes. Similar to the SP504,
the SP505 offers the same hardware interface modes for RS-232 (V.28), RS-422A
(V.11), RS-449, RS-485, V.35, EIA-530 and
includes V.36 and EIA-530A. The interface
mode selection is done via a 4–bit switch
for the drivers and receivers. The SP505
is fabricated using low–power BiCMOS
process technology, and incorporates a
Exar–patented (5,306,954) charge pump
allowing +5V only operation. Each device
is packaged in an 80–pin JEDEC Quad
FlatPack package.
+4V to +6V during an open-circuit (no
load). The charge pump would need to
be regulated down from +10V to +5V.
A typical +10V charge pump would require
external clamping such as 5V zener diodes
on VDD and VSS to ground. The +5V output
has symmetrical levels as in the +10V output.
The +5V is used in the following modes where
RS-423 (V.10) are used: RS-449, EIA-530,
EIA-530A and V.36.
Phase 1 (±10V)
— VSS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. Cl+ is
then switched to ground and the charge on
C1– is transferred to C2–. Since C2+ is connected to +5V, the voltage potential across
capacitor C2 is now 10V.
The SP505 is ideally suited for wide area
network connectivity based on the interface
modes offered and the driver and receiver
configurations. The SP505 has seven (7)
independent drivers and seven (7) independent receivers. In V.35 mode, the SP505
includes the necessary components and
termination resistors internal within the device for compliant V.35 operation.
Phase 1 (±5V)
— VSS & VDD charge storage and transfer
— With the C1 and C2 capacitors initially
charged to +5V, Cl+ is then switched to ground
and the charge on C1– is transferred to the VSS
storage capacitor. Simultaneously the C2– is
switched to ground and 5V charge on C2+ is
transferred to the VDD storage capacitor.
Theory of Operation
The SP505 is made up of five separate
circuit blocks — the charge pump, drivers,
receivers, decoder and switching array. Each
of these circuit blocks is described in more
detail below.
V CC = +5V
+5V
Charge–Pump
The SP505 charge pump is based on the
SP504 design where Exar's patented charge
pump design (5,306,954) uses a four–phase
voltage shifting technique to attain symmetrical 10V power supplies. The charge pump
still requires external capacitors to store the
charge. In addition the SP504 charge pump
supplies +10V or +5V on VSS and VDD depending on the mode of operation. There is
a free–running oscillator that controls the four
phases of the voltage shifting. A description
of each phase follows.
C1
+
C2
–
+
C4
+
–
V DD S torage C apa citor
+
V SS S torage C apa citor
–
–5 V
–
C3
–5 V
Figure 45. Charge Pump Phase 1 for +10V.
V CC = +5V
+5V
C1
+
–
C2
+
C4
+
–5 V
The SP505 charge pump is used for RS232 where the output voltage swing is
typically +10V and also used for RS-423.
However, RS-423 requires the voltage
swing on the driver output be between
–
V DD S torage C apa citor
+
V SS S torage C apa citor
–
–
C3
Figure 46. Charge Pump Phase 1 for +5V.
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SP505_100_081308
External Power Supplies
For applications that do not require +5V
only, external supplies can be applied at the
V+ and V– pins. The value of the external
supply voltages must be no greater than
+l0.5V. The tolerance should be +5% from
+10V. The current drain for the supplies is
used for RS-232 and RS-423 drivers. For
the RS-232 driver, the current requirement
will be 3.5mA per driver. The RS-423 driver
worst case current drain will be 11mA per
driver. Power sequencing is required for the
SP505. The supplies must be sequenced
accordingly: +10V, +5V and –10V. It is
important to prevent VSS from starting up
before VCC or VDD.
Phase 2 (±10V)
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to
the VSS storage capacitor and the positive
terminal of C2 to ground, and transfers the
generated –l0V or the generated –5V to C3.
Simultaneously, the positive side of capacitor
C 1 is switched to +5V and the negative side
is connected to ground.
Phase 2 (±5V)
— VSS & VDD charge storage — C1+ is reconnected to VCC to recharge the C1 capacitor.
C2+ is switched to ground and C2– is connected
to C3. The 5V charge from Phase 1 is now
transferred to the VSS storage capacitor. VSS
receives a continuous charge from either C1
or C2. With the C1 capacitor charged to 5V,
the cycle begins again.
V CC = +5V
C4
Phase 3
— VDD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C1 produces
–5V in the negative terminal of C1, which
is applied to the negative side of capacitor
C2. Since C2+ is at +5V, the voltage potential
across C2 is l0V. For the 5V output, C2+ is
connected to ground so that the potential
on C2 is only +5V.
C1
+
–
+
+
C2
–
V DD S torage C apa citor
+
V SS S torage C apa citor
–
–
–1 0V
C3
Figure 47. Charge Pump Phase 2 for +10V.
V CC = +5V
C4
+
C1
Phase 4
— VDD transfer — The fourth phase of the
clock connects the negative terminal of C2
to ground and transfers the generated l0V
or the generated 5V across C2 to C4, the VDD
storage capacitor. Again, simultaneously
with this, the positive side of capacitor C1
is switched to +5V and the negative side is
connected to ground, and the cycle begins
again.
+
C2
–
+
–
V DD S torage C apa citor
+
V SS S torage C apa citor
–
–5 V
–
C3
Figure 48. Charge Pump Phase 2 for +5V.
V CC = +5V
C4
+5V
C1
+
C2
–
+
+
–
V DD S torage C apa citor
+
V SS S torage C apa citor
–
–5 V
–
Since both VDD and VSS are separately generated from VCC in a no–load condition, VDD
and VSS will be symmetrical. Older charge
pump approaches that generate V– from
V+ will show a decrease in the magnitude
of V– compared to V+ due to the inherent
inefficiencies in the design.
C3
–5 V
Figure 49. Charge Pump Phase 3.
V CC = +5V
+10V
C1
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors
must be a minimum of 22µF with a 16V
breakdown rating.
+
–
C2
+
C4
+
–
V DD S torage C apa citor
+
V SS S torage C apa citor
–
–
C3
Figure 50. Charge Pump Phase 4.
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SP505_100_081308
Drivers
The SP505 has seven (7) enhanced independent drivers. Control for the mode
selection is done via a four–bit control word.
The drivers are prearranged such that for
each mode of operation, the relative position and functionality of the drivers are set
up to accommodate the selected interface
mode. As the mode of the drivers is changed,
the electrical characteristics will change to
support the requirements of clock, data, and
control line signal levels. Table 1 shows the
mode of each driver in the different interface
modes that can be selected.
a load of 100Ω. The signal levels and drive
capability of these drivers allow the drivers to
also support RS-485 requirements of ±1.5V
minimum differential output levels with a 54Ω
load. The driver is designed to operate over
a common mode range of +12V to -7V, which
follows the RS-485 specification. This also
covers the +7V to -7V common mode range
for V.11 (RS-422) requirements. The V.11
drivers are used in RS-449, EIA-530, EIA530A and V.36 modes as Category I signals
which are used for clock and data signals.
V.35 Drivers
The fourth type of driver is the V.35 driver.
These drivers were specifically designed
to comply with the requirements of V.35.
Unique to the industry, the Sipex's V.35
driver architecture used in the SP505 does
not need external termination resistors to
operate and comply with V.35. This simplifies existing V.35 implementations that use
external termination schemes. The V.35
drivers can produce +0.55V driver output
signals with minimum deviation (maximum
20%) given an equivalent load of 100Ω.
With the help of internal resistor networks,
the drivers achieve the 50Ω to 150Ω source
impedance and the 135Ω to 165Ω short-circuit impedance for V.35. The V.35 driver is
disabled and transparent when the decoder
is in all other modes. All of the differential
drivers; V.11 (RS-422) and V.35, can operate
over 10Mbps.
There are four basic types of driver circuits
— V.28, V.11, V.10 and V.35.
V.28 Drivers
The V.28 drivers output single–ended signals
with a minimum of +5V (with 3kΩ & 2500pF
loading), and can operate to at least 120kbps
under full load. Since the SP505 uses a
charge pump to generate the RS-232 output
rails, the driver outputs will never exceed
+10V. The V.28 drivers are used in RS-232
mode for all signals, and also in V.35 mode
where four (4) drivers are used as the control
line signals (DTR, RTS, LL, and RL).
V.10 Drivers
The V.10 (RS-423) drivers are also single–
ended signals which produce open circuit VOL
and VOH measurements of +4.0V to +6.0V.
When terminated with a 450Ω load to ground,
the driver output will not deviate more than
10% of the open circuit value. This is in
compliance of the ITU V.10 specification.
The V.10 drivers are used in RS-449, EIA530, EIA-530A and V.36 modes as Category
II signals from each of their corresponding
specifications.
Driver Enable and Input
All the drivers in the SP505 contain individual
enable lines which can tri-state the driver outputs when a logic "1" is applied. This simplifies half-duplex configurations for some applications and also provides simpler DTE/DCE
flexibility with one integrated circuit.
V.11 Drivers
The third type of driver is a V.11 (RS-422)
type differential driver. Due to the nature of
differential signaling, the drivers are more
immune to noise as opposed to single-ended
transmission methods. The advantage is evident over high speeds and long transmission
lines. The strength of the driver outputs can
produce differential signals that can maintain
typically +2.2V differential output levels with
The driver inputs are both TTL or CMOS
compatible. Each driver input should have a
pull-down or pull-up resistor so that the output will be at a defined state. Unused driver
inputs should not be left floating.
Receivers
The SP505 has seven (7) independent receivers which can be programmed for the
different interface modes. Control for the
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SP505_100_081308
mode selection is done via a 4–bit control
word, which is the same as the driver's 4-bit
control word.
Like the drivers, the receivers are prearranged for the specific requirements of
the synchronous serial interface. As the
operating mode of the receivers is changed,
the electrical characteristics will change to
support the requirements of clock, data,
and control line receivers. Table 2 shows
the mode of each receiver in the different
interface modes that can be selected.
V.11 receivers are actually subsets of RS485, the V.11 receivers can accept RS-485
signals. However, these receivers cannot
support 32-transceivers on the signal bus due
to the lower input impedance as specified in
the RS-485 specification. Three receivers
(RxD, RxC, and SCT) include a typical 120Ω
cable termination resistor across the A and B
inputs. The resistor for the three receivers is
switched on when the SP505 is configured
in a mode which uses V.11 receivers. The
V.11 cable termination resistor is switched off
when the receiver is disabled or in another
operating mode not using V.11 receivers.
The V.11 receivers are used in X.21, RS-449,
EIA-530, EIA-530A and V.36 as Category I
signals for receiving clock, data, and some
control line signals not covered by Category
II V.10 circuits. The differential receivers can
receive signals over 10Mbps.
There are three basic types of receiver circuits — V.28, V.10, and V.11.
V.28 Receivers
The V.28 receiver is single–ended and accepts V.28 signals from the V.28 driver. The
V.28 receiver has an operating voltage range
of +15V and can receive signals down to +3V.
The input sensitivity complies with RS-232
and V.28 specifications at +3V. The input
impedance is 3kΩ to 7kΩ in accordance to
RS-232 and V.28 over a +15V input range.
The receiver output produces a TTL/CMOS
signal with a +2.4V minimum for a logic "1"
and a +0.8V maximum for a logic "0". V.28
receivers are used in RS-232 mode for all
data, clock and control signals. They are also
used in V.35 mode for control line signals:
CTS, DSR, LL, and RL. The V.28 receivers
can operate to at least 120kbps.
V.35 Receiver
The V.11 receivers are also used for the
V.35 mode. Unlike the older implementations of differential receivers used for V.35,
the SP505 contains an internal resistor
termination network that ensures a V.35
input impedance of 100Ω (+10Ω) and a
short-circuit impedance of 150Ω (+15Ω). The
traditional V.35 implementations required
external termination resistors to achieve
the proper V.35 impedances. The internal
network is connected via low on-resistance
FET switches when the decoder is changed
to V.35 mode. These FET switches can accept input signals of up to +15V without any
forward biasing and other parasitic affects.
The V.35 termination resistor network is
switched off when the receiver is disabled
either by the decoder or receiver enable
pin. The termination network is transparent
when all other modes are selected. The V.35
receivers can operate over 10Mbps.
V.10 Receivers
The V.10 receivers are also single–ended
as with the V.28 receivers but have an input threshold as low as +200mV. The input
impedance is guaranteed to be greater than
4KΩ, with an operating voltage range of +7V.
The V.10 receivers can operate to at least
120kbps. V.10 receivers are used in RS449, EIA-530, EIA-530A and V.36 modes
as Category II signals as indicated by their
corresponding specifications.
To Inverting Input
of R eceiver
R IN [a]
V.11 TERMINA TION
MODE [0100]
V.35 MODE
rON = 20Ω
V.11 Receivers
The third type of receiver is a differential
which supports V.11 and RS-485 signals.
This receiver has a typical input impedance
of 10kΩ and a typical differential threshold
of +200mV, which complies with the V.11
specification. Since the characteristics of the
rON = 1Ω
51Ω
rON = 1Ω
124Ω
51Ω
To N on-Inverting
Input of R eceiver
R IN [b]
Figure 51. Simplified RIN Termination Circuit
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21
SP505_100_081308
Receiver Enable and Output
Only one receiver includes an enable line.
The SCTEN input for the SCT receiver can
enable or tri-state the output of the receiver.
When the pin is at a logic "0", the receiver
output is high impedance and any input
termination internal connected is switched
off. The inputs will be at approximately 10kΩ
during tri-state.
outputs and receiver outputs can be put
into tri-state mode by writing 0000 to the
driver decode switch. All internal termination
networks are switched off during this mode.
Individual tri-state capability is possible for
all drivers through each driver's own enable
control input. The SCT receiver also contains
an individual enable input. When this control
pin is disabled (logic "0"), the V.11 and V.35
input termination is deactivated. The 0000
decoder word will override the enable control
line for the one receiver (SCT).
All receivers include a fail-safe feature that
outputs a logic "1" when the receiver inputs
are open. The differential receivers allocated
for data and clock signals (RxD, RxC, and
SCT) have advanced fail-safe that outputs
a logic "1" when the inputs are either open,
shorted, or terminated. Other discrete or
integrated implementations require external
pull-up and pull-down resistors to define the
receiver output state. For single-ended V.28
receivers, there are internal 5kΩ pull-down
resistors on the inputs which produces a
logic high ("1") at the receiver outputs. The
single-ended V.10 receivers produce a logic
LOW ("0") on the output when the inputs are
open. This is due to an internal pull-up device
connected to the input. The differential receivers have the same internal pull-up device
on the non-inverting input which produces
a logic HIGH ("1") at the receiver output,
representing an "OFF" state to the HDLC
controller. The three differential receivers
when configured in V.35 mode (RxD, RxC
& SCT) will also include fail-safe even when
the internal termination resistor network is
connected and the inputs are either shorted
or floating.
The SP505 contains internal loopback capabilities for self-diagnostic tests. Loopback
is enabled through the decoder. To initiate
single-ended mode loopback, the decoder
word is 1010. To initiate differential mode
loopback, the decoder word is 1011. The
minimum transmission rates into the SP505
under loopback conditions are 120kbps for
single-ended mode and 5Mbps for differential
mode. The driver outputs are tri-stated and
the receiver inputs are disabled during loopback. The receiver input impedance during
loopback is approximately 10kΩ.
The SP505 is equipped with a latch control
for the four (4) decoder bits. The latch control
pin is pin 8 of the SP505. The latch control
is active low, a logic low on pin 8 will latch
the decoder signals. A logic "1" on pin 8 will
force the latch to be transparent to the user.
A pulse width of at least 30ns is required to
latch the decoder for the next mode. The
resultant output is typically 600ns after the
latch control pin is toggled assuming that
the decoder word is set.
Decoder
The SP505 has the ability to change the
interface mode of the drivers or receivers
via a 4–bit switch. The decoder for the drivers and receivers can be latched through a
control pin.
NET1/2 & TBR2 European Compliancy
As with all of Sipex's previous multi-protocol serial transceiver ICs, the drivers and
receivers have been designed to meet all
the requirements to NET1/2. The SP505 is
internally tested to all the NET1/2 physical
layer testing parameters and the ITU Series
V specifications.
The control word can be latched either high
or low to write the appropriate code into the
SP505. The codes shown in Tables 1 and
2 are the only specified, valid modes for the
SP505. Undefined codes may represent
other interface modes not specified (consult
the factory for more information). The drivers
and receivers are controlled with the data
bits labeled DEC3–DEC0. All of the drivers
With the emergence of ETSI TBR2 (Technical
Basis for Regulation) document now in place
as an alternative for European compliancy,
Sipex has tested the SP505 to TBR2 specifications to ensure "CE" approval for either
testing method.
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22
SP505_100_081308
The SP505 was externally tested by TUV
Telecom Services, Division of TUV Rheinland, and passed both NET1/2 and TBR2
requirements. Test reports (NET2/052101/98 for
NET1/2 and CTR2/05101/98 for TBR2) can be furnished
upon request.
Please note that although the SP505 adheres to NET1/2 testing; any complex or
unusual configuration should be doublechecked to ensure NET compliance. Consult
factory for details.
SP505 Driver Mode Selection
Pin Label
Mode:
RS232
V.35
RS422 w/Term
RS422
RS449
EIA530
EIA-530A
DEC3 – DEC 0
0000
0010
1110
0100
0101
1100
1101
1111
0110
SD(a)
tri-state
V.28
V.35–
V.11–
V.11–
V.11–
V.11–
V.11–
V.11–
SD(b)
tri-state
tri-state
V.35+
V.11+
V.11+
V.11+
V.11+
V.11+
V.11+
TR(a)
tri-state
V.28
V.28
V.11–
V.11–
V.11–
V.11–
V.10
TR(b)
tri-state
tri-state
tri-state
V.11+
V.11+
V.11+
V.11+
tri-state
RS(a)
tri-state
V.28
V.28
V.11–
V.11–
V.11–
V.11–
V.11–
V.10
RS(b)
tri-state
tri-state
tri-state
V.11+
V.11+
V.11+
V.11+
V.11+
tri-state
RL(a)
tri-state
V.28
V.28
V.11–
V.11–
V.10
V.11–
V.11–
V.10
RL(b)
tri-state
tri-state
tri-state
V.11+
V.11+
V.11+
V.11+
tri-state
LL(a)
tri-state
V.28
V.28
V.11–
V.11–
V.10
V.10
V.10
V.10
LL(b)
tri-state
tri-state
tri-state
V.11+
V.11+
tri-state
tri-state
tri-state
tri-state
ST(a)
tri-state
V.28
V.35–
V.11–
V.11–
V.11–
V.11–
V.11–
V.11–
ST(b)
tri-state
tri-state
V.35+
V.11+
V.11+
V.11+
V.11+
V.11+
V.11+
TT(a)
tri-state
V.28
V.35–
V.11–
V.11–
V.11–
V.11–
V.11–
V.11–
TT(b)
tri-state
tri-state
V.35+
V.11+
V.11+
V.11+
V.11+
V.11+
V.11+
tri-state
V.36
V.10
tri-state
Table 1. SP505 Driver Decoder Table
SP505 Receiver Mode Selection
V.35
RS422 w/Term
RS422
RS449
EIA530
EIA-530A
DEC3 – DEC 0
0000
0010
1110
0100
0101
1100
1101
1111
RD(a)
>10kΩ to GND
V.28
V.35–
>10kΩ to GND >10kΩ to GND
V.35+
V.11+
CS(a)
>10kΩ to GND
CS(b)
V.11+
V.11–
V.11+
V.11+
V.11+
V.11–
V.11+
V.11+
V.11–
V.11+
V.11+
V.11–
V.11+
120 Ω
RT(b)
V.11+
V.11–
0110
V.11–
120 Ω
V.11–
V.11–
120 Ω
V.11+
V.35–
V.28
V.11–
V.36
120 Ω
V.35+
>10kΩ to GND
V.11–
120 Ω
>10kΩ to GND >10kΩ to GND
V.11–
120 Ω
RD(b)
RT(a)
120 Ω
V.11–
120 Ω
RS232
120 Ω
Mode:
120 Ω
Pin Label
V.11–
V.11–
V.10
>10kΩ to GND >10kΩ to GND >10kΩ to GND
V.11+
V.11+
V.11+
V.11+
V.11+
>10kΩ to GND
DM(a)
>10kΩ to GND
V.11–
V.11–
V.11–
V.11–
V.10
V.10
DM(b)
>10kΩ to GND >10kΩ to GND >10kΩ to GND
V.11+
V.11+
V.11+
V.11+
>10kΩ to GND
>10kΩ to GND
RR(a)
>10kΩ to GND
V.11–
V.11–
V.11–
V.11–
V.11–
V.10
RR(b)
>10kΩ to GND >10kΩ to GND >10kΩ to GND
V.11+
V.11+
V.11+
V.11+
V.11+
>10kΩ to GND
IC(a)
>10kΩ to GND
V.28
V.11–
V.11–
V.10
V.10
V.10
V.10
IC(b)
>10kΩ to GND >10kΩ to GND
>10kΩ to GND
V.11+
V.11+
>10kΩ to GND
>10kΩ to GND
V.28
SCT(a)
>10kΩ to GND
SCT(b)
>10kΩ to GND >10kΩ to GND
V.28
V.28
V.35–
V.11–
V.35+
V.11+
V.11–
V.11–
V.11+
V.11+
V.11–
V.11+
>10kΩ to GND >10kΩ to GND
V.11–
V.11+
V.11–
V.11+
120 Ω
V.28
V.28
120 Ω
V.28
120 Ω
V.11–
120 Ω
V.11–
V.28
120 Ω
V.11–
V.28
Table 2. SP505 Receiver Decoder Table
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23
SP505_100_081308
(SEE PINOUT FOR VCC PINS)
1N5819
22µF
22µF
+5V
27
25
10µF
VCC
26
22µF
31
30 28
VDD C1+ C1- C2+ C232
Charge Pump
VSS
B
A
RD(a) 70
59 SD(b)
RD(b) 71
RT(a) 37
2 SDEN
13 DTR
RxC 20
58 TR(a)
56 TR(b)
RT(b) 38
CS(a) 66
3 TREN
16 RTS
CTS 80
54 RS(a)
CS(b) 67
52 RS(b)
DM(a) 68
4 RSEN
17 RL
DSR 78
47 RL(a)
DM (b) 69
45 RL(b)
RR(a) 35
18 RLEN
24 LL
DCD 19
51 LL(a)
RR(b) 36
49 LL(b)
IC(a) 39
5
RI 21
IC(b) 40
42 ST(a)
SCT(a) 76
44 ST(b)
23 STEN
0
SCTEN 7
SCT(b) 77
63 TT(a)
65 TT(b)
9
10
11
12
6
8
LATCH
TTEN
MODEX
0
15 TxC
DECODER LATCH
1
LLEN
22 ST
SCT 79
0
14 TxD
61 SD(a)
RxD 1
RS-422 Mode
Input Word
22µF
SP505
(SEE PINOUT ASSIGNMENTS FOR GROUND PINS)
A — Receiver Tr-State circuitry
V.11 & V.35 termination
resistor circuitry (RxD,
RxC & SCT)
.
B — Driver Tri-State circuitry &
V.35 Termination circuitry
(TxD, TxC & ST)
.
Figure 52. SP505 Typical Operating Circuit
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24
SP505_100_081308
MODE: RS-232 (V.28)
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
0
0
1
0
14 TxD
RD(a) 70
61 SD(a)
RxD 1
2 SDEN
13 DTR
RT(a) 37
58 TR(a)
RxC 20
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
4 RSEN
17 RL
DM(a) 68
47 RL(a)
DSR 78
18 RLEN
24 LL
RR(a) 35
51 LL(a)
DCD 19
5 LLEN
IC(a) 39
22 ST
RI 21
42 ST(a)
23 STEN
SCT(a) 76
15 TxC
SCT 79
63 TT(a)
SCTEN 7
6 TTEN
RECEIVERS
DRIVERS
Figure 53. Mode Diagram — RS-232
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25
SP505_100_081308
MODE V.35
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
1
1
1
0
14 TxD
RD(b) 71
V.35 Ntwk
RxD 1
V.35 Ntwk
RD(a) 70
2 SDEN
V.35 Ntwk
RT(b) 38
59 SD(b)
13 DTR
RT(a) 37
RxC 20
61 SD(a)
58 TR(a)
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
4 RSEN
17 RL
DM(a) 68
47 RL(a)
DSR 78
18 RLEN
24 LL
RR(a) 35
51 LL(a)
DCD 19
5 LLEN
22 ST
V.35 Ntwk
IC(a) 39
RI 21
42 ST(a)
44 ST(b)
23 STEN
SCT(a) 76
V.35 Ntwk
SCTEN 7
SCT(b) 77
V.35 Ntwk
SCT 79
15 TxC
63 TT(a)
65 TT(b)
6 TTEN
RECEIVERS
DRIVERS
Figure 54. Mode Diagram — V.35
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26
SP505_100_081308
MODE: RS-422 (w/ termination)
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
0
1
0
0
14 TxD
RD(a) 70
61 SD(a)
120 Ω
RxD 1
59 SD(b)
RD(b) 71
2 SDEN
13 DTR
RT(a) 37
58 TR(a)
120 Ω
RxC 20
56 TR(b)
RT(b) 38
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
4 RSEN
DM(a) 68
17 RL
47 RL(a)
DSR 78
45 RL(b)
DM(b) 69
18 RLEN
RR(a) 35
24 LL
51 LL(a)
DCD 19
49 LL(b)
RR(b) 36
5 LLEN
IC(a) 39
22 ST
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
63 TT(a)
120 Ω
SCT 79
15 TxC
65 TT(b)
SCTEN 7
SCT(b) 77
6 TTEN
RECEIVERS
DRIVERS
Figure 55. Mode Diagram — RS-422
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27
SP505_100_081308
MODE: RS-449
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
1
1
0
0
14 TxD
RD(a) 70
61 SD(a)
120 Ω
RxD
1
59 SD(b)
RD(b) 71
2 SDEN
13 DTR
RT(a) 37
58 TR(a)
120 Ω
RxC 20
56 TR(b)
RT(b) 38
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
4 RSEN
17 RL
DM(a) 68
DSR 78
47 RL(a)
DM(b) 69
18 RLEN
RR(a) 35
24 LL
DCD 19
51 LL(a)
RR(b) 36
5 LLEN
IC(a) 39
22 ST
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
120 Ω
SCT 79
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
TTEN
DRIVERS
Figure 56. Mode Diagram — RS-449
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28
SP505_100_081308
MODE: RS-422 (w/o termination)
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
0
1
0
1
14 TxD
RD(a) 70
RxD
61 SD(a)
1
59 SD(b)
RD(b) 71
2 SDEN
13 DTR
RT(a) 37
58 TR(a)
RxC 20
56 TR(b)
RT(b) 38
3
TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
4 RSEN
DM(a) 68
17 RL
47 RL(a)
DSR 78
45 RL(b)
DM(b) 69
18 RLEN
RR(a) 35
24 LL
51 LL(a)
DCD 19
49 LL(b)
RR(b) 36
5
IC(a) 39
LLEN
22 ST
42 ST(a)
RI 21
44 ST(b)
IC(b) 40
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
SCT 79
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
TTEN
DRIVERS
Figure 57. Mode Diagram — RS-422 w/o termination
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29
SP505_100_081308
MODE: EIA-530
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
1
1
0
1
14 TxD
RD(a) 70
61 SD(a)
120 Ω
RxD 1
59 SD(b)
RD(b) 71
2 SDEN
13 DTR
RT(a) 37
58 TR(a)
120 Ω
RxC 20
56 TR(b)
RT(b) 38
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
4 RSEN
17 RL
DM(a) 68
47 RL(a)
DSR 78
45 RL(b)
DM(b) 69
18 RLEN
RR(a) 35
24
LL
DCD 19
51
LL(a)
RR(b) 36
5
IC(a) 39
22
ST
42
ST(a)
44
ST(b)
23
STEN
15
TxC
63
TT(a)
65
TT(b)
6
TTEN
RI 21
120 Ω
SCT(a) 76
SCT 79
SCTEN 7
SCT(b) 77
RECEIVERS
LLEN
DRIVERS
Figure 58. Mode Diagram — EIA-530
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
30
SP505_100_081308
MODE: EIA-530A
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
1
1
1
1
14 TxD
RD(a) 70
61 SD(a)
120 Ω
RxD 1
59 SD(b)
RD(b) 71
2
SDEN
13 DTR
RxC 20
58 TR(a)
120 Ω
RT(a) 37
RT(b) 38
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
52 RS(b)
CS(b) 67
4
DM(a) 68
17 RL
RSEN
47 RL(a)
DSR 78
45 RL(b)
18 RLEN
RR(a) 35
24 LL
DCD 19
51 LL(a)
RR(b) 36
5
LLEN
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
15 TxC
63 TT(a)
120 Ω
SCT 79
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
TTEN
DRIVERS
Figure 59. Mode Diagram — EIA-530A
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31
SP505_100_081308
MODE:V.36
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
0
1
1
0
14 TxD
RD(a) 70
61 SD(a)
120 Ω
RxD 1
59 SD(b)
RD(b) 71
2 SDEN
13 DTR
RxC 20
58 TR(a)
120 Ω
RT(a) 37
RT(b) 38
3 TREN
16 RTS
CS(a) 66
54 RS(a)
CTS 80
4 RSEN
17 RL
DM(a) 68
47 RL(a)
DSR 78
18 RLEN
24 LL
RR(a) 35
51 LL(a)
DCD 19
5 LLEN
22 ST
IC(a) 39
42 ST(a)
RI 21
44 ST(b)
23 STEN
SCT(a) 76
63 TT(a)
120 Ω
SCT 79
15 TxC
65 TT(b)
SCTEN 7
SCT(b) 77
6
RECEIVERS
TTEN
DRIVERS
Figure 60. Mode Diagram — V.36
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32
SP505_100_081308
LOOPBACK MODE...
The SP505 is equipped with two loopback
modes. Single-ended loopback internally
connects V.28 driver outputs to V.28 receiver
inputs. The signal path is non-inverting and
will support data rates up to 120kbps. The
propagation delay times are as specified
in the electrical specifications. To initiate
a single-ended loopback, the code "1010"
should be written to the driver decoder.
Differential loopback is implemented by
applying "1011" to the driver decoder. This
internally connects V.11 driver outputs to
V.11 receiver inputs. The signal path again
is non-inverting; the differential loopback
data rate can be at least 5Mbps.
Under loopback conditions the receiver
decoder is disabled. While the SP505 is in
either single-ended or differential loopback
mode, the driver outputs are tri-stated and
the receiver inputs are disabled.
MODE: Single-Ended Loopback
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
1
0
1
0
MODE: Differential Loopback
DRIVER/RECEIVER
DEC3 DEC2 DEC1 DEC0
1
0
1
1
14 TxD
RD(a) 70
RxD 1
RxD 1
2 SDEN
RD(b) 71
13 DTR
RT(a) 37
RxC 20
CTS 80
58 TR(a)
RxC 20
3 TREN
RT(b) 38
DSR 78
RR(a) 35
54 RS(a)
CTS 80
4 RSEN
CS(b) 67
Mode
18 RLEN
LL
51
LL(a)
Loopback
DEC = 1010
DEC = 1011
45 RL(b)
DCD 19
49
LL(b)
5
LLEN
IC(a) 39
22
ST
RI 21
42
ST(a)
44
ST(b)
23
STEN
15
TxC
63
TT(a)
RR(b) 36
IC(b) 40
SCT(a) 76
SCT 79
SCTEN 7
SCT(b) 77
TTEN
RECEIVERS
DRIVERS
Driver Output
non-inverting
47 RL(a)
24
6
4 RSEN
17 RL
RR(a) 35
63 TT(a)
RECEIVERS
52 RS(b)
24 LL
15 TxC
SCTEN 7
54 RS(a)
DM(b) 69
23 STEN
SCT 79
3 TREN
16 RTS
18 RLEN
42 ST(a)
SCT(a) 76
56 TR(b)
DSR 78
22 ST
RI 21
58 TR(a)
47 RL(a)
5 LLEN
IC(a) 39
2 SDEN
13 DTR
DM(a) 68
51 LL(a)
DCD 19
59 SD(b)
CS(a) 66
17 RL
DM(a) 68
61 SD(a)
RT(a) 37
16 RTS
CS(a) 66
14 TxD
RD(a) 70
61 SD(a)
inverting
TT(b)
6
TTEN
DRIVERS
Receiver Input
non-inverting
65
inverting
Driver Receiver
Input
Output
tri-state
tri-state
>10KΩ to GND
>10KΩ to GND
active
active
tri-state
tri-state
>10KΩ to GND
>10KΩ to GND
active
active
Power down
clamped
VCC=VDD=VSS=0V
tri-state
tri-state
>10KΩ to GND >10KΩ to GND inactive at ±0.6V
Tri-state
DEC = 0000
tri-state
tri-state
>10KΩ to GND >10KΩ to GND inactive tri-state
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
33
SP505_100_081308
PACKAGE: 80 PIN LQFP
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
34
SP505_100_081308
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP505ACM-L..........................0°C to +70°C .................................................80–pin LQFP
SP505BCM-L......................... 0°C to +70°C .................................................80–pin LQFP
REVISION HISTORY
Date
REVISION
2-24-05
---
8-13-08
1.0.0
DESCRIPTION
Legacy Sipex Data Sheet
SP505A/SP505B are no longer available in MQFP package
per PCN 07-1102-06a. Device is now only available in LQFP
package. Package drawing and ordering information have
been updated. Changed to Exar data sheet format and revision to 1.0.0.
Notice
EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for
illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for
use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been
minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2008 EXAR Corporation
Datasheet August 2008
Send your Interface technical inquiry with technical details to: uarttechsupport@exar.com
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • Fax (510) 668-7017 • www.exar.com
35
SP505_100_081308
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