SLD-2000

Product Description Sirenza Microdevices’ SLD2000 is a robust 12 Watt, high performance LDMOS transistor die, designed for operation from 10 to 2700MHz. It is an excellent solution for applications requiring high linearity and efficiency. The SLD2000 is typically used as a driver or output stage for power amplifier, or transmitter applications. These robust power transistors are fabricated using Sirenza’s high performance XEMOS IITM process. SLD-2000 12 Watt Discrete LDMOS FET -Bare Die Functional Schematic Diagram ESD Protection • • • • • • • Product Features 12 Watt Output P1dB Single Polarity Operation 19dB Gain at 900 MHz XeMOS IITM LDMOS Integrated ESD Protection, Class 1B Aluminum Topside Metallization Gold Backside Metallization Gate Manifold Drain Manifold Source - Backside Contact RF Specifications Symbol Frequency Gain Efficiency Linearity Linearity RTH Parameter Frequency of Operation 10 Watt CW, 902 - 928MHz Drain Efficiency at 10 Watt CW, 915MHz 3rd Order IMD at 10 Watt PEP (Two Tone), 915MHz 1dB Compression (P1dB) • • • • • Applications Base Station PA Driver Repeaters Military Communications RFID GSM, CDMA, Edge, WDCDMA Unit MHz dB % dBc W ºC/W Min 10 Typ 19 47 -32 12 4 Max 2700 - Thermal Resistance (Junction-to-Case, mounted in package) Test Conditions: Mounted in ceramic package and tested in Sirenza Evaluation Board VDS = 28.0V, IDQ = 150mA, TMounting Surface = 25ºC T DC Specifications Symbol gm VGS Threshold VDS Breakdown Ciss Crss Coss RDSON Parameter Forward Transconductance @ 125mA IDQ, VDS=28V IDS=3mA 1mA VDS current Input Capacitance (Gate to Source) VGS=0V, VDS=28V Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V Output Capacitance (Drain to Source) VGS=0V, VDS=28V Drain to Source Resistance, VGS=10V VDS=250mV Unit mA / V V V pF pF pF R 3.0 65 Min Typical 590 3.8 70 27.5 0.8 14.7 0.6 0.75 5.0 Max The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-104292 Rev C SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die Quality Specifications Parameter ESD Rating MTTF Description Human Body Model 200oC Channel Unit Volts Hours Typical 750 1.2 X 106 Contact Description Pad # 1 2 3 Function Gate Drain Source Description Aluminum metallized manifold MOSFET Gate with ESD protection structure. (Topside contact) Aluminum metallized manifold MOSFET Drain. (Topside contact) Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for proper operation. (Backside contact) Pad Diagram ESD Protection Note 1: Gate voltage must be applied to to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly terminated on both input and output. Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage with LDMOS transistors. Note 3: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Unit Volts Volts dBm VSWR ºC ºC Pad #3 Backside Source = Ground Pad #1 Gate Manifold Pad #2 Drain Manifold Absolute Maximum Ratings Parameters Drain Voltage (VDS ) Gate Voltage (VGS), VDS =0 RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Storage Temperature Range Value 35 20 +33 10:1 +200 -40 to +150 Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-104292 Rev C SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die Impedance Data Frequency (MHz) 880 960 1840 1960 2140 Zsource 0.5 + j 2.5 0.8 + j 1.3 0.7 - j 0.4 0.5 -j 1.3 0.7 - j 2.3 Zload 3.9 + j 4.9 4.5 + j 3.6 1.3 + j 0.0 1.3 + j 0.1 1.2 + j 0.2 De-embedding Information Description Number of Bond Wires Length of Bond Wires Height of Bond Wires Pitch of Bond Wires Bond Wire Diameter Gate 6 0.037 0.006 0.012 0.002 Drain 9 0.040 0.007 0.008 0.002 Impedances Referenced to Wirebond/PCB Interface. All Dimensions in Inches. Wirebond Heights Referenced to Top Surface of Die. Zsource and Zload are the optimal impedances presented to the SLD2000 when operating at 28V, Idq=150mA, Pout=10 W PEP. Device under test Input Matching Network Z source 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 Output Matching Network Z load http://www.sirenza.com EDS-104292 Rev C SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die Typical Performance Curves for packaged die tested in SLD-2083CZ 900 MHz Application Circuit CW Gain, Efficiency vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz 25 24 23 22 Gain (dB) 21 20 19 18 17 16 15 0 2 60 55 50 45 Efficiency (%) 40 35 30 60 CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W 0 50 Gain (dB), Efficiency (%) -4 40 30 Gain Efficiency IRL -8 -12 Gain Efficiency 25 20 15 10 20 -16 10 -20 4 6 8 Pout (W) 10 12 14 16 0 900 905 910 915 920 -24 925 Frequency (MHz) 60 2 Tone Gain, Efficiency, Linearity and IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W PEP, Delta F=1 MHz Gain IM3 IM7 Efficiency IM5 IRL 0 45 40 35 2 Tone Gain, Efficiency, Linearity vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz, Delta F=1 MHz -25 -30 -35 -40 -45 -50 -55 -60 IMD (dBc) 50 Gain (dB), Efficiency (%) -10 Gain (dB), Efficiency (%) 40 -20 IMD(dBc), IRL (dB) 30 25 20 15 10 5 30 -30 20 -40 10 -50 Gain IM3 IM7 1 3 5 7 Pout (W PEP) Efficiency IM5 -65 -70 0 900 905 910 915 920 Frequency (MHz) -60 925 0 9 11 13 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-104292 Rev C Input Return Loss (dB) SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die Die Map Dimensions Inches [mm] 0.0850 [2.16] GATE 0.0450 [1.14] DRAIN SOURCE - BACKSIDE CONTACT - NOT SHOWN DIE THICKNESS - 0.004 [0.10] AuSi, AuSn, or AuGe eutectic die attach is recommended. AlSi bond wires are recommended. Part Number Ordering Information Part Number SLD-2000 Gel Pack 100 pcs. per pack Die are screened prior to dicing to DC parameters and are shipped per Sirenza application note AN-039 Visual Criteria of Unpackaged Die. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-104292 Rev C