SL74HCT74D

SL74HCT74 Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The SL74HCT74 is identical in pinout to the LS/ALS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION SL74HCT74N Plastic SL74HCT74D SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Set L H L PIN 14 =VCC PIN 7 = GND H H H H H Reset H L L H H H H H L H Clock X X X Data X X X H L X X X Outputs Q H L H * Q L H H* L H H L No Change No Change No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don’t care SLS System Logic Semiconductor SL74HCT74 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD T stg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond whitch damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temp erature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN a nd VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT74 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 °C to -55°C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1 1.0 ≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0 10 ≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 ±1.0 40 µA µA V Unit VIH VIL VOH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V V V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IIN ICC M aximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND VIN=VCC or GND IOUT=0µA VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA ∆ICC ≥-55°C 25°C to 125°C 2.4 mA 5.5 2.9 SLS System Logic Semiconductor SL74HCT74 AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V±10%,CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C 30 24 24 15 10 ≤85°C ≤125°C Unit fmax tPLH, t PHL tPLH, t PHL tTLH, t THL CIN Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Enabled Output) 24 30 30 19 10 20 36 36 22 10 MHz ns ns ns pF Typical @25°C,VCC=5.0 V 130 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC TIMING REQUIREMENTS (VCC =5.0 V±10%,CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol tsu th trec tw tw tr, t f Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Set or Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) 25 °C to-55°C 15 3 6 15 15 500 ≤85°C 19 3 8 19 19 500 ≤125°C 22 3 9 22 22 500 Unit ns ns ns ns ns ns SLS System Logic Semiconductor SL74HCT74 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor