SL74LV373N

SL74LV373 OCTAL D-TYPE TRANSPARENT LATCH (3-State) S L74LV373 are compatible by pinning with SL74HC373 and SL74HCT373 series. Input voltage levels are compatible with standard CMOS levels. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Voltage supply range: 2.0 to 3.2 V • LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • Input current LOW/HIGH: 8 mÀ • Latch current: not less than 150 mÀ at Ò = 125 °Ñ • ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM • BLOCK DIAGRAM ORDERING INFORMATION S L74LV373N Plastic DIP S L74LV373D SOIC TA = -40° to 125° C for all packages D0 D1 D2 D3 D4 D5 D6 D7 03 04 07 08 13 14 17 18 02 05 06 09 12 15 16 Q0 Q1 Q2 Q3 Q4 Q5 Q6 OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 PIN ASSIGNMENT 01 02 03 04 05 20 19 18 17 16 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE 373 06 07 08 09 10 15 14 13 12 11 19 Q7 11 GND LE OE 01 Pin 20=VCC Pin 10 = GND OE L L L H FUNCTION TABLE Inputs LE H H L X Dn H L X X Output Qn H L no change Z SLS System Logic Semiconductor SL74LV373 ABSOLUTE MAXIMUM RATINGS* Symbol VCC IIK * 1 2 Parameter Supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP *4 SOIC *4 Storage temperature range Rating -0.5 to +5.0 ±20 ±50 ±35 ±70 ±70 750 500 -65 to +150 Unit V mÀ mÀ mÀ mÀ mÀ mW IOK * IO * ICC 3 IGND PD Tstg * °C In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the absolute maximum ratings functioning is guarateed at the recommended operatng conditions. *1 Provided VI < -0.5 V or VI > VCC + 0.5 V. *2 Provided VO < -0.5 V or VO > VCC + 0.5 V. *3 Provided -0.5 V < VO < VCC + 0.5 V. *4 When operating in the temperature range of 70°Ñ to 125°C power dissipation value decreses: - for Plastic DIP by 12 m W/ °C - for SOIC by 8 m W/ °C RECOMMENDED OPERAING CONDITIONS Symbol VCC VIN VOUT TA tLH, tHL Supply voltage Input voltage Output voltage Operating ambient temperature range. For all types of packages Input rise and fall times VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Parameter Min 1.2 0 0 -40 0 Max 3.6 VCC VCC 125 1000 700 500 400 Unit V V V °C ns SLS System Logic Semiconductor SL74LV373 DC CHARACTERISTICS Test Symbol Parameter conditions VCC, V 25° C min max VIH HIGH level voltage VO = VCC-0.1 V 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 3.0 1.2 2.0 3.0 3.6 3.0 3.6 3.6 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 0.3 0.6 0.9 1.1 0.09 0.09 0.09 0.09 0.33 ±0.1 ±0.5 Limits -40° C to 85° C min 0.9 1.4 2.1 2.5 1. 0 1.9 2.9 3.5 2.34 m ax 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.4 ±1.0 ±5 125° C min 0.9 1.4 2.1 2.5 1. 0 1.9 2.9 3.5 2.20 m ax 0.3 0.6 0.9 1.1 0.1 0.1 0.1 0.1 0.5 ±1.0 ±10 V Unit VIL LOW level voltage VO =0.1 V V VOH HIGH level output voltage VI = VIH or VIL IO = -50 µÀ V VI = VIH or VIL IO = -8 mÀ VOL LOW level output voltage VI = VIH or VIL IO = 50 µÀ V V VI = VIH or VIL IO = 8 mÀ II IOZ Input current OFF-state output current VI = VCC or 0 V 3-state outputs VI = VIL or VIH VO =VCC or 0V VI =VCC or 0 V IO = 0 µÀ V µÀ µÀ ICC Supply current 3.6 - 8.0 - 80 - 160 µÀ SLS System Logic Semiconductor SL74LV373 AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns) Test Symbol Parameter conditions VCC, V 25° C Limits -40°C to 85°C m ax 190 48 29 230 56 34 200 43 28 200 50 30 100 20 13 125°C min 450 41 24 100 15 12 25 5 5 m ax 220 58 35 270 68 41 240 45 32 240 60 36 120 24 15 pF ns Unit min max min tPHL, tPLH Propagation delay Figure 1 from Dn to Qn tPHL, tPLH Propagation delay Figure 2 from LE to Qn tPHZ tPLZ 3-state output from OE to Qn enable time tPZH tPZL 3-state disable from OE to Qn time tTHL, tTLH Figure 4 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 1.2 2.0 3.0 3.0 VI = 0 V or VCC 3.0 250 30 18 45 15 9 25 5 5 150 38 23 180 45 27 160 35 23 160 40 24 75 16 10 7 80 350 34 20 50 17 10 25 5 5 - Figure 4 HIGH-to-LOW and Figures 1,2 LOW-to-HIGH transition time Clock pulse width HIGH or LOW Set-up time Dn to LE Hold time Dn to LE Input capacitance Power dissipation capacitance (per flip-flop) Figure 2 tW tSU Figure 3 tH Figure 3 CI CPD SLS System Logic Semiconductor SL74LV373 tLH 0.9 Dn V1 0.1 tPLH V1 tHL 0.9 VCC 0.1 tPHL GND 0.9 V1 0.1 tTLH V1 = 0.5V CC 0.9 V1 0.1 0V B Qn tTHL Figure 1 - Time diagram tLH 0.9 LE 0.1 V1 tW tPLH tPHL V1 V1 GND VCC 0.9 V1 Qn 0.1 tTLH V1 = 0.5V CC 0.9 V1 0.1 0V B tTHL Figure 2 - Time diagram. SLS System Logic Semiconductor SL74LV373 VCC V1 V1 V1 V1 Dn GND tSU tH tSU tH VCC LE V1 V1 GND V1 = 0.5V CC Figure 3 - Time diagram tLH 0.9 OE V1 0.1 tPZH V1 V1 tHL 0.9 VCC 0.1 GND VOH 0.9 tPHZ Qn 0V B tPLZ Qn V1 tPZL 0.1 VOL V1 = 0.5V CC VCC Figure 4 -Time diagram SLS System Logic Semiconductor SL74LV373 1.66 mm 18 19 17 16 15 14 13 12 1.68 mm 20 11 74LV373/374 1 10 On-chip marking 2 9 7 8 3 4 5 6 Drawing of the chip Pads allocation Table Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 coordinates (counted from lower left corner), mm X Y 0.142 0.628 0.142 0.377 0.142 0.125 0.498 0.125 0.693 0.125 0.871 0.125 1.095 0.125 1.423 0.130 1.423 0.329 1.423 0.587 1.423 0.949 1.423 1.198 1.423 1.447 1.085 1.447 0.868 1.447 0.696 1.447 0.461 1.447 0.142 1.447 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 SLS System Logic Semiconductor SL74LV373 19 20 0.142 0.142 1.245 0.997 0.108 x 0.108 0.108 x 0.108 SLS System Logic Semiconductor