SCH3112I-NU

SCH3112, SCH3114, SCH3116 LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports PRODUCT FEATURES ■ Datasheet — Port 92 Support — Fast Gate A20 and KRESET Outputs — Phoenix Keyboard BIOS ROM ■ General Features — — — — — — — — — — — — — 3.3 Volt Operation (SIO Block is 5 Volt Tolerant) Low Pin Count Bus (LPC) Interface Programmable Wake-up Event (PME) Interface PC99, PC2001 Compliant ACPI 2.0 Compliant Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems ISA Plug-and-Play Compatible Register Set Four Address Options for Power On Configuration Port System Management Interrupt (SMI) 40 General Purpose I/O pins 6 GPIO with VID compatible inputs Support for power button on PS/2 Keyboard Security Key Register (32 byte) for Device Authentication Multiple Serial Ports — — — — — — — — — — — SCH3112 - 2 Full Function Serial Ports SCH3114 - 4 Full Function Serial Ports SCH3116 - 4 Full Function and 2 Four-Pin Serial Ports High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k, 460k, 921k and 1.5M Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options Support IRQ Sharing among serial ports RS485 Auto Direction Control Mode Multiprotocol Infrared Interface IrDA 1.0 Compliant SHARP ASK IR 480 Addresses, Up to 15 IRQ ■ ■ ■ ■ Watchdog Timer Resume and Main Power Good Generator Programmable Clock Output to 16 HZ. 2.88MB Super I/O Floppy Disk Controller — — — — — — — — — — — — Licensed CMOS 765B Floppy DiskController Supports Two Floppy Drives Configurable Open Drain/Push-Pull Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM® Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers 480 Address, Up to Eight IRQ and Four DMA Options Support FDD Interface on Parallel Port Pins ■ Infrared Port — — — — ■ Multi-Mode™ Parallel Port with ChiProtect™ — Standard Mode IBM PC/XT®, PC/AT®, and PS/2™ Compatible Bi-directional Parallel Port — Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) — EEE 1284 Compliant Enhanced Capabilities Port (ECP) — ChiProtect Circuitry for Protection — 960 Address, Up to 15 IRQ and Four DMA Options — Monitor Power supplies (+2.5V, +5V, +12V, Vccp (processor voltage), VCC, Vbat and Vtr. — Remote Thermal Diode Sensing for Two External Temperature Measurements accurate to 1.5oC — Internal Ambient Temperature Measurement — Limit Comparison of all Monitored Values — Programmable Automatic FAN control based on temperature — nHWM_INT Pin for out-of-limit Temperature or Voltage Indication — Configurable offset for internal or external temperature channels — Thermtrip signal for over temperature indication ■ Hardware Monitor ■ Enhanced Digital Data Separator — 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbp Data Rates — Programmable Precompensation Modes ■ Keyboard Controller — — — — — 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface — Asynchronous Access to Two Data Registers and One Status Register — Supports Interrupt and Polling Access — 8 Bit Counter Timer ■ ■ ■ ■ IDE Reset Output and 3 PCI Reset Buffers with Software Control Capability (SCH3112 and SCH3114 Only) Power Button Control and AC Power Failure Recovery (SCH3112 and SCH3114 Only) Industrial (+85°C to -40°C) Temperature Range 128 Pin VTQFP Package Rev 0.2 (09-28-04) SMSC SCH311X DATASHEET LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet ORDER NUMBER(S): SCH3112I-NE FOR 128 PIN, VTQFP PACKAGE (INDUSTRIAL TEMPERATURE RANGE) SCH3114I-NE FOR 128 PIN, VTQFP PACKAGE (INDUSTRIAL TEMPERATURE RANGE) SCH3116I-NE FOR 128 PIN, VTQFP PACKAGE (INDUSTRIAL TEMPERATURE RANGE) SCH3112I-NU FOR 128 PIN, VTQFP PACKAGE (LEAD-FREE, INDUSTRIAL TEMPERATURE RANGE) SCH3114I-NU FOR 128 PIN, VTQFP PACKAGE (LEAD-FREE, INDUSTRIAL TEMPERATURE RANGE) SCH3116I-NU FOR 128 PIN, VTQFP PACKAGE (LEAD-FREE, INDUSTRIAL TEMPERATURE RANGE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2004. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Rev 0.2 (09-28-04) DATASHEET ii SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 0.1 Reference Documents 1. Intel Low Pin Count Specification, Revision 1.0, September 29, 1997 2. PCI Local Bus Specification, Revision 2.2, December 18, 1998 3. Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999 4. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. 5. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. 6. SMSC Application Note (AN 8-8) “Keyboard and Mouse Wakeup Functionality”, dated 03/23/02. SMSC SCH311X DATASHEET iii Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Rev 0.2 (09-28-04) DATASHEET iv SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table of Contents 0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Chapter 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 2.2 2.3 SCH311X Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 4 Power Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 VCC Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HVTR Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Volt Operation / 5 Volt Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VTR Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Trickle Power Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vbat Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.768 KHz Trickle Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Super I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Events (PME/SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 26 27 27 28 28 Chapter 5 SIO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 5.2 Super I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Host Processor Interface (LPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Chapter 6 LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 6.2 6.3 LPC Interface Signal Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 LPC Required Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 LPC Optional Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported LPC Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 SYNC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Reset Policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 31 32 32 33 Chapter 7 Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 FDC Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Status Register A (SRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 PS/2 Model 30 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Status Register Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5 Data Transfer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 36 47 55 64 Chapter 8 Serial Port (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.1 8.2 8.3 8.4 Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 IR Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS485 Auto Direction Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reduced Pin Serial Ports (SCH3116 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 93 93 95 97 Chapter 9 Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.1 IBM XT/AT Compatible, Bi-Directional and EPP Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SMSC SCH311X DATASHEET v Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 9.2 9.3 Extended Capabilities Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 FDC/PP Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 120 121 122 Chapter 10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 11 Serial IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 12 8042 Keyboard Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Keyboard and Mouse Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Keyboard/Mouse Swap Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard and Mouse PME Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 131 131 131 132 132 132 133 133 136 Chapter 13 General Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.1 13.2 13.3 13.4 13.5 13.6 13.7 GPIO Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO PME and SMI Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Either Edge Triggered Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 141 148 148 149 150 150 Chapter 14 System Management Interrupt (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Chapter 15 PME Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15.1 15.2 15.3 15.4 15.5 PME Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling SMI Events onto the PME Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PME Function Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake on Specific Key Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake on Specific Mouse Click . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 155 155 155 156 Chapter 16 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Chapter 17 Programmable Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Chapter 18 Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 18.1 18.2 18.3 Watchdog Timer for Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 PWRGD_OUT TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Power Supply Voltage Scaling and Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Chapter 19 Buffered PCI Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.1 Buffered PCI Outputs Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.1.1 IDE Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 19.1.2 nPCIRSTx Output Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Chapter 20 Power Control Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Rev 0.2 (09-28-04) DATASHEET vi SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 20.1 20.2 20.3 20.4 20.5 20.6 nIO_PME Pin use in Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Front Panel Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/C Power Failure Recovery Control (SCH3112 and SCH3114 Devices only) . . . . . . . . . . . . . . 20.3.1 PB_OUT# and PS_ON# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2 Power Supply Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resume Reset Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Power Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1 Keyboard Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.2 System for Decoding Scan Code Make Bytes Received from the Keyboard . . . . . . . . 20.5.3 System for Decoding Scan Code Break Bytes Received from the Keyboard . . . . . . . . Wake on Specific Mouse Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 171 172 173 174 175 175 175 177 178 181 Chapter 21 Low Battery Detection Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 21.1 21.2 VBAT POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.1 Under Battery Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.2 Under VTR Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.3 Under VCC Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 183 183 184 184 Chapter 22 Battery Backed Security Key Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Chapter 23 Temperature Monitoring and Fan Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 23.1 23.2 23.3 23.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HWM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resetting the SCH311X Hardware Monitor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.1 VTR Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.2 VCC Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.3 Soft Reset (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.1 Continuous Monitoring Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2 Cycle Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.8.1 Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.8.2 Diode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.1 Interrupt Pin (nHWM_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.2 Interrupt as a PME Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.3 Interrupt as an SMI Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.4 Interrupt Event on Serial IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.1 Internal Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.2 External Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.4 Offset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.1 Limit and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.2 Device Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.3 PWM Fan Speed Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.4 Operation of PWM Pin Following a Power Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.5 Active Minimum Temperature Adjustment (AMTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 187 188 188 188 188 189 189 189 189 190 191 191 192 194 194 195 195 195 196 196 196 196 196 197 198 198 198 198 199 200 207 213 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 SMSC SCH311X DATASHEET vii Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 23.14 nTHERMTRIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.14.1 nTHERMTRIP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.14.2 Fan Speed Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.14.3 Locked Rotor Support for Tachometer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.14.4 Linking Fan Tachometers to PWMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.15 High Frequency PWM Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.15.1 PWM Frequencies Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 216 217 223 223 223 223 Chapter 24 Hardware Monitoring Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 24.1 24.2 Undefined Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defined Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.1 Register 10h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.2 Register 1Dh, 1Eh, 1Fh: Offset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.3 Registers 20-24h, 99-9Ah: Voltage Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.4 Registers 25-27h: Temperature Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.5 Registers 28-2Dh: Fan Tachometer Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.6 Registers 30-32h: Current PWM Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.7 Register 3Dh: Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.8 Register 3Eh: Company ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.9 Register 3Fh: Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.10 Register 40h: Ready/Lock/Start Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.11 Register 41h: Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.12 Register 42h: Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.13 Registers 44-4Dh, 9B-9Eh: Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.14 Registers 4E-53h: Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.15 Registers 54-59h: Fan Tachometer Low Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.16 Registers 5C-5Eh: PWM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.17 Registers 5F-61h: Zone Temperature Range, PWM Frequency . . . . . . . . . . . . . . . . . . 24.2.18 Register 62h, 63h: Min/Off, PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.19 Registers 64-66h: Minimum PWM Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.20 Registers 67-69h: Zone Low Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.21 Registers 6A-6Ch: Absolute Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.22 Registers 6D-6Eh: Zone Hysteresis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.23 Register 70-72h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.24 Register 73-78h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.25 Register 79h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.26 Register 7Ch: Special Function Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.27 Register 7Eh: Interrupt Enable 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.28 Register 7Fh: Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.29 Register 80h: Interrupt Enable 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.30 Register 81h: TACH_PWM Association Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.31 Register 82h: Interrupt Enable 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.32 Register 83h: Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.33 Registers 84h-88h: A/D Converter LSbs Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.34 Registers Registers 89h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.35 Registers 8Ah: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.36 Registers 8Bh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.37 Registers 8Ch: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.38 Registers 8Dh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.39 Registers 8Eh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.40 Registers 90h-92h: FANTACHX Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.41 Registers 94h-96h: PWMx Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.42 Register 97h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.43 Register 98h:SMSC Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.44 Registers 99h-9Ah:Voltage Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 230 230 230 230 231 232 233 234 234 234 235 236 238 239 241 242 242 244 246 247 248 249 250 250 251 251 251 252 253 254 254 255 256 256 257 257 257 257 257 258 258 259 259 260 260 Rev 0.2 (09-28-04) DATASHEET viii SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 24.2.45 24.2.46 24.2.47 24.2.48 24.2.49 24.2.50 24.2.51 24.2.52 24.2.53 24.2.54 24.2.55 24.2.56 24.2.57 24.2.58 24.2.59 24.2.60 24.2.61 24.2.62 24.2.63 24.2.64 24.2.65 24.2.66 24.2.67 24.2.68 24.2.69 24.2.70 24.2.71 Registers 9B-9EH: Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register A3h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register A4h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register A5h: Interrupt Status Register 1 - Secondary . . . . . . . . . . . . . . . . . . . . . . . . . Register A6h: Interrupt Status Register 2 - Secondary . . . . . . . . . . . . . . . . . . . . . . . . . Register A7h: Interrupt Status Register 3 - Secondary . . . . . . . . . . . . . . . . . . . . . . . . . Register ABh: TACH 1-3 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register ADh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers AE-AFh, B3h: Top Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . Register B4h: Min Temp Adjust Temp RD1, RD2 (Zones 1& 3) . . . . . . . . . . . . . . . . . . Register B5h: Min Temp Adjust Temp and Delay AMB (Zone 2) . . . . . . . . . . . . . . . . . Register B6h: Min Temp Adjust Delay RD1, RD2 (ZONE 1 & 3) Register . . . . . . . . . . Register B7h: Min Temp Adjust Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register B8h: Top Temp Exceeded Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Register BAh: SMSC Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register BBh: SMSC Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register 0BDh: SMSC Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register BFh: SMSC Reserved Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register C0h: SMSC Reserved Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register C1h: SMSC Reserved Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers C4-C5, C9h: THERMTRIP Temperature Limit Zone Registers . . . . . . . . . . . Register CAh: THERMTRIP Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register CBh: THERMTRIP Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . Register CEh: SMSC Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers D1,D6,DBh: PWM Max Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . Register E0h: Enable LSbs for Auto Fan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register FFh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 260 260 260 261 261 261 262 262 262 263 263 264 264 265 265 265 265 265 266 266 266 267 267 267 267 268 Chapter 25 Config Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 25.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 25.1.1 Global Config Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 25.1.2 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Chapter 26 Runtime Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 26.1 26.2 Runtime Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Runtime Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Chapter 27 Valid Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Chapter 28 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 28.1 28.2 28.3 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.1.1 Super I/O section (pins 3 to 112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.1.2 Hardware Monitoring Block (pins 1 and 2 and pins 113 to 128) . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance Values for Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 339 339 339 345 Chapter 29 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LPC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Floppy Disk Controller Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IR Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 348 349 352 353 360 363 364 SMSC SCH311X DATASHEET ix Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 29.9 29.10 29.11 29.12 Keyboard/Mouse Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resume Reset Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nLEDx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 365 366 366 Chapter 30 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Appendix A ADC Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Appendix B Example Fan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Appendix C Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 C.1 XNOR-Chain Test Mode Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 C.1.1 Board Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Rev 0.2 (09-28-04) DATASHEET x SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet List of Figures Figure 2.1 SCH3112 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2.2 SCH3114 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.3 SCH116 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2.4 SCH3116 Summary - 6 Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3.1 SCH311X Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8.1 Serial Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 8.2 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 8.3 Half Duplex Operation with Direction Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 8.4 Reduce Pin Serial Port Control Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 12.1 SCH311X Keyboard and Mouse Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 12.2 Keyboard Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 12.3 Mouse Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 13.1 GPIO Function Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 15.1 8042 Isolation and Keyboard and Mouse Port Swap Representation . . . . . . . . . . . . . . . . . 157 Figure 18.1 Reset Generation Circuit (For Illustrative Purposes Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 18.2 PWRGD_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 19.1 nPCIRSTx Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 20.1 Power Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 20.2 nFPRST Debounce Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 20.3 Power Supply during Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 20.4 Power Supply After Power Failure (Return to Off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 20.5 Power Supply After Power Failure (Return to On) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 20.6 Sample Single-Byte Make Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 20.7 Sample Multi-Byte Make Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 20.8 Option 1: KB_PB_STS wake event fixed pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 20.9 Option 2: Assert KB_PB_STS wake event until scan code not programmed make code . . 179 Figure 20.10Option 3: De-assert KB_PB_STS when scan code equal break code . . . . . . . . . . . . . . . . 180 Figure 21.1 External Battery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 23.1 HWM Block Embedded in SCH311X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 23.2 HWM Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Figure 23.3 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 23.4 Automatic Fan Control Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 23.5 Automatic Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 23.6 Spin Up Reduction Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 23.7 Illustration of PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 23.8 AMTA Illustration, Adjusting Minimum Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 23.9 AMTA Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Figure 23.10nTHERMTRIP Output Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 23.11PWM and Tachometer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 24.1 Fan Activity Above Fan Temp Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Figure 29.1 Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Figure 29.2 Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Figure 29.3 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Figure 29.4 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Figure 29.5 Output Timing Measurement Conditions, LPC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Figure 29.6 Input Timing Measurement Conditions, LPC Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Figure 29.7 I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Figure 29.8 I/O Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Figure 29.9 DMA Request Assertion through LDRQ#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Figure 29.10DMA Write (First Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Figure 29.11DMA Read (First Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Figure 29.12Floppy Disk Drive Timing (AT Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Figure 29.13EPP 1.9 Data or Address Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 SMSC SCH311X DATASHEET xi Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Figure 29.14EPP 1.9 Data or Address Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.15EPP 1.7 Data or Address Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.16EPP 1.7 Data or Address Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.17Parallel Port FIFO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.18ECP Parallel Port Forward Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.19ECP Parallel Port Reverse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.20IrDA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.21IrDA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.22Amplitude Shift-Keyed IR Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.23Amplitude Shift-Keyed IR Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.24Setup and Hold Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.25Serial Port Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.26Keyboard/Mouse Receive/Send Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.27Resume Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.28nLEDx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29.29PWMx Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 30.1 128 Pin VTQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure B.1 Fan Drive Circuitry for Low Frequency Option (Apply to PWM Driving Two Fans) . . . . . . . Figure B.2 Fan Drive Circuitry for Low Frequency Option (Apply to PWM Driving One Fan) . . . . . . . . Figure B.3 Fan Tachometer Circuitry (Apply to Each Fan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure B.4 Remote Diode (Apply to Remote2 Lines). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure B.5 Suggested Minimum Track Width and Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure C.1 XNOR-Chain Test Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 355 355 357 358 359 360 361 362 363 363 364 364 365 366 366 367 373 374 374 375 375 377 Rev 0.2 (09-28-04) DATASHEET xii SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet List of Tables Table 2.1 SCH3112 Summary - 2 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2.2 SCH3114 Summary - 4 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2.3 SCH311X Signal Difference Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2.5 SCH3112 Specific Signals (Note 2.15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2.6 SCH3114 Specific Signals (Note 2.15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2.7 SCH3116 Specific Signals (Note 2.15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 2.8 Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5.1 Super I/O Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6.1 Supported LPC Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 7.1 Status, Data and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7.2 Internal 2 Drive Decode – Normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 7.3 Tape Select Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 7.4 Drive Type ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 7.5 Precompensation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 7.6 Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 7.7 DRVDEN Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 7.8 Default Precompensation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 7.9 FIFO Service Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 7.10 Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 7.11 Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 7.12 Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 7.13 Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 7.14 Description of Command Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 7.15 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 7.16 Sector Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 7.17 Effects of MT and N Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.18 Skip Bit vs. Read Data Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.19 Skip Bit vs. Read Deleted Data Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7.20 Result Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7.21 Verify Command Result Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7.22 Typical Values for Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 7.23 Interrupt Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 7.24 Drive Control Delays (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 7.25 Effects of WGATE and GAP Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 8.1 Addressing the Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 8.2 Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 8.3 Serial Ports Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 8.4 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 8.5 register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 8.6 Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 8.7 Register Summary for an Individual UART Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 8.8 SCH311X IRQ Sharing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 8.9 nRTS/nDTR Automatic Direction Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 9.1 Parallel Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 9.2 EPP Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 9.3 ECP Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 9.4 ECP Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 9.5 Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 9.6 Extended Control Register (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 9.7 Extended Control Register (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 9.8 Extended Control Register (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 9.9 Channel/Data Commands Supported in ECP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SMSC SCH311X DATASHEET xiii Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 9.10 Parallel Port Floppy Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9.11 PP Buffer Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10.1 State of Floppy Disk Drive Interface Pins in Powerdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12.1 I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12.2 Host Interface Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12.4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13.1 GPIO Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13.2 SCH311X General Purpose I/O Port Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13.3 GPIO Configuration Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13.4 GPIO Read/Write Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15.1 PME Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15.2 PME Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18.1 RESGEN Strap Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18.2 RESGEN Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18.3 PWRGD_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19.1 Buffered PCI outputs Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19.2 nIDE_RSTDRV Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19.3 nIDE_RSTDRV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.1 Power Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.2 Internal PWROK Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.3 Definition of APF Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.4 Decoding Keyboard Scan Code for Make Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.5 Decoding Keyboard Scan Code for Break Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 22.1 Security Key Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 22.2 Description of Security Key Control (SKC) Register Bits[2:1] . . . . . . . . . . . . . . . . . . . . . . . . Table 23.1 AVG[2:0] BIT DECODER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 23.2 ADC Conversion Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 23.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 23.4 PWM Ramp Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 23.5 Minimum RPM Detectable Using 3 Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 23.6 Minimum RPM Detectable Using 2 Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.2 Voltage vs. Register Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.3 Temperature vs. Register Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.4 PWM Duty vs Register Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.5 Voltage Limits vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.6 Temperature Limits vs. Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.7 Fan Zone Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.8 Fan Spin-Up Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.9 PWM Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.10Register Setting vs. Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.11PWM output below Limit depending on value of Off/Min . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.12PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.13PWM Duty vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.14Temperature Limit vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.15Absolute Limit vs. Register Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.16Hysteresis Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.17AVG[2:0] BIT DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24.18Programming Options for the PWMx_n[1:0] Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.1 SYSOPT Strap Option Configuration Address Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.2 SCH311X Logical Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.3 Configuration Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.4 Chip-Level (Global) Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.5 Test Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev 0.2 (09-28-04) 120 121 123 130 130 132 133 139 142 148 149 153 153 163 163 165 167 167 167 169 171 173 178 180 185 186 190 190 197 206 221 222 225 231 232 234 240 241 243 244 245 245 246 247 248 248 249 250 252 268 269 271 272 276 278 DATASHEET xiv SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 25.6 Logical Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.7 Base I/O Range for Logical Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.8 Primary Interrupt Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.9 DMA Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.10Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0X00 . . . . . . . . . . . . . Table 25.11Parallel Port, Logical Device 3 [Logical Device Number = 0x03] . . . . . . . . . . . . . . . . . . . . . Table 25.12Serial Port 1, Logical Device 4 [Logical Device Number = 0X04 . . . . . . . . . . . . . . . . . . . . . Table 25.13Serial Port 2. Logical Device 5 [Logical Device Number = 0X05]. . . . . . . . . . . . . . . . . . . . . Table 25.14KYBD. Logical Device 7 [Logical Device Number = 0X07]. . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.15Logical Device A [Logical Device Number = 0X0A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 25.16Serial Port 3, Logical Device B [Logical Device Number = 0X0B . . . . . . . . . . . . . . . . . . . . . Table 25.17Serial Port 4, Logical Device C Logical Device Number = 0X0C . . . . . . . . . . . . . . . . . . . . . Table 25.18Serial Port 5, Logical Device D [Logical Device Number = 0X0D] . . . . . . . . . . . . . . . . . . . . Table 25.19Serial Port 6, Logical Device E Logical Device Number = 0X0E . . . . . . . . . . . . . . . . . . . . . Table 26.1 SCH311X Runtime Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 26.2 Runtime Register POR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 26.3 Detailed Runtime Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 27.1 Valid Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 28.1 Buffer Operational Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 28.2 Capacitance TA = 25; fc = 1MHz; VCC = 3.3V ±10%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 29.1 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 30.1 128 Pin VTQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.1 Analog-to-Digital Voltage Conversions for Hardware Monitoring Block. . . . . . . . . . . . . . . . . Table C.1 Toggling Inputs in Descending Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table C.2 Toggling Inputs in Ascending Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 281 283 283 285 286 286 287 288 288 289 290 290 291 293 297 303 337 339 345 365 367 369 379 379 SMSC SCH311X DATASHEET xv Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Rev 0.2 (09-28-04) DATASHEET xvi SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 1 General Description The SCH3112/SCH3114/SCH3116 Product Family is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface. The SCH3112/SCH3114/SCH3116 Product Family also includes Hardware Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic. The SCH3112/SCH3114/SCH3116 Product Family's hardware monitoring capability includes temperature, voltage and fan speed monitoring. It has the ability to alert the system of out-of-limit conditions and automatically control the speeds of multiple fans. There are four analog inputs for monitoring external voltages of +5V, +2.5V, +12V and Vccp (core processor voltage), as well as internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The SCH3112/SCH3114/SCH3116 Product Family includes support for monitoring two external temperatures via thermal diode inputs and an internal sensor for measuring ambient temperature. The nHWM_INT pin is implemented to indicate outof-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the SCH3112/SCH3114/SCH3116 Product Family is accessible via the LPC bus. The same interrupt event reported on the nHWM_INT pin also creates PME wakeup events. A separate THERMTRIP output is available, which generates a pulse output on a programmed over temperature condition. This can be used to generate an reset or shutdown indicator to the system. The hardware monitoring capability also has programmable automatic FAN control. Three fan tachometer inputs and three pulse width modulator (PWM) outputs are available. The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST, a programmable Clock output, and reset generation. The reset generation includes a watchdog timer which can be used to generate a reset pulse. The width of this pulse is selectable via an external strapping option. The SCH3112/SCH3114/SCH3116 Product Family incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, multiple serial ports, one IrDA 1.0 infrared ports, and a floppy disk controller with SMSC's true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with SMSC's proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, General Purpose I/O control functions, and control of two LED's. The serial ports are fully functional NS16550 compatible UARTs that support data rates up to 1.5 Mbps. There are four, 8 pin Serial Ports and two, 4pin Serial Ports. The reduced pin serial ports have selectable input and output controls. The Serial Ports contain programmable direction control, which will automatically Drive nRTS when the Output Buffer is loaded, then Drive nRTS when the Output Buffer is Empty. The SCH3112/SCH3114/SCH3116 Product Family is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard. The SCH3112/SCH3114/SCH3116 Product Family supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH3112/SCH3114/SCH3116 Product Family may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and Three DMA channels. SMSC SCH311X DATASHEET 1 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 1.1 Device Specific Summary FUNCTION LPC Bus Interface Legacy functional Blocks (Note 1.1) Floppy on Parallel Port Option Reset Generator Serial Ports Programmable Clock Output IDE / PCI Reset Outputs Power Button / AC Fail Support GPIOs GPIO with VID Compatible Inputs Dedicated GPIOs Hardware Monitor Note 1.1 Note 1.2 SCH3112 YES YES SCH3114 YES YES SCH3116 YES YES YES YES YES YES 2 YES YES 4 YES YES 6 (Note 1.2) YES YES YES NO YES YES NO 40 6 40 6 40 6 16 YES 0 YES 0 YES Legacy Blocks include floppy disk, parallel port, watchdog timer and keyboard controller 2 of the 6 serial ports have 4 pin interfaces Rev 0.2 (09-28-04) DATASHEET 2 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 2 Pinout +12V_IN +5V_IN GP40 /DRVDEN0 VTR nMTR0 nDSKCHG nDS0 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# PCI_CLK SER_IRQ VSS VCC nIDE_RSTDRV/GP44 nPCRST1 / GP45 nPCIRST2 / GP46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 +2.5V_IN VCCP_IN REMOTE1+ REMOTE1REMOTE2+ REMOTE2HVTR HVSS FANTACH1 FANTACH2 FANTACH3 PWM1 PWM2 PWM3 nHWM_INT nTHERMTRIP VSS VTR nFPRST/GP30 PWRGD_PS PWRGD_OUT GP34 GP62* GP67* GP66* GP65* GP64* VSS nRSMRST CLKI32 GP63* GP31 HVTR 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GP12 GP13 GP60 / nLED1 / WDT GP61 / nLED2/ CLKO GP15 VTR GP42 / nIO_PME GP16 GP17 / TSTOUT GP14 GP11 GP10 SLP_SX# PB_IN# PS_ON# PB_OUT# GP57 / nDTR2 GP56/ nCTS2 GP55/nRTS2/RESGEN GP54 / nDSR2 GP53 / TXD2 (IRTX2) GP52 / RXD2 (IRRX2) GP51 / nDCD2 VSS VTR GP50 / nRI2 nDTR1 / SYSOPT1 nCTS1 nRTS1 / SYSOPT0 nDSR1 TXD1 /SIOXNOROUT RXD1 V T R V C C SCH3112 128 PIN VTQFP VBAT HVTR VTR VCC VCC V C C SMSC SCH311X nPCIRST 3/ GP47 AVSS VBAT GP27 / nIO_SMI / P17 KDAT / GP21 KCLK / GP22 MDAT / GP32 MCLK/ GP33 GP36 /nKBDRST GP37 /A20M VSS VTR nINIT / nDIR nSCLTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPRT PD3 / nRDATA PD4 / nDSKCHG PD5 PD6 / nMTR0 PD7 VSS SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN0 nSTROBE / nDS0 nRI1 nDCD1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Note: SYSOPT1 Pin 68 SYSOPT0 Pin 70 and RESGEN Pin 78 are only sampled during power on configuration Figure 2.1 SCH3112 Pin Diagram DATASHEET 3 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 2.1 SCH311X Pinout Summary Table 2.1 SCH3112 Summary - 2 Serial Ports PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME +12V_IN +5V_IN GP40 / DRVDEN0 VTR nMTR0 nDSKCHG nDS0 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# PCI_CLK SER_IRQ VSS VCC nIDE_RSTDRV / GP44 nPCIRST1 / GP45 nPCIRST2 / GP46 PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME nPCIRST3 / GP47 AVSS VBAT GP27/nIO_SMI/P1 7 KDAT/GP21 KCLK/GP22 MDAT/GP32 MCLK/GP33 GP36/nKBDRST GP37/A20M VSS VTR nINIT / nDIR nSLCTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPRT PD3 / nRDATA PD4 / nDSKCHG PD5 PD6 / nMTR0 PD7 VSS SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN0 nSTROBE / nDS0 nRI1 nDCD1 PIN # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME RXD1 TXD1/ SIO XNOR_OUT nDSR1 nRTS1/SYSOPT0 nCTS1 nDTR1/SYSOPT1 GP50 / nRI2 VTR VSS GP51 / nDCD2 GP52 / RXD2(IRRX2) GP53 / TXD2(IRTX2) GP54 / nDSR2 GP55 / nRTS2 / RESGEN GP56 / nCTS2 GP 57 / nDTR2 PB_OUT# PS_ON# PB_IN# SLP_SX# GP10 GP11 GP14 GP17 GP16 GP42/nIO_PME_ VTR GP15 GP61/nLED2/CLK O GP60/nLED1/WD T GP13 GP12 PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME GP31 GP63* CLKI32 nRSMRST VSS GP64* GP65* GP66* GP67* GP62* GP34 PWRGD_OUT PWRGD_PS nFPRST / GP30 VTR VSS nTHERMTRIP nHWM_INT PWM3 PWM2 PWM1 FANTACH3 FANTACH2 FANTACH1 HVSS HVTR REMOTE2REMOTE2+ REMOTE1REMOTE1+ VCCP_IN +2.5V_IN Rev 0.2 (09-28-04) DATASHEET 4 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet +12V_IN +5V_IN GP40 /DRVDEN0 VTR nMTR0 nDSKCHG nDS0 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# PCI_CLK SER_IRQ VSS VCC nIDE_RSTDRV/GP44 nPCRST1 / GP45 nPCIRST2 / GP46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 +2.5V_IN VCCP_IN REMOTE1+ REMOTE1REMOTE2+ REMOTE2HVTR HVSS FANTACH1 FANTACH2 FANTACH3 PWM1 PWM2 PWM3 nHWM_INT nTHERMTRIP VSS VTR nFPRST/GP30 PWRGD_PS PWRGD_OUT GP34 / nDTR4 GP62* / nCTS4 GP67* / nRTS4 GP66* / nDSR4 GP65* / TXD4 GP64* / RXD4 VSS nRSMRST CLKI32 GP63* / nDCD4 GP31 / nRI4 HVTR 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GP12 / nDCD3 GP13 / nRI3 GP60 / nLED1 / WDT GP61 / nLED2/ CLKO GP15 / nDTR3 VTR GP42 / nIO_PME GP16 / nCTS3 GP17 / nRTS3/TSTOUT GP14 / nDSR3 GP11 / TXD3 GP10 / RXD3 SLP_SX# PB_IN# PS_ON# PB_OUT# GP57 / nDTR2 GP56/ nCTS2 GP55/nRTS2/RESGEN GP54 / nDSR2 GP53 / TXD2 (IRTX2) GP52 / RXD2 (IRRX2) GP51 / nDCD2 VSS VTR GP50 / nRI2 nDTR1 / SYSOPT1 nCTS1 nRTS1 / SYSOPT0 nDSR1 TXD1 /SIOXNOROUT RXD1 V T R V C C SCH3114 128 PIN VTQFP VBAT HVTR VTR VCC VCC V C C SMSC SCH311X nPCIRST 3/ GP47 AVSS VBAT GP27 / nIO_SMI / P17 KDAT / GP21 KCLK / GP22 MDAT / GP32 MCLK/ GP33 GP36 /nKBDRST GP37 /A20M VSS VTR nINIT / nDIR nSCLTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPRT PD3 / nRDATA PD4 / nDSKCHG PD5 PD6 / nMTR0 PD7 VSS SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN0 nSTROBE / nDS0 nRI1 nDCD1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Note: SYSOPT1 Pin 68 SYSOPT0 Pin 70 and RESGEN Pin 78 are only sampled during power on cinfiguration Figure 2.2 SCH3114 Pin Diagram DATASHEET 5 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.2 SCH3114 Summary - 4 Serial Ports PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME +12V_IN +5V_IN GP40/DRVDEN 0 VTR nMTR0 nDSKCHG nDS0 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# PCI_CLK SER_IRQ VSS VCC nIDE_RSTDRV / GP44 nPCIRST1 / GP45 nPCIRST2 / GP46 PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME nPCIRST3 / GP47 AVSS VBAT GP27/nIO_SMI/P1 7 KDAT/GP21 KCLK/GP22 MDAT/GP32 MCLK/GP33 GP36/nKBDRST GP37/A20M VSS VTR nINIT / nDIR nSLCTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPRT PD3 / nRDATA PD4 / nDSKCHG PD5 PD6 / nMTR0 PD7 VSS SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN0 nSTROBE / nDS0 nRI1 nDCD1 PIN # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME RXD1 TXD1/ SIO XNOR_OUT nDSR1 nRTS1/SYSOPT0 nCTS1 nDTR1/SYSOPT1 GP50 / nRI2 VTR VSS GP51 / nDCD2 GP52 / RXD2(IRRX2) GP53 / TXD2(IRTX2) GP54 / nDSR2 GP55 / nRTS2 / RESGEN GP56 / nCTS2 GP 57 / nDTR2 PB_OUT# PS_ON# PB_IN# SLP_SX# GP10/RXD3 GP11 / TXD3 GP14 / nDSR3 GP17 / nRTS3 GP16 / nCTS3 GP42/nIO_PME_ VTR GP15 / nDTR3 GP61/nLED2/CLK O GP60/nLED1/WD T GP13 / nRI3 GP12 / nDCD3 PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME GP31 / nRI4 GP63* / nDCD4 CLKI32 nRSMRST VSS GP64* / RXD4 GP65* / TXD4 GP66* / nDSR4 GP67* / nRTS4 GP62* / nCTS4 GP34 / nDTR4 PWRGD_OUT PWRGD_PS nFPRST / GP30 VTR VSS nTHERMTRIP nHWM_INT PWM3 PWM2 PWM1 FANTACH3 FANTACH2 FANTACH1 HVSS HVTR REMOTE2REMOTE2+ REMOTE1REMOTE1+ VCCP_IN +2.5V_IN Rev 0.2 (09-28-04) DATASHEET 6 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet SMSC SCH311X GP47/nSCOUT6 - nPCIRST 3/ GP47 33 AVSS 34 VBAT 35 GP47/nSCOUT6 33 36 GP27 / nIO_SMI / P1734 AVSS KDATVBAT 35 / GP21 37 KCLK / GP22 38 GP27 / nIO_SMI / P17 36 MDAT / GP32 39 KDAT / GP21 37 KCLK / GP22 38 MCLK/ GP33 40 MDAT / GP32 41 GP36 /nKBDRST39 MCLK/ GP33 40 GP37 /A20M 42 GP36 /nKBDRST 41 VSS 43 GP37 /A20M 42 VTR 44 VSS 43 nINIT /VTR 44 nDIR 45 nSCLTIN // nSTEP45 nINIT nDIR 46 PD0 nINDEX 47 nSCLTIN / /nSTEP 46 PD1 / nTRK0 48 PD0 / nINDEX 47 PD1 / nTRK0 49 PD2 / nWRTPRT48 PD2 / nWRTPRT 49 PD3 / nRDATA 50 PD3 / nRDATA 51 PD4 / nDSKCHG50 PD4 / nDSKCHG 51 PD5 52 PD5 52 PD6 / nMTR0 53 PD6 / nMTR0 53 PD7 54 PD7 54 VSS 55 VSS 55 SLCT / nWGATE 56 SLCT / nWGATE 56 PE / nWDATA 57 PE / nWDATA 57 BUSY / nMTR1 58 BUSY / nMTR1 58 nACK / nDS1 59 nACK / nDS1 59 nERROR / nHDSEL 60 nERROR / nHDSEL 60 nALF / DRVDEN0 61 nALF / DRVDEN0 61 nSTROBE / nDS0 62 nSTROBE / nDS0 62 nRI1 63 nRI1 63 nDCD1 64 nDCD1 64 HVTR +12V_IN 1 HVTR +5V_IN 2 1 3 GP40 /DRVDEN0+12V_IN 2 4 VTR +5V_IN GP40 /DRVDEN0 3 5 nMTR0 4 nDSKCHG 6 VTR 5 7 nDS0 nMTR0 nDSKCHG 6 VSS 8 nDS0 7 nDIR 9 VSS 8 nSTEP 10 nDIR 9 nWDATA 11 10 12 nWGATE nSTEP nWDATA 11 nHDSEL 13 nWGATE 12 nINDEX 14 13 15 nTRK0nHDSEL nINDEX 14 16 nWRTPRT 17 V 15 nRDATA nTRK0 nWRTPRT 16 V CLOCKI 18 C nRDATA 17 C LAD0 19 20 C 18 C LAD1CLOCKI LAD0 19 LAD2 21 LAD1 20 LAD3 22 LAD2 21 LFRAME# 23 LAD3 22 LDRQ# 24 LFRAME# 23 PCI_RESET# 25 24 26 PCI_CLK LDRQ# PCI_RESET# 25 27 SER_IRQ PCI_CLK 26 VSS 28 SER_IRQ 27 VCC 29 VSS 28 GP44 / TXD6 30 VCC 29 E_RSTDRV/GP44 GP44 TXD6 30 GP45 / RXD6 /31 31 GP45 nPCRST1 / GP45 / RXD6 32 GP46 / 32 GP46 / nSCIN6 nSCIN6 nPCIRST2 / GP46 128 +2.5V_IN 127 VCCP_IN 126 REMOTE1+ 128 +2.5V_IN 125 REMOTE1127 VCCP_IN 124 REMOTE2+ 126 REMOTE1+ 123 REMOTE2125 REMOTE1122 HVTR 124 REMOTE2+ 123 REMOTE2121 HVSS 122 HVTR 120 FANTACH1 121 HVSS 119 FANTACH2 120 FANTACH1 118 FANTACH3 119 FANTACH2 117 PWM1 118 FANTACH3 116 PWM2 117 PWM1 115 PWM3 116 PWM2 114 nHWM_INT 115 PWM3 113 nTHERMTRIP 114 nHWM_INT 113 nTHERMTRIP 112 VSS 112 VSS 111 VTR 111 VTR 110 nFPRST/GP30 110 nFPRST/GP30 109 PWRGD_PS 109 PWRGD_PS 108 PWRGD_OUT 108 PWRGD_OUT 107 GP34 / nDTR4 107 GP34 / nDTR4 106 GP62* / nCTS4 106 GP62* / nCTS4 105 GP67* / nRTS4 105 GP67* / nRTS4 / 104 GP66* / nDSR4 104 GP66* / nDSR4 103 GP65* / TXD4 103 GP65* / TXD4 102 GP64* / RXD4 102 GP64* / RXD4 101 VSS 101 VSS 100 nRSMRST 100 nRSMRST 99 CLKI32 99 CLKI32 98 GP63* / nDCD4 98 GP63* / nDCD4 97 GP31 / nRI4 97 GP31 / nRI4 SCH3116 SCH3116 Preliminary 128 PIN VTQFP 128 PIN VTQFP VBAT VBAT HVTR HVTR VTR VTR VCC VCC VCC VCC 96 GP12 / nDCD3 96 GP12 / nDCD3 95 GP13 / nRI3 95 GP13 / nRI3 94 GP60 / nLED1 / WDT 94 GP60 / nLED1 / WDT 93 GP61 / nLED2/ CLKO 93 GP61 / nLED2/ CLKO 92 GP15 / nDTR3 92 GP15 / nDTR3 V VTR V 9191 VTR / nIO_PME GP42 T 9090 GP42 / nIO_PME T 89 GP16 / nCTS3 R 89 GP16 / nCTS3 GP17 / nRTS3/TSTOU R 8888 GP17 / nRTS3/TSTOUT T 87 GP14 / nDSR3 87 GP14 / nDSR3 86 GP11 / TXD3 86 GP11 / TXD3 85 GP10 / RXD3 85 GP10 / RXD3 / nSCIN5 84 SLP_SX# 84 nSCIN5 83 PB_IN# / nSCOUT5 83 nSCOUT5 / TXD5 82 PS_ON# 82 TXD5 81 PB_OUT# / RXD5 81 RXD5 / nDTR2 80 GP57 80 GP57 / nDTR2 79 GP56/ nCTS2 79 GP56/ nCTS2 78 GP55/nRTS2/RESGE N 78 GP55/nRTS2/RESGEN 77 GP54 / nDSR2 77 GP54 / nDSR2 (IRTX2) 76 GP53 / TXD2 TXD2 GP52 / RXD2 (IRRX2) V 7675 GP53 // RXD2 (IRTX2) (IRRX2) V 7574 GP52 / nDCD2 GP51 C 7473 GP51 / nDCD2 VSS C 73 VSS C 72 VTR C 7271 VTR / nRI2 GP50 71 GP50 / nRI2SYSOPT1 70 nDTR1 / 70 nDTR1 / SYSOPT1 69 nCTS1 69 nCTS1 68 nRTS1 / SYSOPT0 68 nRTS1 / SYSOPT0 67 nDSR1 67 nDSR1 /SIOXNOROUT 66 TXD1 66 TXD1 /SIOXNOROUT 65 RXD1 65 RXD1 Note: Note: SYSOPT1 Pin 68 SYSOPT1 Pin 68 SYSOPT0 Pin 70 and SYSOPT0 Pin 70 and RESGEN Pin 78 are only sampled during power on cinfiguration RESGEN Pin 78 are only sampled during power on configuration Figure 2.3 SCH116 Pin Diagram DATASHEET 7 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Figure 2.4 SCH3116 Summary - 6 Ports PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME +12V_IN +5V_IN GP40/DRVDEN 0 VTR nMTR0 nDSKCHG nDS0 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# PCI_CLK SER_IRQ VSS VCC GP44 / TXD6 GP45 / RXD6 GP46 / nSCIN6 PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME GP47 / nSCOUT6 AVSS VBAT GP27/nIO_SMI/P1 7 KDAT/GP21 KCLK/GP22 MDAT/GP32 MCLK/GP33 GP36/nKBDRST GP37/A20M VSS VTR nINIT / nDIR nSLCTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPRT PD3 / nRDATA PD4 / nDSKCHG PD5 PD6 / nMTR0 PD7 VSS SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN0 nSTROBE / nDS0 nRI1 nDCD1 PIN # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME RXD1 TXD1/ SIO XNOR_OUT nDSR1 nRTS1/SYSOPT0 nCTS1 nDTR1/SYSOPT1 GP50 / nRI2 VTR VSS GP51 / nDCD2 GP52 / RXD2(IRRX2) GP53 / TXD2(IRTX2) GP54 / nDSR2 GP55 / nRTS2 / RESGEN GP56 / nCTS2 GP 57 / nDTR2 RXD5 TXD5 nSCOUT5 nSCIN5 GP10/RXD3 GP11 / TXD3 GP14 / nDSR3 GP17 / nRTS3 GP16 / nCTS3 GP42/nIO_PME_ VTR GP15 / nDTR3 GP61/nLED2/CLK O GP60/nLED1/WD T GP13 / nRI3 GP12 / nDCD3 PIN # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME GP31 / nRI4 GP63* / nDCD4 CLKI32 nRSMRST VSS GP64* / RXD4 GP65* / TXD4 GP66* / nDSR4 GP67* / nRTS4 GP62* / nCTS4 GP34 / nDTR4 PWRGD_OUT PWRGD_PS nFPRST / GP30 VTR VSS nTHERMTRIP nHWM_INT PWM3 PWM2 PWM1 FANTACH3 FANTACH2 FANTACH1 HVSS HVTR REMOTE2REMOTE2+ REMOTE1REMOTE1+ VCCP_IN +2.5V_IN Table 2.3 SCH311X Signal Difference Summary PIN # 30 31 Rev 0.2 (09-28-04) SCH3112 nIDE_RSTDRV / GP44 nPCIRST1 / GP45 SCH3114 nIDE_RSTDRV / GP44 nPCIRST1 / GP45 8 SCH3116 GP44 / TXD6 GP45 / RXD6 SMSC SCH311X DATASHEET LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.3 SCH311X Signal Difference Summary (continued) PIN # 32 33 81 82 83 84 85 86 87 88 89 92 95 96 97 98 102 103 104 105 106 107 SCH3112 nPCIRST2 / GP46 nPCIRST3 / GP47 PB_OUT# PS_ON# PB_IN# SLP_SX# GP10 GP11 GP14 GP17 GP16 GP15 GP13 GP12 GP31 GP63* GP64* GP65* GP66* GP67* GP62* GP34 SCH3114 nPCIRST2 / GP46 nPCIRST3 / GP47 PB_OUT# PS_ON# PB_IN# SLP_SX# GP10/RXD3 GP11/TXD3 GP14/nDSR3 GP17/nRTS3 GP16/nCTS3 GP15/nDTR3 GP13/nRI3 GP12/nDCD3 GP31 / nRI4 GP63* / nDCD4 GP64* / RXD4 GP65* / TXD4 GP66* /nDSR4 GP67* / nRTS4 GP62* /nCTS4 GP34 / nDTR4 SCH3116 GP46 / nSCIN6 GP47 / nSCOUT6 RXD5 TXD5 nSCOUT5 nSCIN5 GP10/RXD3 GP11/TXD3 GP14/nDSR3 GP17/nRTS3 GP16/nCTS3 GP15/nDTR3 GP13/nRI3 GP12/nDCD3 GP31 / nRI4 GP63* / nDCD4 GP64* / RXD4 GP65* / TXD4 GP66* /nDSR4 GP67* / nRTS4 GP62* /nCTS4 GP34 / nDTR4 2.2 Pin Functions The SCH311X family of devices have the same basic pinout for legacy functions, as shown in Table 2.5. The pin descriptions for the SCH3112 is shown in Table 2.6. Signals specific to the SCH3114 are shown in Table 2.7. Signals specific to the SCH3116 are shown in Table 2.8. Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) POWER PINS (16) 29 2.3, 2.4 VCC +3.3 Volt Supply Voltage SMSC SCH311X DATASHEET 9 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) (continued) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) 4,44 ,72, 91, 111 35 8,28 ,43, 55, 73, 101, 112 34 122 2.3, 2.4 VTR +3.3 Volt Standby Supply Voltage 2.8 VBAT VSS +3.0 Volt Battery Supply) Ground AVSS 2.3 HVTR Analog Ground Analog Power. +3.3V VTR pin dedicated to the Hardware Monitoring block. HVTR is powered by +3.3V Standby power VTR. Analog Ground. Internally connected to all of the Hardware Monitoring Block circuitry. CLOCK PINS (2) 123 2.3 HVSS 99 18 CLKI32 CLOCKI 32.768kHz Trickle Clock Input 14.318MHz Clock Input CLOCKI CLKI32 No Gate IS IS LPC INTERFACE (9) 1922 23 LAD[3:0] LFRAME # Multiplexed Command Address and Data Frame signal. Indicates start of new cycle and termination of broken cycle Encoded DMA Request PCI Reset PCI Clock Serial IRQ LAD[3:0] LFRAME# GATE/ Hi-Z GATE PCI_IO PCI_I 24 25 26 27 LDRQ# PCI_RES ET# PCI_CLK SER_IRQ LDRQ# PCI_RES ET# PCI_CLK SER_IRQ GATE/Hi-Z NO GATE GATE GATE / Hi-Z PCI_O PCI_I PCI_ICLK PCI_IO FDD INTERFACE (13) 3 2.9 GP40/ DRVDEN 0 General Purpose I/O /Drive Density Select 0 GP40/ DRVDEN0 GP40 GP40 NO GATE / HIZ (I/O12/OD1 2)/ (O12/OD12 ) SMSC SCH311X Rev 0.2 (09-28-04) DATASHEET 10 LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) (continued) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) Hi-Z GATE HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z GATE GATE GATE GATE 5 6 7 9 10 11 12 13 14 15 16 17 nMTR0 nDSKCH G nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPR T nRDATA Motor On 0 Disk Change Drive Select 0 Step Direction Step Pulse Write Disk Data Write Gate Head Select Index Pulse Input Track 0 Write Protected Read Disk Data nMTR0 nDSKCH G nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPR T nRDATA (O12/OD12 ) IS (O12/OD12 ) (O12/OD12 ) (O12/OD12 ) (O12/OD12 ) (O12/OD12 ) (O12/OD12 ) IS IS IS IS SERIAL PORT 1 INTERFACE (8) 65 66 RXD1 TXD1 /SIO XNOR_O UT nDSR1 2.7 nRTS1/ SYSOPT 0 nCTS1 nDTR1 / SYSOPT 1 2.9 nRI1 nDCD1 Receive Data 1 Transmit Data 1 / XNOR-Chain test mode Output for SIO block Data Set Ready 1 Request to Send 1/ SYSOPT (Configuration Port Base Address Control) Clear to Send 1 Data Terminal Ready 1 RXD1 TXD1 /SIO XNOR_O UT nDSR1 nRTS1/ SYSOPT0 GATE HI-Z IS O12/O12 67 68 GATE GATE/ Hi-Z I OP14/I 69 70 nCTS1 nDTR1 / SYSOPT1 nRI1 nDCD1 GATE GATE/ Hi-Z I O6 63 64 Ring Indicator 1 Data Carrier Detect 1 GATE GATE IS I SERIAL PORT 2 INTERFACE (8) SMSC SCH311X DATASHEET 11 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) (continued) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) NO GATE/ HI-Z NO GATE/ HI-Z NO GATE/ HI-Z NO GATE/ HI-Z NO GATE/ HI-Z NO GATE/ HI-Z NO GATE/ HI-Z NO GATE/ HI-Z 71 74 75 2.9 2.9 2.9 GP50 / nRI2 GP51 / nDCD2 GP52 / RXD2 (IRRX) GP53 / TXD2 (IRTX) GP54 / nDSR2 GP55 / nRTS2 / RESGEN GP56 / nCTS2 GP57 / nDTR2 Ring Indicator 2 Data Carrier Detect 2 Receive Data 2 (IRRX) GP50 GP51 / nDCD2 GP52 / RXD2 (IRRX) GP53 / TXD2 (IRTX) GP54 / nDSR2 GP55 / nRTS2 / RESGEN GP56 / nCTS2 GP57 / nDTR2 nRI2 I/ IOD8 I IS 76 2.11, 2.9 2.9 2.9 Transmit Data 2 (IRTX) O12 77 78 Data Set Ready 2 Request to Send 2 / Reset Generator Pulse Width Strap Option Clear to Send 2 Data Terminal Ready 2 I OP14 / I I O6 79 80 2.9 2.9 SHARED PARALLEL PORT / FDC INTRERFACE (17) 45 46 2.12 2.12 nINIT / nDIR nSLCTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPR T PD3 / nRDATA PD4 / nDSKCH G PD5 PD6 / nMTR0 PD7 Initiate Output Printer Select Input nINIT / nDIR nSLCTIN / nSTEP PD0 / nINDEX PD1 / nTRK0 PD2 / nWRTPR T PD3 / nRDATA PD4 / nDSKCH G PD5 PD6 / nMTR0 PD7 GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z (OD14/OP1 4) (OD14/OP1 4) IOP14 IOP14 IOP14 47 48 49 2.12 2.12 2.12 Port Data 0 Port Data 1 Port Data 2 50 51 2.12 2.12 Port Data 3 Port Data 4 IOP14 IOP14 52 53 54 2.12 2.12 2.12 Port Data 5 Port Data 6 Port Data 7 IOP14 IOP14 IOP14 Rev 0.2 (09-28-04) DATASHEET 12 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) (continued) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z GATE / HI-Z 56 57 58 59 60 2.12 2.12 2.12 2.12 2.12 SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN 0 nSTROB E/ nDS0 Printer Selected Status Paper End Busy Acknowledge Error SLCT / nWGATE PE / nWDATA BUSY / nMTR1 nACK / nDS1 nERROR / nHDSEL nALF / DRVDEN0 nSTROBE / nDS0 I I I I I 61 2.12 Autofeed Output (OD14/OP1 4) (OD14/OP1 4) 62 2.12 Strobe Output KEYBOARD/MOUSE INTERFACE (6) 37 2.9 KDAT/GP 21 KCLK/GP 22 MDAT/GP 32 MCLK/GP 33 GP36/ nKBDRS T Keyboard Data I/O General Purpose I/O Keyboard Clock I/O General Purpose I/O Mouse Data I/O /General Purpose I/O Mouse Clock I/O /General Purpose I/O General Purpose I/O. GPIO can be configured as an Open-Drain Output. Keyboard Reset OpenDrain Output (Note 10) General Purpose I/O. GPIO can be configured as an Open-Drain Output. Gate A20 Open-Drain Output (Note 10) KDAT/GP 21 KCLK/GP 22 MDAT/GP 32 MCLK/GP 33 GP36/ nKBDRST NO GATE / HI-Z NO GATE / HI-Z NO GATE / HI-Z NO GATE / HI-Z NO GATE / HI-Z (I/OD16)/ (I/O16/OD1 6) I/OD16)/ (I/O16/OD1 6) (I/OD16) /(I/O16/OD1 6) (I/O16/OD1 6) /(I/OD16) (I/O8/OD8) /OD8 38 2.9 39 2.9 40 2.9 41 2.6 42 2.6 GP37/ A20M GP37/ A20M NO GATE / HI-Z (I/O8/OD8) /OD8 MISCELLANEOUS PINS (5) SMSC SCH311X DATASHEET 13 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) (continued) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) NO GATE 90 GP42/ nIO_PME General Purpose I/O. Power Management Event Output. This active low Power Management Event signal allows this device to request wake-up in either S3 or S5 and below. General Purpose I/O /nLED1 Watchdog Timer Output GP42/ nIO_PME (I/O12/OD1 2) /(O12/OD12 ) 94 2.8, 2.9 GP60 /nLED1 /WDT GP60 /nLED1 /WDT NO GATE (I/O12/OD1 2) /(O12/OD12 ) /(O12/OD12 ) ISPU_400 / 110 nFPRST / GP30 PWRGD_ PS PWRGD_ OUT nRSMRS T 2.8, 2.9 GP61 /nLED2 / CLKO GP27 /nIO_SMI /P17 Front Panel Reset / General Purpose IO Power Good Input from Power Supply Power Good Output – Open Drain Resume Reset Output General Purpose I/O /nLED2 / Programmable Clock Output General Purpose I/O /System Mgt. Interrupt /8042 P17 I/O GP27 /nIO_SMI /P17 nFPRST / GP30 PWRGD _PS PWRGD _OUT nRSMRS T GP61 /nLED2 / CLKO GP27 NO GATE 109 108 100 93 NO GATE NO GATE NO GATE NO GATE ISPU_400 OD8 O8 (I/O12/OD1 2) /(O12/OD12 ) (I/O12/OD1 2) /(O12/OD12 ) /(I/O12/OD1 2) 36 2.9 / HI-Z HARDWARE MONITORING BLOCK (23) 114 nHWM_I NT 2.10 2.10 2.10 +5V_IN +2.5_IN VCCP_IN Interrupt output for Hardware monitor Analog input for +5V Analog input for +2.5V Analog input for +Vccp (processor voltage: 1.5 V nominal). Analog input for +12V This is the negative Analog input (current sink) from the remote thermal diode 1. HVTR HVTR HVTR nHWM_I NT OD8 2 128 127 IAN IAN IAN 1 125 2.10 +12V_IN REMOTE 1- HVTR HVTR IAN IAND- Rev 0.2 (09-28-04) DATASHEET 14 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.4 SCH311X Pin Core Functions Description (Note 2.14) (continued) VCC POWER PLANE VTRPOWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) PIN NOTE NAME DESCRIPTION (Note 2.16) 126 REMOTE 1+ REMOTE 2- This is the positive input (current source) from the remote thermal diode 1. This is the negative Analog input (current sink) from the remote thermal diode 2. This is the positive input (current source) from the remote thermal diode 2. Fan Speed Control 1 Output. Fan Speed Control 2 Output Fan Speed Control 3Output Thermtrip output Tachometer Input 1 for monitoring a fan. Tachometer Input 2 for monitoring a fan. Tachometer Input 4 for monitoring a fan. HVTR IAND+ 123 HVTR IAND- 124 REMOTE 2+ PWM1 PWM2 PWM3 nTHERM TRIP FANTAC H1 FANTAC H2 FANTAC H3 HVTR IAND+ 117 118 119 113 120 121 122 PWM1 PWM2 PWM3 nTHERM TRIP FANTAC H1 FANTAC H2 FANTAC H3 OD8 OD8 OD8 OD_PH IM IM IM Table 2.5 SCH3112 Specific Signals (Note 2.15) PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTR POWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) (Note 2.16) RESET OUTPUTS 33 2.13 nPCIRST3 / GP47 PCI Reset output 3 GPIO with schmidt trigger input PCI Reset output 2 GPIO with schmidt trigger input PCI Reset output1 GPIO with schmidt trigger input IDE Reset output GPIO with schmidt trigger input GLUE LOGIC GP47 / nPCIRST 3 nPCIRST 2 GP45 / nPCIRST 1 GP44 / nIDE_RS TDRV NO GATE (IO8/IOD8) NO GATE (IO8/IOD8) 32 2.13 nPCIRST2 / GP46 nPCIRST1 / GP45 nIDE_RST DRV / GP44 31 2.13 NO GATE (IO8/IOD8) 30 2.13 NO GATE (IO8/IOD8) SMSC SCH311X DATASHEET 15 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.5 SCH3112 Specific Signals (Note 2.15) (continued) PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTR POWER PLANE VCC=0 OPERATION BUFFER MODES (Note 2.1) (Note 2.16) 83 PB_IN# / Power Button In is used to detect a power button event / Sx Sleep State Input Pin. / Power Button Out/ Power supply On/ GPIO PB_IN# I/ (O8/OD8) NO GATE I/ I (O8/OD8) IS OD8 / (O12) 84 2.9 SLP_SX# SLP_SX# 81 82 PB_OUT# PS_ON# PB_OUT # PS_ON# NO GATE NO GATE 95 96 85 86 87 88 89 92 97 98 102 103 104 105 106 107 2.9 2.9 2.9 2.11, 2.9 2.9 2.9 2.9 2.9 2.9 2.9 2.9 2.11, 2.9 2.9 2.9 2.9 2.9 GP13 GP12 GP10 GP11 GP14 GP17 // GP16 GP15 GP31 GP63* GP64* GP65* GP66* GP67* GP62* GP34 GPIO GPIO GPIO GPIO GPIO GPIO / GPIO GPIO GPIO GPIO with I_VID buffer Input GPIO with I_VID buffer Input GPIO with I_VID buffer Input GPIO with I_VID buffer Input GPIO with I_VID buffer Input GPIO with I_VID buffer Input GPIO GP17 GP16 GP15 GP10 GP13 GP12 NO GATE NO GATE HI-Z I/ IO8 I IS O12 I OP14 / I I O6 GP11 GP14 NO GATE NO GATE GP31 GP63* GP64* GP65* GP66* GP67* GP62* GP34 NO GATE NO GATE NO GATE NO GATE NO GATE NO GATE NO GATE NO GATE I I IS O12 I OP14 / I I O6 Rev 0.2 (09-28-04) DATASHEET 16 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.6 SCH3114 Specific Signals (Note 2.15) VCC=0 OPERATION PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTRPOWER PLANE (Note 2.1 6) NO GATE BUFFER MODES (Note 2.1) 33 2.13 nPCIRST3 / GP47 PCI Reset output 3 GPIO with schmidt trigger input PCI Reset output 2 GPIO with schmidt trigger input PCI Reset output1 GPIO with schmidt trigger input IDE Reset output GPIO with schmidt trigger input GLUE LOGIC GP47 / nPCIRST 3 nPCIRST 2 GP45 / nPCIRST 1 GP44 / nIDE_RS TDRV (IO8/IOD8) 32 2.13 nPCIRST2 / GP46 nPCIRST1 / GP45 nIDE_RST DRV / GP44 NO GATE NO GATE NO GATE (IO8/IOD8) 31 2.13 (IO8/IOD8) 30 2.13 (IO8/IOD8) 83 PB_IN# / Power Button In is used to detect a power button event / Sx Sleep State Input Pin. / Power Button Out/ Power supply On/ SERIAL PORT 3 INTERFACE (8) PB_IN# NO GATE I/ (O8/OD8) 84 2.9 SLP_SX# SLP_SX# NO GATE NO GATE NO GATE I/ I (O8/OD8) IS OD8 / (O12) 81 82 PB_OUT# PS_ON# PB_OUT # PS_ON# 95 96 85 86 87 88 2.9 2.9 2.9 2.11, 2.9 2.9 2.9 GP13 / nRI3 GP12 / nDCD3 GP10 / RXD3 GP11 / TXD3 GP14 / nDSR3 GP17 / nRTS3/ GP16 / nCTS3 GP15 / nDTR3 GPIO / Ring Indicator 3 GPIO / Data Carrier Detect 3 GPIO / Receive Data 3 GPIO / Transmit Data 3 GPIO / Data Set Ready 3 GPIO / Request to Send 3 GPIO / Clear to Send 3 GPIO / Data Terminal Ready 3 nDCD3 GP10 / RXD3 TXD3 nDSR3 GP17 / nRTS3/ GP16 / nCTS3 GP15 / nDTR3 GP13 / nRI3 GP12 NO GATE NO GATE / HI-Z I/ IO8 I IS O12 I OP14 / I I O6 GP11 GP14 / HI-Z NO GATE / HI-Z / HI-Z / HI-Z 89 92 2.9 2.9 SERIAL PORT 4 INTERFACE (8) SMSC SCH311X 17 Rev 0.2 (09-28-04) DATASHEET LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.6 SCH3114 Specific Signals (Note 2.15) (continued) VCC=0 OPERATION PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTRPOWER PLANE (Note 2.1 6) NO GATE NO GATE NO GATE / HI-Z NO GATE / HI-Z NO GATE / HI-Z I I BUFFER MODES (Note 2.1) 97 98 2.9 2.9 GP31 / nRI4 GP63* / nDCD4 GP64* / RXD4 GP65* / TXD4 GP66* / nDSR4 GP67* / nRTS4 GP62* / nCTS4 GP34 / nDTR4 GPIO / Ring Indicator 4 GPIO with I_VID buffer Input / Data Carrier Detect 4 GPIO with I_VID buffer Input / Receive Data 4 GPIO with I_VID buffer Input / Transmit Data 4 GPIO with I_VID buffer Input / Data Set Ready 4 GPIO with I_VID buffer Input / Request to Send 4 GPIO with I_VID buffer Input / Clear to Send 4 GPIO / Data Terminal Ready 4 nDCD4 GP31 / nRI4 GP63* 102 2.9 RXD4 GP64* IS 103 2.11, 2.9 2.9 TXD4 GP65* O12 104 nDSR4 GP66* I 105 2.9 nRTS4 GP67* OP14 / I I 106 2.9 nCTS4 GP62* 107 2.9 nDTR4 GP34 O6 Table 2.7 SCH3116 Specific Signals (Note 2.15) VCC=0 OPERATION PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTRPOWER PLANE (Note 2.1 6) BUFFER MODES (Note 2.1) SERIAL PORT 6 I/F 33 2.13 GP47 / nSCOUT6 GPIO with schmidt trigger input Serial Port 6 output control GPIO with schmidt trigger input Serial Port 6 input Control GPIO with schmidt trigger input Receive serial port 6 GPIO with schmidt trigger input Serial Port 6 Transmit RXD6 GP46 / nSCIN6 NO GATE (IO8/IOD8) nSCOUT6 GP47 / HI-Z (IO8/IOD8) 32 2.13 GP46 / nSCIN6 31 2.13 GP45 / RXD6 GP44 / TXD6 GATE PG (IO8/IOD8) 30 2.13 TXD6 GP44 NO GATE/ Hi-Z (IO8/IOD8) SERIAL PORT 5 I/F Rev 0.2 (09-28-04) DATASHEET 18 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.7 SCH3116 Specific Signals (Note 2.15) (continued) VCC=0 OPERATION PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTRPOWER PLANE (Note 2.1 6) / HI-Z BUFFER MODES (Note 2.1) 83 84 81 82 2.9 nSCOUT5 nSCIN5 RXD5 TXD5 Serial Port 5 out control Serial Port 5 input Control Receive 5 Serial Port 5 Transmit nSCOUT5 nSCIN5 RXD5 TXD5 I/ (O8/OD8) I/ I (O8/OD8) IS OD8 / (O12) NO GATE GATE NO GATE / HI-Z SERIAL PORT 3 INTERFACE (8) 95 96 85 86 87 88 2.9 2.9 2.9 2.11, 2.9 2.9 2.9 GP13 / nRI3 GP12 / nDCD3 GP10 / RXD3 GP11 / TXD3 GP14 / nDSR3 GP17 / nRTS3/ GP16 / nCTS3 GP15 / nDTR3 GPIO / Ring Indicator 3 GPIO / Data Carrier Detect 3 GPIO / Receive Data 3 GPIO / Transmit Data 3 GPIO / Data Set Ready 3 GPIO / Request to Send 3 GPIO / Clear to Send 3 GPIO / Data Terminal Ready 3 nDCD3 GP10 / RXD3 TXD3 nDSR3 GP17 / nRTS3/ GP16 / nCTS3 GP15 / nDTR3 GP11 GP14 GP13 / nRI3 GP12 NO GATE NO GATE / HI-Z / HI-Z NO GATE / HI-Z / HI-Z / HI-Z I/ IO8 I IS O12 I OP14 / I I O6 89 92 2.9 2.9 SERIAL PORT 4 INTERFACE (8) 97 98 2.9 2.9 GP31 / nRI4 GP63* / nDCD4 GP64* / RXD4 GP65* / TXD4 GP66* / nDSR4 GPIO / Ring Indicator 4 GPIO with I_VID buffer Input / Data Carrier Detect 4 GPIO with I_VID buffer Input / Receive Data 4 GPIO with I_VID buffer Input / Transmit Data 4 GPIO with I_VID buffer Input / Data Set Ready 4 nDCD4 GP31 / nRI4 GP63* NO GATE NO GATE I I 102 2.9 RXD4 GP64* NO GATE IS 103 2.11, 2.9 2.9 TXD4 GP65* / HI-Z NO GATE O12 104 nDSR4 GP66* I SMSC SCH311X DATASHEET 19 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.7 SCH3116 Specific Signals (Note 2.15) (continued) VCC=0 OPERATION PIN NOTE NAME DESCRIPTION VCC POWER PLANE VTRPOWER PLANE (Note 2.1 6) / HI-Z NO GATE BUFFER MODES (Note 2.1) 105 2.9 GP67* / nRTS4 GP62* / nCTS4 GP34 / nDTR4 GPIO with I_VID buffer Input / Request to Send 4 GPIO with I_VID buffer Input / Clear to Send 4 GPIO / Data Terminal Ready 4 nRTS4 GP67* OP14 / I I 106 2.9 nCTS4 GP62* 107 2.9 nDTR4 GP34 / HI-Z O6 Note: The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low” signal. Note 2.1 Note 2.2 Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis represent multiple buffer types for a single pin function. Pins that have input buffers must always be held to either a logical low or a logical high state when powered. Bi-directional buses that may be trisected should have either weak external pull-ups or pull-downs to hold the pins in a logic state (i.e., logic states are VCC or ground). VCC and VSS pins are for Super I/O Blocks. HVTR and HVSS are dedicated for the Hardware Monitoring Block. VTR can be connected to VCC if no wake-up functionality is required. The Over Current Sense Pin requires an external pull-up (30ua pull-up is suggested). External pull-ups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must ensure that these pins are high. The nRTS1/SYSOPT0 pin requires an external pull-down resistor to put the base I/O address for configuration at 0x02E. An external pull-up resistor is required to move the base I/O address for configuration to 0x04E. The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power. This pin is an input into the wake-up logic that is powered by VTR. In the case of a ring indicator for a serial port, or a GPIO it will also go to VCC powered logic. This logic must be disabled when VCC=0. Note 2.3 Note 2.4 Note 2.5 Note 2.6 Note 2.7 Note 2.8 Note 2.9 Note 2.10 This analog input is backdrive protected. Although HVTR is powered by VTR, it is possible that monitored power supplies may be powered when HVTR is off. Note 2.11 The GP53/TXD2(IRTX) pin defaults to the GPIO input function on a VTR POR and presents a tristate impedance. When VCC=0 the pin is tristate. If GP53 function is selected and VCC is power is applied, the pin reflects the current state of GP53. The GP53/TXD2(IRTX) pin is tristate when it is configured for the TXD2 (IRTX) function under various conditions detailed in Section 8.1.1, "IR Transmit Pin," on page 93. Note 2.12 These pins are multiplexed internally with the FDC I/F. When the FDC on PP mode is selected, the PP port alternate functions are used for the FDC I/F. Rev 0.2 (09-28-04) DATASHEET 20 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Note 2.13 The reset glue logic is only available in SCH3112, SCH3114. The serial port is only available in the SCH3116. In all the SCH311X family, GP44 -47 have schmidt trigger inputs. Note 2.14 The pins listed here are pins used in all of the SCH311X devices. Note 2.15 The pins listed here represent addition functionality to those pins listed in Table 2.5. Note 2.16 All logic is powered by VTR. Vcc on pin 29 is used as an indication of the presence of the VCC rail being active. All logic that requires VCC power only, is enabled only when the VCC rail is active. User’s Note: Open-drain pins should be pulled-up externally to supply shown in the power well column. All other pins are driven under the power well shown. ■ NOMENCLATURE: No Gate indicates that the pin is not protected, or affected by VCC=0 operation Gate indicates that the pin is protected as an input (if required) or set to a HI-Z state as an output (if required) In these columns, information is given in order of pin function: e.g. 1st pin function / 2nd pin function 2.3 Buffer Description Table 2.8 lists the buffers that are used in this device. A complete description of these buffers can be found in TBD. Table 2.8 Buffer Description BUFFER I IL IM IAN IANP IANDIAND+ IS I_VID IMOD3 IMO3 O6 O8 OD8 IO8 IOD8 SMSC SCH311X DESCRIPTION Input TTL Compatible - Super I/O Block. Input, Low Leakage Current. Input - Hardware Monitoring Block. Analog Input, Hardware Monitoring Block. Back Bias Protected Analog Input, Hardware Monitoring Block. Remote Thermal Diode (current sink) Negative Input Remote Thermal Diode (current source) Positive Input Input with Schmitt Trigger. Input. See DC Characteristics Section. Input/Output (Open Drain), 3mA sink. Input/Output, 3mA sink, 3mA source. Output, 6mA sink, 3mA source. Output, 8mA sink, 4mA source. Open Drain Output, 8mA sink. Input/Output, 8mA sink, 4mA source. Input/Open Drain Output, 8mA sink, 4mA source. 21 Rev 0.2 (09-28-04) DATASHEET LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 2.8 Buffer Description (continued) BUFFER IS/O8 O12 OD12 OD4 IO12 IOD12 OD14 OP14 OD_PH IOP14 IO16 IOD16 PCI_IO PCI_O PCI_I PCI_ICLK nSW ISPU_400 ISPU DESCRIPTION Input with Schmitt Trigger/Output, 8mA sink, 4mA source. Output, 12mA sink, 6mA source. Open Drain Output, 12mA sink. Open Drain Output, 4mA sink. Input/Output, 12mA sink, 6mA source. Input/Open Drain Output, 12mA sink, 6mA source. Open Drain Output, 14mA sink. Output, 14mA sink, 14mA source. Input/Output (Open Drain), See DC Electrical Characteristics on page 339 Input/Output, 14mA sink, 14mA source. Backdrive protected. Input/Output 16mA sink. Input/Output (Open Drain), 16mA sink. Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) Output. These pins must meet the PCI 3.3V AC and DC Characteristics. Input. These pins must meet the PCI 3.3V AC and DC Characteristics. Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. n Channel Switch (Ron~25 Ohms) Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up. Input with Schmitt Trigger and Integrated Pull-Up. Note 2.17 See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2. Note 2.18 See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3. Rev 0.2 (09-28-04) DATASHEET 22 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 3 Block Diagram PD[7:0] BUSY,nSCLTIN SCLT, PE nERROR, nACK nSTROBE, nINIT, nALF WDT* CLKI32 CLOCKI SER_IRQ PCICLK CLOCK GEN WDT LEDs LED1* LED2* SERIAL IRQ Internal Bus (Data, Address, and Control lines) LAD[3:0] LFRAME# LDRQ# PCI_RESET# LPC Bus Interface Multi-Mode Parallel Port with ChiProtectTM/ AND FDC MUX High-Speed 16550A UART PORT 1 & 2 Power Mgmt High-Speed 16550A UART PORT 3& 4 32 byte Security Key Register TXD1, RXD1 nCTS1, nRTS1 nDSR1, nDTR1 nDCD1, nRI1 TXD2 (IRTX2) RXD2 (IRRX2) nCTS2, nRTS2 nDSR2, nDTR2 nDCD2, nRI2 TXD3, RXD3 nCTS3, nRTS3 nDSR3, nDTR3 nDCD3, nRI3 TXD4, RXD4, nCTS4, nRTS4 nDSR4, nDTR4 nDCD4, nRI4 nIDE_RSTDRV nPCIRST[1:3] MCLK, MDAT A20M, nKBDRST, KCLK,KDAT nIO_PME nIO_SMI GP10-17 GP21,22, GP27, GP30-34, GP36-37, GP40, GP42, GP44-47, GP50-57, GP60-67 General Purpose I/O nMTR0, nTRK0, nINDEX nWGATE, nHDSEL, DRVDEN0*, nWRTPRT, nDIR, nSTEP, nDSKCHG, nDS0, nRDATA, nWDATA SMSC Proprietary 82077 Compatible Floppydisk Controller with Digital Data Separator & Write Precompensation PCI Reset Outputs Keyboard/Mouse 8042 controller VCC VTR Vbat HWN_INT 14.318Mhz 96 Mhz PCI_RESET# Power Control and Recovery PB_IN# PS_ON# SLP_SX# PB_OUT# nFPRST PWRGD_PS PWRGD_OUT Reset Generation Watchdog Timer nThremtrip Hardware Monitor High-Speed 16550A UART PORT 5 & 6 TXD5, RXD5 nSCIN5 nSCOUT5 TXD6, RXD6 nSCIN6 nSCOUT6 +5VTR_IN +12V_IN +2.5V_IN VCCP_IN +5V_IN HVTR HVSS Remote1Remote1+ Remote2Remote2+ FANTACH1 FANTACH2 FANTACH3 PWM1 PWM2 PWM3 nHWM_INT nTHERMTRIP SCH3112, SCH3114 ONLY SCH3114, SCH3116 ONLY SCH3116 ONLY Figure 3.1 SCH311X Block Diagram SMSC SCH311X DATASHEET 23 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Rev 0.2 (09-28-04) DATASHEET 24 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 4 Power Functionality TheSCH311X has five power planes: VCC, HVTR, VREF, VTR, and Vbat. 4.1 VCC Power The SCH311X is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). VCC is the main power supply for the Super I/O Block. See Section 28.2, "DC Electrical Characteristics," on page 339. 4.2 HVTR Power The SCH311X is family of 3.3 Volt devices. The HVTR supply is 3.3 Volts (nominal). HVTR is a dedicated power supply for the Hardware Monitoring Block. HVTR is connected to the VTR suspend well. See Section 28.2, "DC Electrical Characteristics," on page 339. Note: The hardware monitoring logic is powered by HVTR, but only operational when VCC is on. The hardware monitoring block is connected to the suspend well to retain the programmed configuration through a sleep cycle. 4.3 3 Volt Operation / 5 Volt Tolerance The SCH311X is a 3.3-Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.5V Max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC powered circuitry). The 5V tolerant pins are applicable to the Super I/O Block only. The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: ■ ■ ■ LAD[3:0] LFRAME# LDRQ# The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins in the Super I/O Block: ■ ■ ■ ■ PCI_RESET# PCI_CLK SER_IRQ nIO_PME The Hardware Monitoring Block digital pins are 3.3V only. 4.4 VTR Support The SCH311X requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See Chapter 28, "Operational Description," on page 339. The maximum VTR current that is required depends on the functions that are used in the part. See Chapter 28, "Operational Description," on page 339. If the SCH311X is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full SMSC SCH311X DATASHEET 25 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet minimum potential at least 10 ms before Vcc begins a power-on cycle. Note that under all circumstances, the hardware monitoring HVTR must be driven as the same source as VTR. 4.4.1 Trickle Power Functionality When the SCH311X is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. (See PME_STS1.) The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. ■ I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present. ■ The GPIOs that are used for PME wakeup as input are GP21-GP22, GP27, GP32, GP33, GP50-GP57, GP60, GP61 (See PME_STS1.)These GPIOs function as follows (with the exception of GP60 and GP61 - see below): ■ Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR. All GPIOs listed above are PME wakeup as a GPIO (or alternate function). GP32 and GP33 revert to their non-inverting GPIO input function when VCC is removed from the part. The other GPIOs function as follows: GP36, GP37 and GP40: ■ Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR, and are not used for wakeup. GP42, GP60 and GP61: ■ Buffers powered by VTR. GP42 are the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin under VTR. The following list summarizes the blocks, registers and pins that are powered by VTR. ■ ■ ■ ■ ■ ■ ■ ■ PME interface block PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers) Digital logic in the Hardware Monitoring block “Wake on Specific Key” logic LED control logic Watchdog Timer Power Recovery Logic Pins for PME Wakeup: GP42/nIO_PME (output, buffer powered by VTR) CLOCKI32 (input, buffer powered by VTR) nRI1 (input) GP50/nRI2 (input) GP52/RXD2(IRRX) (input) KDAT/GP21 (input) MDAT/GP32 (input) Rev 0.2 (09-28-04) DATASHEET 26 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet GPIOs (GP21-GP22, GP27, GP32, GP33, GP50-GP57, GP60, GP61) – all input-only except GP60, GP61. See below. ■ Other Pins GP60/LED1 (output, buffer powered by VTR) GP61/LED2 (output, buffer powered by VTR) nRSMRST PWRGD_PS PB_IN# PB_OUT# PS_ON# nFPRST SLP_SX# PWRGD_OUT 4.5 Vbat Support Vbat is a battery generated power supply that is needed to support the power recovery logic. The power recovery logic is used to restore power to the system in the event of a power failure. Power may be returned to the system by a keyboard power button, the main power button, or by the power recovery logic following an unexpected power failure. The Vbat supply is 3.0 Volts (nominal). See Chapter 28, "Operational Description," on page 339. The following Runtime Registers are powered by Vbat: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Bank 2 of the Runtime Register block used for the 32kbyte Security Key register PME_EN7 at offset 10h PWR_REC Register at offset 49h PS_ON Register at offset 4Ah PS_ON Previous State Register at offset 53h DBLCLICK register at offset 5Bh Keyboard Scan Code – Make Byte 1 at offset 5Fh Keyboard Scan Code – Make Byte 2 at offset 60h Keyboard Scan Code – Break Byte 1 at offset 61h Keyboard Scan Code – Break Byte 2 at offset 62h Keyboard Scan Code – Break Byte 3 at offset 63h Keyboard PWRBTN/SPEKEY at offset 64h Note: All Vbat powered pins and registers are powered by VTR when VTR power is on and are battery backed-up when VTR is removed. 4.6 32.768 KHz Trickle Clock Input The SCH311X utilizes a 32.768 KHz trickle input to supply a clock signal for the WDT, LED blink, Power Recovery Logic, and wake on specific key function. Indication of 32KHZ Clock There is a bit to indicate whether or not the 32KHz clock input is connected to the SCH311X. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: SMSC SCH311X DATASHEET 27 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 0=32KHz clock is connected to the CLKI32 pin (default) 1=32KHz clock is not connected to the CLKI32 pin (pin is grounded). Bit 0 controls the source of the 32KHz (nominal) clock for the LED blink logic and the “wake on specific key” logic. When the external 32KHz clock is connected, that will be the source for the fan, LED and “wake on specific key” logic. When the external 32KHz clock is not connected, an internal 32KHz clock source will be derived from the 14MHz clock for the LED and “wake on specific key” logic. The following functions will not work under VTR power (VCC removed) if the external 32KHz clock is not connected. These functions will work under VCC power even if the external 32 KHz clock is not connected. ■ ■ ■ ■ ■ Wake on specific key LED blink Power Recovery Logic WDT Front Panel Reset with Input Debounce, Power Supply Gate, and CPU Powergood Signal Generation 4.7 Super I/O Functions The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The super I/O pins that are powered by VTR are as follows: GP42/nIO_PME, GP60/LED1, GP61/LED2, PWRGD_OUT, and CLKI32. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving. The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). The maximum Vbat current, Ibat, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). 4.8 Power Management Events (PME/SCI) The SCH311X offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal. See the Chapter 15, "PME Support," on page 153 section. Rev 0.2 (09-28-04) DATASHEET 28 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 5 SIO Overview The SCH311X is a Super I/O Device with hardware monitoring. The Super I/O features are implemented as logical devices accessible through the LPC interface. The Super I/O blocks are powered by VCC, VTR, or Vbat. The Hardware Monitoring block is powered by HVTR and is accessible via the LPC interface. The following chapters define each of the functional blocks implemented in the SCH311X, their corresponding registers, and physical characteristics. This chapter offers an introduction into the Super I/O functional blocks, registers and host interface. Details regarding the hardware monitoring block are defined in later chapters. The block diagram in PME_STS1 further details the layout of the device. Note that the Super I/O registers are implemented as typical Plug-and-Play components. 5.1 Super I/O Registers The address map, shown below in Table 5.1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of all the Super I/O Logical Blocks, including the configuration register block, can be moved or relocated via the configuration registers. Note: Some addresses are used to access more than one register. 5.2 Host Processor Interface (LPC) The host processor communicates with the Super I/O features in the SCH311X through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 5.1, "Super I/O Block Addresses". Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. Table 5.1 Super I/O Block Addresses ADDRESS Base+(0-5) and +(7) na na Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base+(0-7) Base+(0-7) na 60, 64 na Base1 + (0-7F) Base2 + (0-1F) Base+(0-7) SMSC SCH311X BLOCK NAME Floppy Disk Reserved Reserved Parallel Port SPP EPP ECP ECP+EPP+SPP Serial Port Com 1 Serial Port Com 2 Reserved KYBD Reserved Runtime Registers Security Key Registers Serial Port Com 3 29 LOGICAL DEVICE 0 1 2 3 NOTES (Note 5.5) (Note 5.5) 4 5 6 7 8,9 A B (Note 5.2) (Note 5.3) Rev 0.2 (09-28-04) DATASHEET LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 5.1 Super I/O Block Addresses (continued) ADDRESS Base+(0-7) Base+(0-7) Base+(0-7) na Base + (0-1) Note 5.1 Note 5.2 Note 5.3 Note 5.4 Note 5.5 BLOCK NAME Serial Port Com 4 Serial Port Com 5 Serial Port Com 6 Reserved Configuration LOGICAL DEVICE C D E F (Note 5.1) NOTES Note 5.3 Note 5.3, Note 5.4 Note 5.3, Note 5.4 Refer to the configuration register descriptions for setting the base address. Logical Device A is referred to as the Runtime Register block at Base1 or PME Block and may be used interchangeably throughout this document. Reserved in SCH3112 Device Reserved in SCH3114 Device na = not applicable Rev 0.2 (09-28-04) DATASHEET 30 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 6 LPC Interface 6.1 LPC Interface Signal Definition The signals implemented for the LPC bus interface are described in the tables below. LPC bus signals use PCI 33MHz electrical signal characteristics. 6.1.1 SIGNAL NAME LAD[3:0] LFRAME# LPC Required Signals TYPE I/O Input Input Input DESCRIPTION LPC address/data bus. Multiplexed command, address and data bus. Frame signal. Indicates start of new cycle and termination of broken cycle PCI Reset. Used as LPC Interface Reset. Same functionality as RST_DRV but active low 3.3V. PCI Clock. PCI_RESET# PCI_CLK 6.1.2 SIGNAL NAME LDRQ# SER_IRQ CLKRUN# nIO_PME LPCPD# LSMI# LPC Optional Signals TYPE Output I/O OD OD I OD DESCRIPTION Encoded DMA/Bus Master request for the LPC interface. Serial IRQ. Clock Run Same as the PME# or Power Mgt Event signal. Allows the SCH311X to request wakeup in S3 and below. Power down - Indicates that the device should prepare for LPC I/F shutdown Only need for SMI# generation on I/O instruction for retry. COMMENT Implemented Implemented Not Implemented Implemented Not Implemented Not Implemented 6.2 Supported LPC Cycles Table 6.1 summarizes the cycle types are supported by the SCH311X. All other cycle types are ignored. Table 6.1 Supported LPC Cycles CYCLE TYPE I/O Write I/O Read Memory Write Memory Read TRANSFER SIZE 1 Byte 1 Byte 1 Byte 1 Byte COMMENT Supported Supported Not Supported Not Supported SMSC SCH311X DATASHEET 31 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 6.1 Supported LPC Cycles (continued) CYCLE TYPE DMA Write DMA Write DMA Write DMA Read DMA Read DMA Read Bus Master Memory Write Bus Master Memory Write Bus Master Memory Write Bus Master Memory Read Bus Master Memory Read Bus Master Memory Read Bus Master I/O Write Bus Master I/O Write Bus Master I/O Write Bus Master I/O Read Bus Master I/O Read Bus Master I/O Read TRANSFER SIZE 1 Byte 2 Byte 4 Byte 1 Byte 2 Byte 4 Byte 1 Byte 2 Byte 4 Byte 1 Byte 2 Byte 4 Byte 1 Byte 2 Byte 4 Byte 1 Byte 2 Byte 4 Byte COMMENT Supported Supported Not Supported Supported Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported 6.3 Device Specific Information The LPC interface conforms to the “Low Pin Count (LPC) Interface Specification”. The following section will review any implementation specific information for this device. 6.3.1 SYNC Protocol The SYNC pattern is used to add wait states. For read cycles, the SCH311X immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the SCH311X needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The SCH311X will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The SCH311X uses a SYNC of 0101 for all wait states in a DMA transfer. The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the SCH311X uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. Rev 0.2 (09-28-04) DATASHEET 32 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 6.3.2 Reset Policy The following rules govern the reset policy: ■ When PCI_RESET# goes inactive (high), the PCI clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. When PCI_RESET# goes active (low): ■ 1. The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal. 2. The SCH311X ignores LFRAME#, tristates the LAD[3:0] pins and drives the LDRQ# signal inactive (high). SMSC SCH311X DATASHEET 33 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Rev 0.2 (09-28-04) DATASHEET 34 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Chapter 7 Floppy Disk Controller The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. SCH311X supports a single floppy disk drive. The FDC is compatible to the 82077AA using SMSC’s proprietary floppy disk controller core. 7.1 FDC Internal Registers The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 7.1 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. (Shown with base addresses of 3F0 and 370) Table 7.1 Status, Data and Control Registers PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 SECONDARY ADDRESS 370 371 372 373 374 374 375 376 377 377 R/W R R R/W R/W R W R/W R W REGISTER Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR) 7.1.1 Status Register A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F0. PS/2 MODE 7 INT PENDING RESET COND. 0 6 nDRV2 1 5 STEP 0 4 nTRK0 N/A 3 HDSEL 0 2 nINDX N/A 1 nWP N/A 0 DIR 0 SMSC SCH311X DATASHEET 35 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Bit 0 DIRECTION Active high status indicating the direction of head movement. A logic “1” indicates inward direction; a logic “0” indicates outward direction. Bit 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic “0” indicates that the disk is write protected. Bit 2 nINDEX Active low status of the INDEX disk interface input. Bit 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0. Bit 4 nTRACK 0 Active low status of the TRK0 disk interface input. Bit 5 STEP Active high status of the STEP output disk interface output pin. Bit 6 nDRV2 This function is not supported. This bit is always read as “1”. Bit 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. 7.1.2 PS/2 Model 30 Mode 7 INT PENDING RESET COND. 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 nHDSEL 1 2 INDX N/A 1 WP N/A 0 nDIR 1 Bit 0 DIRECTION Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic “1” indicates outward direction. Bit 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write protected. Bit 2 INDEX Active high status of the INDEX disk interface input. Bit 3 HEAD SELECT Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side 0. Rev 0.2 (09-28-04) DATASHEET 36 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Bit 4 TRACK 0 Active high status of the TRK0 disk interface input. Bit 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. Bit 6 DMA REQUEST Active high status of the DMA request pending. Bit 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F1. PS/2 MODE 7 Reserved RESET COND. 1 6 Reserved 1 5 DRIVE SEL0 0 4 WDATA TOGGLE 0 3 RDATA TOGGLE 0 2 WGATE 0 1 Reserved 0 0 MOT EN0 0 Bit 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Bit 1 Reserved Reserved will return a zero (0) when read. This bit is low after a hardware reset and unaffected by a software reset. Bit 2 WRITE GATE Active high status of the WGATE disk interface output. Bit 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. Bit 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. Bit 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. SMSC SCH311X DATASHEET 37 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Bit 6 RESERVED Always read as a logic “1”. Bit 7 RESERVED Always read as a logic “1”. PS/2 MODEL 30 MODE 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 Bit 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. Bit 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. Bit 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. Bit 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. Bit 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. Bit 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. Bit 6 nDRIVE SELECT 1 The DS 1 disk interface is not supported. Bit 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. Rev 0.2 (09-28-04) DATASHEET 38 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet 7 MOT EN3 RESET COND. 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 nRESET 0 1 DRIVE SEL1 0 0 DRIVE SEL0 0 Bit 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. For proper device operation, they must be programmed to 0b00. Bit 2 nRESET A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. Bit 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable the DMA and interrupt functions. This bit is a logic “0” after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic “0”. Bit 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active. Bit 5 MOTOR ENABLE 1 The MTR1 disk interface output is not support in the LPC$&M262. For proper device operation this bit must be programmed with a zero (0). DRIVE 0 DOR VALUE 1CH Table 7.2 Internal 2 Drive Decode – Normal DIGITAL OUTPUT REGISTER Bit 4 1 X X Bit1 0 1 X Bit 0 0 0 1 DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS0 0 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR0 nBIT 4 nBIT 4 nBIT 4 SMSC SCH311X DATASHEET 39 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Bit 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the SCH311X. Bit 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the SCH311X. TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 7.3 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 7.3 Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 (not supported) 2 (not supported) 3 (not supported) APPLICATION NOTE: Note that in this device since only drive 0 is supported, the tape sel0/1 bits must be set to 0b00 for proper operation. NORMAL FLOPPY MODE Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 – 7 are ‘0’ Note only drive 0 is supported. DB7 REG 3F3 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0 ENHANCED FLOPPY MODE 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. Note only drive 0 is supported DB7 REG 3F3 Reserved DB6 Reserved DB5 DB4 DB3 DB2 DB1 tape sel1 DB0 tape sel0 Drive Type ID Floppy Boot Drive Rev 0.2 (09-28-04) DATASHEET 40 SMSC SCH311X LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 7.4 Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 0 0 1 1 Bit 0 0 1 0 1 REGISTER 3F3 – DRIVE TYPE ID Bit 5 L0-CRF2 – B1 L0-CRF2 – B3 L0-CRF2 – B5 L0-CRF2 – B7 Bit 4 L0-CRF2 – B0 L0-CRF2 – B2 L0-CRF2 – B4 L0-CRF2 – B6 Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. 7 S/W RESET RESET COND. 0 6 POWER DOWN 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 PRECOMP0 0 1 DRATE SEL1 1 0 DRATE SEL0 0 This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. Bit 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 7.6 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. Bit 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7.5 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. SMSC SCH311X DATASHEET 41 Rev 0.2 (09-28-04) LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports Datasheet Table 7.5 Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 Default: See Table 7.8 on page 43. Bit 5 UNDEFINED Should be written as a logic “0”. Bit 6 LOW POWER A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. Bit 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block Separator circuits will be turned off. The controller will come out of manual low power. PRECOMPENSATION DELAY (NSEC)