CXA1352AS

CXA1352AS 2-channel 5 Elements Graphic Equalizer IC Description The CXA1352AS is a bipolar IC for graphic equalizer use. All controls are DC performed while the addition of single-potentiometers easily composes a 2-channel graphic equalizer. Features • Microcomputer control possible • Built-in electronic volume • Built-in pseudo loudness function • Built-in balance function • Each channel corresponds to 5 elements • 2 channels of FIX OUT and LINE OUT pins Applications Graphic equalizer for cassette tape recorder with radio, mobile stereo and portable stereo Structure Bipolar silicon monolithic IC 22 pin SDIP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 12 V • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1200 mW Operating Conditions • Supply voltage • Operating temperature VCC DVCC Topr 4.0 to 10.0 3.5 to VCC –20 to +75 V V °C Block Diagram and Pin Configuration OUT2 (VARIABLE) 13 10 OUT1 (VARIABLE) 10kHz LINE OUT2 OUT2 (FIX) DVCC 1kHz 4kHz DC2 IN2 VCC 22 21 20 19 18 17 14dB 16 15 14 12 29dB VOLUME GRAPHIC EQUALIZER CONTROL GRAPHIC EQUALIZER BIAS 14dB 29dB VOLUME 1 400Hz 2 100Hz 3 BAL 4 VOL 5 DC1 6 1N1 7 GND 8 LINE OUT1 9 OUT1 (Fix) 11 ISET Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— VG E91912B95-TE CXA1352AS Pin Description Pin No. 1 2 20 21 22 Symbol Voltage 400 Hz 100 Hz 10 kHz 4 kHz 1 kHz I/O resistance DVCC 1 2 Equivalent circuit Description Graphic equalizer control pin DC input VCC DVCC 2 147 40k 20k 10k 60 kΩ 4 20 21 4 VOL 22 GND Volume control pin DC input DVCC 9k 147 40k VCC 3 BAL DVCC 2 60 kΩ 3 20k Balance control pin DC input GND VCC 30k 5 18 DC1 DC2 VCC 2 147 — 5 18 Connects the DC feedback capacitor of the LPF used in the 100 Hz graphic equalizer GND VCC 6 17 IN1 IN2 VCC 2 25 kΩ 147 6 17 50k 5k 50k 1k GND Signal input pin 7 GND GND 7 GND pin —2— CXA1352AS Pin No. Symbol Voltage I/O resistance Equivalent circuit Description VCC 8 15 L OUT1 L OUT2 VCC 2 147 300 300 27k 0 8 15 Line output pin GND VCC 9 14 F OUT1 F OUT2 VCC 2 147 300 300 30k 0 9 14 Fix output pin GND VCC 10 13 OUT1 OUT2 VCC 2 147 250 250 20k 0 10 13 Electronic volume output pin GND VCC 147 300 11 ISET 1.3 V 0 11 Reference current setting pin (for graphic equalizer) Normally 160 kΩ resistor is connected GND —3— CXA1352AS Pin No. Symbol Voltage I/O resistance Equivalent circuit Description VCC 40k 12 VG VCC 2 20 kΩ 147 12 40k 300 300 Signal reference voltage pin A capacitor is connected for ripple rejection GND 16 VCC VCC 16 VCC Power supply pin (operation) DVCC VCC 19 19 DVCC DVCC 60 kΩ 30k Power supply pin (control) 30k 42k GND —4— CXA1352AS Electrical Characteristics No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Item Supply voltage (operation) Supply voltage (control) Current consumption Reference input level Reference output level Reference LINE output level Reference FIX output level Graphic equalizer setting frequency (1) Graphic equalizer setting frequency (2) Graphic equalizer setting frequency (3) Graphic equalizer setting frequency (4) Graphic equalizer setting frequency (5) Graphic equalizer frequency deviation Maximum boost (1) Maximum boost (2) Maximum cut (1) Maximum cut (2) Total harmonic distortion Volume attenuation (1) Volume attenuation (2) Balance adjustment (1) Balance adjustment (2) Noise level Output offset voltage Symbol VCC DVCC ICC VIN VOUT VLINE VFIX GEQ1 GEQ2 GEQ3 GEQ4 GEQ5 ∆ EQ GEQB1 GEQB2 GEQC1 GEQC2 THD VOL1 VOL2 BAL1 BAL2 VNOIS VOFF Graphic equalizer ALL FLAT, Volume MAX, f=1 kHz f=1 kHz Graphic equalizer ALL FLAT, f=1 kHz LPF cut off frequency (–3 dB) BPF (1) central frequency BPF (2) central frequency BPF (3) central frequency HPF cut off frequency (–3 dB) Graphic equalizer ALL FLAT, Volume MID Test conditions (Ta=25 °C, VCC=8 V, DVCC=5 V) Min. 4.0 3.5 8.0 — Typ. — — 12.0 –34.0 Max. 10.0 VCC 16.0 — Unit V V mA dBm dBm dBm dBm Hz Hz kHz kHz kHz % dB dB dB dB % dB dB dB dB dB V –23.0 –20.0 –17.0 –6.5 –4.5 –2.5 –23.0 –20.0 –17.0 — — — — — 200 400 1.0 4.0 8.0 — — — — — Cut off frequency and central –20 0 20 frequency deviation f=400 Hz, 1 kHz, 4 kHz 9.0 11.2 14.0 maximum boost f=100 Hz, 10 kHz maximum boost 8.0 10.7 14.0 f=400 Hz, 1 kHz, 4kHz –13.0 –10.7 –8.5 maximum cut f=100 Hz, 10 kHz maximum cut –12.0 –9.5 –7.0 RL=2 kΩ, Graphic equalizer ALL FLAT, Volume MAX, f=1 kHz, — 0.25 1.0 Reference +10 dB is input Graphic equalizer ALL FLAT, –1.5 0 1.5 Volume MAX, f=1 kHz Graphic equalizer ALL FLAT, — –94.4 –80.0 Volume MIN, f=1 kHz Graphic equalizer ALL FLAT, — 0 — BAL=MAX,Volume MAX, f=1kHz Graphic equalizer ALL FLAT, — –66 — BAL=MIN, Volume MAX, f=1kHz Rg=5 kΩ, Graphic equalizer ALL — –93.1 –88.0 FLAT, Volume MAX, “A” WTG filter Graphic equalizer ALL FLAT, 3.5 4.0 4.5 Volume MAX —5— Electrical Characteristics Test Circuit GND POWER SUPPLY S10 S9 S8 S4 R20 2k S16 S15 S14 S20 1kHz BPF S19 DIN AUDIO DC VOLTMETER POWER SUPPLY BOOST ∗ C8 100µ/ 25V S2 R10 39k C15 4.7µ/25V C17 4.7µ/25V C19 4.7µ/25V 13 12 VG 15 L OUT2 F OUT2 OUT2 14 R19 20k ∗ C10 4.7µ/ 25V 19 IN2 DVCC DC2 VCC 18 R12 5.1k C12 4.7µ/ 25V 17 16 ∗ C13 100µ/ A 25V R14 20k CUT R7 50k ∗ C20 R16 47µ/ 20k 25V BOOST CUT R6 50k ∗ C2 1000p ∗ C4 1000p ∗ C6 1000p BOOST 20 10kHz CUT 22 21 1kHz 4kHz R5 50k CXA1352AS “A” WTG OUT1 ISET NOISE FILTER 11 BAL VOL DC1 400Hz 100Hz IN1 GND L OUT1 R4 50k 3 ∗ C9 4.7µ/ 25V C11 4.7µ/ 25V C16 4.7µ/25V R9 39k R11 5.1k C14 4.7µ/25V R13 20k S1 4 5 6 7 8 9 10 C18 4.7µ/25V BOOST CUT 1 2 F OUT1 —6— ∗ ∗ C5 C7 1000p 1000p R15 R17 R18 20k 160k 20k NOTE 1. RESISTOR TOLERANCE ∗±5% ±1% 2. CAPACITOR TOLERANCE ∗±5% ±2% COUPLING CAPACITPR ±10% S18 R3 50k OUT IN S17 FILTER S13 S12 S11 R21 2k S3 S7 S6 S5 BOOST CUT ∗ C1 1000p ∗ C3 1000p AC VOLTMETER R2 50k CH2 CH1 DISTORTION ANALYZER R1 50k OSCILLO –SCOPE MAX MIN R8 620 CXA1352AS AUDIO SG Application Circuit To line amplifier For spectrum analyzer display or recording through graphic equalizer To power amplifier GND DVCC Signal input DVCC GND GND GND VCC GND R7 50k R6 50k C8 220µ C10 4.7µ C12 4.7µ 22 21 IN2 4kHz DVCC DC2 VCC 10kHz L OUT2 F OUT2 20 19 18 17 16 15 14 1kHz 13 OUT2 C13 220µ C15 2.2µ C17 2.2µ C19 2.2µ C7 2.2µ R9 5.1k C20 4.7µ R5 50k C6 2.2µ 12 VG R4 50k CXA1352AS C5 2.2µ 400Hz 100Hz BAL VOL DC1 IN1 GND L OUT1 F OUT1 OUT1 1 2 3 4 5 6 7 8 9 10 11 R2 50k C9 4.7µ C3 2.2µ C11 4.7µ C14 2.2µ R8 5.1k C16 2.2µ C18 2.2µ R10 160k R1 50k C2 2.2µ GND GND GND Signal input C1 2.2µ GND To power amplifier For spectrum analyzer display or recording through graphic equalizer To line amplifier CXA1352AS GND GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ISET —7— R3 50k C4 2.2µ CXA1352AS Description of Operation 1. Graphic equalizer • Conventional system R1 VI VO OPERATIONAL AMPLIFIER RV CUT L BOOST R2 R0=R1=R2 Z (s) C R Fig. 1. Fig. 1. indicates the conventional graphic equalizer system. This circuit performs boost and cut near “fO” controlled by the variable volume RV. (“fO” is resonance frequency determined by Z (s) (formed LCR).) The operation can be seen as follows : When the LCR circuit goes to the far left of RV, a state of graphic equalizer becomes maximum cut. At that time, assuming transmittance as T (s), we have T (s) = Z (s) Z (s)+ RO 1 sC Here as Z (s) = sL+R+ Then T (s) = LCs2+RCs+1 LCs2 + (R+Ro) Cs+1 ωo 1 ωoL , ωo as ωo = , and Q as Q = , 2π LC R Defining fo as fO = we can obtain the frequency characteristics at cut. Also, when LCR circuit goes to the far right of RV, a state of graphic equalizer becomes maximum boost. At that time transmittance is : T (s) = Z (s) +RO = Z (s) LCs2+ (R+Ro) Cs+1 LCs2+RCs+1 Defining fo, ωo and Q as for cut, we can obtain the frequency characteristics at boost. —8— CXA1352AS Fig. 2. Indicates frequency characteristics at boost and cut. Response (dB) Boost 0dB FIat fO= 1 2π LC Cut Frequency (Hz) fO Fig. 2. • CXA1352AS system R VI VO ωo s Q 2+ ωo s+ωo2 s Q Operational amplifier H(s)= R Z(s) Z(s) H(s) Ic Gm1 Gm2 Ib Fig. 3. The structure of the graphic equalizer used in this IC is shown on Fig. 3. This circuit performs boost and cut controlled by 2 transconductance amplifiers that can vary the conversion coefficient through control currents Ib, and Ic around ωo. (“ωo” is central frequency determined by Band Pass Filter.) Considering output impedance Z (s) of Gm1, Gm2 we have Z (s) = 1 H(s) • Gm1 —9— CXA1352AS Here, using ωo and Q we can express BPF transmittance H (s) as ωo •s Q ωo s2 + s + ωo2 Q Q 1 ωo • Q s+ + ωo • Gm1 Gm1 Gm1 • s H (s) = Z (s) = This formula shows that this system and the aforementioned LCR circuit have equivalent impedance characteristics on Z (s). Then, regarding Gm as the maximum value of Gm1 and Gm2, the operation can be observed as follows. Maximum cut occurs when Gm1=Gm and Gm2=0. At that time we have transmittance T (s) as ωo s2 + • s + ωo2 Z (s) Q T (s) = = (1+R • Gm) • ωo2 Z (s) +R • s+ ωo2 s2 + Q This is equal to the frequency characteristics of the conventional graphic equalizer at cut. Also, maximum boost occurs when Gm1=0 and Gm2=Gm. At that time we have transmittance T (s) as (1+R • Gm) • ωo2 s2 + • s+ ωo2 Q Z (s) +R T (s) = = ωo Z (s) s2 + • s + ωo2 Q This is equal to the frequency characteristics of the conventional graphic equalizer at boost. We can then deduce that, as far as the operation is concerned the graphic equalizer on this IC and the conventional graphic equalizer are equal, even when the system differs. The merit in using this IC’s system rests with the fact that monolithic filter technology realizes a graphic equalizer without external parts. The structure of the actual graphic equalizer, including BPF, is shown on Fig. 4. VI R1 30k C3 VI R2 30k Gm1 C1 Gm3 I CUT GND GND GND GND Gm4 I BOOST GND SUM VO 1 1 C2 Gm2 Fig. 4 —10— CXA1352AS 2. Control through microcomputer possible Volume, balance and the 100 Hz, 400 Hz, 1 kHz, 4 kHz, 10 kHz boost, cut control respectively are all executed through DC voltage. Also, the control voltage range is determined through DVCC (control power supply, independent from VCC) and is from 0 V to DVCC. Accordingly, the control range can be varied at will, by changing DVCC voltage. By setting DVCC 5 V, control through the microcomputer becomes possible. Setting to DVCC=VCC enables usage with single power supply. 3. Pseudo loudness A loudness function interlocking with volume (VOL) is featured. With this IC, to provide a loudness effect, the 100 Hz and 10 kHz graphic equalizer part does not use a BPF but is composed of a low pass filter (LPF) and a high pass filter (HPF) respectively. The operation is explained as follows. As VOL drops below the center, the 100 Hz and 10 kHz graphic equalizer part Ib (See Fig. 3.) gradually increases even if the graphic equalizer control pin (100 Hz and 10 kHz) is flat, boost applies and as a result loudness effect is obtained. —11— CXA1352AS Notes on Operation 1. Power supply DVCC can be used independently from VCC but supply voltage should be VCC≥DVCC, without fall. 2. Pseudo loudness As mentioned in the paragraph on Description of Operation, as it is interlocked with VOL, loudness can not be put OFF. 3. Output pin This IC features 2 channels for each of OUT pin, LINE OUT pin and FIX OUT pin. Usage of the respective output pins is indicated as follows. • OUT pin Normally used as the graphic equalizer output. • LINE OUT pin A sound from a source that has not passed through the graphic equalizer is only amplified and output from this pin. • FIX OUT pin This pin is useful for REC or spectrum analyzer display after the sound formation at the graphic equalizer. The relation between the input and the respective outputs is shown on Fig. 5. IN AMP –34dBm IN 14dB GRAPHIC EQUALIZER GEBPF+GEHPF+ GELPF+SUM AMP F OUT –20dBm VOLUME LINE AMP 29dB OUT –20dBm (VARIABLE) L OUT –5dBm Fig. 5. 4. Reference resistor To check the central frequency deviation of the graphic equalizer, the control current that determines the filter time constant is determined by means of an external, not an internal, resistor. This is the 160 kΩ external resistor connected to ISET pin (Pin 11). Accordingly, for the resistor to be connected to ISET pin, it is recommended to use a resistor with excellent dispersion and temperature characteristics. Also, by varying the value of the resistor connected to ISET pin, the frequency characteristics of the graphic equalizer can be shifted. By reducing the resistor value the shift moves to the high band and by increasing the value the shift moves to the low band. However, 5 elements cannot be shifted independently. —12— CXA1352AS Example of Representative Characteristics Frequency characterlstlcs 15 ALL BOOST 10 ALL FLAT RESPONSE(dB) 5 BOOST VCC=8V DVCC=5V 0dB=–20dBm, 1kHz VOL : MAX 0 –5 CUT –10 ALL CUT –15 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY(Hz) Loudness characteristics 8 VOL=0.0V 1.0V BOOST(dB) 4 1.5V 2.0V 0 VCC=8V DVCC=5V 0dB=at 1kHz ALL FLAT –4 50 100 200 500 1k 2k 5k 10k 2.5V 5.0V 20k FREQUENCY(Hz) —13— CXA1352AS THD-OUT characteristics (ALL FLAT) VCC=8V, DVCC=5V 0dB=–20dBm, VOL : MAX 10.0 5.0 2.0 THD+N (%) 1.0 0.5 0.2 0.1 0.05 10kHz 100Hz 1kHz THD+N (%) 10.0 5.0 2.0 1.0 0.5 THD-OUT characteristics (ALL BOOST) VCC=8V, DVCC=5V 0dB=–20dBm‚ VOL : MAX 1kHz 0.2 0.1 10kHz 0.05 100Hz 0 10 20 0 10 20 OUT pin output level (dB) OUT pin output level (dB) THD-OUT characteristics (ALL CUT) VCC=8V, DVCC=5V 0dB=–20dBm, VOL : MAX 10.0 5.0 2.0 THD+N (%) 1.0 0.5 0.2 0.1 0.05 1kHz 10kHz 100Hz THD+N (%) 10.0 5.0 2.0 1.0 0.5 THD-F OUT characteristics (ALL FLAT) VCC=8V, DVCC=5V 0dB=–20dBm, VOL : MAX 10kHz 0.2 0.1 0.05 1kHz 100Hz 0 10 20 0 10 20 30 OUT pin output level (dB) FIX OUT pin output level (dB) —14— CXA1352AS THD-F OUT characteristics (ALL BOOST) VCC=8V, DVCC=5V 0dB=–20dBm, VOL : MAX 10.0 5.0 2.0 THD+N (%) THD+N (%) 1.0 0.5 0.2 0.1 0.05 1kHz 10.0 5.0 2.0 1.0 0.5 0.2 100Hz 0.1 0.05 THD-F OUT characteristics (ALL CUT) VCC=8V, DVCC=5V 0dB=–20dBm, VOL : MAX 1kHz 10kHz 100Hz 10kHz 0 10 20 30 0 10 20 FIX OUT pin output level (dB) FIX OUT pin output level (dB) THD-L OUT characteristics VCC=8V, DVCC=5V 0dB=–6dBm, VOL : MAX 10.0 OUT pin output level (dBm) 5.0 2.0 THD+N (%) 1.0 0.5 0.2 0.1 0.05 1kHz –80 0 Output voltage vs. Control voltage (VOL) –20 –40 z kH 10 Hz 0 10 –60 VCC=8V DVCC=5V VIN=–14dBm,1kHz ALL FLAT –10 0 10 0.1 LINE OUT pin output level (dB) 0.2 0.5 1 2 5 Control voltage (V) —15— CXA1352AS Output voltage vs. Control voltage (VOL) 0 100 Output voltage vs. Control voltage (VOL) –20 OUT pin output level (dBm) 80 –40 OUT pin output level (%) 60 –60 40 –80 VCC=8V DVCC=5V VIN=–14dBm, 1kHz ALL FLAT –100 0 1.0 2.0 3.0 4.0 5.0 20 VCC=8V DVCC=5V VIN=–14dBm, 1kHz 100%=0dBm ALLFLAT 0 0 1.0 2.0 3.0 4.0 5.0 Control voltage (V) Control voltage (V) —16— CXA1352AS Package Outline Unit : mm 22PIN SDIP (PLASTIC) + 0.1 0.05 0.25 – + 0.4 19.2 – 0.1 22 12 + 0.3 6.4 – 0.1 1 1.778 11 0.5 ± 0.1 + 0.15 0.9 – 0.1 + 0.15 3.25 – 0.2 0.51 MIN + 0.4 3.9 – 0.1 7.62 0° to 15° Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-22P-01 SDIP022-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.95g —17—