CXA1396D

CXA1396D 8-bit 125 MSPS Flash A/D Converter Description The CXA1396D are 8-bit ultrahigh-speed flash A/D converter ICs capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of these A/D converters are compatible with the ECL 100K/10KH/10K. The CXA1396D is pin-compatible with the earlier model CX20116. They can replace the earlier models respectively, without any design changes, in most cases. Compared with the earlier models, these new models have been greatly improved in performance, by incorporating advanced process, new circuit design and carefully considered layout. Features • Ultrahigh-speed operation with maximum conversion rate of 125 MSPS (Min.) • Wide analog input bandwidth: 200MHz (Min. for full-scale input) • Low power consumption: 870mW (Typ.) • Single power supply: –5.2V • Low input capacitance • Built-in integral linearity compensation circuit • Low error rate • Operable at 50% clock duty cycle • Good temperature charactcristics • Capable of driving 50Ω loads 42 pin DIP (Ceramic) Structure Bipolar silicon monolithic IC Applications • Digital oscilloscopes • HDTV (high-definition TVs) • Other apparatus requiring ultrahigh-speed A/D conversion Pin Configuration Pins without name are NC pins (not connected). AVEE 1 2 LINV DVEE DGND1 DGND2 (LSB) D0 D1 D2 3 4 5 6 7 8 9 42 41 VRT 40 39 AVEE 38 AVEE 37 36 35 AGND 34 VIN 33 AGND 32 VRM 31 AGND 30 VIN 29 AGND 28 27 26 AVEE 25 AVEE 24 23 VRB 22 D3 10 D4 11 D5 12 D6 13 (MSB) D7 14 DGND2 15 DGND1 16 DVEE 17 MINV 18 19 CLK 20 CLK 21 (Top View) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94521A79-PS CXA1396D Absolute Maximum Ratings (Ta = 25°C) • Supply voltage AVEE, DVEE • Analog input voltage VIN • Reference input voltage VRT, VRB, VRM  VRT – VRB  • Digital input voltage • VRM pin input curent • Digital output current • Storage temperature CLK, CLK, MINV, LINV  CLK – CLK  IVRM ID0 to ID7 Tstg –7 to +0.5 –2.7 to +0.5 –2.7 to +0.5 2.5 –4 to +0.5 2.7 –3 to +3 –30 to 0 –65 to +150 Typ. –5.2 0 0 0 –2.0 V V V V V V mA mA °C Max. –4.95 +0.05 +0.05 +0.1 –1.8 VRT unit V V V V V ns ns °C Recommended Operating Conditions • Supply voltage AVEE, DVEE AVEE – DVEE AGND – DGND • Reference input voltage VRT VRB • Analog input voltage VIN • Pulse width of clock TPW1 TPW0 • Operating temperature Ta Min. –5.5 –0.05 –0.05 –0.1 –2.2 VRB 4.0 4.0 –20 +75 –2– CXA1396D Block Diagram MINV r1 VRT r/2 r r r 1 2 • • • Comparator D7 (MSB) r VIN 63 D6 64 r 65 r r r2 r r D5 • • • OUTPUT 126 D4 ENCODE LOGIC 127 128 129 D3 VRM D2 r r VIN • • • D1 191 192 D0 (LSB) r 193 r r r3 r/2 • • • 254 255 VRB CLK CLK CLOCK DRIVER LINV –3– CXA1396D Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol I/O Standard voltage level Equivalent circuit Description Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. Analog VEE. –5.2V (Typ.). Internally connected with DVEE (resistance: 4 to 6Ω). A ceramic chip capacitor of at least 0.1µF should be used to connect to AGND and be placed near the pins. DGND1 29, 31, 33, 35 AGND — 0V 1, 25, 26, 38, 39 AVEE — –5.2V r r 21 CLK CLK r r CLK input I ECL CLK 20 CLK DVEE r r Complementary input to CLK. With open connection, kept at threshold voltage (–1.3V). Device is operable without CLK input, but use of omplementary inputs of CLK and CLK is recommended to obtain the stable high-speed operation. Digital GND for internal circuits. Digital GND for output transistors. Digital VEE. Internally connected with AVEE (resistance: 4 to 6Ω). A ceramic chip capacitor of at least 0.1µF should be used to connect to DGND near the pins. 5, 16 6, 15 DGND1 DGND2 — — 0V 0V 4, 17 DVEE — –5.2V –4– CXA1396D Pin No. Symbol I/O Standard voltage level Equivalent circuit DGND2 Description LSB of data outputs. External pull-down resistor is required. 7 8 9 10 11 12 13 14 D0 D1 D2 D3 D4 D5 D6 D7 DVEE Di O ECL Data outputs. External pull-down resistors are required. MSB of data outputs. External pull-down resistor is required. Input pin for D0 (LSB) to D6 output polarity inversion (see output code table). With open connection, kept at "L" level. –1.3V DGND1 3 LINV I ECL r LINV or MINV r r 18 MINV I ECL DVEE r Input pin for D7(MSB) output polarity inversion (see output code table). With open connection, kept at "L" level. AGND VIN 30, 34 VIN I VRT to VRB VIN Analog input pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions. AVEE –5– CXA1396D Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VRT r1 r/2 r Comparator r Comparator 2 . . . 127 128 129 130 . . . . . . . 255 1 23 VRB I –2V Reference voltage (bottom). Typically –2V. A ceramic capacitor of at least 0.1µF and a tantalum capacitor of at least 10µF should be used to connect to AGND near the pins. 32 VRM I VRB/2 VRM r2 r Comparator r Comparator r Comparator r Comparator Reference voltage mid point. Can be used as a pin for integral linearity compensation. 41 VRT I 0V VRB r3 r Comparator r/2 Reference voltage (top). Typically 0V. When a voltage except for AGND is applied to this pin, a ceramic capacitor of at least 0.1µF and a tantalum capacitor of at least 10µF should be used to connect to AGND near the pins. 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 NC — — Unused pins. No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended. –6– CXA1396D Electrical Characteristics Item Resolution Symbol n Fc = 125MSPS Fc = 125MSPS (Ta = 25°C, AVEE = DVEE = –5.2V, VRT = 0V, VRB = –2V) Condition Min. Typ. 8 ±0.3 ±0.3 17 190 130 75 8 0 –1.13 Input connected to –0.8V Input connected to –1.6V 0 –50 7 Fc Taj Tds Tdo TPW1 TPW0 VOH VOL Tr Tf Error rate 10–9 TPS∗1 125 10 1.5 3.6 –1.50 50 50 110 19 15 ±0.5 ±0.5 Max. Unit bits LSB LSB pF kΩ µA Ω mV mV V V µA µA pF MSPS ps ns ns ns ns V V ns ns MHz dB dB TPS∗1 % deg mA mW DC characteristics EIL Integral linearity error Differential linearity error EDL Analog input Analog input capacitance Analog input resistance Input bias current Reference inputs Reference resistance Offset voltage VRT VRB Digital inputs Logic H level Logic L level Logic H current Logic L current Input capacitance Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Output delay H pulse width of clock L pulse width of clock Digital outputs Logic H level Logic L level Output rising time Output falling time Dynamic characteristics Input bandwidth S/N ratio CIN RIN IIN RREF EOT EOB VIH VIL IIH IIL VIN = –1V + 0.07Vrms VIN = –1V 320 155 32 24 3.0 4.0 4.0 RL = 50Ω to –2V RL = 50Ω to –2V RL = 50Ω to –2V, 20% to 80% RL = 50Ω to –2V, 80% to 20% VIN = 2Vp-p, 3dB down Input = 1MHz, FS Clock = 125MHz Input = 31.5MHz, FS Clock = 125MHz Input = 31.249MHz, FS Error > 16LSB Clock = 125MHz NTSC 40IRE mod.ramp, Fc = 125MSPS –1.10 4.2 –1.62 0.8 1.0 200 46 40 { { Error rate { } 10–9 1.0 0.5 –230 –160 870 Differential gain error Differential phase error Power supply Supply current Power consumption∗2 ∗1 TPS: times Per Sample ∗2 Pd = IEE • VEE + DG DP IEE Pd (VRT – VRB)2 RREF –7– CXA1396D Output Code Table VIN∗ Step D7 0V 0 1 MINV LINV 1 1 D0 D7 0 0 0 …… 0 0 0 0 0 …… 0 0 0 0 0 …… 0 1 : : 0 1 1 …… 1 1 1 0 0 …… 0 0 : : 1 1 1 …… 1 0 1 1 1 …… 1 1 1 1 1 …… 1 1 0 1 D0 1 0 0 …… 0 0 1 0 0 …… 0 0 1 0 0 …… 0 1 : : 1 1 1 …… 1 1 0 0 0 …… 0 0 : : 0 1 1 …… 1 0 0 1 1 …… 1 1 0 1 1 …… 1 1 D7 0 1 1 …… 1 1 0 1 1 …… 1 1 0 1 1 …… 1 0 : : 0 0 0 …… 0 0 1 1 1 …… 1 1 : : 1 0 0 …… 0 1 1 0 0 …… 0 0 1 0 0 …… 0 0 1 0 D0 D7 0 0 D0 1 1 1 …… 1 1 1 1 1 …… 1 1 1 1 1 …… 1 0 : : 1 0 0 …… 0 0 0 1 1 …… 1 1 : : 0 0 0 …… 0 1 0 0 0 …… 0 0 0 0 0 …… 0 0 –1V 127 128 254 255 –2V ∗ VRT = 0V, VRB = –2V Timing diagram Tds N Analog in Tpw1 CLK CLK Tpw0 N+2 N+1 Digital out Tdo N–1 80% 20% Tr N 80% N+1 20% Tf –8– CXA1396D Electrical Characteristics Test Circuit Maximum conversion rate test circuit Vin 8 CXA1396D CLK CLK A B + ECL Latch Comparator A>B Pulse Counter Signal Source ECL Latch fCLK – 1kHz 4 2Vp-p Sine Wave DATA 16 Signal Source fCLK 1/4 Differential gain error test circuit Differential phase error test circuit (CX20202A-1) VIN Amp 10Ω 8 8 DUT CXA1396D ECL Latch 10bit D/A CLK NTSC Signal Source CLK Delay VBB SG (CW) 50 DG.DP Vector Scope Integral linearity error test circuit Differential linearity error test circuit +V S2 S1: A < B: ON S2: A > B: ON S1 –V AB Comparator VIN 8 DUT CXA1396D A8 to A1 A0 "0" DVM CLK (125MHz) Controller B8 to B1 B0 8 Buffer "1" 8 00000000 to 11111110 –9– CXA1396D Power Supply Current Test Circuit Analog input bias current test circuit –1V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CXA1396D 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 –2V A IIN A IEE –5.2V Sampling delay test circuit Aperture jitter test circuit 67.5MHz Amp OSC1 φ: Variable VIN fr CLK CXA1396D 8 Aperture jitter test method 0V VIN –1V –2V CLK Logic Analizer VIN 1024 samples ECL Buffer ∆v ∆t 129 128 127 126 125 σ (LSB) t OSC2 67.5MHz CLK Aperture jitter Apeature jitter is defined as follows: Taj = σ/ ∆v ∆t = σ/( 256 2 × 2πf ), Where σ (unit : LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. – 10 – CXA1396D 8-bit, 125MSPS ADC Evaluation board Description The CXA1396D EVALUATION BOARD WITH DAC is a tool for customers to evaluate the performance of the CXA1396D (8-bit, 125MSPS, high-speed A/D converter). In addition to indispensable features such as the reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high-speed DAC, and the 20-pin cable connector for digital outputs. This evaluation board provides full performance of the CXA1396D and it is designed to facilitate evaluation. Features • Resolution: 8bits • Maximum conversion rate: 125MSPS • Supply voltage: +5.0V, –5.2V, –2.0V • Two analog inputs (Direct input, buffer amplifier input) • Clock level converter: Sine wave to ECL level signal • Reference voltage adjustment circuit for the A/D converter • Built-in clock frequency decimation circuit: (1/1 to 1/16) Fig. 1. Block Diagram –5.2V (A) VR2 (2k) VRB –2V H L –5.2V (A) VR1 (2k) Vin OFFSET VR3 (1k) SW1 SW2 DIGITAL OUT (CONNECTOR) (D7 to D0) 8 DATA LATCH 8 BUFFER 8 LINV MINV VRB J1 A 1k B CLK VRM CXA1396D AMP.IN 240 51 X (–2) C D Vin CLK (D7 to D0) 8 2 (CLK.CLK) 51 DIR.IN 0.1µ CLK DECIMATOR CLK D/A CONVERTER D/A OUT SW3 1/1 to 1/16 +5V –5.2V (A) AGND –5.2V (D) DGND –2V (D) – 11 – CXA1396D Supply Current Item –5.2V +5.0V –2.0V Min. Typ. 0.85 15 0.45 Max. 1.0 30 0.6 Unit A mA A (Note: Supply current –2.0V is the value when Rn10, Rn11 and Rn12 are not mounted.) Analog Input (DIR. IN, AMP. IN) Item Input voltage (DIR. IN) (AMP. IN) ∗1 Input impedance (∗1: Adjustable by VR1) Min. –2.0 –0.5 50 Typ. Max. 0 +0.5 Unit V V Ω Clock Input (CLK) Item Input voltage (Peak to Peak) Input impedance Min. Typ. 1.0 50 Max. Unit Vp-p Ω Digital Output (D0 to D7) ECL 10KH level Clock Output ECL 10KH level, complementary output Output Code Table MINV LINV 0V : : : : : : : : –2V 0 0 1 1 1 …… 1 1 1 1 1 …… 1 0 : : 1 0 0 …… 0 0 0 1 1 …… 1 1 : : 0 0 0 …… 0 1 0 0 0 …… 0 0 0 1 1 0 0 …… 0 0 1 0 0 …… 0 1 : : 1 1 1 …… 1 1 0 0 0 …… 0 0 : : 0 1 1 …… 1 0 0 1 1 …… 1 1 1 0 0 1 1 …… 1 1 0 1 1 …… 1 0 : : 0 0 0 …… 0 0 1 1 1 …… 1 1 : : 1 0 0 …… 0 1 1 0 0 …… 0 0 1 1 0 0 0 …… 0 0 0 0 0 …… 0 1 : : 0 1 1 …… 1 1 1 0 0 …… 0 0 : : 1 1 1 …… 1 0 1 1 1 …… 1 1 VIN – 12 – CXA1396D Fig. 2. Timing Chart N A/D input pin Vin (DIR. IN, AMP. IN) N+1 PCB input pin CLK CLK A/D clock CLK A/D output D7 to D0 N–1 N PCB output pin D7 to D0 (For 1/1 frequency division) N–2 Tdh 1.8ns (Typ) N–1 N CLKN PCB output pin CLK (For 1/1 frequency division) PCB output pin DATA OUT (For 1/2 frequency division) N–4 N–2 Tdh 1.8ns (Typ) N CLKN PCB output pin CLK (For 1/2 frequency division) – 13 – CXA1396D Adjustment Methods and Notes on Operation 1) Vin Offset (VR1) The volume to adjust the signal range (0V center assumed) with the A/D converter input range when a waveform is input through AMP. IN. 2) A/D Full Scale (VR2) The volume to adjust A/D converter VRB voltage. Linearity (VR3) The volume to adjust VRM (linearity) voltage. When DIR. IN input selected and it is supplied through the capacitor, VR3 can be used to adjust the input offset voltage. D/A Full Scale (VR4) The volume to adjust D/A output full scale (–1V). J1 (Input selection) A: Shorts to adjust VRM voltage. B: Shorts to supply DC voltage to Vin. C: Shorts to select AMP.IN input. D: Shorts to select DIR.IN input. 3) 4) 5) [Jumper Position at Shipment] J1 A Input through the B buffer amplifier C D 6) J1 A B C D Input through the A B buffer amplifier (When the linearity C D is adjusted) J1 Input through the capacitor (When the offset is adjusted using the DIR IN. at the evaluation board) 0.1µF SW1 The switch for LINV High/Low. SW2 The switch for MINV High/Low. SW3 (Decimation) The switch to select clock frequency decimation. Switch position: decimation ratio 0: 1/1 1: 1/2 2: 1/4 3: 1/8 4: 1/16 SW4 (D/A INV) The switch for D/A converter output inversion. 7) 8) 9) – 14 – CXA1396D 10) Rn10, Rn11 and Rn12 are not mounted at shipment. They are not required during evaluation. 11) Waveform probe pins P5 and P8 through P28 are devised to facilitate GND connection in order to reduce the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300 mil, and there is φ1.2mm through hole at each. The signal and GND locations are suit for a Tektronix GND tip (part number 013-1185-00). φ1.2mm GND 300mil Probe point Fig. 3 12) D/A converter (IC13) input data (waveform probe pins P21 through P28) are the complementary signals of the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction of reproduced waveform can agree with the A/D input signal converter. 13) The part unmber of the digital output connector is KEL 8830E-020-170S. A corresponding connector and cable assembly is JUNKOSMA KBO020MCG50BI. – 15 – CXA1396D PCB Circuit Schematic +5V (A) FERRITE BEAD C9 0.1µ P9 P8 CLK CLKN R17 51 VRB P2 AGND C20 10 AGND C18 0.1µ 22 NC C19 0.1µ CLK 21 CLKN 20 NC 19 MINV 18 DVEE 17 DGND1 16 DGND2 15 D7 14 D6 13 IC6: CXA1396D D5 12 D4 11 D3 10 D2 9 D1 8 D0 DGND P14 D4 P15 D5 C25 0.1µ C22 0.1µ –2V (D) P16 D6 AGND R9 AGND 1.3k A/D Full Scale VR2 2k –5.2V (A) R5/11k R4 2 6 22k 1 3 4 IC1-1 C3 TL4558 0.1µ R6 240 R8 510 VR1 2K Q1 2SA970 6 5 IC3 TL431CP 87 4 IC1-2 TL4558 VR3 1k AGND Linearity 23 VRB 24 NC 25 AVEE 26 AVEE 27 NC 28 NC 29 AGND R16 51 DGND P17 D7 C27 0.1µ #1 P17 DVEE –5.2V (D) Vin Offset VRM P1 C8 0.1µ –5.2V (A) #2 #3 #4 –5.2V (A) AGND R7 1k AGND +5V (A) C4 3.3µ C12 C7 0.1µ 1µ AGND AGND AGND AGND AGND R13 R2 R10 R11 1k 240 510 43 2 76 AMP.IN 3 R1 4 IC4 51 CLC404AJP R12 C6 51 AGND AGND 1µ AGND AGND C11 0.1µ –5.2V (A) AGND AGND AGND 30 VIN 31 AGND A B C D J1 VIN P5 AGND P4 AGND AVEE P3 C17 0.1µ AGND 32 VRM 33 AGND 34 VIN 35 AGND 36 NC 37 NC 38 AVEE 7 P6 DGND C25 0.1µ –5.2V (D) C24 0.1µ D2 P12 D3 P13 DGND DGND2 6 DGND1 5 DVEE –5.2V (A) DIR.IN C15 1µ AGND AGND C16 0.1µ 39 AVEE 40 NC 41 VRT 42 NC 4 C26 1µ LINV 3 NC 2 AVEE 1 #5 #6 FERRITE BEAD –5.2V (A) #7 #8 P10 D0 SW1 LINV SW2 MINV P11 D1 D1 H DGND D2 D3 L R15 330 –5.2V (D) #9 #10 –2V (D) 1 VCC1 DGND VCC2 16 DGND Cout 15 Cout_ 14 IC8: 10H116 Cin 13 Cin_ 12 VBB 11 Bin 10 Bin_ 9 C5 0.1µ DGND Rn1 51 Rn1 51 Rn1 51 Rn1 51 Rn1 C10 0.1µ C13 0.1µ C14 0.1µ DGND 1 VCC1 2 Q2 3 Q3 IC5: 10H136 VCC2 16 Q1 15 Q0 14 CLK 13 D0 12 D1 11 Cin_ 10 S1 9 C37 0.1µ DGND R14 51 –2V (D) DGND C23 0.1µ 1 VCC2 VCC1 16 DGND Z 15 X7 14 X6 13 X5 12 X4 11 C 10 B9 C29 0.1µ –2V (D) DGND R18 C31 51 0.1µ 2 Aout_ 3 Aout C1 0.1µ CLK R3 51 4 Ain_ 5 Ain 4 Cout_ 5 D3 6 D2 7 S2 8 VEE –5.2V (D) 6 Bout_ DGND C2 0.1µ DGND 2 Enable_ DGND Rn2 3 X3 Rn2 51 4 X2 Rn2 51 5 X1 Rn2 51 6 X0 Rn2 51 C22 C21 0.1µ 0.1µ #11 7 Bout 8 VEE –5.2V (D) 7A 8 VEE IC7: 10H164 C30 0.1µ DGND SW3 Decimation DGND DGND DGND –2V (D) DGND DGND DGND –5.2V (D) DGND #12 #13 #14 – 16 – CXA1396D Rn6 Rn6 75 Rn6 75 Rn6 75 Rn6 75 –2V (D) CONNECTOR KEL: 8830E-020-170S (TOP VIEW) Rn12 Rn12 DGND 51 Rn12 51 Rn12 51 Rn12 51 Rn11 51 Rn11 51 Rn11 C52 0.1µ DGND –2V (D) 51 Rn11 51 Rn11 Rn10 1 D0 3 D1 2 DGND C53 0.1µ DGND C42 0.1µ DGND 1 DGND VCC1 Q0 Q1 Q2 D0 D1 D2 VEE VCC2 16 DGND Q5 15 Q4 14 Q3 13 D5 12 D4 11 D3 10 CLK 9 CLK P18 –2V (D) 1 VCC1 DGND VCC2 16 2 3 2 Aout_ Dout_ 15 3 Bout_ IC12: 10H101 Cout_ 14 Din 13 COM IN 12 Cout 11 Cin 10 Dout 9 Rn4 4 5 6 7 8 4 Ain 5 Aout 6 C41 0.1µ Bout #1 #2 #3 #4 Rn4 75 Rn4 75 Rn4 75 Rn4 75 C36 C26 0.1µ 0.1µ –2V (D) DGND DGND 7 Bin 8 VEE –5.2V (D) R19 51 –5.2V (D) –2V (D) Rn5 Rn5 75 Rn5 75 Rn5 75 Rn5 75 DGND 75 Rn10 75 Rn10 75 Rn10 75 Rn10 C51 0.1µ –2V (D) DGND 4 DGND 6 DGND 8 7 DGND D3 10 9 DGND D4 12 11 D5 DGND 13 14 D6 DGND 15 16 DGND D7 17 18 CLK DGND 19 20 DGND CLKN 5 D2 DIGITAL OUT IC10: 10H176 DGND 1 DGND VCC1 Q0 Q1 IC9: 10H176 Q2 D0 D1 D2 VEE VCC2 16 Q5 15 DGND Q4 14 Q3 13 D5 12 D4 11 D3 10 CLK 9 –2V (D) C40 0.1µ DGND DGND 1 VCC1 VCC2 16 P34 +5V (A) +5V (A) C57 33µ AGND P33 AGND AGND AGND P32 –5.2V (A) C56 33µ AGND P31 –5.2V (D) C55 33µ DGND P30 DGND DGND DGND P29 –2V (D) –2V (D) –5.2V (D) –5.2V (A) 2 3 4 2 Aout_ Dout_ 15 DGND 3 IC11: 10H101 Bout_ Cout_ 14 Din 13 COM 12 IN Cout 11 Cin 10 Dout 9 Rn3 4 Ain 5 Aout 6 C39 0.1µ Bout #5 #6 #7 #8 Rn3 75 Rn3 75 Rn3 75 Rn3 75 DGND C35 0.1µ –2V (D) DGND C24 0.1µ 5 6 7 8 7 Bin 8 VEE –5.2V (D) –5.2V (D) DGND #9 #10 C45 0.1µ DGND D7 P28 –2V (D) R22 C49 240 0.1µ C48 R21 0.1µ VR4 1k 2k D/A Full Scale IC14 TL431CP C54 33µ DGND Rn9 Rn9 75 Rn9 75 Rn9 75 Rn9 75 Rn8 75 Rn8 75 Rn8 75 Rn8 75 Rn8 1 MSB AGND2 28 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 LSB IC13: CX20202A-1 VREF 27 AVEE 26 NC 25 NC 24 NC 23 NC 22 NC 21 OUT 20 NC 19 AGND C50 33µ 1 VCC1 VCC2 16 Cout 15 Cout_ 14 IC8: 10H116 Cin 13 Cin_ 12 VBB 11 Bin 10 Bin_ 9 C37 0.1µ DGND R20 51 C38 0.1µ –2V (D) DGND DGND D6 P27 D5 P26 D4 P25 D3 P24 D2 P23 D1 P22 D0 P21 #11 DGND 2 3 Aout_ Aout –5.2V (A) 4 Ain_ 5 6 Ain Bout_ 7 Bout C34 0.1µ 8 VEE D/A OUT C44 0.1µ DGND –2V (D) Rn7 DGND –5.2V (D) 11 NC AGND1 18 AGND AGND #12 CLKN P20 51 Rn7 51 Rn7 51 Rn7 51 Rn7 –2V (D) DGND 12 NC 13 CLKN 14 CLK DGND 17 DGND INV 16 DVEE 15 C46 0.1µ #13 #14 CLK P19 SW4 D4 D/A INV L D5 C47 0.1µ D6 H R23 3.2k DGND C43 0.1µ DGND –5.2V (D) DGND DGND –5.2V (D) – 17 – CXA1396D Characteristic Graph Fig. 5. Gain vs. Input frequency 2 0 –2 (CLK = 125MHz) Gain [dB] –4 –6 –8 –10 10 Input frequency [MHz] 100 Fig. 6. SNR vs. Input frequency 50 45 40 (CLK = 125MHz) DIR. IN AMP. IN SNR [dB] 35 30 25 20 1 10 Input frequency [MHz] 100 Fig. 7. 2nd, 3rd harmonic distortion vs. Input frequency (CLK = 125MHz) –20 2nd DIR. IN 2nd AMP. IN 3rd DIR. IN 3rd AMP. IN 2nd, 3rd harmonic distortion [dB] –30 –40 –50 –60 –70 –80 1 10 Input frequency [MHz] 100 Measurement data Figs. 5, 6 and 7 show the characteristic graphs. DIR. IN is the characteristic where the signal is directry input to the ADC and AMP. IN is the characteristic where the signal is input to ADC through the amplifier. – 18 – CXA1396D Parts Layout – 19 – CXA1396D Printed Pattern 1st layer Component plane (Top View) 4th layer Solder plane (Top View) – 20 – CXA1396D 2nd layer GND plane (Top View) 3rd layer Power supply plane (Top View) – 21 – CXA1396D Package Outline Unit: mm 42PIN DIP (CERAMIC) 600mil 13.2 ± 0.2 42 22 15.24 ± 0.25 + 0.05 0.25 – 0.02 53.4 ± 0.5 0° to 15° 1 2.54 21 0.46 ± 0.1 1.0 ± 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-42C-01 ∗DIP042-C-0600-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 6.7g – 22 – 3.3 MIN 1.0 MIN 6.91 MIN 6.6 MIN