CXA3236N

CXA3235/3236N All Band TV Tuner IC with On-chip PLL Description The CXA3235/3236N is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. The PLL on this IC supports the I2C bus format. Features • Low noise figure • Low power consumption (5 V, 54 mA typ.) • On-chip tuning PLL (I2C bus format) • Selection of frequency steps 31.25 kHz, 50 kHz and 62.5 kHz • On-chip 4-output band switch Applications • TV tuners • VCR tuners • CATV tuners Structure Bipolar silicon monolithic IC 30 pin SSOP (Plastic) Absolute Maximum Ratings (Ta = 25 °C) • Supply voltage VCC1,VCC2 –0.3 to +5.5 VCC3 –0.3 to +10.0 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD 880 V V °C mW (when mounted on a substrate) Operating Conditions • Supply voltage VCC1, VCC2 VCC3 • Operating temperature Topr 4.75 to 5.30 4.75 to 9.45 –25 to +75 V V °C Note) Electrostatic discharge strength is weak, and care should be taken in handling this IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E97943A81-TE CXA3235/3236N Block Diagram and Pin Configuration 30 SCL SDA ADSW VCC3 1 2 3 4 5 6 Divider 14/15bit Band SW Driver Phase Detector Charge Pump LOCK Det 28 27 I2C BUS Receiver Shift Register Divider 1/512,640,1024 REF OSC 29 REFOSC FMT CPO CPE BVL BVH 26 LOCK BU 7 USW Prescaler 1/8 25 IF OUT VCC1 8 V.REG Bias 24 GND IF AMP 23 VCC2 MIXout1 9 Buffer 22 UHF OSC 21 20 19 UOSCB2 UOSCE2 UOSCE1 UOSCB1 MIXout2 10 GND1 11 MS 12 Buffer VHF MIX VHFin 13 18 Buffer UHFin1 14 UHFin2 15 UHF MIX VHF OSC VOSC2 17 GND 16 VOSC1 —2— CXA3235/3236N Pin Description Pin No. Symbol 22 100k 5k Equivalent circuit VCC2 Pin voltage (V) Description 1 SCL 1 — Clock input. 22 100k 5k VCC2 2 SDA 2 — Data I/O. 22 150k VCC2 3 ADSW 3 50k Address selection. This pin controls bits 2 and 1 of (when open) the address byte. 1.25 4 FMT 30 VCC3 20k 5 BVL 4 5 6 ON : VCC3 OFF : 0 6 BVH 7 4 : Output for FM TRAP. 5 : Power supply output for VL band. 6 : Power supply pin for VH band. 7 : Power supply output for UHF band. The pin corresponding to the selected band goes High. Analog circuit power supply. 7 8 BU VCC1 9 10 9 MIXout1 Mixer outputs. 10 MIXout2 11 GND1 — —3— — Analog circuit GND. CXA3235/3236N Pin No. Symbol Equivalent circuit Pin voltage (V) Description VCC2 12 MS 120k Pin used for selecting a frequency step mode. 1.5 Any of the five modes can be (when open) selected by applying an input voltage. 2.3 (VHF) 0 (UHF) 0 (VHF) 2.3 (UHF) 0 (VHF) 2.3 (UHF) 3 (VHF) 3.1 (UHF) 3.5 (VHF) 5.0 (UHF) — 3.2 (VHF) 2.9 (UHF) — (VHF) 2.4 (UHF) — (VHF) 2.4 (UHF) 3.2 (VHF) 2.9 (UHF) VHF input. The input format is unbalanced input. 50k 13 VHFin 13 12 14 UHFin1 14 15 3k 3k 15 UHFin2 UHF inputs. The input method can be selected from balanced input or unbalanced input. 18 16 VCC1 50 16 VOSC1 8 8p 3k 600 External resonance circuit connection for VHF oscillator. 18 VOSC2 3k 15p 17 GND GND 19 UOSCB1 19 20 21 22 VCC1 20 UOSCE1 3k External resonance circuit connection for UHF oscillator. 21 UOSCE2 3k 22 UOSCB2 —4— CXA3235/3236N Pin No. 23 24 Symbol VCC2 GND2 8 Equivalent circuit — — VCC1 Pin voltage Description (V) — PLL circuit power supply. — PLL circuit GND. 25 IFOUT 25 40 2.3 IF output. VCC2 40k 22 26 LOCK 26 5.0 (Lock) 0.2 (UNLock) LOCK detection. High when locked, Low when unlocked. VCC2 22 27 CPE 200 28 500 0.6 NPN transistor connection for varicap diode drive. 28 CPO 27 20k 2.0 Charge pump output. Connect a loop filter. 60k 30p 30p 29 REFOSC 29 4.3 Crystal connection for reference oscillator. 30 VCC3 — Power supply for external supply. —5— CXA3235/3236N Electrical Characteristics Circuit Current Item Circuit current A Symbol AICCV AICCU Circuit current D DICC See the Electrical Characteristics Measurement Circuit. (VCC=5 V, Ta=25 °C) Measurement conditions VCC1 current, Band switch output open during VHF operation VCC1 current, Band switch output open during UHF operation VCC2 current Min. 30 31 7 Typ. 41 42 11 Max. 55 56 15 Unit mA mA mA OSC/MIX/IF Amplifier Block Item Symbol Conversion gain ∗1 CG1 CG2 CG3 CG4 Noise figure ∗1, ∗2 NF1 NF2 NF3 NF4 1 % cross CM1 modulation ∗1, ∗3 CM2 CM3 CM4 Maximum output power Pomax ∆fsw1 ∆fsw2 ∆fsw3 ∆fsw4 Switch ON drift ∗4 Supply voltage drift ∆fst1 ∗4 ∆fst2 ∆fst3 ∆fst4 Measurement conditions VHF operation fRF = 55 MHz VHF operation fRF = 360 MHz UHF operation fRF = 360 MHz UHF operation fRF = 800 MHz VHF operation fRF = 55 MHz VHF operation fRF = 360 MHz UHF operation fRF = 360 MHz UHF operation fRF = 800 MHz VHF operation fD = 55 MHz, fUD = ±12 MHz VHF operation fD = 360 MHz, fUD = ±12 MHz UHF operation fD = 360 MHz, fUD = ±12 MHz UHF operation fD = 800 MHz, fUD = ±12 MHz 50 Ω load saturation output VHF operation fOSC = 100 MHz ∆f from 3 s to 3 min after switch ON VHF operation fOSC = 405 MHz ∆f from 3 s to 3 min after switch ON UHF operation fOSC = 405 MHz ∆f from 3 s to 3 min after switch ON UHF operation fOSC = 845 MHz ∆f from 3 s to 3 min after switch ON VHF operation fOSC = 100 MHz ∆f when VCC 5 V changes ±5 % VHF operation fOSC = 405 MHz ∆f when VCC 5 V changes ±5 % UHF operation fOSC = 405 MHz ∆f when VCC 5 V changes ±5 % UHF operation fOSC = 845 MHz ∆f when VCC 5 V changes ±5 % —6— Min. 21 22 26 27 Typ. 24 25 29 30 12 11 8.5 9.5 101 100 96 92 +10 Max. 27 28 32 33 15 14 12.5 13.5 Unit dB dB dB dB dB dB dB dB dBµ dBµ dBµ dBµ dBm 97 96 92 88 +5 ±300 ±400 ±400 ±500 ±150 ±250 ±200 ±250 kHz kHz kHz kHz kHz kHz kHz kHz CXA3235/3236N ∗1 Measured value for untuned inputs. ∗2 Noise figure is the direct-reading value of NF meter in DSB. ∗3 Desired signal (fD) input level is –30 dBm. Undesired signal (fUD) is 100 kHz, 30 % AM at ±12 MHz. The measurement value is undesired signal level, it measured with a spectrum analyzer at S/I=46 dB. ∗4 Value when the PLL is not operating. PLL Block Item Symbol SDA, SCL “H” level input voltage VIH “L” level input voltage VIL “H” level input current IIH “L” level input current IIL SDA “L” output voltage LSDA Clock input hysteresis CIHYS Clock rate CIRATE CPO (charge pump) Output current 1 ICPO1 Output current 2 ICPO2 LeakCP1 Leak current 1 LeakCP2 Leak current 2 REFOSC Oscillator FXTOSC frequency range CXTOSC Input capacitance VXTOSC Drive level BVL, BVH, BU (Band SW) IBS1 Output current VSAT1 Saturation voltage LeakBS1 Leak current FMT (Band SW) Output current Saturation voltage Leak current Bus timing SCL clock frequency Start waiting time Start hold time Low hold time High hold time Start setup time Data hold time Data setup time Rise time Fall time Start setup time Measurement conditions Min. 3 GND VIH = VCC VIL = GND Sink current = 3 mA 0.25 0 –1 0.4 Typ. Max. VCC 1.5 –0.1 –2 0.4 0.65 0.5 ±75 ±300 30 100 Unit V V µA µA V V MHz µA µA nA nA Byte4/Bit6 = 0 Byte4/Bit6 = 1 Byte4/Bit6 = 0 Byte4/Bit6 = 1 ±35 ±140 ±50 ±200 3 17.5 200 When ON When ON Sink current = 20 mA When OFF 19 400 12 20.5 MHz pF mVp-p mA mV µA mA mV µA kHz ns ns ns ns ns ns ns ns ns ns 100 0.5 –25 200 3 –7 150 0.1 400 IBS2 When ON VSAT2 When ON Sink current = 5 mA LeakBS2 When OFF fSCL tWSTA tHSTA tLOW tHIGH tSSTA tHDAT tSDAT tR tF tSSTO 0 1300 600 1300 600 600 1300 600 75 0.03 See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. See Timing Chart on Page 15. —7— 300 300 600 CXA3235/3236N Electrical Characteristics Measurement Circuit +30V 22k 8200p 1.2k 47k 0.047µ 33p +5V 47k 2SC2785 3.3µ 1n 2.5ø2.5t LOCK IF OUT 1T363 47k 56p 47k 56p 1n 8p 30 29 28 27 26 25 24 23 22 21 4p 20 8p 19 18 17 16 1p 1n 1T362 16p 0.5p 0.5p 7p 47k 3.2ø 5.5t 1n 47k 51 BVL 3.0ø 2.5t 1n 47k 51 BVH 0.5p 1T363 150p 47k 1T363 XTAL 4MHz 100p 47k UOSCB2 UOSCE1 VOSC2 GND2 LOCK VCC3 CPO REFOSC UOSCE2 UOSCB1 IFOUT VCC2 GND CPE CXA3235/3236N MIX out1 MIX out2 UHFin1 1 2 3 4 5 6 7 8 9 2k 10 11 12 13 14 15 1n 4.5t SCL SDA ADSW 56p FMT BVL BVH BU 100 56p 1n 4.5t 1n 1n UHFin2 1n UHF IN FMT BVH VCC1 BVL GND1 DA MS CL CE BU VHF IN 3.3µ +5V 1n —8— VHF in VOSC1 CXA3235/3236N Description of Functions The CXA3235/3236N is a terrestrial wave broadcast tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF, CATV and UHF band signals. In addition to the mixer, local oscillator and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillator frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal. 2. Local oscillator circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. 4. PLL circuit This PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of a prescaler, main divider, reference divider, phase comparator, charge pump and reference oscillator. The control format supports the I2C bus format. The following five modes can be selected according to the combination of the frequency division values of the main and reference dividers. Mode B-0 B-1 B-2 B-3 B-4 Main divider 15 bit 14 bit 15 bit 15 bit 15 bit Reference divider 1024 fixed 512 fixed 640 fixed 512 fixed 512/1024 switching —9— CXA3235/3236N Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.) VHF oscillator circuit • This circuit is a differential amplifier type oscillator circuit. Pin 18 is the output and Pin 16 is the input. Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 18 via coupled capacitance, inputting to Pin 16 with feedback capacitance, and applying positive feedback. • The amplifier between Pins 16 and 18 has an extremely high gain. Therefore, care should be taken to avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal oscillation. VHF mixer circuit • The mixer circuit employs a double balance mixer with little local oscillation signal leakage. The input format is base input type, with Pin 12 grounded and the RF signal input to Pin 13. • The RF signal is inserted from the oscillator, converted to IF frequency and output from Pins 9 and 10. • Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9 and 10 at this time must be DC 4.0 V or more. UHF oscillator circuit • This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap. Connect resonator capacitance composing colpitts oscillators between Pins 19 and 20, Pins 20 and 21, and Pins 21 and 22. • Then, LC resonance circuit comprising a varicap diode is connected across Pins 19 and 22. UHF mixer circuit • This circuit employs a double balance mixer like the VHF mixer circuit. The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input consisting of grounding Pin 14 via a capacitor and input to Pin 15. • Pins 9 and 10 are the mixer outputs. • Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9 and 10 at this time must be DC 4.0 V or more. IF amplifier circuit • The signals frequency converted by the mixer are output from Pins 9 and 10, and at the same time are AC coupled inside the IC and input to the IF amplifier. • Single-tuned filters are connected to Pins 9 and 10 in order to improve the interference characteristics of the IF amplifier. • The signal amplified by the IF amplifier is output from Pin 25. The output impedance is approximately 75 Ω. —10— CXA3235/3236N Description of PLL Block The PLL on this IC supports the I2C bus control format. The control pins are as shown in the table below. Symbol ADSW SCL SDA Description Address selection SCL input SDA I/O 1) Mode Setting Method The modes for each frequency step are set according to the MS pin voltage. Mode B-0 B-1 B-2 B-3 B-4 MS pin voltage 0 to 0.15 VCC OPEN 0.45 VCC to 0.55 VCC 0.65 VCC to 0.75 VCC 0.85 VCC to VCC Main divider 15 bit 14 bit 15 bit 15 bit 15 bit Reference divider 1024 512 640 512 512/ 640/ 1024 Reference frequency 3.90625 kHz 7.8125 kHz 6.25 kHz 7.8125 kHz 7.8125 kHz/ 6.25 kHz/ 3.90625 kHz Frequency step∗ 31.25 kHz 62.5 kHz 50 kHz 62.5 kHz 62.5 kHz/ 50 kHz/ 31.25 kHz ∗ Frequency step is for when X’tal OSC = 4 MHz. 2) Address Setting The responding address can be changed according to the ADSW pin voltage, so that multiple PLL can exist within one system. Address ADSW pin voltage 0 to 0.1 VCC OPEN or 0.2 VCC to 0.3 VCC 0.4 VCC to 0.6 VCC 0.9 VCC to VCC MA1 0 0 1 1 MA0 0 1 0 1 —11— CXA3235/3236N 3) Programming The VCO lock frequency is obtained according to the following formula. fosc = fref × 8 × (32 M + S) fosc : local oscillator frequency fref : reference frequency 8 : prescaler fixed frequency division ratio M : main divider frequency division ratio S : swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. 32 ≤ M ≤ 1023 (32 ≤ M ≤ 511 for B-1 mode) 0 ≤ S ≤ 31 3-1) The CXA3235N control format is as follows. 3-1-1 : B-0/B-1/B-2/B-3 Modes Slave Receiver MSB bit7 1 0 M2 1 X bit6 1 M9∗ M1 CP X bit5 0 M8 M0 T1 X bit4 0 M7 S4 CD X bit3 0 M6 S3 X BU bit2 MA1 M5 S2 X FMT bit1 MA0 M4 S1 X BVH LSB bit0 0 M3 S0 OS BVL Write-mode : MODE Address byte Divider byte 1 Divider byte 2 Control byte Band SW byte X : Don’t care ∗ M9 is “0” for B-1 mode. A A A A A 3-1-2 : B-4 Mode Slave Receiver MSB bit7 1 0 M2 1 X bit6 1 M9 M1 CP X bit5 0 M8 M0 T1 X bit4 0 M7 S4 CD X bit3 0 M6 S3 X BU bit2 MA1 M5 S2 R1 FMT bit1 MA0 M4 S1 R0 BVH LSB bit0 0 M3 S0 OS BVL Write-mode : MODE Address byte Divider byte 1 Divider byte 2 Control byte Band SW byte X : Don’t care A A A A A —12— CXA3235/3236N 3-2) The CXA3236N control format is as follows. The BU and FMT data order is switched for the CXA3235N. 3-2-1 : B-0/B-1/B-2/B-3 Modes : Slave Receiver MSB MODE bit7 Address byte 1 Divider byte 1 0 Divider byte 2 M2 Control byte 1 Band SW byte X Write-mode bit6 1 M9∗ M1 CP X bit5 0 M8 M0 T1 X bit4 0 M7 S4 CD X bit3 0 M6 S3 X FMT bit2 MA1 M5 S2 X BU bit1 MA0 M4 S1 X BVH LSB bit0 0 M3 S0 OS BVL A A A A A X : Don’t care ∗ M9 is “0” for B-1 mode. 3-2-2 : B-4 Mode : Slave Receiver MSB bit7 1 0 M2 1 X bit6 1 M9 M1 CP X bit5 0 M8 M0 T1 X bit4 0 M7 S4 CD X bit3 0 M6 S3 X FMT bit2 MA1 M5 S2 R1 BU bit1 MA0 M4 S1 R0 BVH LSB bit0 0 M3 S0 OS BVL Write-mode MODE Address byte Divider byte 1 Divider byte 2 Control byte Band SW byte X : Don’t care A MA0, MA1 M0 to S0 to T1 CD OS CP BVL BVH FMT BU R0, R1 : : : : : : : : : : : : : A A A A A Acknowledge bit address setting main divider frequency division ratio setting swallow counter frequency division ratio setting test mode selection (when “1”) charge pump OFF (when “1”) varicap output OFF (when “1”) charge pump current switching (200 µA when “1”, 50 µA when “0”) VL band switch control (output PNP Tr ON when “1”) VH band switch control (output PNP Tr ON when “1”) FM trap switch control (output PNP Tr ON when “1”) UHF band switch control (output PNP Tr ON when “1”) Reference divider frequency division ratio setting —13— CXA3235/3236N Reference Divider Frequency Division Ratio Table R1 0 1 X X : Don’t care 3-3) The read data format is as shown below. Read-mode : Slave Transmitter bit7 1 PR bit6 1 FL bit5 0 1 bit4 0 1 bit3 0 1 bit2 MA1 X bit1 MA0 X bit0 1 X A A R0 1 1 0 Reference divider 1024 512 640 MODE Address byte Status byte A PR FL MA0, MA1 : : : : acknowledge bit power-on reset lock detection signal address setting —14— CXA3235/3236N I2C Bus Timing Chart tWSTA SDA tSSTA tR tF tSSTO SCL tHSTA START tLOW tHIGH CLOCK tSDAT tHDAT STOP DATACHANGE tSSTA =Start setup time tWSTA =Start waiting time tHSTA =Start hold time tLOW =LOW clock pulse width tHIGH =HIGH clock pulse width tSDAT tHDAT tSSTO tR tF =Data setup time =Data hold time =Stop setup time =Rise time =Fall time —15— CXA3235/3236N Circuit current vs. Supply voltage 1 45 15 Circuit current vs. Supply voltage 2 AICC - Circuit current [mA] VHF DICC - Circuit current [mA] UHF 40 10 35 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 VCC1 - Supply voltage [V] Band SW output voltage vs. Output current (BU, BVH, BVL) 9.2 VCC2 - Supply voltage [V] Band SW output voltage vs. Output current (FMT) 9.2 9.0 VCC3=9V 9.0 VCC3=9V 8.8 8.8 Output voltage [V] Output voltage [V] VCC3=5V 8.6 8.6 5.0 5.0 VCC3=5V 4.8 4.8 4.6 4.6 4.4 0 5 10 15 20 25 4.4 0 1 2 3 4 5 6 Output current [mA] I/O characteristics (Untuned input) 20 Output current [mA] 0 IF output level [dBm] –20 fRF=100MHz (VHF) fRF=450MHz (UHF) fIF is both f=45MHz –40 –60 –60 –50 –40 –30 –20 –10 0 10 RF input level [dBm] —16— CXA3235/3236N CG - Conversion gain [dB] Conversion gain vs. Reception frequency (Untuned input) 40 fIF=45MHz 35 30 25 20 15 10 5 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] Next adjacent cross modulation vs. Reception frequency (Untuned input) 120 VHF (Low) VHF (High) UHF Noise figure vs. Reception frequency (Untuned input, in DSB) 20 fIF=45MHz NF - Noise figure [dB] 15 VHF (Low) VHF (High) 10 UHF 5 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] Oscillation frequency power supply fluctuation (PLL off) 400 300 200 VHF (High) VHF (Low) UHF VCC+5% VCC–5% (VCC=5V) CM - Cross modulation [dBµ] 100 +B drift [kHz] 80 60 40 20 0 fIF=45MHz fUD=fD+12MHz fUD=fD–12MHz (100kHz, 30% AM) 100 0 –100 –200 –300 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] –400 0 100 200 300 400 500 600 700 800 900 Oscillation frequency [MHz] PCS beat characteristics +20 +10 0 –10 fIF IF output level [dBm] –20 –30 –40 –50 fBeat –60 –70 –80 fLocal=129MHz fP=83.25MHz fC=86.83MHz, (fP–12dB) fS=87.75MHz, (fP–1.7dB) fIF=45.75MHz fBeat=fIF±920kHz –30 –20 –10 0 +10 +20 SG output level [dBm] (fP level) —17— CXA3235/3236N Tuning Response Time VHF (Low) 95MHz → VHF (High) 395MHz T=70ms 5.0V/div offset 10.0V –90,0000ms 10,0000ms 20.0ms/div 110,000ms UHF 413MHz → UHF 847MHz T=70ms 5.0V/div offset 10.0V –90,0000ms 10,0000ms 20.0ms/div 110,000ms —18— CXA3235/3236N IF output spectrum RL=0dBm 10dB/div VHF (Low) fRF=55MHz fLO=100MHz RF input level : –40dBm CENTER 45.0MHz RES BW 1.0kHz VBW 10Hz SPAN 100.0kHz SWP 30.0s IF output spectrum RL=0dBm 10dB/div VHF (High) fRF=350MHz fLO=395MHz RF input level : –40dBm CENTER 45.0MHz RES BW 1.0kHz VBW 10Hz SPAN 100.0kHz SWP 30.0s —19— CXA3235/3236N IF output spectrum RL=0dBm 10dB/div UHF (Low) fRF=800MHz fLO=845MHz RF input level : –40dBm CENTER 45.0MHz RES BW 1.0kHz VBW 10Hz SPAN 100.0kHz SWP 30.0s —20— CXA3235/3236N VHF Input Impedance j50 j25 j100 0 50 50MHz 1000p 12 13 VHFin S11 15 350MHz –j25 –j100 –j50 UHF Input Impedance j50 j25 j100 UHFin1 MS 0 14 50 1000p UHFin2 S11 350MHz –j25 800MHz –j100 –j50 —21— CXA3235/3236N IF output Impedance j50 j25 j100 0 50 45MHz –j25 –j100 –j50 —22— CXA3235/3236N Package Outline Unit : mm 30PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗9.7 ± 0.1 0.10 30 16 ∗5.6 ± 0.1 A 1 + 0.1 0.22 – 0.05 0.13 M 15 0.65 + 0.05 0.15 – 0.02 0.1 ± 0.1 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-30P-L01 SSOP030-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —23— 0.5 ± 0.2 7.6 ± 0.2