CXB1596AR

CXB1596AR 10-bit Transceiver Description The CXB1596AR is a transceiver IC with a built-in PLL for Fibre Channel and Gigabit Ethernet. For a receiver 1.0625/1.25Gbaud serial data is received and output as 10-bit parallel data; for a transmitter 10-bit parallel data is received and output as 1.0625/1.25Gbaud serial data. Features • Transmitter and receiver in a single chip • ANSI X3T11 Fibre Channel compatible (FC_0) at 1.0625Gbaud • IEEE802.3z Gigabit Ethernet compatible at 1.25Gbaud • Conforms to 10-bit interface specification • TTL/ECL compatible • PLL for clock generation and clock & data recovery • Byte synchronization detector (positive character of Comma) • Frequency autolock function • Low power consumption (620mW typ.) • 64-pin plastic LQFP package (10mm × 10mm) Applications • 1.0625Gbaud Fibre Channel Interface • 1.25Gbaud Gigabit Ethernet Interface • Work Station/Server/HDD Interface • High-speed data communications • Switched networks Structure Bipolar silicon monolithic IC 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage VCC –0.3 to +4 • TTL DC input voltage VI_T –0.5 to +5.5 • ECL DC input voltage VI_E VCC – 2 to VCC • ECL differential input voltage amplitude VIS_E –4 to +4 • TTL high level output current IOH_T –20 to 0 • TTL low level output current IOL_T 0 to 20 • ECL output current IO_E –30 to 0 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 880 V V V V mA mA mA °C mW Recommended Operating Conditions • Supply voltage VCC 3.135 to 3.465 V (3.3V Typ.) • PECL AC coupling differential output load resistance RL (to VCC –2V) 50 Ω (to VEE) 150 Ω • Ambient temperature Ta 0 to +70 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99212-PS CXB1596AR Block Diagram TX0 to 9 REFCLK 10 106.25MHz (125MHz) D Q 10 Parallel to Serial CONV. SDOUT SDOUT∗ TXPLL LPF_TX0 LPF_TX1 LCLK 106.25MHz (125MHz) TCLK 1.0625GHz (1.25GHz) Transmitter block Receiver block LBEN I SDIN SDIN∗ LCKREF∗ LPF_RX0 LPF_RX1 BYTSYNCEN O RXPLL RDATA RCLK 1.0625GHz (1.25GHz) Serial to Parallel CONV. and BYTE SYNC 10 RX0 to 9 BYTSYNC Frequencies in parentheses are for Gigabit Ethernet, other frequencies are for Fibre Channel. DIV (1/10) FCLK 106.25MHz (125MHz) RBC (1/2) RBC1 RBC0 Pin Configuration (Top View) BYTSYNC LPF_RX0 VCCT VEET VCCT RX1 RX2 RX0 VEET 32 VEET 31 RBC0 30 RBC1 29 VCCT 28 VCCG 27 LCKREF∗ 26 TEST∗ 25 VEEG 24 BYTSYNCEN 23 VCCG 22 REFCLK 21 VEEG 20 VCCG 19 LBEN 18 VCCP_TX 17 LPF_TX1 1 VEET 2 TX0 3 TX1 4 TX2 5 RDSELN 6 TX3 7 TX4 8 TX5 9 10 11 12 13 14 15 16 VCCG VEET VEEP_TX TX6 TX7 TX8 TX9 LPF_TX0 RX3 RX4 RX5 RX6 RX7 RX8 RX9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LPF_RX1 49 VCCP_RX 50 VEEP_RX 51 SDIN∗ 52 VCCE 53 SDIN 54 VCCG 55 VEEG 56 VCCG 57 VEEG 58 VCCG 59 VCCE 60 SDOUT∗ 61 SDOUT 62 VCCE 63 VEEE 64 –2– CXB1596AR Pin Description Pin No. Symbol Type Power supply Typical pin voltage 0V Equivalent circuit Description Negative power supply for TTL output. 1, 14, 32, 33, VEET 46 VCCG 2 to 4, 6 to 9, TX0 to TX9 11 to 13 TTL input TTL level TTL_IN Parallel data inputs. Input data is converted to serial data in order from TX0. VEEG VEET 5 RDSELN Test input TTL High level Test input. Set to TTL high level or leave open. Positive power supply for internal circuits. Negative power supply for TXPLL. VCCP LPF0 LPF1 10, 20, 23, 28, VCCG 55, 57, 59 15 VEEP_TX Power supply Power supply 3.3V 0V 16 17 LPF_TX0 LPF_TX1 External part connection pin — External loop filter connection for TX. VEEP 18 VCCP_TX Power supply 3.3V Positive power supply for TXPLL. VCCG 19 LBEN TTL input TTL level TTL_IN Loop back enable. When high, the TX serial output is serially input to the RX side inside the IC. When low, both transmit and receive are enabled. VEEG VEET –3– CXB1596AR Pin No. Symbol Type Power supply Typical pin voltage 0V Equivalent circuit Description Negative power supply for internal circuits. VCCG 21, 25, VEEG 56, 58 22 REFCLK TTL input TTL level TTL_IN External reference clock input. VEET VEEG VCCG 24 BYTSYNCEN TTL input TTL level TTL_IN Byte synchronization enable. When high, the Comma detection circuit is enabled to perform byte synchronization. VEEG VEET VCCG 26 TEST∗ Test input TTL High level TTL_IN Test input. Set to TTL high level or leave open. VEET VEEG VCCG 27 LCKREF∗ TTL input TTL level TTL_IN VEET VEEG Forced reference clock lock. When low, the PLL is forcibly locked to the external reference clock (REFCLK). Normally set to high: autolock mode. 29, 37, VCCT 42 Power supply 3.3V Positive power supply for TTL output. –4– CXB1596AR Pin No. Symbol Type Typical pin voltage Equivalent circuit Description VCCT 30 31 RBC1 RBC0 TTL output TTL level TTL_OUT Receive side byte clocks recovered from the serial data. RBC1 and RBC0 output clocks which are 180 degrees out of phase. VEET VCCT 34 to 36, RX0 to 38 to 41, RX9 43 to 45 TTL output TTL level TTL_OUT Parallel data outputs. Serial data is converted to parallel data in order starting from RX0 and ending with RX9. VEET VCCT 47 BYTSYNC TTL output TTL level TTL_OUT Byte synchronization detection signal. This pin outputs high for a 1 byte period when the Comma signal is detected. VEET VCCP LPF0 LPF1 48 49 LPF_RX0 LPF_RX1 External part connection pin — External loop filter connection for RX. VEEP 50 51 VCCP_RX VEEP_RX Power supply Power supply 3.3V 0V Positive power supply for RXPLL. Negative power supply for RXPLL. –5– CXB1596AR Pin No. Symbol Type Typical pin voltage Equivalent circuit Description VCCE VCCG 52 54 SDIN∗ SDIN INP ECL input PECL level INN VCCE –1.3V Serial data inputs. VEEE VEEG 53, 60, VCCE 63 Power supply 3.3V Positive power supply for ECL output. VCCE 61 62 SDOUT∗ SDOUT ECL output PECL level OUTP OUTN Serial data outputs. VEEE 64 VEEE Power supply 0V Negative power supply for ECL output. –6– CXB1596AR Electrical Characteristics DC Characteristics Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current TTL high level output voltage TTL low level output voltage ECL high level input voltage ECL low level input voltage ECL differential input voltage amplitude ECL differential output voltage amplitude Current consumption Power consumption Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T VIH_E VIL_E VIS_E∗1 VOS_E∗2 ICC PD AC coupling input, peak-to-peak Peak-to-peak Output pins open Output pins open VIN = VCC VIN = 0V IOH = –0.4mA IOL = 2mA VCC – 1.17 VCC – 1.81 200 1200 188 620 –400 2.2 0.5 VCC – 0.88 VCC – 1.48 2000 2000 255 870 Conditions (VCC = 3.135 to 3.465V, Ta = 0 to 70°C) Min. 2 0 Typ. Max. 5.5 0.8 20 Unit V V µA µA V V V V mV mV mA mW ∗1 ECL differential input voltage amplitude VCC SDIN VIH_E VIS_E = | VI1 | + | VI2 | VI1 VI2 VIL_E VEE = GND SDIN∗ ∗2 ECL differential output voltage amplitude VCC SDOUT VOH_E VOS_E = | Vo1 | + | Vo2 | Vo1 Vo2 VOL_E VEE = GND SDOUT∗ –7– CXB1596AR AC Characteristics Item TX TTL input rise time TX TTL input fall time REFCLK input rise time REFCLK input fall time TTL output rise time TTL output fall time ECL output rise time ECL output fall time Operating transfer rate REFCLK frequency REFCLK frequency tolerance TXPLL/RXPLL frequency pull-in time RXPLL bit synchronization time TX serial output jitter Random TX serial output jitter Deterministic Symbol Tir_Tx Tif_Tx Tir_REF Tif_REF Tor_T Tof_T Tor_E Tof_E Br F_REF Ftol_REF Tfa Tbs RJ DJ 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF 20 to 80%, CL = 2pF 80 to 20%, CL = 2pF Conditions (VCC = 3.135 to 3.465V, Ta = 0 to 70°C) Min. 0.7 0.7 0.7 0.7 Typ. Max. 4.8 4.8 2.4 2.4 3.5 3.5 400 400 1.052 105.2 –100 Loop damping capacitance = 0.01µF Loop damping capacitance = 0.01µF TX output data K28.7 TX output data ±K28.5 6.2 24 60 Unit ns ns ns ns ns ns ps ps 1.262 Gbps 126.2 MHz 100 500 2500 ppm µs bit ps ps –8– CXB1596AR Description of Operation 1. Transmitter block The input 10-bit parallel data (TX0 to TX9) is latched by the external reference clock (REFCLK), converted from parallel to serial (Parallel to Serial CONV.), and output as serial data (SDOUT/SDOUT∗). The TXPLL multiplies REFCLK by 10 times to generate TCLK, and then frequency-divides this by 1/10 to generate LCLK. Parallel/serial conversion uses these TCLK and LCLK as the clocks. [See P10 "Timing Charts 1) Transmitter block".] 2. Receiver block The RXPLL recovers RCLK from the input serial data (SDIN/SDIN∗), uses this RCLK to retime the serial data and outputs it as RDATA. The DIV (divider) frequency-divides RCLK by 1/10 to generate FCLK, and RDATA is converted from serial to parallel (Serial to Parallel CONV.) using these two clocks (RCLK and FCLK). At the same time the byte synchronization signal (Comma detect word) is detected during Serial to Parallel CONV., and 10-bit parallel data (RX0 to RX9) and the sync signal (BYTSYNC) are output. FCLK is initialized and the 10-bit parallel data is byte synchronized using this sync signal. RBC differentially outputs the clocks (RBC1 and RBC0) obtained by 1/20 frequency-dividing TCLK for loading the 10-bit parallel data. [See P11 "Timing Charts 2) Receiver block".] a. Input serial data amplitude detection The serial data input block has the amplitude detection and amplitude control circuits. When the differential amplitude of the input signal is 100mVp-p or less, the input signal is cut and the output is fixed to high level. All parallel output data (RX0 to RX9) are high. b. Frequency autolock If LCKREF∗ is set high while recovering RCLK with the RXPLL, autolock mode results. In autolock mode, RCLK is locked to 10 times REFCLK when the input serial data is no signal, or to the clock component of the serial data when serial data is input. When LCKREF∗ is set low, RCLK is forcibly locked to 10 times REFCLK. c. Byte synchronization When BYTSYNCEN is set high, Comma data within the input serial data is detected, and the detection signal and byte synchronized 10-bit parallel data are output. At this time RBC1 and RBC0 are also initialized and output. When BYTSYNCEN is set low, the 10-bit parallel data is output in the arbitrary order and the RBC1 and RBC0 edges also rise at the arbitrary position. d. Differential clock output (RBC1 and RBC0) RBC1 and RBC0 output at the positive phase when byte synchronization is synchronized properly and Comma data is detected one time or more. RBC1 and RBC0 are extended when byte synchronization is asynchronous and Comma data is detected one time. e. Loop back When LBEN is set high, the serial data is looped back internally. Set LBEN low to perform transmit and receive. –9– CXB1596AR Timing Charts 1) Transmitter block Item TX setup time TX hold time Latency time REFCLK input rise time REFCLK input fall time TX TTL input rise time TX TTL input fall time Symbol Ts_Tx Th_Tx TLAT_Tx Tir_REF Tif_REF Tir_Tx Tif_Tx 1.0625GHz 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V 2.0 to 0.8V 0.7 0.7 0.7 0.7 Conditions Min. 2.0 1.5 4.7 2.4 2.4 4.8 4.8 (VCC = 3.3V, Ta = 25°C) Typ. Max. Unit ns ns ns ns ns ns ns Tir_REF Tif_REF 2.0V REFCLK 1.4V 0.8V Ts_Tx Th_Tx Tir_Tx Tif_Tx 2.0V TX0 to TX9 DATA N DATA N + 1 0.8V TLAT_Tx SDOUT/∗ 9 TX0 1 2 3 4 5 6 7 8 9 TX0 1 2 3 4 5 6 7 8 9 TX0 DATA N – 1 DATA N – 10 – CXB1596AR 2) Receiver block Item RX setup time Symbol Ts_Rx Conditions 1.0625GHz 1.25GHz 1.0625GHz RX hold time Skew between RBC0 and RBC1 Latency time TTL output rise time TTL output fall time Th_Rx 1.25GHz Min. 3.0 2.5 1.5 1.0 8.91 (VCC = 3.3V, Ta = 25°C) Typ. Max. Unit ns ns ns ns 9.41 18.0 3.5 3.5 9.91 ns ns ns ns TSK_RBC 1.0625GHz TLAT_Rx Tor_T Tof_T 1.0625GHz 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF COMMA2 VALID DATA N SDIN COMMA1 RX0 to RX9 RX0 to RX9 RX0 to RX9 RX0 to RX9 RX0 to RX9 RX0 to TLAT_RX TLAT_RX 2.0V RBC0 HOLD 1.4V 0.8V Tsk_RBC Tor_T Tof_T 2.0V RBC1 HOLD 1.4V 0.8V TS_Rx Th_Rx 2.0V RX0 to RX9 COMMA1 VALID DATA N – 2 COMMA2 VALID DATA N VALID DATA N + 1 0.8V TS_RX Th_RX 2.0V BYTSYNC 0.8V – 11 – CXB1596AR Example of Representative Characteristics Random jitter 6.7ps (RMS) X: 50ps/div Y: 100mV/div 1.0625GHz mode a) TX random jitter (SDOUT) X: 200ps/div Y: 200mV/div 1.0625GHz mode b) TX eye pattern (SDOUT) – 12 – CXB1596AR Electrical Characteristics Measurement Circuit a) TX random jitter (K28.7 fixed) 0011111000 TX0 TX9 Digital oscilloscope 0.01µF SDOUT∗ LPF TX1 TX0 VCC = 3.3V VEE = GND 0.01µF 150Ω ZO = 50Ω TRIG SDOUT 106.25MHz Pulse pattern generator REFCLK Device under test b) TX eye pattern Parallel data 1.0625Gbps random data 0.01µF 100Ω RX0 to RX9 SDIN TX0 to TX9 SDOUT Digital oscilloscope Pulse pattern generator SDIN∗ ZO = 50Ω 106.25MHz Device under test SDOUT∗ ZO = 50Ω TX1 LBEN Low BYTSYNCEN RDSELN TEST∗ LCKREF∗ High TRIG REFCLK RX0 LPF TX0 RX1 VCC = 2.0V VEE = –1.3V 0.01µF 0.01µF – 13 – CXB1596AR Notes on Operation 1. External loop filters Connect 0.01µF capacitors as close to the two sets of external loop filter pins as possible. 16 17 48 49 0.01µF 0.01µF 2. Example of power supply circuit VCC VEE 0.1µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 VEET VCCT VCCT RX9 BYTSYNC LPF_RX0 VEET 49 LPF_RX1 VCC VEE 0.1µF 50 VCCP_RX 51 VEEP_RX 52 SDIN∗ 53 VCCE 0.1µF VEE 54 SDIN 55 VCCG 56 VEEG 57 VCCG 58 VEEG 59 VCCG 60 VCCE 3.3V 22µF GND VEE VCC 61 SDOUT∗ 62 SDOUT 63 VCCE 64 VEEE LPF_TX0 VEEP_TX RDSELN VCCG VEET 32 RBC0 31 RBC1 30 VCCT 29 VCCG 28 LCKREF∗ 27 TEST∗ 26 VEEG 25 BYTSYNCEN 24 VCCG 23 REFCLK 22 VEEG 21 VCCG 20 LBEN 19 VCCP_TX 18 LPF_TX1 17 VCC VEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC VEE 0.1µF 22µF is an electrolytic capacitor, and should be located as close to the power supply as possible. 0.1µF are ceramic capacitors, and should be located as close to the IC power supply pins as possible. 3. Serial data I/O VCC = 3.3V VEE = GND 0.01µF 150Ω 0.01µF 150Ω 150Ω ZO = 75Ω VCC = 3.3V VEE = GND – 14 – VEET TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 CXB1596AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 48 49 10.0 ± 0.1 33 32 A 64 1 0.5 16 0.13 M + 0.2 1.5 – 0.1 17 (0.22) + 0.08 0.18 – 0.03 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 15 – 0.5 ± 0.2 (11.0)