CXD1159AQ

CXD1159AQ Sync Signal Generator for Camera Description The CXD1159AQ is a sync signal generator for consumer video cameras. Features • Adapts to NTSC or PAL through mode switching • Low power consumption • Phase comparator and built-in inverter for active filter (Power supply according to inverter for filter) • Supports external synchronization Structure Silicon gate CMOS Application Video cameras Functions Generation of various sync signals Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS∗1 – 0.5 to +7.0 • Input voltage VI VSS∗1 – 0.5 to VDD + 0.5 • Output voltage VO VSS∗1 – 0.5 to VDD + 0.5 • Storage temperature Tstg –55 to +150 ∗1 VSS = 0V Recommended Operating Conditions • Supply voltage VDD 4.50 to 5.50 • Operating temperature Topr –20 to +75 32 pin QFP (Plastic) V V V °C V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01103-PS CXD1159AQ Block Diagram FSCI 22 FSCO 23 1/4 24 SC 1/5 1/227 PHASE COMPARATOR 17 COMP 16 PSEL 20 AOUT 19 AIN SUB-CARRIER CONTROL 1/4 13 SCOF CLKI CLKO 6 7 1/7 or 6 1/65 1/525 or 625 14 MODE H-DECODER V-DECODER TEST GENERATOR 27 TEST 5 EXT HR VR LR V-CONTROL RESET GENERATOR 2 3 4 OUTPUT CONTROL 15 VINT 28 12 18 21 29 30 31 32 1 8 11 25 26 24 WNDE 25 WND 26 TEST 27 VDD1 28 HDO 29 VDO 30 SYNC 31 BLKO 32 23 22 21 20 19 18 17 16 PSEL 15 VINT 14 MODE 13 SCOF 12 VSS1 11 LALT 10 NC 9 NC 1 2 3 4 5 6 7 BFO HR VR LR EXT CLKI CLKO –2– FLD COMP 8 FSCO AOUT Pin Configuration SC FSCI VDD2 VSS2 AIN WNDE SYNC BLKO WND VSS1 VSS2 HDO VDO BFO FLD LALT VDD1 VDD2 CXD1159AQ Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol BFO HR VR LR EXT CLKI CLKO FLD NC NC LALT VSS1 SCOF MODE VINT PSEL COMP VDD2 AIN AOUT VSS2 FSCI FSCO SC WNDE WND TEST VDD1 HDO VDO SYNC BLKO I/O O I I I I I O O — — O — I I I I O — I O — I O O I O I — O O O O Line alternate pulse GND Sub carrier suppress input L: OFF NTSC/PAL mode switching NTSC/PAL Initialize input Phase comparator polarity switch Phase comparator output Filter inverter +5V Filter inverter input Filter inverter output Filter inverter GND 4fsc clock input 4fsc clock output Sub carrier output WND output enable input (at L: Enable) Window output Test input (Normally "L") +5V Horizontal drive pulse Vertical drive pulse Composite sync pulse Composite blanking pulse Burst flag pulse H reset input V reset input LALT reset input Internal/External mode switching INT/EXT Clock input (NTSC: 14.31818MHz, PAL: 14.1875MHz) Clock output Field pulse Description –3– CXD1159AQ Electrical Characteristics DC Characteristics Item Supply current Output voltage I∗2 Output voltage II∗3 Input voltage Input leak current Input leak current∗4 ∗1 ∗2 ∗3 ∗4 VIH = VDD, VIL = VSS Output pins except "AOUT" "AOUT" pin Tri-state pin High level Low level High level Low level High level Low level Symbol IDD IDDS VOH VOL VOH VOL VIH VIL ILI ILZ VI = 0V to VDD –10 –10 Static state∗1 0 VDD – 0.8 VSS VDD/2 VSS 0.7VDD 0.3VDD 10 10 IOH = –2mA IOL = 4mA IOH = –1.5mA IOL = 1.5mA (VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C) Conditions Min. Typ. 4.5 0.1 VDD 0.4 VDD VDD/2 Max. Unit mA mA V V V V V V µA µA AC Characteristics Item Fall delay time Rise delay time Symbol Conditions VOL = 0.4V VOH = 2.4V Min. Typ. Max. 45 45 Unit ns ns tPDL tPDH CLKI 2.5V HDO tPDL 2.4V 0.4V tPDH I/O Capacitance Item Input pin Output pin Symbol CIN COUT Min. Typ. Max. 9 11 Unit pF pF Test Circuit 1MΩ VDD 18 0.1µF 1µF 19 600Ω 21 VI 1kHz VO 20 Test conditions: VDD = VI = 0V, fM = 1MHz Filter Amplifier Characteristics Voltage gain GV 25dB (Typ.) Gv = 20 log –4– VO VI CXD1159AQ Functions 1. Generation of various sync signals (See the Timing Chart.) Various sync signals are generated from clocks. • Clock frequencies NTSC: 910fH (14.31818MHz) PAL: 908fH (14.1875MHz) 4fsc (17.734475MHz) For the system clock NTSC: 910fH/7 PAL: 908fH/7 or 6 2. PAL PLL for 4fsc To the master clock of 908fH is matched a phase of 4fsc. The polarity of the phase comparator can be switched according to the type of external filter (passive or active). Filter Passive PSEL L Master (908fH) Fast Slow Fast Slow 4fsc Delay Fast Delay Fast COMP H L L H Active H 3. SC (Sub-Carrier) generation INT: Internal mode (EXT = L) EXT: External mode (EXT = H) Mode NTSC NTSC PAL INT or EXT INT EXT x SC 910fH/4 4fsc/4 4fsc/4 In either mode unused counters are stopped. When SC is not required, by setting SCOF to L all SC counters are stopped and SC is not output. 4. Initialization and Reset In INT mode the circuit is initialized with the fall of VINT. At that time, H, V and LALT resets are not accepted. In EXT mode, VINT is not accepted, whereas H, V and LALT resets are accepted. –5– CXD1159AQ • Initialize (VINT) When EXT = L, VINT fall is detected and operation is started as the circuit is initialized at the VD fall position just before field I. (Initialization is completed within 100ns after the fall is detected). NTSC VINT VD HD FLD Initialize point PAL VINT VD HD FLD Initialize point • H reset (HR) Reset is performed with the first fall. However reset is not done anymore unless there is a deviation of more than 2 clocks (0.98µs) to the subsequent edges. The minimum reset pulse width is 0.98µs. HD is reset 2.94 to 3.43µs in advance of HR input. more than 0.98µs HR HD 2.94 to 3.43µs • V reset (VR) VD is reset 3.5H in advance of VR input. The minimum reset pulse width is 32µs. • LALT reset (LR) LALT is reset in the same phase as LR reset. The minimum reset pulse width is 32µs. LR LALT –6– CXD1159AQ Timing Chart H (NTSC) 1/2H 6.36 HDO BLKO HSYNC (SYNC) EO (SYNC) VSYNC (SYNC) 2.45 BFO VD FLD WND ODD 28.36 17.6 (Unit: µs) EVEN 6.85 10.76 4.89 1.47 2.45 1.47 26.89 4.89 1H Timing Chart H (PAL) 1/2H 6.41 HDO BLKO HSYNC (SYNC) 1.48 EO (SYNC) VSYNC (SYNC) 2.47 BFO VD FLD ODD EVEN 6.91 10.70 4.93 2.47 1.48 27.07 4.93 1H LALT 28.55 WND 17.69 (Unit: µs) –7– CXD1159AQ Timing Chart V (NTSC) FIELD E HDO VDO SYNC BLKO BFO FLD WND 80H 121H 20H 9H FIELD O O: ODD E: EVEN FIELD O HDO 9H VDO SYNC BLKO BFO FLD FIELD E 20H 80.5H WND 121H Timing Chart V (PAL) FIELD I, III HDO VDO SYNC 25H BLKO BFO (III – IV) BFO (I – II) LALT (III – IV) LALT (I – II) FLD 97H WND 144H 7.5H FIELD II, IV FIELD II, IV HDO VDO SYNC FIELD I, III 7.5H 25H BLKO BFO (IV – I) BFO (II – III) LALT (IV – I) LALT (II – III) FLD 96.5H WND 144H –8– CXD1159AQ Application Circuit NTSC (Internal mode) PAL (Filter configuration 1, Internal mode) 1M 4fsc {17.73MHz} 1000p 100k 10k 0.01µ 1000p 100 68k 24 SC 23 FSCO 22 FSCI 21 VSS2 20 AOUT 19 AIN 18 VDD2 17 COMP 24 SC 23 FSCO 22 FSCI 21 VSS2 20 AOUT 19 AIN 18 VDD2 17 COMP 25 WNDE 26 WND 27 TEST 28 VDD1 29 HDO 30 VDO 31 SYNC PSEL 16 VINT 15 25 WNDE 26 WND 27 TEST 28 VDD1 29 HDO 30 VDO 31 SYNC PSEL 16 VINT 15 MODE 14 SCOF 13 VSS1 12 LALT 11 NC 10 CLKO MODE 14 SCOF 13 VSS1 12 LALT 11 NC 10 CLKO CLKI BFO CLKI BFO EXT EXT FLD HR VR LR 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 910fH {14.31818MHz} 908fH {14.1875MHz} PAL (Filter configuration 2, Internal mode) 2SC945 4fsc {17.73MHz} 1000p 100k 4.7k 1.5µ 10k 220k 10k 0.1µ 24 SC 23 FSCO 22 FSCI 21 VSS2 20 AOUT 19 AIN 18 VDD2 17 COMP 25 WNDE 26 WND 27 TEST 28 VDD1 29 HDO 30 VDO 31 SYNC PSEL 16 VINT 15 MODE 14 SCOF 13 VSS1 12 LALT 11 NC 10 CLKO CLKI BFO EXT 32 BLKO 1 2 3 4 5 6 7 FLD NC 9 HR VR LR 8 908fH {14.1875MHz} Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– FLD 32 BLKO NC 9 32 BLKO NC 9 HR VR LR 8 CXD1159AQ Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0.1 24 17 + 0.35 1.5 – 0.15 0.1 25 16 A 32 9 + 0.2 0.1 – 0.1 1 0.8 b 8 0.24 M + 0.15 b = 0.30 – 0.10 ( 0.30) 0˚ to 10˚ DETAIL A : SOLDER PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 P-QFP32-7x7-0.8 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 0.2g LEAD SPECIFICATIONS ITEM LEAD MATERIAL LEAD TREATMENT LEAD TREATMENT THICKNESS SPEC. ALLOY 42 Sn-Pb 10% 5-18µm (0.127) + 0.10 0.127 – 0.05 0.50 (8.0) – 10 – Sony Corporation