CXD2443Q
Timing Generator for LCD Panels
Description The CXD2443Q is a timing generator for the LCD panel LCX011 and LCX019 driver. This chip has a built-in serial interface circuit which allows various settings to be performed through external control from a microcomputer, etc. Features • Generates the LCD panel LCX011/LCX019 drive pulse • Supports NTSC/PAL (PAL supported by scanning line conversion of video signal to 525H or pulse eliminate.) • Supports WIDE mode (when driving the LCX011) • Supports HD mode (when driving the LCX011) • Supports up/down and/or right/left inversion • Supports 3-panel projectors • Generates timing signal of external sample-andhold circuit • Generates line inversion and field inversion signals • AC drive of LCD panels during no signal • Line double-speed display realized with a built-in double-speed controller (NTSC/PAL) (4:3 mode only) (Line memory µPD485505: NEC) Applications LCD projectors, etc. Structure Silicon CMOS IC 100 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C, VSS = 0V) • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +75
V °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96X31-PS
CXD2443Q
Block Diagram
CKO3 CKO2 CKSL CKO1
10 8 RPD1 9 HD PHASE COMPARATOR MASTER CLOCK PLL COUNTER HSYNC 13 H-SYNC DETECTOR DECODER 100 HDR 43 VSYNC 14 V-SYNC SEPARATOR HSTA 16 : 9 4:3 LOOP FILTER 86 95 7 PWM1 PWM2 PWM3 PEO1
CKI5
CKI3
TC2
5 83 97
98 99 92
91 89
CKI2
TC3
88 11
RPD2 87 RPD3 93 FPD1 6
CKI1
TC1
85 PEO2 94 PEO3
FPD2 84 FPD3 96
38 HCK1A 37 HCK2A
V-CONTROL COUNTER
36 ENB 35 VCK
V-POSITION COUNTER VST 34 FLDO 21 VWA 30 VWB 2 DECODER & V-TIMING PULSE GENERATOR
FIELD & LINE CONTROLLER
49 FRP 50 XFRP 31 PCG1 47 XCLP1 XCLP2
H-POSITION COUNTER DECODER & H-TIMING PULSE GENERATOR
48
46 PCG2 51 52 SH1A SH2A
PULSE ELIMINATOR SCTR 16 SCLK 17 SDAT 18 PRE 19 SERIAL I/F
55 SH3A 56 SH4A 57 SH5A 58 SH6A DOUBLE SCAN CONVERTER 59 SH7A 42 HSTB 41 HCK1B
H-SYNC DETECTOR
RPD4 76 FPD4 77 TC4 82 CLOCK2 LOOP FILTER DIRECT CLEAR PHASE COMPARATOR
39 HCK2B 61 SH1B 62 63 PLL COUNTER2 DECODER 64 SH2B SH3B SH4B
66 SH5B 67 68 SH6B SH7B
70 71 72 73
75
74
80
81
44 45 32
1
RSTW
CKO4
CKI4
RSTR
PEO4
TEST: 12, 20, 22, 23, 24, 25, 26, 27, 33, 60, 69 VDD: 3, 28, 53, 78 VSS: 4, 15, 29, 40, 54, 65, 79, 90
–2–
PWM4
XRGT
XCLR
WCK
DWN
RCK
RGT
CXD2443Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol XCLR VWB VDD VSS TC1 FPD1 PEO1 PWM1 RPD1 CKO1 CKI1 TEST2 HSYNC VSYNC VSS SCTR SCLK SDAT PRE I/O I O — — I/O O I/O O O I/O I I I I — I I I I System clear (Low: All clear) V window pulse B output Power supply GND FPD1 output pulse width adjustment (NTSC/PAL 4:3) Phase comparator 1 output (NTSC/PAL 4:3) Loop filter integrator 1 output (NTSC/PAL 4:3) Loop filter integrator 1 input (NTSC/PAL 4:3) Phase comparator 1 output (NTSC/PAL 4:3) Oscillation cell 1 output (NTSC/PAL 4:3) Oscillation cell 1 input (NTSC/PAL 4:3) Test (Not connected.) Horizontal sync signal input (Polarity set by serial data HPOL.) Vertical sync signal input (Polarity set by serial data VPOL.) GND Chip select input (serial transfer block) Serial clock input (serial transfer block) Serial data input (serial transfer block) Preset setting (Set to NTSC 4:3 mode when Low.) Test (Not connected.) Field discrimination signal output Test (Not connected.) Test (Not connected.) Test (Not connected.) Test (Not connected.) Test (Not connected.) Test (Connect to GND.) Power supply GND V window pulse A output PCG1 pulse output (positive polarity) Up/down inversion identification signal output (High: Down, Low: Up) Test (Not connected.) V start pulse output (positive polarity) V clock pulse output Description Input pin for open status H — — — — — — — — — — — — — — — — — H — — — — — — — — — — — — — — — —
TEST11 — FLDO TEST1 TEST3 TEST4 TEST5 TEST6 TEST7 VDD VSS VWA PCG1 DWN TEST8 VST VCK O — — — — — — — — O O O — O O
–3–
CXD2443Q
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Symbol ENB HCK2A HCK1A HCK2B VSS HCK1B HSTB HSTA RGT XRGT PCG2 XCLP1 XCLP2 FRP XFRP SH1A SH2A VDD VSS SH3A SH4A SH5A SH6A SH7A TEST9 SH1B SH2B SH3B SH4B VSS SH5B SH6B SH7B TEST10 RCK
I/O O O O O — O O O O O O O O O O O O — — O O O O O — O O O O — O O O — O
Description ENB pulse output (negative polarity) H clock 2A pulse output H clock 1A pulse output H clock 2B pulse output GND H clock 1B pulse output H start B pulse output (positive polarity) H start A pulse output (positive polarity) Right/left inversion identification signal output (High: Right, Low: Left) Right/left inversion identification signal output (Low: Left, High: Right) PCG2 pulse output (positive polarity) Pedestal clamp pulse 1 output (negative polarity) Pedestal clamp pulse 2 output (negative polarity) AC drive inversion timing output AC drive inversion timing output (reverse polarity of FRP) Sample-and-hold pulse 1A output (positive polarity) Sample-and-hold pulse 2A output (positive polarity) Power supply GND Sample-and-hold pulse 3A output (positive polarity) Sample-and-hold pulse 4A output (positive polarity) Sample-and-hold pulse 5A output (positive polarity) Sample-and-hold pulse 6A output (positive polarity) Sample-and-hold pulse 7A output (positive polarity) Test (Not connected.) Sample-and-hold pulse 1B output (positive polarity) Sample-and-hold pulse 2B output (positive polarity) Sample-and-hold pulse 3B output (positive polarity) Sample-and-hold pulse 4B output (positive polarity) GND Sample-and-hold pulse 5B output (positive polarity) Sample-and-hold pulse 6B output (positive polarity) Sample-and-hold pulse 7B output (positive polarity) Test (Not connected.) Read clock output (for line buffer)
Input pin for open status — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
–4–
CXD2443Q
Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol RSTR WCK RSTW CKO4 CKI4 RPD4 FPD4 VDD VSS PEO4 PWM4 TC4 TC2 FPD2 PEO2 PWM2 RPD2 CKO2 CKI2 VSS CKO3 CKI3 RPD3 PEO3 PWM3 FPD3 TC3 CKSL CKI5 HDR
I/O O O O I/O I O O — — I/O O I/O I/O O I/O O O I/O I — I/O I O I/O O O I/O I I O
Description Read reset output (for line buffer, negative polarity) Write clock output (for line buffer) Write reset output (for line buffer, negative polarity) Oscillation cell 4 output (line double-speed controller) Oscillation cell 4 input (line double-speed controller) Phase comparator 4 output (line double-speed controller) Phase comparator 4 output (line double-speed controller) Power supply GND Loop filter integrator 4 output (line double-speed controller) Loop filter integrator 4 input (line double-speed controller) FPD4 output pulse width adjustment (line double-speed controller) FPD2 output pulse width adjustment (NTSC/PAL 16:9) Phase comparator 2 output (NTSC/PAL 16:9) Loop filter integrator 2 output (NTSC/PAL 16:9) Loop filter integrator 2 input (NTSC/PAL 16:9) Phase comparator 2 output (NTSC/PAL 16:9) Oscillation cell 2 output (NTSC/PAL 16:9) Oscillation cell 2 input (NTSC/PAL 16:9) GND Oscillation cell 3 output (HD) Oscillation cell 3 input (HD) Phase comparator 3 output (HD) Loop filter integrator 3 output (HD) Loop filter integrator 3 input (HD) Phase comparator 3 output (HD) FPD3 output pulse width adjustment (HD) PLL system switching (High: Built-in PLL, Low: External PLL) External clock input (for external phase comparison) Phase comparator output (for external phase comparison)
Input pin for open status — — — — — — — — — — — — — — — — — — — — — — — — — — — H — — ∗ H: Pull up, L: Pull down
–5–
CXD2443Q
Electrical Characteristics 1. DC characteristics Item Supply voltage Symbol VDD Conditions Min. 4.5 Vss CMOS input 0.7VDD 0.3VDD 2.2 TTL Schmitt trigger input 0.4 0.8VDD CMOS Schmitt trigger input 0.6 IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –4mA IOL = 6mA IOH = –3mA IOL = 3mA IOH = –12mA IOL = 12mA ∗4 ∗6 ∗8 ∗10 ∗12 –10 –40 –40 –40 –100 VDD/2 VDD/2 10 –240 40 40 110 µA mA µA VDD/2 VDD/2 V VDD – 0.8 0.4 V VDD – 0.8 0.4 V RCK, WCK PEO1, PEO2, PEO3, PEO4, CKO4 CKO1, CKO2, CKO3 ∗5 ∗7 ∗9 ∗11 At a 30pF load∗13 VDD – 0.8 0.4 V ∗3 V ∗2 0.2VDD V TC1, TC2, TC3, TC4 0.8 V HSYNC, SCTR, VSYNC, SCLK, SDAT (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) Typ. 5.0 Max. 5.5 VDD Unit V V V ∗1 Applicable pins
Input, output voltages VI, Vo Input voltage 1 VIH VIL Vt+ Input voltage 2 Vt– Vt+ – Vt– Vt+ Input voltage 3 Vt– Vt+ – Vt– Output voltage 1 VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL II Input leak current IIL II Output leak current Current consumption IOZ IDD
Output voltage 2
Output voltage 3
Output voltage 4
Output voltage 5
∗1 XCLR, PRE, CKSL, CKI1, CKI2, CKI3, CKI4, CKI5, CKO1, CKO2, CKO3, CKO4, PWM1, PWM2, PWM3, PWM4, PEO1, PEO2, PEO3, PEO4 ∗2 HDR, ENB, PCG1, PCG2, XCLP1, XCLP2, VST, FRP, XFRP, VCK, DWN, FLDO, RGT, XRGT, VWA, VWB, RPD1, RPD2, RPD3, RPD4, FPD1, FPD2, FPD3, FPD4, TC1, TC2, TC3, TC4, RSTR, RSTW ∗3 HSTA, HCK1A, HCK2A, SH1A, SH2A, SH3A, SH4A, SH5A, SH6A, SH7A, HSTB, HCK1B, HCK2B, SH1B, SH2B, SH3B, SH4B, SH5B, SH6B, SH7B ∗4 Normal input pins (VIN = VSS or VDD) ∗5 HSYNC, VSYNC, SCLK, SDAT, SCTR, CKI5 ∗6 Pins with pull-up resistors (VIN = VSS) ∗7 PRE, XCLR, CKSL ∗8 Bidirectional pins (input status, VIN = VSS or VDD) ∗9 CKO1, CKO2, CKO3, CKO4, PEO1, PEO2, PEO3, PEO4, TC1, TC2, TC3, TC4 ∗10 At high impedance (VIN = VSS or VDD) ∗11 RPD1, RPD2, RPD3, RPD4, FPD1, FPD2, FPD3, FPD4 ∗12 fclk = 67MHz, VDD = 5.5V ∗13 HSTA, HSTB, HCK1A, HCK2A, HCK1B, HCK2B, SH1A, SH2A, SH3A, SH4A, SH5A, SH6A, SH7A, SH1B, SH2B, SH3B, SH4B, SH5B, SH6B, SH7B, VCK, ENB, FRP, PCG1, PCG2, XCLP1, XCLP2, RGT, DWN –6–
CXD2443Q
2. AC characteristics Item Symbol
(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C) Applicable pins CKI1 CKI2 Min. 21.3 16.0 15 28.2 15 20 20 –10 10 15 15 48 48 52 52 CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF % ns Typ. max. Conditions Unit
Clock input cycle
CKI3 CKI4 CKI5
Output rise time Output fall time Cross-point time difference Output rise delay time Output fall delay time HCK1 Duty HCK2 Duty ∗1 HCK1A, 2A HCK1B, 2B
tr tf
∆t
All outputs All outputs ∗1 All outputs All outputs HCK1A, HCK1B HCK2A, HCK2B
tpr tpf tH/(tH + tL) tL/(tH + tL)
3. Serial transfer AC characteristics Symbol Item
(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C) Min. 4T 2T 4T 2T 2T 2T 5T 5T T: Master clock cycle (ns) ns Typ. Max. Unit
ts0 ts1 th0 th1 tw1L tw1H tw2 tw3
SCTR setup time, activated by rise of SCLK SDAT setup time, activated by rise of SCLK SCTR hold time, activated by rise of SCLK SDAT hold time, activated by rise of SCLK SCLK pulse width SCLK pulse width
–7–
CXD2443Q
4. Timing definitions AC characteristics
CKI1, CKI2 CKI3, CKI4 100% tpr Output 10% 90% tr tf Output 90% tpf 10% VDD 0V VDD 0V VDD 0V
HCK1A HCK1B
50%
VDD 50% 0V VDD
HCK2A HCK2B
50% ∆t ∆t
50% 0V
HCK1A HCK1B
50% tH
50% tL
50%
Note) HCK2 is the reverse phase of HCK1.
Serial transfer AC characteristics
ts0 SCTR 50% tw1L SCLK 50% ts1 SDAT 50% D15 th1 D14 D9 ts1 D8 th1 D7 D0 tw1H tw2 50%
th0
tw3 50%
D15
Note) See "Serial transfer timing" on P. 17 for the timing relationship between D15 to D0 and each pulse.
–8–
LCX011 Dot Arrangement (1) (4:3 display) The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed. R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6.
ODD = 1626 dots EVEN = 1626 dots ODD = 200 dots EVEN = 200 dots (effective 23.7501mm) ODD = 1200 dots EVEN = 1199 dots ODD = 200 dots EVEN = 200 dots ODD = 13 dots EVEN = 13 dots
ODD = 13 dots EVEN = 14 dots
•••• 34 GATE SW •••• •••• GATE SW 234 GATE SW •••• GATE SW 267 GATE SW
DL1 GATE SW
DL2 GATE SW
1 GATE SW
2 GATE SW
••••
DR1 GATE SW
DR2 GATE SW
R1 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 B1 R1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R1 G1 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R1 G1
B1
R2
G2
B2 R1 R2 R2 G2 G1 B2 R1
G1 B1 G1
B1 R1 B1
R2
G2 G2 B2 R2 G2
B2 R1 R2 G1 B2 R1
G1 B1 G1
B1 R1 B1
R2
G2 G2 B2 R2 G2
B2 R2 B2
2 dots
G1 R2
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
G2 B2
1
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2
R2
G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1
B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1
R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1
G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2
R2
G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1
B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1
R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1
G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2
R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2
3
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
4
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
G1 R2
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
480 dots (effective 31.6701mm)
2 dots
–9–
R2 R2 R2 R2 R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
479
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
480
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
SID
PC
PCX
VDD
VSS
WD
WDX
JTN
CXD2443Q
JTP
LCX011 Dot Arrangement (2) (16:9 display) The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed. R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6.
ODD = 1626 dots EVEN = 1626 dots ODD = 1600 dots EVEN = 1599 dots (effective 31.6701mm) ODD = 13 dots EVEN = 13 dots
ODD = 13 dots EVEN = 14 dots
•••• 34 GATE SW •••• •••• GATE SW 234 GATE SW •••• GATE SW 267 GATE SW
DL1 GATE SW
DL2 GATE SW
1 GATE SW
2 GATE SW
••••
DR1 GATE SW
DR2 GATE SW
R1 R2 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 B1 G2 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 B2 B2 R2 G2 G2 B2 R2 B2 R2 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 R1 G1 R1 G1 R1 G1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 B1 G2 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 B2 B2 R2 G2 G2 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 B1 G1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 R1 B1 B1 R1 G1 G1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 G1 B1 B1 R1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 G1 G1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 R1 G1 B1 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G2 B2 R2 G1 B1 R1 G1 B1 R1 G2 B2 R2
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R2 G2
B2
R1
G1
B1
R1 G1
B1
R2
G2
B2 R1 R2 G2 G1 B2 R1
G1 B1 G1
B1 R1 B1
R2
G2 G2 B2 R2 G2
B2 R1 R2 G1 B2 R1
G1 B1 G1
B1 R1 B1
R2
G2 G2 B2 R2 G2
B2 R2 B2
2 dots
G1 G2 B2 R2
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
1
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
2
G2 B2 R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2
R2
G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1
B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1
R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1
G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2
R2
G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1 B2 R1 R2 G1
B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1
R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1
G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2 R2 G2 G2 B2
R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2
3
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
R1 G1
4
G2 B2 R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G1 G2 B2 R2
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
B1 R1
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
480 dots (effective 31.6701mm)
2 dots
– 10 –
G2 B2 R2 R2 G2 G2 B2 R2 B1 R1 G2 B2 R2 G2 B2 R2 R2 G2 G2 B2 R2 B1 R1
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
479
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
480
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G2 B2
R1
G1
B1
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
R2
G1
B1
R1 G2
B2
SID
PC
PCX
VDD
VSS
WD
WDX
JTN
CXD2443Q
JTP
LCX019 Dot Arrangement The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed. R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6.
ODD = 1200 dots EVEN = 1199 dots
DR1 GATE SW GATE SW
DR2 GATE SW
1 GATE SW
201 GATE SW
DL2 GATE SW
DR1 GATE SW
2 dots
R R G R R G B R G B R G B R G B R G G B B R R G G B R B G R B B G R G R B G B G R B G R B G R R B G R B G G R B G R B R B G R B G R B G R B G R B G R B G R B G R B B G R B G R B G R G R B G R B G R B G R B G R B G R B G R B B G R B G R B G R B G R G R B G R B G R B G R B G R B G R B G R B G R B G B G R B G R B G R B G G B R G B R R B G R B G R B G R G B G R B G R B G B R G R B G R B G G B R G B R G B R G R G B R G B R G B R G B B G R B G B R G B R G R B G G B R G B R B G G R G B R G B R G B R G B R G B R B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G G B R G B R R G B R B R G B R G B G B R G B R G R G B R G B B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G G B R G B R G B R R G B R G B R G B R B R G B R G B R G B G B R G B R G B R G R G B R G B R G B R G B B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B B R G B R G B R G B R G G B R G B R G B R G B R R G B R G B R G B R G B B R G B R G B R G B R G B G B R G B R G B R G B R G B B R G B R G B R G B R G B R G B R G B R G B B G G B R R G B R G B R G B G B R G B R G B R G B B G B G B G B G B R B R G B R R G B B R G R G B R
G
B
R
G
B
R
G
B
R
G
B
R B R B R B R B R B R B R B R B R B R B
G R G R G R G R G R G R G R G R G R G R
B G B G B G B G B G B G B G B G B G B G
R B R B R B R B R B R B R B R B R B R B
G
B
R
G
B
R
G
B
R
G
1
R
G
B
R
G
B
R
G
B
2
R
G
B
R
G
B
R
G
3
R
G
B
R
G
B
R
G
B
4R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
G
B
480 dots
2 dots
– 11 –
R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
479
R
G
B
R
G
B
R
G
B
480 R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
PSIG
CXD2443Q
PC
PCX
CXD2443Q
Input Signal Protocol 1. Horizontal sync signal • A double-speed HSYNC or standard HSYNC (or CSYNC) should be input for NTSC and PAL display modes. Double-speed HSYNC and standard HSYNC input switching is set by the serial data (SNSL). Note) The double-speed HSYNC should have a cycle and width 1/2 that of the standard HSYNC. • The signal obtained by cutting off only the bottom of the ternary SYNC should be input for HD display mode. • The input sync signal polarity is not fixed, and is set by the serial data (HPOL). • When using the built-in line double-speed controller, set serial data SNSL to Low. The built-in line doublespeed controller supports only the standard HSYNC (or CSYNC). 2. Vertical sync signal • A normal-speed VSYNC (or CSYNC) should be input for NTSC and PAL display modes. • A VSYNC that has been sync separated by SYNC SEP. should be input for HD display mode. • The input sync signal polarity is not fixed, and is set by the serial data (VPOL). • The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2443Q. (1) Double-speed NTSC
Double-speed HSYNC VSYNC Sync signal phase reference
(2) Double-speed PAL
Double-speed HSYNC VSYNC Sync signal phase reference
(3) NTSC (CSYNC input)
ODD FIELD CSYNC EVEN FIELD CSYNC Sync signal phase reference
(4) PAL (CSYNC input)
ODD FIELD CSYNC EVEN FIELD CSYNC Sync signal phase reference
(5) HD
ODD FIELD HSYNC VSYNC EVEN FIELD HSYNC VSYNC Sync signal phase reference Sync signal phase reference
– 12 –
CXD2443Q
Description of Operation Clock input The CXD2443Q supports two types of PLL circuits. PLL switching is performed by CKSL (Pin 98). (High: Built-in PLL, Low: External PLL) Note) The built-in line double-speed controller PLL is supported only by the built-in PLL. (1) Built-in PLL (CKI1, CKI2, CKI3, CKI4) A PLL circuit is comprised by the built-in phase comparator and an external VCO circuit. There are four clock inputs which support the following modes. CKI1: NTSC/PAL 4:3 CKI2: NTSC/PAL 16:9 CKI3: HD CKI4: For built-in line double-speed controller The PLL lock for this system is adjusted by setting the RPD and FPD transition points so that they fall at the center of the windows as shown in the diagram below. (See the Application Circuit.)
a HSYNC RPD b FPD 800ns b Output waveform during PLL lock a
(2) External PLL (CKI5) The CKI5 pin is the clock input pin when using an external PLL IC. The 1/N frequency divider output is output from the HDR pin (frequency division ratio N/2) for the PLL IC. Set CKSL (Pin 98) to Low to switch to the external PLL.
N fH HSYNC HDR N/2 fH
AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. • Horizontal direction pulse The PLL is set to free running status. The frequency of the horizontal direction pulse at this time is dependent on the PLL free running frequency. • Vertical direction pulse The number of lines is counted by an internal counter and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD2443Q, no signal (free running) status is judged if there is no VSYNC input for longer than the following (free running detection) periods. Mode NTSC PAL HD V cycle for no signal Free running detection 544H (272H) 640H (320H) 576H 1024H (512H)
Note) Numbers in parentheses are for when using the built-in line double-speed controller. – 13 –
CXD2443Q
Right/left and/or up/down inversion In delta arrangement LCD panels, the same signal lines are separated by 1.5 dots for each horizontal line. Therefore, a 1.5 dot offset is added between lines to the LCD's horizontal direction start pulses HST and HCK and sample-and-hold pulse (SH). When driving an LCD panel with right and left inversed, the dot arrangement is asymmetrical so an offset is attached to HST, HCK and SH. When driving with up and down inversed, the relationship between the panel's odd and even line offsets is reversed.
Right scan H SCANNER Down scan
Left scan
V SCANNER
Effective display area
Up scan
1.5fH 1.5fH
MCK
HST
Down scan, odd line Up scan, even line Right and down scan, even line Right and up scan, odd line Left and down scan, even line Left and up scan, odd line
– 14 –
CXD2443Q
When using three LCD panels B outputs (HSTB, HCK1B, HCK2B, SH1B to 7B) are provided for driving three LCD panels with and without right/left inversion at the same time. These B outputs are the right/left inversed timings of the A outputs (HSTA, HCK1A, HCK2A, SH1A to 7A). XRGT (RGT inversed output) is also provided for right/left inversion scanning. Application circuit (driving three LCD panels)
TG
SH1A 51 SH2A 52 SH3A 55 SH4A 56 SIGNAL DRIVER Panel 1 (right scan)
Right scan (A outputs)
SH5A 57 SH6A 58 SH7A 59 HSTA 43 HCK1A 38 HCK2A 37 RGT 44 SH1B 61 SH2B 62 SH3B 63 SH4B 64 SIGNAL DRIVER Panel 3 (left scan) Panel 2 (right scan) SIGNAL DRIVER
Left scan (B outputs)
SH5B 66 SH6B 67 SH7B 68 HSTB 42 HCK1B 41 HCK2B 39 XRGT 45 DWN 32 ENB 36
Common
VCK 35 PCG1 31 or PCG2 46 VST 34
Note) All three panels face the same direction.
– 15 –
CXD2443Q
Built-in line double-speed controller This controller is designed to use the µPD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates the double-speed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK (read clock). Operation is as follows. Write operation is started at the RSTW timing, and this memory information is read twice at double speed at the RSTR timing which is delayed by 1/2H and 1H from the RSTW timing. The write and read clock frequencies at this time are generated by the built-in PLL (CKI4). See the specifications for a detailed description of µPD485505 operation.
R, G, B IN
ADC
LINE Mem. µPD485505 RSTW WCK RSTR RCK CXD2443Q MCK : f Double-speed display system block
DAC
HSYNC VSYNC CSYNC
HSYNC RSTW WCK RSTR RCK f f/2
HSYNC
RSTW
RSTR Double-speed display timing
Note) See the timing charts for details.
– 16 –
CXD2443Q
XCLR pin The CXD2443Q should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. Serial transfer operation 1. Control method The CXD2443Q operation timing is controlled by serial data. The control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise of SCLK. This fetching operation starts from the fall of SCTR and is completed at the next rise of SCTR. Serial transfer timing
SCTR
SCLK
SDAT
D15 D14 D13
D12 D11 D10 Address
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data
2. Control data When using the CXD2443Q, set the control data corresponding to each signal source according to the formats in the table below. Address D15 D14D13 D12 D11D10 D9 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 D7 HP8 — — — — — D6 HP7 — — — — — D5 HP6 — — — — — Data D4 HP5 — — — — — D3 HP4 VP4 D2 HP3 VP3 D1 HP2 VP2 D0 HP1 VP1 Function (A) H-POSITION (B) V-POSITION
SLSH4 SLSH3 SLSH2 SLSH1 (C) SH-POSITION — — — — — — CP2 CP1 (D) XCLP-POSITION
PCGW2 PCGW1 (E) PCG-POSITION VM9J VM8J
0 VM7J VM6J VM5J VM4J VM3J VM2J VM1J VM0J (F) VWA-POSITION (VWA pulse) 1 — — — — — VM9K VM8K — 0 VM7K VM6K VM5K VM4K VM3K VM2K VM1K VM0K 1 0 1 0 1 0 — — — — — — — — — — — — — — — — — — — — — — — — TEST1 SLBA MA TEST2 (G) Double-speed setting (H) Double-speed PAL pulse eliminate (I) Right/left and/or up/down inversion (J) Various settings
DWN RGT
TEST4 TEST3 SL3B VPOL HPOL SLFR — — — — — — SLVWB SLEG
SNSL XHD XWID NT-PAL (K) Mode settings
Note) 1. Set "High" as the TEST1, TEST2, TEST3 and TEST4 data. 2. "—" indicates not set. – 17 –
CXD2443Q
Serial settings during power on The CXD2443Q should be forcibly reset during power on using the XCLR pin. After being forcibly reset, the master clock for the CXD2443Q is supplied from CKI3. The initial serial data after power on is loaded to the CXD2443Q using the clock from CKI3. Serial settings during PLL free running When the PLL is in free running status, the serial clock cycle (F ns) may be less than F ≥ 2T with respect to the master clock cycle (T ns). Take care that the serial clock cycle setting is such that F ≥ 2T during PLL free running. Each control data is described in detail below. (A) H-POSITION (HP1, HP2, HP3, HP4, HP5, HP6, HP7, HP8) These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of up to ±128 dots is possible with respect to the design center value. (data: 8 bits) Design center value HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8 L L L L L L L H
MODE NTSC (4:3) NTSC (16:9) PAL (4:3) PAL (16:9) HD (B) V-POSITION (VP1, VP2, VP3, VP4)
Variable time (±128fH) ±2.8µs ±2.1µs ±2.7µs ±2.0µs ±1.9µs
These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of up to ±8H is possible with respect to the design center value. (data: 4 bits) Design center value VP1 VP2 VP3 VP4 L L L H
– 18 –
CXD2443Q
(C) SH-POSITION (SLSH1, SLSH2, SLSH3, SLSH4) These bits control the phase relationship between HCK1, HCK2 and SH1, 2, 3, 4, 5, 6 and 7. The minimum adjustment width is 0.5 dots, and adjustment of up to 6 dots is possible. (data: 4 bits) RGT = High: A output RGT = Low: B output
SLSH1, 2, 3, 4 HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7
LLLL (0)
HLLL (1)
LHLL (2)
HHLL (3)
LLHL (4)
HLHL (5)
LHHL (6)
RGT = Low: A output RGT = High: B output
HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7
– 19 –
CXD2443Q
RGT = High: A output RGT = Low: B output
SLSH1, 2, 3, 4 HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7
HHHL (7)
LLLH (8)
HLLH (9)
LHLH (A)
HHLH (B) ∗∗HH (C, D, E, F)
RGT = Low: A output RGT = High: B output
HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7
– 20 –
CXD2443Q
(D) XCLP-POSITION (CP1, CP2) These bits control the phase relationship between pedestal clamp pulses XCLP1 and XCLP2 and HSYNC. The phase can be adjusted in 400ns units to four levels. (data: 2 bits)
–250ns 150ns –650ns 0 550ns 950ns 1350ns 1750ns 2150ns 2550ns
HSYNC
XCLP1 CP1 = H, CP2 = H
CP1 = L, CP2 = H (design center value) CP1 = H, CP2 = L
CP1 = L, CP2 = L XCLP2 CP1 = H, CP2 = H CP1 = L, CP2 = H (design center value) CP1 = H, CP2 = L
CP1 = L, CP2 = L
(E) PCG-POSITION (PCGW1, PCGW2) These bits control the PCG1 pulse width (falling edge). The width can be adjusted in 200ns units to four levels. (data: 2 bits)
1.4µs Fixed 1.2µs 1.6µs 1.8µs
PCG pulse
PCGW1, 2 =
LL
HL
LH
HH
– 21 –
CXD2443Q
(F) VWA-POSITION (VM0J, VM1J, VM2J, VM3J, VM4J, VM5J, VM6J, VM7J, VM8J, VM9J, VM0K, VM1K, VM2K, VM3K, VM4K, VM5K, VM6K, VM7K, VM8K, VM9K) The VWA pulse rise and fall can be varied in 1H units in the vertical direction. Rise position: VW0J to 9J (10 bits) Fall position: VW0K to 9K (10 bits) Rise, fall transition points: ENB pulse fall position Reference (0): 1.5H before the VST output position
Reference (0) Double-speed HSYNC
VST
(G) Double-speed setting (SLBA) • This bit sets the built-in line double-speed controller. SLBA High: Line double-speed controller off Low: Line double-speed controller on • The loop counter is an N multiple of the following. NTSC PAL 910fH 1135fH Notes on operation The built-in line double-speed controller is supported only when driving a single LCD panel in NTSC/PAL 4:3 mode. When using the CXD2443Q in other modes (NTSC/PAL 16:9 mode, HD mode, 3-panel mode), be sure to set the line double-speed controller to off (SLBA = High).
– 22 –
CXD2443Q
(H) Double-speed PAL pulse eliminate (MA) This bit sets the double-speed PAL pulse eliminate (conversion from 575 to 480 vertical lines by 6, 7 pulse eliminate). The setting is as follows. MA High: Pulse eliminate off Low: Pulse eliminate on The 2N + 1 field pulse eliminate position is shifted 1H (line) to the rear with respect to the 2N field pulse eliminate position. (I) Right/left and/or up/down inversion (RGT, DWN) These bits switch the right/left inversion and/or up/down inversion timing for the LCD panel. Setting RGT H L H L DWN H H L L A outputs Right scan, down scan Left scan, down scan Right scan, up scan Left scan, up scan Output B outputs Left scan, down scan Right scan, down scan Left scan, up scan Right scan, up scan RGT H L H L XRGT L H L H DWN H H L L
Note) The B outputs (HSTB, HCKnB, SHnB) are the outputs for 3-panel projectors, and are output at the right/left inversed timing of the A outputs. (J) Various settings SLFR This bit sets the cycle of the LCD AC drive signals FRP and XFRP. High: 1H (line) inversion Low: 1F (field) inversion VPOL, HPOL These bits set the input SYNC polarity. High: Negative polarity Low: Positive polarity
– 23 –
CXD2443Q
SL3B This bit sets the 3-panel projector output (B outputs) switching. The HSTB, HCKnB, and SHnB outputs can be switched on and off. High: B outputs off Low: B outputs on Note) When driving a single LCD panel, set the B outputs to off (SL3B = High). SLVWB This bit sets the VWB output. High: VWB off Low: VWB on SLEG This bit sets the VWB transition timing. High: HSYNC front edge Low: HSYNC rear edge Note) VWB is the equalizing pulse masking pulse. The rise position is counted from the VD inside the previous field. Therefore, when the number of lines within one field differs from the standard protocol, the phase between the next field's VSYNC and the VWB rise position changes. The phase also changes when a value other than the default value is used as the V-POSITION setting. (K) Mode settings SNSL This bit sets the double-speed HSYNC and standard HSYNC (or CSYNC) input switching. High: Double-speed HSYNC input Low: Standard HSYNC (CSYNC) input Note) When using the built-in line double-speed controller, only the standard HSYNC is supported. Set SNSL to standard HSYNC input (SNSL = Low). NT-PAL, XWID, HD These bits set the various display modes. NT-PAL H H L L ∗ XWID H L H L ∗ XHD H H H H L
NTSC (4:3) NTSC (16:9) PAL (4:3) PAL (16:9) HD
Note) Test mode Serial data TEST1, TEST2, TEST3 and TEST4 are test mode data. Care should be taken as these bits are not used, and must be set to High.
– 24 –
NTSC (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: H XHD: H Loop counter 1464fH Master Clock 46.07MHz
280 300 320 340 360 380 60 80 100 120 140 160 180 200 220 240 260
1444
0
20
40
MCK
HSYNC
2.35µs (108fH)
XCLP1 0.55µs (26fH) 0.15µs (7fH) 4.38µs (202fH) 12fH 6fH 2.0µs (92fH)
1.2µs (55fH)
XCLP2
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 25 –
0.4µs (18fH) 1.2µs (55fH) 1.8µs (83fH) 0.3µs (14fH) 2.1µs (97fH) ODD LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
FRP
PCG1
1.0µs (46fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
NTSC (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: H XHD: H Loop counter 1464fH Master Clock 46.07MHz
200 220 240 260 280 300 320 340 360 380 80 100 120 140 160 180
1444
0
20
40
60
MCK
HSYNC
2.35µs (108fH)
HSTA 4.38µs (202fH) 6fH 12fH
4.38µs (202fH) 12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 26 –
ODD LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B CXD2443Q
SH7B
NTSC (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: H XHD: H Loop counter 1464fH Master Clock 46.07MHz
280 300 320 340 360 380 60 80 100 120 140 160 180 200 220 240 260
1444
0
20
40
MCK
HSYNC
2.35µs (108fH)
XCLP1 0.55µs (26fH) 0.15µs (7fH) 4.35µs (200.5fH) 6fH 12fH 2.0µs (92fH)
1.2µs (55fH)
XCLP2
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 27 –
0.4µs (18fH) 1.16µs (53.5fH) 1.8µs (83fH) 0.3µs (14fH) 2.1µs (97fH) EVEN LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
FRP
PCG1
1.0µs (46fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
NTSC (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: H XHD: H Loop counter 1464fH Master Clock 46.07MHz
200 220 240 260 280 300 320 340 360 380 80 100 120 140 160 180
1444
0
20
40
60
MCK
HSYNC
2.35µs (108fH)
HSTA 4.42µs (203.5fH) 12fH 6fH
4.35µs (200.5fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 28 –
EVEN LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B CXD2443Q
SH7B
Loop counter 1500fH Master Clock 46.88MHz
280 300 320 340 360 380
PAL (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: H XHD: H
60 80 100 120 140 160 180 200 220 240 260
1480
0
20
40
MCK
HSYNC
2.35µs (110fH)
XCLP1 0.55µs (25fH) 0.15µs (7fH) 6fH 12fH 2.0µs (93fH)
1.2µs (57fH)
XCLP2
HSTA
4.99µs (234fH)
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 29 –
0.4µs (19fH) 1.2µs (57fH) 1.8µs (84fH) 2.1µs (98fH) 0.3µs (14fH) ODD LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
FRP
PCG1
1.0µs (47fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
PAL (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: H XHD: H Loop counter 1500fH Master Clock 46.88MHz
200 220 240 260 280 300 320 340 360 380 80 100 120 140 160 180
1480
0
20
40
60
MCK
HSYNC
2.35µs (110fH)
HSTA 4.99µs (234fH) 6fH 12fH
4.99µs (234fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 30 –
ODD LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B CXD2443Q
SH7B
PAL (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: H XHD: H Loop counter 1500fH Master Clock 46.88MHz
280 300 320 340 360 380 60 80 100 120 140 160 180 200 220 240 260
1480
0
20
40
MCK
HSYNC
2.35µs (110fH)
XCLP1 0.55µs (25fH) 0.15µs (7fH) 6fH 12fH 2.0µs (93fH)
1.2µs (57fH)
XCLP2
HSTA
4.96µs (232.5fH)
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 31 –
0.4µs (19fH) 1.18µs (55.5fH) 1.8µs (84fH) 2.1µs (98fH) 0.3µs (14fH) EVEN LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
FRP
PCG1
1.0µs (47fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
PAL (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: H XHD: H Loop counter 1500fH Master Clock 46.88MHz
200 220 240 260 280 300 320 340 360 380 80 100 120 140 160 180
1480
0
20
40
60
MCK
HSYNC
2.35µs (110fH)
HSTA 5.02µs (235.5fH) 12fH 6fH
4.96µs (232.5fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 32 –
EVEN LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B CXD2443Q
SH7B
NTSC (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: L XHD: H Loop counter 1952fH Master Clock 61.43MHz
280 300 320 340 360 380 60 80 100 120 140 160 180 200 220 240 260
1932
0
20
40
MCK
HSYNC
2.35µs (144fH)
XCLP1 0.55µs (34fH) 2.0µs (123fH) 6fH 12fH 0.15µs (9fH) 4.54µs (279fH)
1.2µs (74fH)
XCLP2
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 33 –
0.4µs (25fH) 1.2µs (74fH) 1.8µs (111fH) 2.1µs (129fH) 0.3µs (18fH) ODD LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
FRP
PCG1
1.0µs (61fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
NTSC (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: L XHD: H Loop counter 1952fH Master Clock 61.43MHz
200 220 240 260 280 300 320 340 360 380 80 100 120 140 160 180
1932
0
20
40
60
MCK
HSYNC
2.35µs (144fH)
HSTA 4.54µs (279fH) 6fH 12fH
4.54µs (279fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 34 –
ODD LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B
SH7B CXD2443Q
NTSC (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: L XHD: H Loop counter 1952fH Master Clock 61.43MHz
280 300 320 340 360 380 60 80 100 120 140 160 180 200 220 240 260
1932
0
20
40
MCK 2.35µs (144fH)
HSYNC
XCLP1 0.55µs (34fH) 0.15µs (9fH) 4.52µs (277.5fH) 12fH 6fH 2.0µs (123fH)
1.2µs (74fH)
XCLP2
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 35 –
0.4µs (25fH) 1.18µs (72.5fH) 1.8µs (111fH) 2.1µs (129fH) 0.3µs (18fH) EVEN LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
FRP
PCG1
1.0µs (61fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
NTSC (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: L XHD: H Loop counter 1952fH Master Clock 61.43MHz
200 220 240 260 280 300 320 340 360 380 80 100 120 140 160 180
1932
0
20
40
60
MCK
HSYNC
2.35µs (144fH)
HSTA 4.57µs (280.5fH) 6fH 12fH
4.52µs (277.5fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 36 –
EVEN LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B
SH7B CXD2443Q
PAL (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: L XHD: H Loop counter 2000fH Master Clock 62.5MHz
280 300 320 340 360 380 60 2.35µs (147fH) 80 100 120 140 160 180 200 220 240 260
1980
0
20
40
MCK
HSYNC
XCLP1 0.55µs (35fH) 0.15µs (10fH) 5.17µs (323fH) 6fH 2.0µs (125fH) 12fH
1.2µs (75fH)
XCLP2
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 37 –
0.4µs (25fH) 1.0µs (63fH) 1.8µs (112fH) 2.1µs (131fH) ODD LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
1.2µs (75fH)
FRP 0.3µs (19fH)
PCG1
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
Loop counter 2000fH Master Clock 62.5MHz
200 220 240 260 280 300 320 340 360 380
PAL (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: L XHD: H
80 100 120 140 160 180
1980
0
20
40
60
MCK
HSYNC
2.35µs (147fH)
HSTA 5.17µs (323fH) 6fH 12fH
5.17µs (323fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 38 –
ODD LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B
SH7B CXD2443Q
PAL (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: L XHD: H Loop counter 2000fH Master Clock 62.5MHz
280 300 320 340 360 380 60 80 100 120 140 160 180 200 220 240 260
1980
0
20
40
MCK 2.35µs (147fH)
HSYNC
XCLP1 0.55µs (35fH) 0.15µs (10fH) 5.14µs (321.5fH) 6fH 2.0µs (125fH) 12fH
1.2µs (75fH)
XCLP2
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 39 –
0.4µs (25fH) 1.0µs (63fH) 1.8µs (112fH) 2.1µs (131fH) EVEN LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
1.18µs (73.5fH)
FRP 0.3µs (19fH)
PCG1
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
Loop counter 2000fH Master Clock 62.5MHz
200 220 240 260 280 300 320 340 360 380
PAL (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: L XHD: H
80 100 120 140 160 180
1980
0
20
40
60
MCK
HSYNC
2.35µs (147fH)
HSTA 5.19µs (324.5fH) 6fH 12fH
5.14µs (321.5fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 40 –
EVEN LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B CXD2443Q
SH7B
Loop counter 1976fH Master Clock 66.69MHz
240 260 280 300 320 340
HD Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H XHD: L
20 40 60 80 100 120 140 160 180 200 220
1916
1936
1956
0
MCK
HSYNC
0.59µs (40fH)
XCLP1 2.0µs (133fH) 3.84µs (256fH) 12fH 6fH
0.55µs (36fH)
1.2µs (80fH)
XCLP2
0.15µs (9fH)
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 41 –
0.4µs (26fH) 1.8µs (120fH) 2.1µs (140fH) 0.3µs (20fH) ODD LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
1.2µs (80fH)
FRP
PCG1
1.0µs (67fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
HD Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L XHD: L Loop counter 1976fH Master Clock 66.69MHz
160 180 200 220 240 260 280 300 320 340 40 60 80 100 120 140
1916
1936
1956
0
20
MCK
HSYNC
0.59µs (40fH)
HSTA 3.84µs (256fH) 6fH 12fH
3.84µs (256fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 42 –
ODD LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B
SH7B CXD2443Q
Loop counter 1976fH Master Clock 66.69MHz
240 260 280 300 320 340
HD Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H XHD: L
20 40 60 80 100 120 140 160 180 200 220
1916
1936
1956
0
MCK
HSYNC
0.59µs (40fH)
XCLP1 2.0µs (133fH) 3.82µs (254.5fH) 6fH 12fH
0.55µs (36fH)
1.2µs (80fH)
XCLP2
0.15µs (9fH)
HSTA
HCK1A
HCK2A
SH1A
SH2A
SH3A
– 43 –
0.4µs (26fH) 1.8µs (120fH) 2.1µs (140fH) 0.3µs (20fH) EVEN LINE
SH4A
SH5A
SH6A
SH7A
ENB
VCK
1.18µs (78.5fH)
FRP
PCG1
1.0µs (67fH)
PCG2
HDR
CXD2443Q
Note) The FRP polarity is not specified for each line and field.
HD Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L XHD: L Loop counter 1976fH Master Clock 66.69MHz
160 180 200 220 240 260 280 300 320 340 40 60 80 100 120 140
1916
1936
1956
0
20
MCK
HSYNC
0.59µs (40fH)
HSTA 3.86µs (257.5fH) 6fH 12fH
3.82µs (254.5fH)
12fH
HSTB
HCK1A
HCK2A
HCK1B
HCK2B
SH1A
– 44 –
EVEN LINE
SH2A
SH3A
SH4A
SH5A
SH6A
SH7A
SH1B
SH2B
SH3B
SH4B
SH5B
SH6B
SH7B CXD2443Q
NTSC (double-speed HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: H NT-PL: H XHD: H
0 10 20 30 40 50 60 70
510
520
VD
HSYNC 21H
1 2 3 4 5 6 7 8 9 10 1112
(BLK) Display start
483 485 484
VST
HDR
HSTA
HSTB
– 45 –
Double-speed HSYNC input
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
NTSC (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: H XHD: H
0 10 20 30 40 50 60 70
510
520
VD
HSYNC 21H
1 2 3 4 5 6 7 8 9 10 11 12
(BLK) Display start
483 485 484
VST
HDR
HSTA
HSTB
– 46 –
ODD FIELD (standard HSYNC input)
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
NTSC (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: H XHD: H
0 10 20 30 40 50 60 70
510
520
VD
HSYNC 21H
1 2 3 4 5 6 7 8 9 10 1112
(BLK) Display start
483 485 484
VST
HDR
HSTA
HSTB
– 47 –
EVEN FIELD (standard HSYNC input)
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
PAL (double-speed HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: H NT-PL: L XHD: H
0 10 20 30 40 50 60 70
610
620
VD
HSYNC 25H
1 2 3 4 5 6 7 8 9 10 1112
(BLK) Display start
598 600 599
VST
HDR
HSTA
HSTB
– 48 –
Double-speed HSYNC input
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
PAL (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H
0 10 20 30 40 50 60 70
610
620
VD
HSYNC 25H
1 2 3 4 5 6 7 8 9 10 1112
(BLK)
598 600 599
Display start
VST
HDR
HSTA
HSTB
– 49 –
ODD FIELD (standard HSYNC input)
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
PAL (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H
0 10 20 30 40 50 60 70
610
620
VD
HSYNC 25H
1 2 3 4 5 6 7 8 9 10 1112
(BLK) Display start
598 600 599
VST
HDR
HSTA
HSTB
– 50 –
EVEN FIELD (standard HSYNC input)
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
PAL (pulse eliminate display, standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: L SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H
0 10 20 30 40 50 60 70
610
620
VD
HSYNC 25H
1 2 3 4 5 6 7 8 9 10 1112
(BLK) Display start
598 600 599
VST
HDR
HSTA
HSTB
– 51 –
ODD FIELD (standard HSYNC input)
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
PAL (pulse eliminate display, standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: L SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H
0 10 20 30 40 50 60 70
610
620
VD
HSYNC 25H
1 2 3 4 5 6 7 8 9 10 1112
(BLK) Display start
598 600 599
VST
HDR
HSTA
HSTB
– 52 –
EVEN FIELD (standard HSYNC input)
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
HD Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H XHD: L
0 10 20 30 40 50 60 70
1110
1120
VD
HSYNC 45H
1 2 3 4 5 6 7 8 9 10 1112 13 1415 16 1718 19 20 21 22 2324 25 26 2728
(BLK)
1033 1035 1034
Display start
VST
HDR
HSTA
HSTB
– 53 –
ODD FIELD
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
HD Vertical Direction Timing Chart VP1, 2, 3, 4 : LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H XHD: L
563 573 583 593 603 613 623 633
553
VD
HSYNC 45H
518 520 522 524 526 528 530 532 534 536 538 540 542 544 519 521 523 525 527 529 531 533 535 537 539 541 543 545
(BLK)
515 517 516
Display start
VST
HDR
HSTA
HSTB
– 54 –
EVEN FIELD
ENB
VCK
FRP (1H inversed)
FRP (1F inversed)
PCG1
PCG2
FLDO
VWA
VWB
CXD2443Q
Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins.
Line Double-Speed Timing Chart
SLBA = L 910fH, Master Clock 28.6MHz
NTSC
Loop counter
40
30
20
10
0
10
20
30
40
900 0 10 20
910
1780
1790
1800
1810
30
40
MCK 4.7µs (68fH)
HSYNC
4.7µs (68fH)
WCK
RSTW
RCK
RSTR
– 55 – 1135fH, Master Clock 35.5MHz
0 10 20 30 40 1130 1140 2230 2240 2250
PAL
Loop counter
40
30
20
10
2260
0
10
20
30
40
MCK 4.7µs (83fH)
HSYNC
4.7µs (83fH)
WCK
RSTW
RCK CXD2443Q
RSTR
CXD2443Q
Application Circuit
RPD4
FPD4 +5V 5.1k 1M 1M +5V
1k
0.1µ
33k 1000p
L : NTSC 1.8µH PAL 1.2µH L
50k
33µ 16V
0.01µ
+13V 10k 50k
33k D4 10k
100p +5V
0.1µ 0.01µ 3.3µ 16V 33µ 25V 0.01µ 3.3k 0.01µ 22p
47µ 16V
µPD485505 (NEC)
0.1µ
0.1µ
47µ 16V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RPD4 RCK RSTR SH7A FPD4 TEST9 SH5B WCK VDD VSS VSS RSTW PEO4 CKO4 TEST10 RPD2 FPD2 +5V 5.1k 1M 1k 1M 81 82 83 84 SH4B SH6A SH2A SH1A VDD SH6B SH1B SH7B SH2B SH3B SH5A SH4A SH3A VSS CKI4
PWM4 TC4 TC2 FPD2
XFRP 50 FRP 49
XCLP2 48 XCLP1 47 PCG2 46 XRGT 45 RGT 44 HSTA 43 HSTB 42 HCK1B 41 VSS 40 HCK2B 39 HCK1A 38 HCK2A 37 ENB 36 VCK 35 VST 34 TEST8 33 HSYNC VSYNC TEST11 TEST1 TEST2 TEST3 TEST4 TEST5 PWM1 TEST6 TEST7 DWN 32 PCG1 31
85 PEO2 86 87 0.1µ 33k 1000p +13V 10k 50k 3.3µ 16V 33µ 25V 3.3k 62p 33k D2 10k 0.39µ PWM2 RPD2
88 CKO2 89 CKI2
90 VSS 91 CKO3 92 CKI3
93 RPD3 94 PEO3 PWM3 FPD3 TC3 CKSL CKI5 CKO1 SCTR PEO1 RPD1 XCLR VWB SCLK FPD1 SDAT CKI1 PRE TC1 VDD VSS VSS
0.01µ
0.01µ
0.01µ
95 96 97 98
+5V
+5V
99
FLDO
50k
50k
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSS VWA
VDD
100 HDR
+5V 33µ 16V 0.01µ 100p 33µ 16V 0.01µ 100p 33k 47µ 16V
1µ RPD3 FPD3 RPD1 +5V 1M 680 1M 5.1k 1k +5V
0.1µ
0.1µ
0.1µ
47µ 16V
FPD1 1M 5.1k 1M Serial I/F Sync signal
0.1µ
33k 1000p
0.33µ
+5V
0.1µ
33k 1000p
0.68µ
+13V 10k
33k D3 10k 50k 47p 50k 10k
+13V
33k D1 10k 50k 47p OFF ON 0.01µ PRE
0.01µ
3.3µ 16V
33µ 25V
0.01µ
3.3k
0.01µ
33µ 16V
0.01µ
100p
0.01µ
3.3µ 16V
33µ 25V
0.01µ
3.3k
D1, D2, D3, D4 : 1T363A (Sony)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 56 –
CXD2443Q
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 – 0.05
23.9 ± 0.4 + 0.4 20.0 – 0.1
+ 0.4 14.0 – 0.01 17.9 ± 0.4
15.8 ± 0.4
A
0.65 ±0.12 M
+ 0.35 2.75 – 0.15
0.15
0° to 15° DETAIL A
0.8 ± 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 ∗QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
– 57 –
工商网监
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