CXD3300R

CXD3300R 10-bit 20MSPS Video A/D Converter Description The CXD3300R is a 10-bit CMOS A/D converter for video applications. This IC is ideally suited for the A/D conversion of video signals in TVs, VCRs, camcorders, etc. Features • Resolution: 10 bits ± 1.0LSB (D.L.E.) • Maximum sampling frequency: 20MSPS • Low power consumption: 40mW (Except self-bias ) • Low input capacitance • Built-in self-bias circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage AVDD DVDD • Reference voltage VRT, VRB • Input voltage VIN (analog) • Input voltage VIH, VIL (digital) • Output voltage VOH, VOL (digital) • Storage temperature Tstg 48 pin LQFP (Plastic) Structure Silicon gate CMOS IC AVSS – 0.5 to +4.5 DVSS – 0.5 to +4.5 AVDD + 0.5 to AVSS – 0.5 AVDD + 0.5 to AVSS – 0.5 AVDD + 0.5 to AVSS – 0.5 DVDD + 0.5 to DVSS – 0.5 –55 to +150 V V V V V V °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 3.0 ± 0.3 DVDD, DVSS 3.0 ± 0.3 | DVSS – AVSS | 0 to 100 • Reference input voltage VRB 0.3AVDD to 0.5AVDD VRT 0.6AVDD to 0.8AVDD • Analog input VIN 0.9Vp-p or more • Clock pulse width tPW1 25 (min.) tPW0 25 (min.) • Operating ambient temperature Topr –40 to +85 V V mV V V ns ns °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97310-PS CXD3300R Block Diagram VIN 38 S/H Amp + – ×8 Coarse Correction & Latch 12 D9 VRT 28 VRTC 29 11 D8 10 9 8 D7 D6 D5 VRTS 27 DAC VRMC 30 BE 36 Coarse Comparate & Encode Calibration Unit VRB 32 Fine Comparate & Encode 5 4 Fine Latch 3 2 1 D4 D3 D2 D1 D0 (LSB) VRBS 33 20 MINV 19 LINV 18 TESTMODE CAL VRBC 31 CLK 22 OE 23 CE 24 Timing Gen. Auto Calibration Pulse Generator 42 15 RESET VRMC VRBC VRTC VRBS AVDD VRTS AVDD AVSS VRB 36 35 34 33 32 31 30 29 28 27 26 25 TSTR 37 VIN 38 VRT AVSS Pin Configuration BE 24 CE 23 OE TS 39 AVDD 40 AVSS 41 CAL 42 AVDD 43 AT 44 AVDD 45 AVSS 46 DVDD 47 DVSS 48 22 CLK 21 AVDD 20 MINV 19 LINV 18 TESTMODE 17 AVDD 16 AVSS 15 RESET 14 TIN 13 TO 1 2 3 4 5 6 7 8 9 10 11 12 D1 D4 D5 D0 D3 DVDD D2 DVSS D6 D7 D8 –2– D9 CXD3300R Pin Description Pin No. Symbol DVDD Equivalent circuit Description 1 to 5 8 to 12 D0 to D9 D0 (LSB) to D9 (MSB) output. DVSS 6, 48 7, 47 13 DVSS DVDD TO Digital VSS. Digital VDD. Test pin. High impedance when TS = High. Test signal input. Normally fixed to AVDD or AVSS. AVDD 14 TIN 15 RESET 15 Calibration circuit reset and startup calibration restart. AVSS 16, 25, 34, 41, 46 AVSS Analog VSS. Analog VDD. AVDD 17, 21, 26, 35, AVDD 40, 43, 45 18 TESTMODE 18 Test mode. High: Output state Low: Output fixed AVSS AVDD 19 LINV 19 Output inversion. High: D0 to D8 are inverted and output. Low: D0 to D8 are normal output. AVSS –3– CXD3300R Pin No. Symbol Equivalent circuit AVDD Description 20 MINV 20 Output inversion. High: D9 is inverted and output. Low: D9 is normal output. AVSS AVDD 22 CLK 22 Clock. AVSS AVDD 23 OE 23 D0 to D9 output enable. Low: Output state High: High impedance state AVSS AVDD 24 CE 24 Chip enable. Low: Active state High: Standby state AVSS –4– CXD3300R Pin No. Symbol AVDD Equivalent circuit Description 27 VRTS 27 Self-bias. (Reference top) AVSS AVDD 28 VRT 28 Reference top. AVSS AVDD 29 VRTC 29 Reference top output. AVSS AVDD 30 VRMC 30 Reference middle output. AVSS AVDD 31 VRBC 31 Reference bottom output. AVSS AVDD 32 VRB 32 Reference bottom. AVSS AVDD 33 VRBS 33 AVDD AVSS 36 Self-bias. (Reference bottom) 36 BE AVSS Bias enable. –5– CXD3300R Pin No. 37 Symbol TSTR Equivalent circuit Description Test signal input. Normally fixed to AVDD or AVSS. Test signal input. High impedance when TS = High. 44 AT AVDD 38 VIN 38 Analog input. AVSS AVDD 42 CAL 42 Calibration pulse input. AVSS 39 TS Test signal input. Normally fixed to AVDD. –6– CXD3300R Digital Output The following table shows the correlation between the analog input voltage and the digital output code. (TESTMODE = 1, LINV, MINV = 0) Input signal voltage VRT Step 1023 512 511 VRB 0 Digital output code MSB LSB 1111111111 1000000000 0111111111 0000000000 The following table shows the output state for the combination of TESTMODE, LINV, and MINV states. TESTMODE 1 1 1 1 0 0 0 0 LINV 0 1 0 1 0 1 0 1 MINV 0 0 1 1 0 0 1 1 D0 P N P N 1 0 1 0 D1 P N P N 0 1 0 1 D2 P N P N 1 0 1 0 D3 P N P N 0 1 0 1 D4 P N P N 1 0 1 0 D5 P N P N 0 1 0 1 D6 P N P N 1 0 1 0 D7 P N P N 0 1 0 1 D8 P N P N 1 0 1 0 D9 P P N N 0 0 1 1 P: Forward-phase output N: Inverted output Timing Chart 1 tPW1 tPW0 Clock 1.5V tSD N+1 Analog input N N+2 tDL N+3 N+4 Data output N–3 N–2 N–1 N 1.5V : Indicates point at which analog data is sampled Timing Chart 2 1.5V Output enable (OE) tPEZ tPZE 1.5V 1.5V Data output Active High Impedance Active –7– CXD3300R Electrical Characteristics Item Maximum conversion rate Minimum conversion rate Supply current Standby current Analog Digital Analog Digital (Fc = 20MSPS, AVDD = 3V, DVDD = 3V, VRB = 1V, VRT = 2V, Ta = 25°C) Symbol Fc max Fc min IADD IDDD IAST IDST IRT1 IRB1 IRT2 VRTS, VRBS: Open Between VRT and VRB BE = AVDD Between VRTC and VRBC –1dB 87 –111 1.81 –2.33 97 97 2.04 –2.04 85 10 Between VRTS and VRT, VRT and VRB, VRB and VRBS Between VRTC and VRBC BE = AVDD EOT1 = Theoretical value – Measured value EOB1 = Measured value – Theoretical value BE = AVSS EOT2 = Theoretical value – Measured value EOB2 = Measured value – Theoretical value Conditions FIN = 1.0kHz sine wave input FIN = 1.0kHz sine wave input BE = High CE = AVDD Min. 20 Typ. Max. Unit MSPS 0.5 11 14 1.0 17 4 3.0 1.0 111 –87 2.33 1.81 mA mA µA µA Reference pin current 1 Reference pin current 2 Analog input band Analog input capacitance Reference resistance value 1 Reference resistance value 2 Offset voltage1 IRB2 BW CIN RREF1 RREF2 EOT1 EOB1 EOT2 EOB2 VIH VIL AIH AIL IIH IIL IOH IOL IOZH IOZL mA MHz pF 9k 430 –30 –30 –30 –20 0.7AVDD 10.3k 490 +5 +5 +5 +10 11.5k 550 +40 +40 +40 +40 Ω Ω mV Offset voltage2 mV Digital input voltage AVDD = 2.7 to 3.3V VIN = 2V VIN = 1V AVDD = 3.3V VIH = AVDD VIL = AVSS 0.2AVDD 40 –55 48 –48 55 –40 5 5 1.0 1.0 1 1 6 3 8 5 ±1.0 ±0.5 10 7 ±3.0 ±1.0 V Analog input current µA Digital input current µA Digital output current OE = AVSS VOH = DVDD – 0.4V DVDD = 2.7V VOL = 0.4V OE = AVDD VOH = DVDD DVDD = 3.3V VOL = 0V Clock not synchronized for active → high impedance Clock not synchronized for high impedance → active mA Digital output current Tri-state output disable time Tri-state output enable time Integral nonlinearity error Differential nonlinearity error µA ns ns LSB LSB tPEZ tPZE EL ED –8– CXD3300R Item Differential gain error Differential phase error Output data delay Sampling delay Symbol DG DP Conditions NTSC 40 IRE mod ramp, Fc = 14.3MSPS CL = 3pF, Ta = –40 to +85°C Min. Typ. 1.0 0.3 Max. Unit % deg tDL tSD 6 6 9 7 50 50 50 50 45 44 52 52 52 52 49 50 18 8 ns ns FIN = 100kHz FIN = 500kHz SNR FIN = 1MHz SNR FIN = 3MHz FIN = 7MHz FIN = 10MHz FIN = 100kHz FIN = 500kHz FIN = 1MHz SFDR SFDR FIN = 3MHz FIN = 7MHz FIN = 10MHz dB dB –9– CXD3300R Application Circuit 1 When not using self-bias and the internal bias circuits, and supplying the reference voltage from an external source. 1V AVDD 2V AVDD AVSS 36 35 34 33 32 31 30 29 28 27 26 25 VRBC AVSS VRT VRMC VRBS VRTS BE 2.0V 1.0V Signal input 37 TSTR 38 VIN 39 TS 40 AVDD 41 AVSS 42 CAL Calibration pulse 43 AVDD 44 AT 45 AVDD 46 AVSS AVSS DVDD DVSS 47 DVDD AVSS AVDD VRTC AVDD AVDD VRB CE 24 OE 23 CLK 22 Clock input AVDD 21 MINV 20 LINV 19 TESTMODE 18 AVDD 17 AVSS 16 RESET 15 TIN 14 AVSS Reset pulse AVDD DVSS DVDD 48 DVSS TO 13 D4 D7 D1 D3 D6 D0 D2 1 2 3 4 5 6 7 D5 8 9 10 11 12 : 0.1µF DVSS DVDD Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – D8 D9 CXD3300R Application Circuit 2 When not using self-bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source. 1V AVDD AVSS 2V AVDD AVSS 36 35 34 33 32 31 30 29 28 27 26 25 VRBC AVSS VRT VRMC VRBS VRTS BE 2.0V 1.0V Signal input 37 TSTR 38 VIN 39 TS 40 AVDD 41 AVSS 42 CAL Calibration pulse 43 AVDD 44 AT 45 AVDD 46 AVSS AVSS DVDD DVSS 47 DVDD AVSS AVDD VRTC AVDD AVDD VRB CE 24 OE 23 CLK 22 Clock input AVDD 21 MINV 20 LINV 19 TESTMODE 18 AVDD 17 AVSS 16 RESET 15 TIN 14 AVSS Reset pulse AVDD DVSS DVDD 48 DVSS TO 13 D4 D7 D1 D3 D6 D0 D2 1 2 3 4 5 6 7 D5 8 9 10 11 12 : 0.1µF DVSS DVDD Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – D8 D9 CXD3300R Application Circuit 3 When using the self-bias and internal bias circuits, and supplying the reference voltage. AVDD AVDD AVSS 36 35 34 33 32 31 30 29 28 27 26 25 AVSS VRBC AVSS VRT VRMC VRBS VRTS BE 2.0V 1.0V Signal input 37 TSTR 38 VIN 39 TS 40 AVDD 41 AVSS 42 CAL Calibration pulse 43 AVDD 44 AT 45 AVDD 46 AVSS AVSS DVDD DVSS 47 DVDD AVSS AVDD VRTC AVDD AVDD VRB CE 24 OE 23 CLK 22 Clock input AVDD 21 MINV 20 LINV 19 TESTMODE 18 AVDD 17 AVSS 16 RESET 15 TIN 14 AVSS Reset pulse AVDD DVSS DVDD 48 DVSS TO 13 D4 D7 D1 D3 D6 D0 D2 1 2 3 4 5 6 7 D5 8 9 10 11 12 : 0.1µF DVSS DVDD Digital output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 12 – D8 D9 CXD3300R 1. Calibration function 1) Activating startup calibration To achieve superior linearity, the CXD3300R has a built-in calibration circuit. When using this IC, therefore, startup calibration must be activated when the power supply and reference voltage have risen and stabilized. Care should be taken as only the upper five bits may be output in the worst case if startup calibration is not activated. Startup calibration can be activated either at the rise of the RESET pin (Pin 15) or at the fall of the CE pin (Pin 24). The startup calibration activation method for each case is shown in Fig. 1. a) When using RESET [V] 3 AVDD [V] 3 b) When using CE AVDD VRT VRT VRB VRB 0 [t] 0 [t] RESET H L H L RESET H L H L CE Startup calibration CE Startup calibration 33,000 CLK 33,000 CLK Fig. 1. Startup Calibration Activation Methods As shown in the figure above, startup calibration must be activated after the supply voltage has risen and stabilized (full scale of 90% or more). After activation, startup calibration is performed for an interval of about 33,000 clocks. Therefore, care should be taken as the output data during this interval (about 2.3ms at 14.3MHz) cannot be used. 2) Calibration pulse supply The IC's operating status with changes due to fluctuations in the supply voltage and ambient temperature during use can be constantly monitored and then compensated appropriately by inputting a pulse at regular intervals to the CAL pin (Pin 41). Fig. 2 shows the timing chart. 10ns or more 7 clocks CLK 1 clock or more CAL D0 to D9 N–3 N–2 N–1 N N+5 Fig. 2. Calibration Timing Chart – 13 – CXD3300R Calibration starts when the fall of the pulse input to the CAL pin (Pin 41) is detected at the clock rise. At this time, the comparator is used in an exclusive manner for a four clock interval. So, the output data holds the immediately previous data for a four clock interval after seven clocks from the rise of the clock where the fall of the calibration pulse was detected, and then the data during this interval is missing. Therefore, the effects of this function can be avoided by inputting a sync or other signal as the calibration pulse so that calibration is performed outside of the interval of the actually used video signal. An input example is shown below. [1] Input every H sync Input CLK CAL [2] Input every V sync Input CLK RESET CAL 2. Latch-up Ensure that the AVDD and DVDD pins share the same power supply on a board to prevent latch-up which may be caused by power-ON time lag. 3. Board To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate its characteristics adequately. – 14 – CXD3300R Example of Representative Characteristics Supply current vs. Ambient temperature 20 38 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave Maximum operating frequency vs. Ambient temperature AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 36 18 16 Maximum operating frequency [MHz] 85 Supply current [mA] 34 14 –40 0 25 50 Ambient temperature [°C] 32 –40 0 25 50 85 Ambient temperature [°C] Output data delay vs. Ambient temperature 11 8 Sampling delay vs. Ambient temperature Output data delay [ns] 10 Sampling delay [ns] AVDD = 3.0V DVDD = 3.0V Fc = 2MHz CL = 30pF 6 9 4 AVDD = 3.0V DVDD = 3.0V Fc = 2MHz 2 8 –40 0 25 50 85 Ambient temperature [°C] –40 0 25 50 85 Ambient temperature [°C] VRTC vs. Ambient temperature 2.0 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 1.95 1.15 1.20 VRBC vs. Ambient temperature VRTC [V] 1.90 VRBC [V] 1.10 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz fIN = 1kHz sine wave 1.85 –40 1.05 0 25 50 85 –40 0 25 50 85 Ambient temperature [°C] Ambient temperature [°C] – 15 – CXD3300R SNR vs. Analog input frequency 70 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C 60 60 70 SFDR vs. Analog input frequency AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C 50 SFDR [dB] 50 40 100k 1M Analog input frequency [Hz] 100M 40 100k SNR [dB] 1M Analog input frequency [Hz] 100M Effective bit vs. Analog input frequency 1 8 Analog input band 0 Output level [dB] Effective bit [bit] –1 7 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C 6 100k 1M Analog input frequency [Hz] 100M –2 AVDD = 3.0V DVDD = 3.0V Fc = 20MHz VIN = 1Vp-p Ta = 25°C –3 5M 10M 50M 75M 85M 100M Analog input frequency [Hz] – 16 – CXD3300R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 12 13 B (0.22) + 0.05 0.127 – 0.02 0.13 M 0.1 0.1 ± 0.1 0.5 ± 0.2 S (0.127) +0.05 0.127 – 0.02 (0.18) 0.18 ± 0.03 0° to 10° 0.5 ± 0.2 DETAIL B:SOLDER DETAIL A DETAIL B:PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g – 17 – 0.127 ± 0.04 + 0.08 0.18 – 0.03