CXG1125ER

CXG1125ER High Power 6 × 4 Antenna Switch MMIC with Integrated Control Logic for PDC Full Packet Description The CXG1125ER is a high power antenna switch MMIC for PDC dual 800MHz and 1.5GHz. This IC is suited to connect 2Tx/3Rx to one of 4 antennas equipped with full packet mode. The CXG1125ER has on-chip logic circuit for operation with 6 CMOS inputs. The Sony's GaAs J-FET process is used for low insertion loss and low voltage operation. Features • Low insertion loss: 0.5dB @900MHz, 0.7dB @1.5GHz • High linearity: Harmonic < – 65dBc • CMOS compatible input control • Small package: 24-pin VQFN (4.0mm × 4.0mm) Applications 6 × 4 antenna switch for digital cellular such as PDC handsets Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) • Bias voltage VDD • Control voltage • Operating temperature • Storage temperature Vctl Topr Tstg 24 pin VQFN (Plastic) 7 5 –35 to +85 –65 to +150 V V °C °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02112A25-PS CXG1125ER Block Diagram F1 Tx800 F2 F14 F5 Tx1.5 F6 F24 F23 GND5 F4 Dup_Out F25 Rx800D F10 Rx800A F11 Rx1.5 F13 D_Ext F19 F27 GND3 GND4 F8 F26 F17 F18 F7 F12 GND1 GND2 D_Ant F3 F15 F16 Ant Ext –2– CXG1125ER Pin Configuration and Recommended Circuit Tx800 Tx1.5 Ext CRF CRF 12 Dup_Out CRF GND5 14 13 11 10 9 8 CRF GND2 GND GND 7 6 CRF 5 GND1 Ant Rx800D CRF CTLA Cbypass CTLB Cbypass Rx800A CRF 15 4 GND 16 3 CRF D_Ext 17 2 Cbypass CTLF 18 19 20 21 22 23 24 1 Cbypass GND3/CTLE Cbypass Cbypass Cbypass VDD CTLC CTLD GND4 CRF When using this IC, the following external components should be used: CRF: This capacitor is used for RF de-coupling and must be used for all applications. 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. –3– D_Ant Rx1.5 CXG1125ER Truth Table A: Rx/Tx B: Main/diversity C: External/antenna D: 800MHz digital/800MHz analog E: 800MHz/1.5GHz F: TDMA/duplex State 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 On Pass Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Rx800D – Ext Rx800A – Ext Rx1.5 – Ext Rx800D – Ant Rx800A – Ant Rx1.5 – Ant Rx800D – D_Ext Rx800A – D_Ext Rx1.5 – D_Ext Rx800D – D_Ant Rx800A – D_Ant Rx1.5 – D_Ant Dup_Out – Ext Rx800D – Ext Dup_Out – Ant Rx800D – Ant Dup_Out – Ext Rx800D – D_Ext Dup_Out – Ant Rx800D – D_Ant A H H H H L L L L L L L L L L L L H B — — — — L L L L L L H H H H H H L C L H L H L L L H H H L L L H H H L D — — — — L H — L H — L H — L H — L E L L H H L L H L L H L L H L L H L F L L — — — — — — — — — — — — — — H F1 H L L L L L L L L L L L L L L L L F2 L H L L L L L L L L L L L L L L L F3 L L L L H L L L L L L L L L L L H F4 L L L L L L L H L L L L L L L L L F5 L L H L L L L L L L L L L L L L L F6 L L L H L L L L L L L L L L L L L F7 L L L L L H H L L L L L L L L L L F8 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F23 F24 F25 F26 F27 L L L L L L L L H H L L L L L L L L L L L L H L L H L L H L L H L L L L L L L L H L L H L L H L L H L L L L L L L L L L L L L L L H H L L L L L L L L L L L L H H L L L L L H L H L L L H H H H H H H H H L H L L L H H L L L L H H L H H L H L L H L L L H L L L L L H L L H L H H L L H H L H H L H H L L L L H L L H H L L H L L H L L H L L L L H H H H H H H H H H L L L H H H H H H H H L H H L H H H H H H H H L H H L L H H H H H H H H H H H H H L L L L H L L H L L L L L L L L H L L L L L L L L L L L L L H L L L L L L L L L L L L L H L L L L L L 18 H L H L L H L L L H L L L L L L L L H L L H L H L H H L L 19 H H L L L H L L H L L L L L L L L L L H L H L L L H L L H 20 H H H L L H L L L H L L L L L L L L H L L L L H L H L H L DC Bias Condition Item VDD Vctl (H) Vctl (L) Min. 2.7 2.0 0.0 Typ. 3.0 3.0 (Ta = 25°C) Max. 3.3 3.3 0.4 Unit V V V –4– CXG1125ER Electrical Characteristics Item Symbol State 1 2 3 4 5 6 7 8 9 10 11 Insertion loss IL 12 13 14 15 16 17 18 19 20 Port Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Rx800D – Ext Rx800A – Ext Rx1.5 – Ext Rx800D – Ant Rx800A – Ant Rx1.5 – Ant Rx800D – D_Ext Rx800A – D_Ext Rx1.5 – D_Ext Rx800D – D_Ant Rx800A – D_Ant Rx1.5 – D_Ant Dup_Out – Ext Rx800D – Ext Dup_Out – Ant Rx800D – Ant Dup_Out – Ext Rx800D – D_Ext Dup_Out – Ant Rx800D – D_Ant Condition ∗1 ∗1 ∗2 ∗2 ∗3 , ∗7 ∗3 ∗4 ∗3 , ∗7 ∗3 ∗4 ∗3 ∗3 ∗4 ∗3 ∗3 ∗4 ∗1 , ∗8 ∗3 , ∗7 ∗1 , ∗8 ∗3 , ∗7 ∗1 ∗3 ∗1 ∗3 (Ta = 25°C) Min. Typ. Max. Unit 0.50 0.80 0.55 0.85 0.70 1.00 0.70 1.00 1.20 1.45 1.25 1.55 1.40 1.60 1.20 1.45 1.15 1.45 1.35 1.55 0.55 0.85 1.00 1.30 1.15 1.35 0.65 0.95 1.20 1.50 1.35 1.55 0.90 1.20 1.20 1.50 0.95 1.25 1.25 1.55 0.75 1.00 0.55 0.85 0.80 1.10 0.70 1.00 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB –5– CXG1125ER Item Symbol State 2 1 4 3 8 9 10 5 6 7 14 15 16 11 12 13 18 17 20 19 Port Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Rx800D – Ext Rx800A – Ext Rx1.5 – Ext Rx800D – Ant Rx800A – Ant Rx1.5 – Ant Rx800D – D_Ext Rx800A – D_Ext Rx1.5 – D_Ext Rx800D – D_Ant Rx800A – D_Ant Rx1.5 – D_Ant Dup_Out – Ext Rx800D – Ext Dup_Out – Ant Rx800D – Ant Dup_Out – Ext Rx800D – D_Ext Dup_Out – Ant Rx800D – D_Ant Condition ∗1 ∗1 ∗2 ∗2 ∗3, ∗7 ∗3 ∗4 ∗3, ∗7 ∗3 ∗4 ∗3 ∗3 ∗4 ∗3 ∗3 ∗4 ∗1, ∗8 ∗3, ∗7 ∗1, ∗8 ∗3, ∗7 ∗1 ∗3 ∗1 ∗3 Min. Typ. Max. Unit 25 25 25 25 25 25 25 25 25 20 25 25 25 25 25 25 25 25 25 25 25 25 25 25 37 39 35 30 37 41 51 39 38 26 37 38 33 33 33 37 37 37 38 38 37 37 41 33 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Isolation ISO. –6– CXG1125ER Item Symbol State 1 2 3 4 17 18 19 20 1 2 3 4 17 18 19 20 1 2 3 4 17 18 19 20 1 2 3 4 17 18 19 20 Port Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Dup_Out – Ext Dup_Out – Ant Dup_Out – Ext Dup_Out – Ant Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Dup_Out – Ext Dup_Out – Ant Dup_Out – Ext Dup_Out – Ant Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Dup_Out – Ext Dup_Out – Ant Dup_Out – Ext Dup_Out – Ant Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Dup_Out – Ext Dup_Out – Ant Dup_Out – Ext Dup_Out – Ant Condition ∗5 ∗5 ∗6 ∗6 ∗5, ∗8 ∗5, ∗8 ∗5 ∗5 ∗5 ∗5 ∗6 ∗6 ∗5, ∗8 ∗5, ∗8 ∗5 ∗5 ∗5 ∗5 ∗6 ∗6 ∗5, ∗8 ∗5, ∗8 ∗5 ∗5 ∗5 ∗5 ∗6 ∗6 ∗5, ∗8 ∗5, ∗8 ∗5 ∗5 Min. Typ. Max. Unit –75 –78 –70 –75 –72 –74 –73 –76 –72 –71 –70 –70 –75 –74 –73 –72 –67 –66 –67 –65 –66 –67 –67 –67 –74 –74 –73 –72 –74 –73 –74 –73 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –60 –57 –57 –57 –57 –57 –57 –57 –57 –65 –65 –65 –65 –65 –65 –65 –65 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 2fo Harmonics 3fo ±50kHz ACP ±100kHz –7– CXG1125ER Item Symbol State 1 2 3 4 17 18 19 20 Port Tx800 – Ext Tx800 – Ant Tx1.5 – Ext Tx1.5 – Ant Dup_Out – Ext Dup_Out – Ant Dup_Out – Ext Dup_Out – Ant Condition VDD = 3.0V VDD = 3.0V VDD = 3.0V VDD = 3.0V VDD = 3.0V, ∗8 VDD = 3.0V, ∗8 VDD = 3.0V VDD = 3.0V VDD = 3.0V Vctl (H) = 3V Min. Typ. Max. Unit 32 32 32 32 32 32 32 32 34 34 34 34 34 34 34 34 2 1.3 40 5 1.8 70 dBm dBm dBm dBm dBm dBm dBm dBm µs mA µA P1dB P1dB Switching speed Bias current Control current ∗1 ∗2 ∗3 ∗4 ∗5 TSW IDD Ictl Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 940MHz to 958MHz Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz Pin = 7dBm, 0/3V control, VDD = 3.0V, 810MHz to 885MHz Pin = 7dBm, 0/3V control, VDD = 3.0V, 1,477MHz to 1,501MHz π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 940MHz to 958MHz, ACP (±50kHz) < – 65dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 65dBc, 3rd harmonics < – 65dBc ∗6 π/4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz, ACP (±50kHz) < – 65dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 65dBc, 3rd harmonics < – 65dBc ∗7 Dup_Out port open ∗8 Rx800D port open –8– CXG1125ER Package Outline Unit: mm 24PIN VQFN(PLASTIC) 4.0 3.6 C 13 0.7 0.9 ± 0.1 0.05 S 0.6 ± 0.1 18 19 A 12 B 4. 78 9) .3 (0 PIN 1 INDEX 24 7 1 6 0.4 x4 0.2 S A-B C x4 0.2 S A-B C 0.05 M S A-B C 0. 6 ˚ 45 S C 1.0 0.03 ± 0.03 (∗1) (Stand Off) Solder Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 TERMINAL SECTION PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VQFN-24P-03 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.04g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm 0.2 ± 0.01 0.225 ± 0.03 (0 .1 5) –9– Sony Corporation