CXK58512M-70LL

CXK58512TM/M -55LL/70LL/10LL ∗ 65536-word × 8-bit High Speed CMOS Static RAM ∗Under development For the availability of this product, please contact the sales office. Description The CXK58512TM/M is a high speed CMOS static RAM organized as 65536-words by 8 bits. A polysilicon TFT cell technology realized extremely low stand-by current and higher data retention stability. Special feature are low power consumption, high speed. The CXK58512TM/M is a suitable RAM for portable equipment with battery back up. Features • Fast access time (Access time) -55LL 55ns (Max.) -70LL 70ns (Max.) -10LL 100ns (Max.) • Low standby current 10µA (Max.) • Low data retention current 6µA (Max.) • Single +5V supply: +5V ± 10% • Low voltage data retention: 2.0V (Min.) • Broad package line-up CXK58512TM 8mm × 20mm 32 pin TSOP package CXK58512M 525mil 32 pin SOP Package Function 65536-word × 8 bit static RAM Structure Silicon gate CMOS IC CXK58512TM 32 pin TSOP (Plastic) CXK58512M 32 pin SOP (Plastic) Block Diagram A15 A13 A8 A11 A9 A7 A6 A5 A14 A12 Buffer Row Decoder Memory Matrix 1024 × 512 VCC GND A4 A3 A10 A0 A2 A1 OE Buffer I/O Gate Column Decoder Buffer WE CE1 CE2 I/O Buffer I/O1 I/O8 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94915A58-PK CXK58512TM/M Pin Configuration (Top View) A11 A9 A8 A13 WE CE2 A15 Vcc NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 OE 31 A10 30 CE1 29 I/O8 28 I/O7 27 I/O6 26 I/O5 Pin Description NC 1 NC 2 A14 3 A12 4 A7 5 A6 6 A5 A4 A3 A2 7 8 9 1 32 Vcc 31 A15 30 CE2 29 WE 28 A13 27 26 25 24 Symbol A0 to A15 I/O1 to I/O8 CE1, CE2 WE OE VCC GND NC Description Address input Data input output Chip enable 1, 2 input Write enable input Output enable input Power supply Ground No connection CXK58512TM 25 I/O4 24 GN D 23 I/O3 22 I/O2 21 I/O1 20 A0 19 A1 18 A2 A3 17 A8 A9 A11 OE A10 1 I/O1 12 A1 0 A0 1 23 CE1 22 I/O8 21 I/O7 20 I/O6 19 18 17 I/O2 1 3 I/O3 1 4 GND 15 16 I/O5 I/O4 CXK58512M Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature • time Symbol VCC VIN VI/ O PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +7.0 –0.5∗ to VCC + 0.5 –0.5∗ to VCC + 0.5 0.7 0 to +70 –55 to +150 235 • 10 Unit V V V W °C °C °C • s ∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE1 CE2 H × L L L × L H H H OE × × H L × WE × × H H L Mode Not selected Not selected Output disable Read Write I/O pin High Z High Z High Z Data out Data in VCC Current ISB1, ISB2 ISB1, ISB2 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ICC1, ICC2, ICC3 ×: "H" or "L" DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min. 4.5 2.2 –0.3∗ (Ta = 0 to +70°C, GND = 0V) Typ. 5.0 — — Max. 5.5 VCC + 0.3 0.8 Unit V V V ∗ VIL = –3.0V Min. for pulse width less than 50ns. –2– CXK58512TM/M Electrical Characteristics • DC Characteristics Item Input leakage current Output leakage current Symbol ILI ILO (VCC = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) Test conditions VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA Min. cycle duty = 100% IOUT = 0mA Cycle time 1µs duty = 100% IOUT = 0mA CE1 ≤ 0.2V CE2 ≥ Vcc – 0.2V VIL ≤ 0.2V VIH ≥ Vcc – 0.2V CE2 ISB1 Standby current ISB2 Output high voltage Output low voltage ∗ VCC = 5V, Ta = 25°C VOH VOL or r 0 to +70°C 0.2V CE1 ≥ Vcc – 0.2V 0 to +40°C CE2 ≥ Vcc – 0.2V +25°C -55LL -70LL -10LL Min. –1 –1 Typ.∗ — — Max. +1 +1 Unit µA µA Operating power supply current ICC1 — — — — 7 45 40 35 15 90 70 60 mA ICC2 mA Average operating current ICC3 — 10 20 mA — — — — 2.4 — — — 0.4 0.6 — — 10 2 1 3 — 0.4 mA V V µA o CE1 = VIH or CE2 = VIL IOH = –1.0mA IOL = 2.1mA –3– CXK58512TM/M I/O capacitance Item Input capacitance I/O capacitance Symbol Test conditons CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 7 8 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions Item Input pulse high level Input pulse low level Input rise time Input fall time (VCC = 5V ± 10%, Ta = 0 to +70°C) Conditions VIH = 2.2V VIL = 0.8V tr = 5ns tf = 5ns 1.5V CL∗ = 30pF, 1TTL CL∗ = 100pF, 1TTL CL TTL • Ts crut et ici Input and output reference level Output load conditions -55LL -70LL/10LL ∗ CL includes scope and jig capacitances. –4– CXK58512TM/M • Read cycle (WE = "H") Item Read cycle time Address access time Symbol tRC (Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) -55LL Min. 55 — — — — 15 10 5 — — Max. — 55 55 55 30 — — — 25 25 -70LL Min. 70 — — — — 15 10 5 — — Max. — 70 70 70 40 — — — 25 25 -10LL Min. 100 — — — — 15 10 5 — — Max. — 100 100 100 50 — — — 35 35 ns ns ns ns ns ns ns ns ns ns Unit tAA tCO1 Chip enable access time (CE1) tCO2 Chip enable access time (CE2) tOE Output enable to output valid tOH Output hold from address change Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2 tOLZ Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) tHZ1∗, tHZ2∗ tOHZ∗ Output disable to output in high Z (OE) ∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z Symbol (Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C) -55LL Min. Max. — — — — — — — — — — 25 -70LL Min. 70 60 60 30 0 50 0 0 0 10 — Max. — — — — — — — — — — 25 -10LL Min. 100 70 70 40 0 70 0 0 0 10 — Max. — — — — — — — — — — 30 ns ns ns ns ns ns ns ns ns ns ns Unit tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗ 55 50 50 25 0 40 0 0 0 10 — ∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –5– CXK58512TM/M Timing Waveform • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2) : WE = VIH tRC Address tAA CE1 tCO 1 ttHZ HZ1 tLZ 1 CE2 tCO 2 tLZ 2 tHZ 2 OE tOE tOLZ Data out Data valid High impedance tOHZ –6– CXK58512TM/M • Write cycle (1) : WE control tWC Address tAW OE tCW CE1 tCW CE2 tAS WE tDW Data in tWHZ tOW Data out *2 High impedance *2 Data valid tDH tWP *1 tWR • Write cycle (2) : CE1 control tWC Address tAW OE tAS CE1 tCW CE2 tCW tWR1 *3 tWP WE tDW Data in Data valid tDH Data out High impedance –7– CXK58512TM/M • Write cycle (3) : CE2 control tWC Address tAW OE tCW CE1 tAS CE2 tCW tWR1 *3 tWP WE tDW Data in Data valid tDH Data out High impedance ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. –8– CXK58512TM/M Data retention waveform • Low supply voltage data retention waveform (1) (CE1 control) tCDRS VCC 4.5V 2.2V VDR CE1 CE1 VCC| 0.2V GND Data retention mode tR • Low supply voltage data retention waveform (2) (CE2 control) Data retention mode VCC 4.5V CE2 VDR 0.4V CE2 GND 0.2V tCDRS tR Data Retention Characteristics Item Data retention voltage Symbol VDR ∗ 0 to +70°C Data retention current ICCDR1 VCC = 3.0V∗ VCC = 2.0 to 5.5V∗ Chip disable to data retention mode 0 to +40°C +25°C ICCDR2 Data retention setup time tCDRS Recovery time tR Test conditions Min. 2.0 — — — — 0 5 Typ. — — — 0.2 0.4 — — (Ta = 0 to +70°C) Max. 5.5 6 1.2 0.6 10 — — µA ns ms µA Unit V ∗ CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control) –9– CXK58512TM/M Example of Representative Characteristics Supply current vs. Supply voltage ICC1, ICC2– Supply current (Relative Value) 1.5 1.2 Supply current vs. Ambient temperature ICC1, ICC2– Supply current (Relative Value) 1.25 1.1 ICC2 (Read) 1.0 ICC2 (Write) ICC1 0.9 VCC = 5.0V 0.8 1.0 ICC 2 ICC 1 Ta = 25°C 0.75 0.5 4.5 4.75 5 5.25 5.5 0 20 40 60 80 VCC – Supply voltage [V] Ta– Ambient temperature [°C] Supply current vs. Frequency 1.0 100ns 70ns 55ns Access time vs. Load capacitance TAA, TCO1, TCO2, TOE– Access time (Relative Value) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 VCC = 5.0V Ta = 25°C 0 100 200 300 400 TAA, TCO1, TCO2 TO E ICC2– Supply current (Relative Value) Write 0.8 Read 0.6 0.4 0.2 VCC = 5.0V Ta = 25°C 0 0 4 8 12 16 20 Frequency (1 / tRC, 1 / tWC) [ MHz] CL– Load capacity [pF] Access time vs. Supply voltage TAA, TCO1, TCO2, TOE– Access time (Relative Value) TAA, TCO1, TCO2, TOE– Access time (Relative Value) 1.4 1.4 Access time vs. Ambient temperature 1.2 TO E 1.2 TOE 1.0 TAA, TCO1, TCO2 1.0 TCO1, TCO2, TAA 0.8 Ta = 25°C 0.6 4.5 0.8 VCC = 5.0V 0.6 4.75 5 5.25 VCC– Supply voltage [V] 5.5 0 20 40 60 80 Ta– Ambient temperature [°C] – 10 – CXK58512TM/M Standby current vs. Supply voltage 2.0 20 Standby current vs. Ambient temperature ISB1, ISB2 – Standby current (Relative value) ISB1 – Standby current (Relative value) 10 5 1.5 1.0 2 1 0.5 VCC = 5.0V 0.2 ISB1 0.5 ISB2 Ta = 25°C 0 2.0 3.0 4.0 5.0 6.0 0 20 40 60 80 VCC – Supply voltage [V] Ta – Ambient temperature [°C] Input voltage level vs. Supply voltage 1.2 1.4 Standby current vs. Ambient temperature VIL, VIH – Input voltage (Relative value) ISB2 – Standby current (Relative value) 1.1 VIL, VIH 1.0 1.2 1.0 0.9 Ta = 25°C 0.8 4.5 0.8 VCC = 5.0V 0.6 4.75 5.0 5.25 VCC – Supply voltage [V] 5.5 0 20 40 60 80 Ta – Ambient temperature [°C] Output high current vs. Output high voltage 1.4 Output low current vs. Output low voltage IOL – Output low current (Relative value) IOH – Output high current (Ralative value) 1.8 1.2 1.4 1.0 1.0 0.8 VCC = 5.0V Ta = 25°C 0.6 1 2 3 4 VOH – Output high voltage [V] 5 0.6 VCC = 5.0V Ta = 25°C 0 0.2 0.4 0.6 0.8 VOL – Output low voltage [V] – 11 – CXK58512TM/M Package Outline Unit: mm CXK58512TM 32PIN TSOP (I) (PLASTIC) 8.0 ± 0.2 32 17 + 0.2 1.07 – 0.1 0.1 ∗18.4 ± 0.2 20.0 ± 0.2 0° to 10° DETAIL A A + 0.08 0.2 – 0.03 1 0.08 M 16 0.5 + 0.05 0.02 0.127 – NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP (I) -32P-L01 TSOP (I) 032-P-0820-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY CXK58512M 32PIN SOP (PLASTIC) 525mil + 0.4 20.5 – 0.1 32 17 0.1 + 0.15 2.9 – 0.25 + 0.3 11.2 – 0.1 14.0 ± 0.4 11.9 A 1 0.4 ± 0.1 1.27 16 + 0.1 0.15 – 0.05 0° to 10° 0.12 M DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-32P-L02 ∗SOP032-P-0525-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY – 12 – 0.8 ± 0.2 0.2 ± 0.1 0.5 ± 0.1 0.1 ± 0.1