CXK5V8257BYM

CXK5V8257BTM/BYM/BM -70LL/10LL 32768-word × 8-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. Description The CXK5V8257BTM/BYM/BM is 262,144 bits high speed CMOS static RAM organized as 32768words by 8 bits. A polysilicon TFT cell technology realized extermely low stand-by current and higher data retention stability. Operating on a single 3.3V supply, directly LVTTL compatible (All inputs and outputs). And special feature are, low power consumption, high speed and broad package line-up. The CXK5V8257BTM/BYM/BM is a suitable RAM for portable equipment with battery back up. Features • Single +3.3V supply: 3.3V ±0.3V • Directly LVTTL compatible: All inputs and outputs • Fast access time: (Access time) CXK5V8257BTM/BYM/BM -70LL 70ns (Max.) -10LL 100ns (Max.) • Low standby current: CXK5V8257BTM/BYM/BM -70LL/10LL 3.5µA (Max.) • Low power data retention: 2.0V (Min.) • Available in many packages CXK5V8257BTM/BYM 8mm × 13.4mm 28 pin TSOP Package CXK5V8257BM 450mil 28 pin SOP Package Function 32768-word × 8 bit static RAM Structure Silicon gate CMOS IC CXK5V8257BTM 28 pin TSOP (Plastic) CXK5V8257BYM 28 pin TSOP (Plastic) CXK5V8257BM 28 pin SOP (Plastic) Block Diagram A14 A13 A12 A11 A9 A8 A7 A6 A5 A10 A4 A3 A2 A1 A0 OE WE CE I /O1 I /O8 Buffer Row Decoder Memory Matrix 512 × 512 VCC GND Buffer I /O Gate Column Decoder Buffer I /O Buffer Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93836A5Z-ST CXK5V8257BTM/BYM/BM Pin Configuration (Top View) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 A3 A4 A5 A6 A7 A12 A14 Vcc WE A13 A8 A9 A11 OE 22 23 24 25 26 27 28 1 2 3 4 5 6 7 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 8 9 10 11 12 13 Pin Description A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE A10 Symbol A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O1 11 I/O2 12 I/O3 13 GND 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Description Address input data input/output Chip enable input Write enable input Output enable input +3.3V power supply Ground Vcc WE A13 A8 A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 A0 to A14 I/O1 to I/O8 CE WE OE VCC GND CXK5V8257BTM (Standard Pinout) CXK5V8257BYM (Mirror Image Pinout) 14 15 16 17 18 19 20 21 CXK5V8257BM Absolute Maximum Ratings Item Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature · time Symbol VCC VIN VI/O PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +4.6 –0.5∗1 to VCC + 0.5 –0.5∗1 to VCC + 0.5 0.7 0 to +70 –55 to +150 235 · 10 Unit V V V W °C °C °C · s ∗1 VIN, VI/O = –3.0V Min. for pulse width less than 50ns. Truth Table CE H L L L OE × H L × WE × H H L Mode Not selected Output disable Read Write I/O1 to I/O8 High Z High Z Data out Data in VCC Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 × : “H” or “L” DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min. 3.0 2.0 –0.3∗2 (Ta = 0 to +70°C, GND = 0V) Typ. 3.3 — — Max. 3.6 VCC + 0.3 0.8 V Unit ∗2 VIL = –3.0V Min. for pulse width less than 50ns. –2– CXK5V8257BTM/BYM/BM Electrical Characteristics • DC characteristics Item Symbol (VCC = 3.3V ± 0.3V, GND = 0V, Ta = 0 to +70°C) Test Conditions VIN = GND to VCC CE = VIH, OE = VIH or WE = VIL, VI/O = GND to VCC CE = VIL, VIN = VIH or VIL, IOUT = 0mA Min. cycle, Duty = 100%, IOUT = 0mA 70LL 10LL 0 to +70°C Min. –0.5 –0.5 Typ.∗1 — — Max. 0.5 0.5 Unit µA µA Input leakage current ILI Output leakage current ILO Operating power supply current ICC1 — — — — — — — 2.4 — 0.9 21 18 — — 0.12 0.06 — — 2 40 35 3.5 0.7 0.35 0.7 — 0.4 mA Average operating ICC2 current mA Standby current ISB1 CE ≥ VCC – 0.2V 0 to +40°C +25°C µA ISB2 Output high voltage Output low voltage VOH VOL CE = VIH IOH = –2mA IOL = 2.0mA mA V V ∗1 VCC = 3.3V, Ta = 25°C I/O capacitance Item Input capacitance I/O capacitance Symbol Test condition CIN CI/O VIN = 0V VI/O = 0V Min. — — (Ta = 25°C, f = 1MHz) Typ. — — Max. 8 10 Unit pF pF Note) This parameter is sampled and is not 100% tested. AC Characteristics • AC test conditions (VCC = 3.3V ± 0.3V, Ta = 0 to +70°C) Item Input pulse high level Input pulse low level Input rise time Input fall time Input and output reference level Output load conditions -70LL -10LL Conditions VIH = 2.0V VIL = 0.8V TTL tr = 5ns tf = 5ns 1.4V CL∗2 = 30pF, 1TTL CL∗2 = 100pF, 1TTL CL ∗2 CL includes scope and jig capacitances. –3– CXK5V8257BTM/BYM/BM • Read cycle (WE = “H”) -70LL Item Read cycle time Address access time Chip enable access time (CE) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in high Z (CE) Output disable to output in high Z (OE) ∗1 Symbol Min. 70 — — — 20 10 5 — — Max. — 70 70 35 — — — 30 30 -10LL Min. 100 — — — 20 10 10 — — Max. — 100 100 50 — — — 35 35 Unit ns ns ns ns ns ns ns ns ns tRC tAA tCO tOE tOH tLZ tOLZ tHZ∗1 tOHZ∗1 tHZ and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle -70LL Item Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE) Output active from end of write Write to output in high Z ∗2 Symbol Min. 70 60 60 30 0 55 0 0 0 10 — Max. — — — — — — — — — — 30 -10LL Min. 100 80 80 35 0 60 0 0 0 10 — Max. — — — — — — — — — — 35 Unit ns ns ns ns ns ns ns ns ns ns ns tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. –4– CXK5V8257BTM/BYM/BM Timing Waveform • Read cycle (1): CE = OE = VIL, WE = VIH tRC Address tAA tOH Data out Previous data valid Data valid • Read cycle (2): WE = VIH tRC Address tAA CE tCO tHZ tLZ OE tOE tOLZ Data out High impedance Data valid tOHZ • Write cycle (1): WE control tWC Address tAW OE tCW CE tAS WE tDW Data in tWHZ tOW Data out (∗2) High impedance (∗2) Data valid tDH tWP (∗1) tWR –5– CXK5V8257BTM/BYM/BM • Write cycle (2): CE control tWC Address tAW OE tAS CE tWP WE tDW Data in Data valid tDH tCW tWR1 (∗3) Data out High impedance ∗1 Write is executed when both CE and WE are at low simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is measured at the period from the rising edge of CE to the end of write cycle. –6– CXK5V8257BTM/BYM/BM Data retention waveform • Low supply voltage data retention waveform tCDRS VCC 3.0V 2.0V VDR CE GND Data retention mode tR CE ≥ VCC – 0.2V Data Retention Characteristics Item Symbol Test condiitions CE ≥ VCC – 0.2V 0 to +70°C Data retention current ICCDR1 VCC = 3.0V, CE ≥ 2.8V VCC = 2.0 to 3.6V, CE ≥ VCC – 0.2V Chip disable to data retention mode 0 to +40°C +25°C ICCDR2 Data retention setup time Recovery time Min. 2.0 — — — — 0 5 (Ta = 0 to +70°C) Typ. — — — 0.1 0.12∗1 — — Max. 3.6 3 0.6 0.3 3.5 — — µA ns ms µA Unit V Data retention voltage VDR tCDRS tR ∗1 VCC = 3.3V, Ta = 25°C –7– CXK5V8257BTM/BYM/BM Package Outline Unit: mm CXK5V8257BTM 28PIN TSOP (Plastic) ∗8.0 ± 0.1 21 8 1.2 MAX 0.1 ∗11.8 ± 0.1 13.4 ± 0.3 A 22 + 0.1 0.2 – 0.05 28 1 7 0.55 ± 0.1 + 0.07 0.127 – 0.02 + 0.1 0.05 – 0.05 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-28P-L01 TSOP028-P-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.2g CXK5V8257BYM 28PIN TSOP (Plastic) ∗8.0 ± 0.1 8 21 1.2 MAX 0.1 ∗11.8 ± 0.1 13.4 ± 0.3 A 0.5 ± 0.1 7 + 0.1 0.2 – 0.05 1 28 22 0.55 ± 0.1 + 0.1 0.05 – 0.05 + 0.07 0.127 – 0.02 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSOP-28P-L01R TSOP028-P-0000-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.2g –8– 0.5 ± 0.1 CXK5V8257BTM/BYM/BM CXK5V8257BM 28PIN SOP (PLASTIC) + 0.4 18.0 – 0.1 28 15 + 0.4 2.3 – 0.15 0.15 + 0.2 0.1 – 0.05 11.8 ± 0.4 + 0.3 8.4 – 0.1 1 14 0.4 ± 0.1 1.27 0° to 10° 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-28P-L05 ∗SOP028-P-0450 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.7g –9– 1.0 ± 0.2 + 0.1 0.05 0.15 –