CXK77V3211Q-12

CXK77V3211Q -12/14 32768-word by 32-bit High Speed Synchronous Static RAM For the availability of this product, please contact the sales office. Description The CXK77V3211Q is a 32K × 32 high performance synchronous SRAM with a 2-bit burst counter and output register. All synchronous inputs pass through register controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), four individual byte write enables (BW1, BW2, BW3, BW4), one byte write enable (BWE), and global write enable (SGW). Asynchronous inputs include the output enable (OE) and power down control (ZZ). Two mode control pins (LBO, FT) define four different operation modes: Linear/Interleaved burst sequence and Flow-Thru/Pipelined operations. WRITE cycles can be from one to four bytes wide as controlled by BW1 through BW4 and BWE or SGW. The output register is included on-chip and controlled by clock, it can be activated by connecting FT to high for high speed pipeline operation. Burst operation can be initiated with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Burst order sequence can be controlled by connecting LBO to high for Interleaved burst order (i486/Pentium™) or by connecting LBO to low for Linear burst order. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. WRITE pass through makes written data immediately available at the output register during READ cycle following a WRITE as controlled by OE. The CXK77V3211Q operates from a +3.3V power supply and all inputs and outputs are LVTTL compatible. The device is ideally suited for i486 and Pentium™ systems and those systems which benefit from a very wide data bus. 100 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • Fast address access times and High frequency operation Symbol -12 -14 Flow-through Access 12ns 14ns Cycle 60MHz 50MHz Pipeline Access 7ns 8ns Cycle 75MHz 66MHz • 5V tolerant inputs except I/O pins • A FT pin for pipelined or flow-thru architecture • A LBO mode pin as burst control pin (i486/Pentium™ and Linear burst sequence) • Single +3.3V +10% power supply – 5% • Common data inputs and data outputs • All inputs and outputs are LVTTL compatible • Four Individual BYTE WRITE enables, GLOBAL WRITE and BYTE WRITE ENABLE • Three Chip Enables for simple depth expansion • One cycle output disable for both pipelined and flow-thru operation • Internal input registers for address, data and control signals • Self-timed WRITE cycle • Write pass through capability • High 30pF output drive capability at rated access time • A ZZ pin for powerdown • 100-lead QFP package for high density, high speed operation i486/Pentium is a trademark of Intel Corp. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95721-PS Block Diagram 15 Address Register A1 A0 01 Mux A1 A0 A1' A0' Counter q1 Load q0 01 Mux 15 13 15 A0 to A14 ADV CLK LBO ADSC 8 Byte 4 Write Register 8 Byte 3 Write Register 8 Byte 2 Write Register 8 Byte 1 Write Register Byte 2 Write Driver 8 8 Byte 3 Write Driver 8 Byte 4 Write Driver ADSP SGW BWE BW4 –2– 8 Byte 1 Write Driver Enable Register 32 POWER DOWN DQ1 · · · DQ32 32 BW3 32K × 8 ×4 32 Sense 32 Output Output Memory Amps Registers Buffers Array BW2 32 BW1 32 Input Registers 4 CE CE2 CE2 OE FT CXK77V3211Q ZZ CXK77V3211Q Pin Configuration ADSC SGW BW3 BWE BW4 ADSP BW2 BW1 VDD VSS OE CE ADV CE2 CE2 CLK 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 A6 A7 A8 A9 80 NC 79 DQ16 78 DQ15 77 VDDq 76 Vssq 75 DQ14 74 DQ13 73 DQ12 72 DQ11 71 Vssq 70 VDDq 69 DQ10 68 DQ9 67 Vss 66 NC 65 VDD 64 ZZ 63 DQ8 62 DQ7 61 VDDq 60 59 58 Vssq DQ6 DQ5 57 DQ4 56 DQ3 55 Vssq 54 VDDq 53 DQ2 52 DQ1 51 NC DQ17 2 DQ18 3 VDDq 4 Vssq 5 DQ19 DQ20 DQ21 DQ22 6 7 8 9 Vssq 10 VDDq 11 DQ23 12 DQ24 13 FT 14 VDD 15 NC 16 Vss 17 DQ25 18 DQ26 19 VDDq 20 Vssq 21 DQ27 22 DQ28 23 DQ29 24 DQ30 25 Vssq 26 VDDq 27 DQ31 28 DQ32 29 NC 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A12 A10 A14 NC NC NC VDD NC A3 LBO –3– A11 A13 Vss NC NC A5 A1 A4 A2 A0 CXK77V3211Q Pin Description Symbol A0 to A14 I/O I Description Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Synchronous Individual Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A BYTE WRITE enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW1 controls DQ1 to DQ8. BW2 controls DQ9 to DQ16. BW3 controls DQ17 to DQ24. BW4 controls DQ25 to DQ32. Data I/O are tristated if any of these four inputs are LOW. Clock: This signal latches the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions internal use of ADSP. This input is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. Output Enable: This active LOW asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait status to be generated (no address advance). This pin must be HIGH at the rising edge of the first clock after an ADSP cycle is initiated if a WRITE cycle is desired (to ensure use of correct address). Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be latched. A READ is performed using the new address, independent of the byte write enables and ADSC but dependent upon CE2 and CE2. ADSP is ignored if CE is HIGH. Power down state is entered if CE2 is LOW or CE2 is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst and causes a new external address to be latched. A READ or WRITE is performed using the new address if all chip enables are active. Powerdown state is entered if one or more chip enables are inactive. No Connect: These signals are not internally connected. SRAM Data I/O: Byte 1 is DQ1 to DQ8; Byte 2 is DQ9 to DQ16; Byte 3 is DQ17 to DQ24; Byte 4 is DQ25 to DQ32. Input data must meet setup and hold times around the rising edge of CLK. Byte Write Enable: This active low input enables individual byte to write. Global Write: This active low input enables to write all bytes. Flow Through: This active low input selects flow through output. Linear Burst: This active high input selects interleaved burst sequence. ZZ: This active high input enables the device in powerdown mode. Power Supply: +3.3V +10% – 5% Ground: GND Isolated Output Buffer Supply: +3.3V +10% – 5% Isolated Output Buffer Ground: GND –4– BW1, BW2, BW3, BW4 I CLK I CE I CE2 I CE2 OE I I ADV I ADSP I ADSC NC DQ1 to DQ32 BWE SGW FT LBO ZZ VDD VSS VDDq VSSq I — I/O I I I I I Supply Supply Supply Supply CXK77V3211Q Interleaved Burst Sequence Table Operation A14 to A2 First access, latch external address Second access (first burst address) Third access (second burst address) Fourth access (third burst address) A14 to A2 latched A14 to A2 latched A14 to A2 latched A14 to A2 Address used A1 A1 latched A1 latched A1 latched A1 A0 A0 latched A0 latched A0 latched A0 Interleaved Burst Address Table First address X...X00 X...X01 X...X10 X...X11 Second address X...X01 X...X00 X...X11 X...X10 Third address X...X10 X...X11 X...X00 X...X01 Fourth address X...X11 X...X10 X...X01 X...X00 Linear Burst Address Table First address X...X00 X...X01 X...X10 X...X11 Second address X...X01 X...X10 X...X11 X...X00 Third address X...X10 X...X11 X...X00 X...X01 Fourth address X...X11 X...X00 X...X01 X...X10 Pass-Through Truth Table Previous cycle Operation Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) Initial WRITE cycle, one byte Address = A (n – 1), data = D (n – 1) BWs All L Present cycle Operation Initial READ cycle Register A (n), Q = D (n – 1) No new cycle Q = D (n – 1) No new cycle Q = HIGH-Z No new cycle Q = D (n – 1) for one byte CE L BWs H OE L Next cycle Operation Read D (n) All L H H L No carryover from previous cycle No carryover from previous cycle No carryover from previous cycle All L H H H One L H H L Note) Previous cycle may be either BURST or NONBURST cycle. –5– CXK77V3211Q Function Linear burst Interleaved burst LBO L H or NC Function Flow-thru output Pipelined output FT L or NC H Function Powerdown to ISB1 Active ZZ H L or NC Partial Truth Table Function READ READ WRITE byte 1 WRITE all bytes WRITE all bytes SGW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X Absolute Maximum Rating Item Supply voltage Input voltage Power dissipation Operating temperature Storage temperature Soldering temperature · time Symbol VDD VIN PD Topr Tstg Tsolder (Ta = 25°C, GND = 0V) Rating –0.5 to +4.6 –0.5 to 6 (Max.) 1.6 0 to +70 –55 to +150 235 · 10 Unit V V W °C °C °C · sec DC Recommended Operating Conditions Item Supply voltage Input high voltage Input low voltage Symbol VDD VIH VIL Min. 3.135 2.0 –0.3 Typ. 3.3 — — (Ta = 0 to +70°C, GND = 0V) Max. 3.63 5.5 0.8 Unit V V V Note 1 1, 2 1, 2 Note) 1. All voltage referenced to VSS (GND). 2. Overshoot: VIH ≤ VDD + 2.0V for t ≤ tKC/2. Undershoot: VIL ≥ –2.0V for t ≤ tKC/2. –6– CXK77V3211Q DC and Operating Characteristics Item Input leakage current Output leakage current Operating supply current Static CMOS supply current Standby current Deselect supply current Output High voltage Output Low voltage ILI ILO IDD-0MHz IDD-66MHz IDD-80MHz IDD1-0MHz ISB1 ISB2-0MHz ISB2-66MHz ISB2-80MHz VOH VOL Symbol (VDD = 3.3V +10% , GND = 0V, Ta = 0 to +70°C) – 5% Test condition VIN = GND to VDD Output disabled, VOUT = GND to VDD Device selected; all inputs ≤ VIL or ≥ VIH; cycle time ≥ tKC min, VDD = MAX; outputs open All inputs ≤ 0.2V or ≥ VDD – 0.2V ZZ ≥ VDD –0.2V, All inputs ≤ 0.2V or ≥ VDD – 0.2V Device deselect IOH = –5.0mA IOL = 5.0mA Min. –1 –1 Max. 1 1 20 210 250 20 20 20 120 140 — 0.4 Unit µA µA — mA — — mA mA — 2.4 — mA V V DC and Operating Characteristics for Special Modes-pins Mode-pins FT ZZ LBO VIN ≥ VIH + 0.5V < VIH + 0.5V ≥ VIL < VIL ILI < 1µA > 10KΩ to VSS < 1µA > 10KΩ to VDD These Mode-pin input buffers (FT, ZZ, LBO) have special self-bias circuit to protect against coupling noise when these pins are not connected during normal operations. –7– CXK77V3211Q AC Electrical Characteristics Item Clock to output valid Flow-thru Clock to output invalid Clock to output in Low-Z Clock cycle time Clock to output valid Pipeline Clock to output invalid Clock to output in Low-Z Clock cycle time Clock HIGH time Clock LOW time Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup time Hold time ZZ setup ZZ hold ZZ recovery (VDD = 3.3V +10% , Ta = 0 to +70°C) – 5% -12 Symbol -14 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Min. Max. — 3 3 16.6 — 2 2 13 3.5 3.5 — — 0 — 2.5 0.5 5 1 20 12 — — — 7 — — — — — 5 5 — 5 — — — — — — 3 3 20 — 2 2 15 4 4 — — 0 — 2.5 0.5 5 1 20 14 — — — 8 — — — — — 6 6 — 6 — — — — — tKQ tKQX tLZ2 tKC tKQ tKQX tLZ2 tKC tKH tKL tHZ2 tOE tOLZ2 tOHZ2 tS tH tZZS3 tZZH3 tZZR 1. All parameters are specified over the range 0 to 70°C. 2. These parameters are sampled and are not 100% tested. 3. Signal is asynchronous, however, to be recognized on any given clock the signal must meet specified setup and hold times. –8– CXK77V3211Q I/O capacitance Item Input capacitance I/O capacitance Symbol CIN COUT Test condition VIN = 0V VI/O = 0V (Ta = 25°C, f = 1MHz) Typ. 4 6 Max. 5 7 Unit pF pF This parameter is sampled and is not 100% tested. AC Test Conditions (VDD = 3.3V +10% , Ta = 0 to +70°C) – 5% Item Input pulse high level Input pulse low level Input rise time Input fall time Input reference level Output reference level Output load conditions Conditions VIH = 2.8V VIL = 0V I/O Zo = 50Ω ∗30pF 50Ω tr = 1V/ns tf = 1V/ns 1.4V 1.4V Fig. 1 and Fig. 2 VT = 1.4V Output load (1) Fig. 1. +3.3V ∗ Include scope and jig capacitance. ∗ Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. ∗ Output load (2) for tLZ and tHZ, tOLZ and tOHZ. 295Ω I/O ∗5pF 217Ω Output load (2) Fig. 2. –9– CXK77V3211Q Truth Tables Operation Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down READ cycle, begin burst READ cycle, begin burst WRITE cycle, begin burst READ cycle, begin burst READ cycle, begin burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst WRITE cycle, continue burst WRITE cycle, continue burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst WRITE cycle, suspend burst WRITE cycle, suspend burst Address used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L L L X X H H X H X X H H X H CE2 CE2 ADSP ADSC ADV BWx OE CLK X X H X H L L L L L X X X X X X X X X X X X X L X L X H H H H H X X X X X X X X X X X X X L L H H L L H H H H H X X H X H H X X H X L X X L L X X L L L H H H H H H H H H H H H X X X X X X X X X X L L L L L L H H H H H H X X X X X X X L H H H H H H L L H H H H L L X X X X X L H X L H L H L H X X L H L H X X DQ L-H High-Z L-H High-Z L-H High-Z L-H High-Z L-H High-Z L-H Q L-H High-Z L-H L-H D Q L-H High-Z L-H Q L-H High-Z L-H Q L-H High-Z L-H L-H L-H D D Q L-H High-Z L-H Q L-H High-Z L-H L-H D D Note) 1. X means "don't care". H means logic HIGH. L means logic LOW. BWx = L means any one or more byte write enable signals (BW1, BW2, BW3, BW4) are LOW. BWx = H means all byte write enable signals are HIGH. 2. BW1 enables writes to Byte 1 (DQ1 to DQ8). BW2 enables writes to Byte 2 (DQ9 to DQ16). BW3 enables writes to Byte 3 (DQ17 to DQ24). BW4 enables writes to Byte 4 (DQ25 to DQ32). 3. All inputs except OE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Wait states are inserted by suspending burst. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in HIGH-Z during power-up. 7. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. – 10 – CXK77V3211Q Read Timing (Pipeline) tKC CLK tKH tKL tS tH ADSP tS tH ADSC tS ADDR. A1 tS tH BW1 to BW4 tS CE (∗2) tS ADV ADV suspends burst OE tOE High-Z Q tKQ (∗1) Burst wrap around to its initial state. Burst READ tLZ Q (A1) tH A2 A3 A4 Burst continued with new base address tH Deselect cycle tH tOHZ tOLZ tKQ tKQX Q (A2) Q (A2 + 1) Q (A2 + 2) Q (A2 + 3) Q (A2) (∗3) tHZ Q (A2 + 1) Single READ DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW. ∗3 On deselect cycle, Q is tri-stated immediately on the same cycle CE is LOW. – 11 – CXK77V3211Q Write Timing (Pipeline) tKC CLK tKH tKL tS tH ADSP tS tH ADSC tS ADDR. A1 tH A2 BYTE WRITE signal are ignored for first cycle when ADSP intiates burst BW1 to BW4 tS tH CE (∗2) tS ADV (∗4) OE ADV suspends burst tH A3 tS tH ADSC extends burst tS tH (∗3) tS tH High-Z D D (A1) D (A2) D (A2 + 1) D (A2 + 1) D (A2 + 2) D (A2 + 3) D (A3) D (A3 + 1) D (A3 + 2) tOHZ Q Burst READ Single WRITE (∗1) Burst WRITE Extended Burst WRITE DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. ∗3 OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. ∗4 ADV must be HIGH to permit a WRITE to the loaded address. – 12 – CXK77V3211Q Read/Write Timing (Pipeline) tKC CLK tKH tKL tS tH ADSP ADSC tS ADDR. A1 tH A2 tS tH A3 BW1 to BW4 tS CE (∗2) tH ADV OE tS tOHZ Q (A1) High-Z D High-Z Q tKQ tLZ tH tOLZ tKQ Q (A2) D (A2) (∗1) Q (A3) Q (A3 + 1) Q (A3 + 2) Single READ Single WRITE Pass Through READ Burst READ DON'T CARE UNDEFINED ∗1 Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from the next internal burst address following A3. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. – 13 – CXK77V3211Q Read Timing (Flow-Thru) tKC CLK tKH tKL tS tH ADSP tS tH ADSC tS ADDR. A1 tS tH BW1 to BW4 tS CE (∗2) tS ADV ADV suspends burst OE tOE High-Z Q tKQ (∗1) Single READ Burst READ Burst wrap around to its initial state. tLZ Q (A1) Q (A2) Q (A2 + 1) Q (A2 + 2) Q (A2 + 3) Q (A2) Q (A2 + 1) Q (A3) tH A2 A3 tH tH tOHZ tOLZ tKQ tKOX tHZ DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW. – 14 – CXK77V3211Q Write Timing (Flow-Thru) tKC CLK tKH tKL tS tH ADSP ADSC extends burst tS tH ADSC tS ADDR. A1 tH A2 BYTE WRITE signal are ignored for first cycle when ADSP intiates burst BW1 to BW4 tS CE (∗2) tS ADV (∗4) OE ADV suspends burst tH tH A3 tS tH tS tH (∗3) tS High-Z tH D (A2) D (A2 + 1) D (A2 + 1) D (A2 + 2) D (A2 + 3) D (A3) D (A3 + 1) D (A3 + 2) D D (A1) tOHZ Q Burst READ Single WRITE (∗1) Burst WRITE Extended Burst WRITE DON'T CARE UNDEFINED ∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. ∗3 OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period to the byte write enable inputs being sampled. ∗4 ADV must be HIGH to permit a WRITE to the loaded address. – 15 – CXK77V3211Q Read/Write Timing (Flow-Thru) tKC CLK tKH tKL tS tH ADSP ADSC tS ADDR. A1 tH A2 tS tH A3 BW1 to BW4 tS CE (∗2) tH ADV OE tS High-Z D High-Z Q Q (A1) Q (A3) tH tOLZ tKQ (∗1) Q (A3 + 1) Q (A3 + 2) Q (A3 + 3) tOHZ D (A2) Single READ Single WRITE Burst READ DON'T CARE UNDEFINED ∗1 Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from the next internal burst address following A3. ∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. – 16 – CXK77V3211Q ZZ Timing tKC CLK tKH tS tH ADSP tKL ADSC tZZS ZZ tZZH tZZR Snooze – 17 – CXK77V3211Q Package Outline Unit: mm 100PIN QFP (PLASTIC) 1420 23.2 ± 0.2 ∗20.0 ± 0.1 80 81 51 50 B ∗14.0 ± 0.1 17.2 ± 0.2 (15.4) A 100 1 0.65 0.12 M 0.25 + 0.15 0.1 – 0.05 0.1 31 30 + 0.35 2.75 – 0.15 + 0.08 0.32 – 0.07 (0.3) 15.6 ± 0.2 (15.4) (0.8) + 0.13 0.9 – 0.15 0° to 10° 1.6 ± 0.2 DETAIL B DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L02 ∗QFP100-P-1420-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER 1.7g – 18 – (0.15) + 0.04 0.17 – 0.03