CXK79M36C165GB

SONY ΣRAM™ Description CXK79M72C165GB / CXK79M36C165GB 3/33/4 18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36) Preliminary The CXK79M72C165GB (organized as 262,144 words by 72 bits) and the CXK79M36C165GB (organized as 524,288 words by 36 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAM™ devices. They integrate input registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Double Late Write (DLW) write operations are supported, providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-synchronous operation. All address and control input signals are registered on the rising edge of the CK input clock. During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control signals are registered. During write operations, input data is registered once, on the rising edge of CK, two full cycles after the address and control signals are registered. Output drivers are series-terminated, and output impedance is selectable via the ZQ control pin. When ZQ is tied “low”, the impedance of the SRAM’s output drivers is set to ~25Ω. When ZQ is tied “high” or left unconnected, the impedance of the SRAM’s output drivers is set to ~50Ω. 333 MHz operation (333 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol. Features • 3 Speed Bins -3 -33 -4 Cycle Time / Data Access Time 3.0ns / 2.0ns 3.3ns / 2.0ns 4.0ns / 2.1ns • Single 1.8V power supply (VDD): 1.7V or 1.75V (min) to 1.95V (max) • Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max) • LVCMOS-compatible I/O interface • Common I/O • Single Data Rate (SDR) data transfers • Pipelined (PL) read operations • Double Late Write (DLW) write operations • Burst capability with internally controlled Linear Burst address sequencing • Burst length of two, three, or four, with automatic address wrap • Full read/write data coherency • Byte write capability • Single-ended input clock (CK) • Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2) • Selectable output driver impedance via dedicated control pin (ZQ) • Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3) • JTAG boundary scan (subset of IEEE standard 1149.1) • 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package 18Mb 1x1Dp, LVCMOS, rev 1.3 1 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB 256Kb x 72 Pin Assignment (Top View) Preliminary 1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQg DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQd DQd DQd DQd DQd 2 DQg DQg DQg DQg DQc DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQh DQd DQd DQd DQd 3 A Bc Bh VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 Bg Bd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A NC (x36) NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A 6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD MCL A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A 8 E3 Bb Be NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A Bf Ba VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb DQf DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQb DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQe DQe DQe DQe DQe 18Mb 1x1Dp, LVCMOS, rev 1.3 2 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB 512Kb x 36 Pin Assignment (Top View) Preliminary 1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC DQc DQc DQc DQc CQ2 NC NC NC NC DQd DQd DQd DQd DQd 2 NC NC NC NC DQc DQc DQc DQc DQc CQ2 NC NC NC NC NC DQd DQd DQd DQd 3 A Bc NC VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 NC Bd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A A (x36) NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A 6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD MCL A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A 8 E3 Bb NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A NC Ba VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb NC NC NC NC NC CQ1 DQa DQa DQa DQa DQa NC NC NC NC 11 DQb DQb DQb DQb DQb NC NC NC NC CQ1 DQa DQa DQa DQa NC NC NC NC NC 18Mb 1x1Dp, LVCMOS, rev 1.3 3 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Pin Description Preliminary Symbol A A1, A0 DQa, DQb DQc, DQd DQe, DQf DQg, DQh Type Input Input I/O Quantity x72 = 16 x36 = 17 2 x72 = 72 x36 = 36 Description Address Inputs - Registered on the rising edge of CK. Address Inputs 1,0 - Registered on the rising edge of CK. Initialize burst counter. Data Inputs / Outputs - Registered on the rising edge of CK during write operations. Driven from the rising edge of CK during read operations. DQa - indicates Data Byte a DQb - indicates Data Byte b DQc - indicates Data Byte c DQd - indicates Data Byte d DQe - indicates Data Byte e DQf - indicates Data Byte f DQg - indicates Data Byte g DQh - indicates Data Byte h Input Clock Output Clocks Chip Enable Control Input - Registered on the rising edge of CK. E1 = 0 enables the device to accept read and write commands. E1 = 1 disables the device. See the Clock Truth Table section for further information. Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See the Clock Truth Table and Depth Expansion sections for further information. Programmable Chip Enable Active-Level Select Inputs - These pins must be tied “high” or “low” at power-up. See the Clock Truth Table and Depth Expansion sections for further information. Address Advance Control Input - Registered on the rising edge of CK. ADV = 0 loads a new address and begins a new operation when the device is enabled. ADV = 1 increments the address and continues the previous operation when the device is enabled. See the Clock Truth Table section for further information. Write Enable Control Input - Registered on the rising edge of CK. W = 0 specifies a write operation when ADV = 0 and the device is enabled. W = 1 specifies a read operation when ADV = 0 and the device is enabled. See the Clock Truth Table section for further information. Byte Write Enable Control Inputs - Registered on the rising edge of CK. Ba = 0 specifies write Data Byte a during a write operation Bb = 0 specifies write Data Byte b during a write operation Bc = 0 specifies write Data Byte c during a write operation Bd = 0 specifies write Data Byte d during a write operation Be = 0 specifies write Data Byte e during a write operation Bf = 0 specifies write Data Byte f during a write operation Bg = 0 specifies write Data Byte g during a write operation Bh = 0 specifies write Data Byte h during a write operation See the Clock Truth Table section for further information. Output Impedance Control Input - This pin must be tied “high” or “low” at power-up. ZQ = 0 selects ~25Ω output impedance ZQ = 1 selects ~50Ω output impedance Note: This pin can also be left unconnected. It is weakly pulled “high” internally. CK CQ1, CQ1 CQ2, CQ2 E1 Input Output Input 1 4 1 E2, E3 EP2, EP3 Input Input 2 2 ADV Input 1 W Input 1 Ba, Bb, Bc Bd, Be, Bf Bg, Bh Input x72 = 8 x36 = 4 ZQ Input 1 18Mb 1x1Dp, LVCMOS, rev 1.3 4 / 29 November 18, 2003 SONY® ΣRAM Symbol VDD VDDQ VSS TCK TMS TDI TDO MCL MCH NC Input Input Input Output *Input* *Input* Type Quantity 14 24 30 1 1 1 1 5 3 x72 = 18 x36 = 57 CXK79M72C165GB / CXK79M36C165GB Description 1.8V Core Power Supply - Core supply voltage. Output Power Supply - Output buffer supply voltage. Ground JTAG Clock JTAG Mode Select - Weakly pulled “high” internally. JTAG Data In - Weakly pulled “high” internally. JTAG Data Out Must Connect “Low” - May not be actual input pins. Must Connect “High” - May not be actual input pins. Preliminary No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VSS. 18Mb 1x1Dp, LVCMOS, rev 1.3 5 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Clock Truth Table Preliminary CK ↑ ↑ ↑ ↑ ↑ E1 E ADV W B (tn) (tn) (tn) (tn) (tn) X X 1 X 0 F X T X T 0 1 0 1 0 X X X X 0 X X X X T Previous Operation X Bank Deselect X Deselect X Current Operation Bank Deselect Bank Deselect (Continue) Deselect Deselect (Continue) Write Loads new address Stores DQx if Bx = 0 Write (Abort) Loads new address No data stored Write Continue Increments address by 1 Stores DQx if Bx = 0 Write Continue (Abort) Increments address by 1 No data stored Read Loads new address Read Continue Increments address by 1 DQ/CQ (tn) *** Hi-Z *** Hi-Z/CQ *** DQ/CQ (tn+1) Hi-Z Hi-Z Hi-Z/CQ Hi-Z/CQ Hi-Z/CQ DQ/CQ (tn+2) --------D1/--- ↑ 0 T 0 0 F X *** Hi-Z/CQ X/--- ↑ X X 1 X T Write Hi-Z/CQ D1/CQ D2/--- ↑ X X 1 X F Write Hi-Z/CQ D1/CQ X/--- ↑ ↑ Notes: 0 X T X 0 1 1 X X X X Read *** Q1/CQ Q1/CQ Q2/CQ ----- 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. “***” indicates that the DQ input requirement or output state and the CQ output state are determined by the previous operation. 3. “---” indicates that the DQ input requirement or output state and the CQ output state are determined by the next operation. 4. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”. 5. If one or more Bx = 0 then B = “T” else B = “F”. 6. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled. 7. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled. 8. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address. 18Mb 1x1Dp, LVCMOS, rev 1.3 6 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB State Diagram X,F,0,X or X,X,1,X Preliminary 0,T,0,1 Bank Deselect 1,T,0,X 0,T,0,0 X,F,0,X Deselect 0,T,0,1 0,T,0,0 1,T,0,X or X,X,1,X 1,T,0,X 0,T,0,0 1,T,0,X Read X,F,0,X 0,T,0,1 X,X,1,X 0,T,0,1 Write X,F,0,X 0,T,0,0 X,X,1,X 0,T,0,1 1,T,0,X X,F,0,X 0,T,0,0 0,T,0,0 0,T,0,1 Read Continue X,X,1,X Write Continue X,X,1,X 1,T,0,X X,F,0,X Notes: 1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively. 2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 3. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”. 18Mb 1x1Dp, LVCMOS, rev 1.3 7 / 29 November 18, 2003 SONY® ΣRAM •Burst (Continue) Operations CXK79M72C165GB / CXK79M36C165GB Preliminary Burst operations follow the Linear Burst address sequence depicted in the table below: A(1:0) 1st (Base) Address 2nd Address 3rd Address 4th Address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sequence Key A1, A0 (A1 xor A0), A0 A1, A0 (A1 xor A0), A0 Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address. •Depth Expansion Depth expansion in these devices is supported via programmable chip enables E2 and E3. The active levels of E2 and E3 are programmable through the static inputs EP2 and EP3 respectively. When EP2 is tied “high”, E2 functions as an active-high input. When EP2 is tied “low”, E2 functions as an active-low input. Similarly, when EP3 is tied “high”, E3 functions as an active-high input. And, when EP3 is tied “low”, E3 functions as an active-low input. The programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming E2 and E3 of four devices in a binary sequence (00, 01, 10, 11), and by driving E2 and E3 with external address signals, the four devices can be made to look like one larger device. When these devices are deselected via chip enable E1, the output clocks continue to toggle. However, when these devices are deselected via programmable chip enables E2 or E3, the output clocks are forced to a Hi-Z state. See the Clock Truth Table for further information. •Output Driver Impedance Control The impedance of the data and clock output drivers in these devices can be controlled via the static input ZQ. When ZQ is tied “low”, output driver impedance is set to ~25Ω. When ZQ is tied “high” or left unconnected, output driver impedance is set to ~50Ω. See the DC Electrical Characteristics section for further information. •Power-Up Sequence For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information. 18Mb 1x1Dp, LVCMOS, rev 1.3 8 / 29 November 18, 2003 SONY® ΣRAM •Absolute Maximum Ratings Parameter Supply Voltage Output Supply Voltage CXK79M72C165GB / CXK79M36C165GB Preliminary Symbol VDD VDDQ VIN VMIN VTIN TA TA TJ TSTG Rating -0.5 to +2.5 -0.5 to +2.3 -0.5 to VDDQ+0.5 (2.3V max) -0.5 to VDD+0.5 (2.5V max) -0.5 to VDD+0.5 (2.5V max) 0 to 70 0 to 85 0 to 110 -55 to 150 Units V V V V V °C °C °C °C Input Voltage (Address, Control, Data, Clock) Input Voltage (EP2, EP3, MCL, MCH, ZQ) Input Voltage (TCK, TMS, TDI) Operating Temperature (-3, -33) Operating Temperature (-4) Junction Temperature Storage Temperature Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. •BGA Package Thermal Characteristics Parameter Junction to Case Temperature Symbol ΘJC Rating 3.6 Units °C/W •I/O Capacitance Parameter Address Input Capacitance Control CK Clock Data Output Capacitance CQ Clock Symbol CIN CIN CKIN COUT COUT Test conditions VIN = 0V VIN = 0V VKIN = 0V VOUT = 0V VOUT = 0V Min ----------- (TA = 25oC, f = 1 MHz) Max 3.5 3.5 4.0 4.5 4.5 Units pF pF pF pF pF Note: These parameters are sampled and are not 100% tested. 18Mb 1x1Dp, LVCMOS, rev 1.3 9 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary (VSS = 0V, TA = 0 to 85oC) •DC Recommended Operating Conditions Parameter Supply Voltage (-3, -33) Supply Voltage (-4) Output Supply Voltage Input High Voltage (Address, Control, Data, Clock) Input Low Voltage (Address, Control, Data, Clock) Input High Voltage (EP2, EP3, MCH, ZQ) Input Low Voltage (EP2, EP3, MCL, ZQ) 1. TA = 0 to 70°C for -3 and -33 speed bins. Symbol VDD VDD VDDQ VIH VIL VMIH VMIL Min 1.75 1.7 1.4 VDDQ/2 + 0.3 -0.3 VDDQ/2 + 0.4 -0.3 Typ 1.8 1.8 ----------- Max 1.95 1.95 VDD VDDQ + 0.3 VDDQ/2 - 0.3 VDD + 0.3 VDDQ/2 - 0.4 Units V V V V V V V Notes 1 2 3 2. VIH (max) AC = VDDQ + 0.9V for pulse widths less than one-quarter of the cycle time (tCYC/4). 3. VIL (min) AC = -0.9V for pulse widths less than one-quarter of the cycle time (tCYC/4). 18Mb 1x1Dp, LVCMOS, rev 1.3 10 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary •DC Electrical Characteristics (Note 1) Parameter Input Leakage Current (Address, Control, Clock) Input Leakage Current (EP2, EP3) Input Leakage Current (MCH) Input Leakage Current (MCL) Output Leakage Current Average Power Supply Operating Current (x72) Average Power Supply Operating Current (x36) Power Supply Deselect Operating Current Output High Voltage Output Low Voltage Symbol ILI IMLI1 IMLI2 IMLI3 ILO IDD-3 IDD-33 IDD-4 IDD-3 IDD-33 IDD-4 IDD2-3 IDD2-33 IDD2-4 VOH VOL Test Conditions VIN = VSS to VDDQ VMIN = VSS to VDD VMIN = VMIH (min) to VDD VMIN = VSS to VMIL (max) VOUT = VSS to VDDQ IOUT = 0 mA VIN = VIH or VIL IOUT = 0 mA VIN = VIH or VIL IOUT = 0 mA VIN = VIH or VIL IOH = -6.0 mA ZQ = VIH IOL = 6.0 mA ZQ = VIH VOH, VOL = VDDQ/2 ZQ = VIL VOH, VOL = VDDQ/2 ZQ = VIH (VDD = 1.7V to 1.95V, VSS = 0V, TA = 0 to 85oC) Min -5 -10 -10 -10 -10 --------------Typ ------------------------Max 5 10 10 10 10 820 750 650 640 580 500 305 280 250 --0.4 33 65 Units uA uA uA uA uA mA Notes mA mA VDDQ - 0.4 --17 35 ----25 50 V V Ω Ω Output Driver Impedance ROUT 1. VDD = 1.75V to 1.95V and TA = 0 to 70°C for -3 and -33 speed bins. 18Mb 1x1Dp, LVCMOS, rev 1.3 11 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary •AC Electrical Characteristics (Note 4) -3 Parameter Symbol Min Input Clock Cycle Time Input Clock High Pulse Width Input Clock Low Pulse Width Address Input Setup Time Address Input Hold Time Control Input Setup Time Control Input Hold Time Data Input Setup Time Data Input Hold Time Input Clock High to Output Data Valid Input Clock High to Output Data Hold Input Clock High to Output Data Low-Z Input Clock High to Output Data High-Z Input Clock High to Output Clock High Input Clock High to Output Clock Low-Z Input Clock High to Output Clock High-Z Output Clock High to Output Data Valid Output Clock High to Output Data Hold tKHKH tKHKL tKLKH tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX tKHQV tKHQX tKHQX1 tKHQZ tKHCH tKHCX1 tKHCZ tCHQV tCHQX 3.0 1.2 1.2 0.7 0.4 0.7 0.4 0.7 0.4 --0.5 0.5 --0.5 0.5 -----0.38 Max ------------------2.0 ----2.0 2.0 --2.0 0.38 --- (VDD = 1.7V to 1.95V, VSS = 0V, TA = 0 to 85oC) -33 Min 3.3 1.3 1.3 0.7 0.4 0.7 0.4 0.7 0.4 --0.5 0.5 --0.5 0.5 -----0.38 Max ------------------2.0 ----2.0 2.0 --2.0 0.38 --Min 4.0 1.5 1.5 0.8 0.5 0.8 0.5 0.8 0.5 --0.5 0.5 --0.5 0.5 -----0.45 -4 Units Notes Max ------------------2.1 ----2.1 2.1 --2.1 0.45 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2 2 2 2,3 2,3 1 1 All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted. 1. These parameters apply to control inputs E1, E2, E3, ADV, W, and Bx. 2. These parameters are guaranteed by design through extensive corner lot characterization. 3. These parameters are measured at ± 50mV from steady state voltage. 4. VDD = 1.75V to 1.95V and TA = 0 to 70°C for -3 and -33 speed bins. 18Mb 1x1Dp, LVCMOS, rev 1.3 12 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary •AC Electrical Characteristics (Note) The two AC timing parameters listed below are tested according to specific combinations of Output Clocks (CQs) and Output Data (DQs): 1. tCHQV 2. tCHQX Output Clock High to Output Data Valid (max) Output Clock High to Output Data Hold (min) The specific CQ / DQ combinations are defined as follows: 256Kb x 72 CQs 1K, 2K DQs 1A, 2A, 1B, 2B, 1C, 2C, 1D, 2D, 1E, 2E, 1F, 2F, 1G, 2G, 1H, 2H, 1J, 2J, 1L, 2L, 1M, 2M, 1N, 2N, 1P, 2P, 2R, 1R, 1T, 2T, 1U, 2U, 1V, 2V, 1W, 2W CQs 1K, 2K 512Kb x 36 DQs 2E, 1F, 2F, 1G, 2G, 1H, 2H, 1J, 2J, 1R, 1T, 2T, 1U, 2U, 1V, 2V, 1W, 2W 10K, 11K 10A, 11A, 10B, 11B, 10C, 11C, 10D, 11D, 11E, 10E, 10F, 11F, 10G, 11G, 10H, 11H, 10J, 11J, 10L, 11L, 10M, 11M, 10N, 11N, 10P, 11P, 10R, 11R, 10T, 11T, 10U, 11U, 10V, 11V, 10W, 11W 10K, 11K 10A, 11A, 10B, 11B, 10C, 11C, 10D, 11D, 11E, 10L, 11L, 10M, 11M, 10N, 11N, 10P, 11P, 10R 18Mb 1x1Dp, LVCMOS, rev 1.3 13 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary •AC Test Conditions (VDDQ = 1.8V) Parameter Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions VKIH VKIL Symbol VIH VIL Conditions 1.4 0.4 2.0 0.9 1.4 0.4 2.0 0.9 0.9 ZQ = VIH (VDD = 1.7V to 1.95V, TA = 0 to 85°C) Units V V V/ns V V V V/ns V V See Figure 1 below Notes 1. VDD = 1.75V to 1.95V and TA = 0 to 70°C for -3 and -33 speed bins. Figure 1: AC Test Output Load (VDDQ = 1.8V) 0.9 V 16.7 Ω 50 Ω 50 Ω 5 pF DQ 16.7 Ω 0.9 V 16.7 Ω 50 Ω 50 Ω 5 pF 18Mb 1x1Dp, LVCMOS, rev 1.3 14 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary •AC Test Conditions (VDDQ = 1.5V) Parameter Input High Level Input Low Level Input Rise & Fall Time Input Reference Level Clock Input High Voltage Clock Input Low Voltage Clock Input Rise & Fall Time Clock Input Reference Level Output Reference Level Output Load Conditions VKIH VKIL Symbol VIH VIL Conditions 1.25 0.25 2.0 0.75 1.25 0.25 2.0 0.75 0.75 ZQ = VIH (VDD = 1.7V to 1.95V, TA = 0 to 85°C) Units V V V/ns V V V V/ns V V See Figure 2 below Notes 1. VDD = 1.75V to 1.95V and TA = 0 to 70°C for -3 and -33 speed bins. Figure 2: AC Test Output Load (VDDQ = 1.5V) 0.75 V 16.7 Ω 50 Ω 50 Ω 5 pF DQ 16.7 Ω 0.75 V 16.7 Ω 50 Ω 50 Ω 5 pF 18Mb 1x1Dp, LVCMOS, rev 1.3 15 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB One Bank Read-Write-Read Timing Diagram Figure 3 Preliminary Read Read Continue Read Deselect Write Write Continue Write Deselect Read Deselect Deselect (Continue) CK tAVKH tKHAX tKHKH tKHKL tKLKH A A1 A2 A3 tBVKH tKHBX A4 A5 E1 ADV W Bx tKHQV tKHQX tKHQZ tDVKH tKHDX tKHQX1 DQ Q11 Q12 tCHQX tCHQV Q21 D31 D32 D41 Q51 tKHCH CQ CQ Note: In the diagram above, a Deselect operation is inserted between Read and Write operations to control the data bus transition from output to input. Similarly, a Deselect operation is inserted between Write and Read operations to control the data bus transition from input to output. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, these Deselect operations may not be necessary. Note: E1 = EP1 and E2 = EP2 in this example (not shown). 18Mb 1x1Dp, LVCMOS, rev 1.3 16 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Two Bank Read-Write-Read Timing Diagram Figure 4 Preliminary B1: B2: Read B-Deselect B-Deselect B-Deselect B-Deselect R-Continue B-Deselect Deselect B-Deselect B-Deselect Write B-Deselect B-Deselect Read B-Deselect Write W-Continue B-Deselect Deselect Read Deselect Deselect CK A A1 A2 A3 A4 A5 E2 E1 ADV W Bx DQ (B1) Q11 Q12 D41 DQ (B2) tKHCZ Q21 tKHCX1 D31 D32 Q51 CQ (B1) CQ (B1) CQ (B2) CQ (B2) Note: In the diagram above, a Deselect operation is inserted between Read and Write operations to control the data bus transition from output to input. Similarly, a Deselect operation is inserted between Write and Read operations to control the data bus transition from input to output. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, these Deselect operations may not be necessary. Note: Bank 1 EP1 = “low”, Bank 2 EP1 “high”, and Bank 1 and Bank 2 E2 = EP2 in this example (not shown). 18Mb 1x1Dp, LVCMOS, rev 1.3 17 / 29 November 18, 2003 SONY® ΣRAM •Test Mode Description CXK79M72C165GB / CXK79M36C165GB Preliminary These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1 functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers). The TAP consists of the following four signals: TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Induces (clocks) TAP Controller state transitions. Inputs commands to the TAP Controller. Sampled on the rising edge of TCK. Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK. Outputs data serially from the TAP Registers. Driven from the falling edge of TCK. Disabling the TAP When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied “high” through a pull-up resistor or left unconnected. TDO should be left unconnected. Note: Operation of the TAP does not disrupt normal SRAM operation except when the EXTEST-A or SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device. JTAG DC Recommended Operating Conditions Parameter JTAG Input High Voltage (TCK, TMS, TDI) JTAG Input Low Voltage (TCK, TMS, TDI) JTAG Output High Voltage (TDO) JTAG Output Low Voltage (TDO) JTAG Output High Voltage (TDO) JTAG Output Low Voltage (TDO) JTAG Input Leakage Current JTAG Output Leakage Current Symbol VTIH VTIL VTOH VTOL VTOH VTOL ITLI ITLO Test Conditions ----ITOH = -100uA ITOL = 100uA ITOH = -8mA ITOL = 8mA VTIN = VSS to VDD VTOUT = VSS to VDD (VDD = 1.7V to 1.95V, TA = 0 to 85°C) Min VDD/2 + 0.3 -0.3 VDD - 0.1 --VDD - 0.4 ---20 -10 Max VDD + 0.3 VDD/2 - 0.3 --0.1 --0.4 10 10 Units V V V V V V uA uA JTAG AC Test Conditions Parameter JTAG Input High Level JTAG Input Low Level JTAG Input Rise & Fall Time JTAG Input Reference Level JTAG Output Reference Level JTAG Output Load Condition Symbol VTIH VTIL Conditions 1.8 0.0 1.0 0.9 0.9 (VDD = 1.7V to 1.95V, TA = 0 to 85°C) Units V V V/ns V V See Fig. 1 (page 14) Notes 18Mb 1x1Dp, LVCMOS, rev 1.3 18 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary JTAG AC Electrical Characteristics Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup Time TMS Hold Time TDI Setup Time TDI Hold Time Capture Setup Time (Address, Control, Data, Clock) Capture Hold Time (Address, Control, Data, Clock) TCK Low to TDO Valid TCK Low to TDO Hold Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQV tTLQX 0 Min 50 20 20 5 5 5 5 5 8 10 Max Units ns ns ns ns ns ns ns ns ns ns ns 1 1 Notes 1. These parameters are guaranteed by design through extensive corner lot characterization. JTAG Timing Diagram Figure 5 tTHTL tTLTH tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV tTLQX TDO 18Mb 1x1Dp, LVCMOS, rev 1.3 19 / 29 November 18, 2003 SONY® ΣRAM TAP Controller CXK79M72C165GB / CXK79M36C165GB Preliminary The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK. The TAP Controller enters the “Test-Logic Reset” state in one of two ways: 1. At power up. 2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK. The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state. TAP Controller State Diagram Figure 6 1 Test-Logic Reset 0 0 Run-Test / Idle 1 Select DR-Scan 1 Select IR-Scan 1 0 1 Capture-DR 0 1 Capture-IR 0 Shift-DR 0 0 Shift-IR 0 1 1 Exit1-DR 1 1 Exit1-IR 0 Pause-DR 0 0 Pause-IR 0 1 Exit2-DR 1 0 Exit2-IR 0 1 Update-DR 1 Update-IR 1 0 1 0 18Mb 1x1Dp, LVCMOS, rev 1.3 20 / 29 November 18, 2003 SONY® ΣRAM TAP Registers CXK79M72C165GB / CXK79M36C165GB Preliminary TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers” (IR), which are manipulated via the “IR” states in the TAP Controller, and “Data Registers” (DR), which are manipulated via the “DR” states in the TAP Controller. Instruction Register (IR - 3 bits) The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE instruction at power-up, and when the TAP Controller is in the “Test-Logic Reset” and “Capture-IR” states. It is inserted between TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction. However, newly loaded instructions are not executed until the TAP Controller has reached the “Update-IR” state. The Instruction Register is 3 bits wide, and is encoded as follows: Code (2:0) 000 Instruction EXTEST-A Description Loads the individual logic states of all signals composing the SRAM’s I/O ring into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Also enables the SRAM’s data and clock output drivers, and moves the contents of the B-Scan Register associated with the data and clock output signals to the input side of the SRAM’s output register. The SRAM’s input clock can then be used to transfer the B-Scan Register contents directly to the data and clock output pins (the input clock controls the SRAM’s output register). Note that newly captured and/or shifted B-Scan Register contents do not appear at the input side of the SRAM’s output register until the TAP Controller has reached the “UpdateDR” state. See the Boundary Scan Register description for more information. Loads a predefined device- and manufacturer-specific identification code into the ID Register when the TAP Controller is in the “Capture-DR” state, and inserts the ID Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. See the ID Register description for more information. Loads the individual logic states of all signals composing the SRAM’s I/O ring into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. Also disables the SRAM’s data and clock output drivers. See the Boundary Scan Register description for more information. Do not use. Reserved for manufacturer use only. Loads the individual logic states of all signals composing the SRAM’s I/O ring into the Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. See the Boundary Scan Register description for more information. Do not use. Reserved for manufacturer use only. Do not use. Reserved for manufacturer use only. Loads a logic “0” into the Bypass Register when the TAP Controller is in the “Capture-DR” state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state. See the Bypass Register description for more information. 001 IDCODE 010 SAMPLE-Z 011 100 PRIVATE SAMPLE 101 110 111 PRIVATE PRIVATE BYPASS Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 18Mb 1x1Dp, LVCMOS, rev 1.3 21 / 29 November 18, 2003 SONY® ΣRAM Bypass Register (DR - 1 bit) CXK79M72C165GB / CXK79M36C165GB Preliminary The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic “0” when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. ID Register (DR - 32 bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The ID Register is 32 bits wide, and is encoded as follows: Revision Number (31:28) xxxx xxxx Part Number (27:12) 0000 0000 0101 1000 0000 0000 0101 1110 Sony ID (11:1) 0000 1110 001 0000 1110 001 Start Bit (0) 1 1 Device 256Kb x 72 512Kb x 36 Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. Boundary Scan Register (DR - 123 bits for x72, 84 bits for x36) The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the individual logic states of all signals composing the SRAM’s I/O ring when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the EXTEST-A, SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state. The Boundary Scan Register contains the following bits: 256Kb x 72 DQx A, A1, A0 CK CQ1, CQ2, CQ1, CQ2 E1, ADV, W, Bx E2, E3, EP2, EP3 ZQ Place Holder 72 18 1 4 11 4 1 12 DQx A, A1, A0 CK CQ1, CQ2, CQ1, CQ2 E1, ADV, W, Bx E2, E3, EP2, EP3 ZQ Place Holder 512Kb x 36 36 19 1 4 7 4 1 12 18Mb 1x1Dp, LVCMOS, rev 1.3 22 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary Boundary Scan Register Bit Order Assignments The tables below depict the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and bit 123 (for x72) or bit 84 (for x36) is the MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out through TDO. 256Kb x 72 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 28 29 30 31 32 33 34 35 Signal NC (1) NC (1) NC (1) (1) (1) Pad 5C 5U 7U 6D 6K 6P 6T 6N 6M 6L 10W 11W 11V 10V 11U 10U 11T 10T 11R 10R 11P 10P 11N 10N 11M 10M 11L 10L 11K 10K 10J 11J 10H 11H 10G Bit 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal DQf DQf DQf DQf DQb DQb DQb DQb DQb DQb DQb DQb DQb Bf Ba Bb Be EP3 EP2 A E3 A A W ADV E1 A E2 A ZQ Bd Bg Bh Bc DQg Pad 11G 10F 11F 10E 11E 10D 11D 10C 11C 10B 11B 11A 10A 9B 9C 8B 8C 6H 6G 9A 8A 7B 7A 6B 6A 6C 5A 4A 3A 6F 4C 4B 3C 3B 2A Bit 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Signal DQg DQg DQg DQg DQg DQg DQg DQg DQc DQc DQc DQc DQc DQc DQc DQc DQc CQ2 CK NC (1) Pad 1A 1B 2B 1C 2C 1D 2D 1E 2E 1F 2F 1G 2G 1H 2H 1J 2J 1K 3K 4K 2K 2L 1L 2M 1M 2N 1N 2P 1P 2R 1R 2T 1T 2U 1U Bit 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Signal DQd DQd DQd DQd MCH A A A A A A A0 A1 A A A A A Pad 2V 1V 1W 2W 6J 3V 4V 4U 5V 6U 5W 6W 6V 7V 8V 7W 8U 9V MCL MCL MCL (1) MCL (1) MCH (2) MCL MCH DQe DQe DQe DQe DQe DQe DQe DQe DQe DQa DQa DQa DQa DQa DQa DQa DQa DQa CQ1 CQ1 DQf DQf DQf DQf DQf CQ2 DQh DQh DQh DQh DQh DQh DQh DQh DQh DQd DQd DQd DQd DQd Note 1: These NC and MCL pins are connected to VSS internally, regardless of pin connection externally. Note 2: This MCH pin is connected to VDD internally, regardless of pin connection externally. 18Mb 1x1Dp, LVCMOS, rev 1.3 23 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary 512Kb x 36 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 28 29 30 31 32 33 34 35 Signal NC (1) NC (1) NC (1) MCL MCL MCL MCH (1) (1) Pad 5C 5U 7U 6D 6K 6P 6T 6N 6M 6L 10R 11P 10P 11N 10N 11M 10M 11L 10L 11K 10K 11E 10D 11D 10C 11C 10B 11B 11A 10A 9C 8B 6H 6G 9A Bit 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal E3 A A W ADV E1 A A E2 A ZQ Bd Bc DQc DQc DQc DQc DQc DQc DQc DQc DQc CQ2 CK NC (1) Pad 8A 7B 7A 6B 6A 6C 5A 5B 4A 3A 6F 4C 3B 2E 1F 2F 1G 2G 1H 2H 1J 2J 1K 3K 4K 2K 1R 2T 1T 2U 1U 2V 1V 1W 2W Bit 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal MCH A A A A A A A0 A1 A A A A A Pad 6J 3V 4V 4U 5V 6U 5W 6W 6V 7V 8V 7W 8U 9V MCL (1) (1) (2) MCL MCH DQa DQa DQa DQa DQa DQa DQa DQa DQa CQ1 CQ1 DQb DQb DQb DQb DQb DQb DQb DQb DQb Ba Bb EP3 EP2 A CQ2 DQd DQd DQd DQd DQd DQd DQd DQd DQd Note 1: These NC and MCL pins are connected to VSS internally, regardless of pin connection externally. Note 2: This MCH pin is connected to VDD internally, regardless of pin connection externally. 18Mb 1x1Dp, LVCMOS, rev 1.3 24 / 29 November 18, 2003 SONY® ΣRAM •Ordering Information Part Number CXK79M72C165GB / CXK79M36C165GB Preliminary TA 0 to 70°C 0 to 70°C 0 to 85°C 0 to 70°C 0 to 70°C 0 to 85°C VDD 1.75V to 1.95V 1.75V to 1.95V 1.7V to 1.95V 1.75V to 1.95V 1.75V to 1.95V 1.7V to 1.95V I/O Type Configuration Speed (Cycle Time / Data Access Time) 3.0ns / 2.0ns 3.3ns / 2.0ns 4.0ns / 2.1ns 3.0ns / 2.0ns 3.3ns / 2.0ns 4.0ns / 2.1ns CXK79M72C165GB-3 CXK79M72C165GB-33 CXK79M72C165GB-4 CXK79M36C165GB-3 CXK79M36C165GB-33 CXK79M36C165GB-4 LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS 256Kb x 72 256Kb x 72 256Kb x 72 512Kb x 36 512Kb x 36 512Kb x 36 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 18Mb 1x1Dp, LVCMOS, rev 1.3 25 / 29 November 18, 2003 SONY® ΣRAM CXK79M72C165GB / CXK79M36C165GB Preliminary •(11x19) 209 Pin BGA Package Dimensions 209PIN BGA (PLASTIC) 14.0 2.0 ± 0.3 0.30 S A X 0.5 ± 0.1 1.0 2.0 13.0 1.0 A W V U T R P N M L K J H G F E D C B A 0.30 S B PIN 1 INDEX 22.0 21.0 1 2 3 4 5 6 7 8 9 10 11 3- . C1 0 x4 0.20 C1 .5 S 209 - φ 0.6 ± 0.1 0.10 M 2.0 PRELIMINARY SONY CODE JEITA CODE JEDEC CODE BGA-209P-01 P-BGA209-14X22-1.0 18Mb 1x1Dp, LVCMOS, rev 1.3 4C 1. 7 0.35 S 0.15 S DETAIL X B S AB PACKAGE STRUCTURE PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 1.1g 26 / 29 November 18, 2003 SONY® ΣRAM •Revision History Rev. # rev 0.0 rev 0.1 Rev. Date 06/23/00 02/23/01 CXK79M72C165GB / CXK79M36C165GB Preliminary Description of Modifications Initial Version. 1. Added Sony Part Numbers for each device. 2. Removed Asynchronous Output Enable (G) support. Pin 6D now defined as “MCL”. 3. Modified DC Recommended Operating Conditions section (p. 10). VMIH-1.8 (min) 1.2V to 1.3V VMIH-1.5 (min) 1.2V to 1.1V VMIL-1.8 (max) 0.3V to 0.5V VMIL-1.5 (max) 0.3V to 0.4V 3. Modified DC Electrical Characteristics section (p. 11). Added IDD-4 Average Power Supply Operating Current specifications. Added IDD2 Power Supply Deselect Operating Current specification. 4. Modified AC Electrical Characteristics section (p. 12). Removed “-5” bin. Added “-44” bin. All Bins Removed tKLCL specifications -33 tAVKH, tBVKH, tDVKH 0.4ns to 0.7ns tKHQV, tKHQZ 1.85ns to 1.8ns tKHCH, tKHCZ 1.65ns to 1.7ns tCHQV 0.2ns to 0.4ns tCHQX -0.2ns to -0.4ns tCHCL tKHKL ± 0.1 to tKHKL ± 0.2 tCLCH tKLKH ± 0.1 to tKLKH ± 0.2 -4 tAVKH, tBVKH, tDVKH 0.5ns to 0.8ns tKHQV, tKHQZ 2.25ns to 2.1ns tCHQV 0.2ns to 0.5ns tCHQX -0.2ns to -0.5ns tCHCL tKHKL ± 0.1 to tKHKL ± 0.25 tCLCH tKLKH ± 0.1 to tKLKH ± 0.25 5. Updated the size and content of the Boundary Scan Registers (p. 21). 1. Modified DC Electrical Characteristics section (p. 11). Added IDD-33 and IDD-44 Average Power Supply Operating Current specifications. 2. Added Slow Down pin (SD) and associated AC Electrical Characteristics section (p. 12). 3. Added 209 Pin BGA Package Dimensions (p. 26). 1. Added BGA Package Thermal Characteristics (p. 10). 2. Removed Slow Down pin (SD) and associated AC Electrical Characteristics section (p. 13). 3. Modified AC Electrical Characteristics section (p. 13). Removed “-44” bin. Added “-5” bin. -4 tCHCL tKHKL ± 0.25 to tKHKL ± 0.2 tCLCH tKLKH ± 0.25 to tKLKH ± 0.2 4. Added JTAG ID Codes (p. 23). 5. Added JTAG Boundary Scan Register Bit Order Assignments (pp. 24-26). 1. Modified Pin Assignment section (p. 2-4). Byte Write Enable Control Inputs Pin 1K Pin 2K Pin 10K Pin 11K Pin 6J Pin 6L Pin 6M 27 / 29 rev 0.2 07/06/01 rev 0.3 02/22/02 rev 1.0 07/19/02 BWx to Bx CQ to CQ2 CQ to CQ2 CQ to CQ1 CQ to CQ1 M4 to MCH M2 to MCH M3 to MCL November 18, 2003 18Mb 1x1Dp, LVCMOS, rev 1.3 SONY® ΣRAM Rev. # Rev. Date CXK79M72C165GB / CXK79M36C165GB Description of Modifications Preliminary 2. Modified I/O Capacitance section (p. 10). CKIN 3.5pF to 4.0pF 3. Modified DC Recommended Operating Conditions section (p. 11). Combined -1.8 and -1.5 line items into one for VDDQ, VIH, VIL, VMIH, and VMIL. VIH (min) 1.0V to VDDQ/2 + 0.3V VIL (max) 0.6V to VDDQ/2 - 0.3V VMIH (min) 1.1V to VDDQ/2 + 0.4V VMIL (max) 0.5V to VDDQ/2 - 0.4V Removed notes 1 and 2. 4. Modified DC Electrical Characteristics section (p. 12). Added MCH and MCL Input Leakage Current specifications. Reduced x72 Average Power Supply Operating Currents by 100mA. Reduced x36 Average Power Supply Operating Currents by 50mA. Reduced x18 Average Power Supply Operating Currents by 20mA. 5. Modified AC Electrical Characteristics section (p. 13). -33 tKHCH (max), tKHCZ 1.7ns to 1.8ns -4 tKHCH (max), tKHCZ 2.0ns to 2.1ns -5 tKHCH (max), tKHCZ 2.2ns to 2.3ns 6. Modified JTAG DC Recommended Operating Conditions section (p. 19). VTIH (min) 1.2V to VDD/2 + 0.3V VTIL (max) 0.6V to VDD/2 - 0.3V ITLI (min) -10uA to -20uA 7. Modified JTAG AC Electrical Characteristics section (p. 20). tTHTH 20ns to 50ns tTHTL, tTLTH 8ns to 20ns Added tCS Capture Setup and tCH Capture Hold specifications. 8. Modified TAP Registers section (p. 22). Instruction Register Codes 011, 110 Bypass to Private 9. Modified Boundary Scan Register Bit Order Assignments section (p. 24-25). x72 Bit 47 10A to 11A x72 Bit 48 11A to 10A x36 Bit 29 10A to 11A x36 Bit 30 11A to 10A rev 1.1 11/08/02 1. Removed x18 organization and all related references. 2. Modified Pin Description section (p. 5). For NC pins, removed reference to VDD and VDDQ. 3. Modified AC Electrical Characteristics section (p. 12). -33 tCHQV 0.4ns to 0.38ns tCHQX -0.4ns to -0.38ns -4 tCHQV 0.5ns to 0.45ns tCHQX -0.5ns to -0.45ns -5 tCHQV 0.6ns to 0.5ns tCHQX -0.6ns to -0.5ns Removed tCHCL and tCLCH Output Clock High and Low Pulse Width specifications. 4. Modified JTAG AC Electrical Characteristics section (p. 19). tCH 5ns to 8ns Added Note 1 for tCS and tCH specifications. 18Mb 1x1Dp, LVCMOS, rev 1.3 28 / 29 November 18, 2003 SONY® ΣRAM Rev. # rev 1.2 Rev. Date 09/07/03 CXK79M72C165GB / CXK79M36C165GB Description of Modifications 1. Removed -5 speed bin and associated specifications. 2. Added -3 speed bin and associated specifications. 3. Modified Absolute Maximum Ratings section (p. 9). Operating Temperature (-33 max) 4. Modified DC Electrical Characteristics section (p. 11). IDD2-33 (max) 5. Modified AC Electrical Characteristics section (p. 12). -33 tKHQV, tKHQZ, tKHCH (max), tKHCZ Added notes 4 and 5. 6. Modified Ordering Information section (p. 25) Added TA for each part number. 1. Modified DC Recommended Operating Conditions section (p. 10). -3, -33 VDD (min) 2. Modified AC Electrical Characteristics section (p. 12). -3 tKHQV, tKHQZ, tKHCH (max), tKHCZ -33 tKHQV, tKHQZ, tKHCH (max), tKHCZ Preliminary 85°C to 70°C 250mA to 280mA 1.8ns to 1.9ns rev 1.3 11/18/03 1.7V to 1.75V 1.8ns to 2.0ns 1.9ns to 2.0ns 18Mb 1x1Dp, LVCMOS, rev 1.3 29 / 29 November 18, 2003