CXP834P16

CXP834P16 CXP834P17 CMOS 8-bit Single Chip Microcomputer Description The CXP834P16 and CXP834P17 are a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, 32kHz timer/counter, LCD controller/driver, remote control receiving circuit and PWM output, as well as basic configurations like 8-bit CPU, PROM, RAM and I/O port. They are integrated into a single chip. Also CXP834P16 and CXP834P17 provide sleep/ stop function which enables to lower power consumption. The CXP834P16 and CXP834P17 are the PROMincorporated version of the CXP83416 and CXP83417 with built-in mask ROM. These provide the additional feature of being able to write directly into the program. Thus, they are most suitable for evaluation use during system development and for small-quantity production. CXP834P16 80 pin QFP (Plastic) 80 pin LQFP (Plastic) CXP834P17 80 pin QFP (Plastic) Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V) • Incorporated PROM capacity 16K bytes • Incorporated RAM capacity 448 bytes (LCD display data area included) • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation system (Conversion time: 32µs/10MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer), 1 circuit 2 channels — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — LCD controller/driver Maximum 128 segments display possible (During 1/4 duty) 4 common outputs, 32 segment outputs Display method: Static, 1/2, 1/3 and 1/4 duty Bias method: 1/2 and 1/3 bias — Remote control receiving circuit 8-bit pulse measurement counter 6-stage FIFO — PWM output 14 bits 1 channel, 8 bits 1 channel • Interruption 12 factors, 12 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 80-pin plastic QFP/LQFP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93Z14B63-ST Block Diagram SPC700 CPU CORE CLOCK GENERATOR/ SYSTEM CONTROL SEG0 to SEG31 32 PORT A AN0 to AN7 8 A/D CONVERTER INT0 INT1 INT2 NMI/INT3 2 TEX TX EXTAL XTAL RST VDD Vss Vpp 8 PA0 to PA7 LCD CONTROLLER/ DRIVER PORT B COM0 to COM3 4 8 PB0 to PB7 PWM0 PWM1 FIFO 14BIT PWM GENERATOR 8BIT PWM GENERATOR INTERRUPT CONTROLLER PROM 16K BYTES RAM 448 BYTES PORT C VL VLC1 VLC2 VLC3 8 PC0 to PC7 RMC REMOCON PORT D PORT E CS0 SI0 SO0 SCK0 CS1 SI1 SO1 SCK1 2 EC 8BIT TIMER/COUNTER 0 PORT F CXP834P16, CXP834P17 ADJ 2 PORT H –2– PRESCALER/ TIME BASE TIMER FIFO 8 PD0 to PD7 5 PE0 to PE4 32kHz TIMER/COUNTER 2 PE5 to PE6 SERIAL INTERFACE UNIT 0 8 PF0 to PF7 TO 8BIT TIMER 1 1 PH0 CXP834P16, CXP834P17 Pin Assignment (Top View) CXP834P16 (QFP package) PE0/INT0/EC PE2/INT2 PE1/INT1 PF7/SEG31 PF6/SEG30 Vpp TEX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PE3/INT3/NMI PE4/RMC PE5/PWM0 PE6/TO/ADJ PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PWM1 PA0/AN0 PA1/AN1 PA2/AN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PD6/SEG22 PD5/SEG21 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 TX VDD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 COM1 PA3/AN3 Note) Vpp (Pin 75) is always connected to VDD. PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL –3– COM0 COM2 XTAL VLC3 VLC2 VLC1 RST VSS VL PD7/SEG23 CXP834P16, CXP834P17 Pin Assignment (Top View) CXP834P16 (LQFP package) PE3/INT3/NMI PE0/INT0/EC PE4/RMC PE2/INT2 PE1/INT1 PF7/SEG31 PF6/SEG30 Vpp TEX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 TX VDD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 PE5/PWM0 PE6/TO/ADJ PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PWM1 PA0/AN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 PA1/AN1 PA2/AN2 PA3/AN3 Note) Vpp (Pin 73) is always connected to VDD. PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL –4– COM0 COM1 COM2 COM3 SEG0 XTAL VLC3 VLC2 VLC1 RST VSS VL CXP834P16, CXP834P17 Pin Assignment (Top View) CXP834P17 (QFP package) PE3/INT3/NMI PE0/INT0/EC PE4/RMC PE2/INT2 PE1/INT1 PF7/SEG31 PF6/SEG30 Vpp TEX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 TX VDD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 PE5/PWM0 PE6/TO/ADJ PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PWM1 PA0/AN0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 PA1/AN1 PA2/AN2 PA3/AN3 Note) Vpp (Pin 73) is always connected to VDD. PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL –5– COM0 COM1 COM2 COM3 SEG0 XTAL VLC3 VLC2 VLC1 RST VSS VL CXP834P16, CXP834P17 Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions PA0/AN0 to PA7/AN7 I/O/Analog input Analog inputs to A/D converter. (8 pins) PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH1). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. External interruption request input. (4 pins) Non-maskable intrruption request input. Remote control receiving circuit input. 14-bit PWM output. Rectangular wave output for 8-bit timer/ counter and 32kHz oscillation frequency divider output. (Port H) 1-bit I/O port. Incorporation of pull-up resistor can be set through the software. (1 pin) PC0 to PC7 I/O PE0/INT0/EC PE1/INT1 PE2/INT2 Input/Input/Input Input/Input Input/Input (Port E) 7-bit port. Lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) PE3/INT3/NMI Input/Input/Input PE4/RMC PE5/PWM0 PE6/TO/ADJ Input/Input Output/Output Output/Output/ Output PH0/PWM1 I/O/Output 8-bit PWM output. –6– CXP834P16, CXP834P17 Symbol PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 I/O Output/Output (Port D) 8-bit output port. (8 pins) (Port F) 8-bit output port. (8 pins) LCD segment signal output. LCD common signal output. LCD bias power supply. Output Input Output Input Output Input Functions LCD segment signal output. (16 pins) Output/Output SEG0 to SEG15 Output COM0 to COM3 Output VLC1 to VLC3 VL EXTAL XTAL TEX TX RST Vpp VDD Vss Control pin to cut off the current flowing to external LCD bias resistor during standby. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock generation circuit. For usage as event counter, connect clock oscillation source to TEX, and leave TX open. Low-level active, system reset. Positive power supply for the on-chip programmable PROM; connect to VDD for normal operation. Positive power supply. GND. –7– CXP834P16, CXP834P17 I/O Circuit Format for Pins Pin Port A Pull-up resistor "0" when reset Port A data Circuit format ∗ When reset PA0/AN0 to PA7/AN7 Data bus Port A direction "0" when reset IP Input protection circuit Hi-Z RD (Port A) Port A input selection "0" when reset A/D converter Input multiplexer ∗ Pull-up transistors approx. 100kΩ 8 pins Port B Pull-up resistor "0" when reset Port B data ∗ PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1 Data bus Port B direction "0" when reset Schmitt input RD (Port B) CS1 CS0 SI0 SI1 IP Hi-Z 4 pins Port B Pull-up resistor "0" when reset SCK OUT Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) ∗ Pull-up transistors approx. 100kΩ ∗ PB2/SCK0 PB5/SCK1 IP Hi-Z Schmitt input 2 pins SCK in ∗ Pull-up transistors approx. 100kΩ –8– CXP834P16, CXP834P17 Pin Port B Pull-up resistor "0" when reset SO Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Circuit format ∗ When reset PB4/SO0 PB7/SO1 IP Hi-Z 2 pins Port C Pull-up resistor "0" when reset Port C data ∗ Pull-up transistors approx. 100kΩ ∗2 PC0 to PC7 Port C direction "0" when reset Data bus RD (Port C) ∗1 Large current 12mA ∗2 Pull-up transistors approx. 100kΩ ∗1 Hi-Z IP 8 pins PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC 5 pins Port E Schmitt input IP INT0/EC INT1 INT2 INT3/NMI RMC Data bus RD (Port E) Hi-Z –9– CXP834P16, CXP834P17 Pin Port E PWM0 Port E output selection "0" when reset Port E data Data bus Circuit format When reset PE5/PWM0 High level "1" when reset RD (Port E) 1 pin Port E Port E data Internal reset signal ∗1 "1" when reset ∗2 TO ADJ16K ADJ2K Port E output selection (upper) Port E output selection (lower) MPX PE6/TO/ADJ TO Output enable ∗1 Pull-up transistors approx. 150kΩ. ∗2 ADJ signals are frequency divider outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. () High level with approx. 150kΩ resistor when reset 1 pin Port H Pull-up resistor "0" when reset PWM1 Port H output selection "0" when reset Port H data Port H direction "0" when reset Data bus RD (Port H) IP ∗ PH0/PWM1 Hi-Z 1 pin ∗ Pull-up transistors approx. 100kΩ – 10 – CXP834P16, CXP834P17 Pin Port D Port F PD7 to PD4 by a bit unit PD3 to PD0 by 4-bit unit PF7 to PF0 Circuit format When reset Port data PD0 to PD7 PF0 to PF7 Port/segment output selection "0" when reset Segment output (VDD level) Segment data Segment driver 24 pins Segment VCH SEG0 to SEG15 VDD level VCL 16 pins Common VDD VCL1 COM0 to COM3 VDD level VCL2 VCL3 4 pins VL LCD control (DSP bit) Hi-Z 1 pin "0" when reset – 11 – CXP834P16, CXP834P17 Pin Circuit format When reset EXTAL XTAL • Diagram shows circuit composition during oscillation. EXTAL IP IP • Feedback resistor is removed during stop, and XTAL becomes "High" level. XTAL Oscillation 2 pins TEX TX TEX IP IP • Digram shows circuit composition during oscillation. 2 pins TX • When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and TEX and TX become "Low" level and "High" level respectively. Oscillation Mask option Pull-up resistor RST OP IP Schmitt input Low level 1 pin – 12 – CXP834P16, CXP834P17 Absolute Maximum Ratings Item Supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Symbol VDD Vpp Rating –0.3 to +7.0 –0.3 to +13.0 Unit V V V V V mA mA mA mA mA °C °C mW mW mW QFP-80P-L01 LQFP-80P-L01 QFP-80P-L03 Incorporated PROM (Vss=0V reference) Remarks VLC1, VLC2, –0.3 to +7.0∗1 VLC3 –0.3 to +7.0∗1 VIN VOUT IOH ∑IOH IOL IOLC ∑IOL Topr Tstg –0.3 to +7.0∗1 –5 –50 15 20 100 –10 to +75 –55 to +150 600 Output (value per pin) Total for all output pins All pins excluding large current output (value per pin) Large current outputs (value per pin ∗2) Total for all output pins Allowable power dissipation PD 380 380 ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. – 13 – CXP834P16, CXP834P17 Recommended Operating Conditions Item Symbol Min. 4.5 VDD 3.5 2.7 2.5 Vpp VLC1 LCD bias voltage VLC2 VLC3 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 0.7VDD 0.8VDD VDD – 0.4 0 0 –0.3 –10 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V °C ∗2 Hysteresis input∗3 EXTAL∗4 ∗2 Hysteresis input∗3 EXTAL∗4 Vss VDD V Max. 5.5 5.5 5.5 5.5 V V Unit (Vss=0V reference) Remarks High-speed mode guaranteed operation range∗1 Low-speed mode guaranteed operation range∗1 Guaranteed operation range with TEX clock Guaranteed data hold range during STOP ∗6 LCD power supply range∗5 Supply voltage Vpp = VDD ∗1 High-speed mode is 1/2 frequency divider clock selection; low-speed mode is 1/16 frequency divider clock selection. ∗2 Value for each pin of normal input ports (PA, PB4, PB7, PC and PH0). ∗3 Value of the following pins: RST, CS0, CS1, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, NMI/INT3, and RMC. ∗4 Specifies only during external clock input. ∗5 Optimal values are determined by LCD used. ∗6 Vpp and VDD should be set to the same voltage. – 14 – CXP834P16, CXP834P17 Electrical Characteristics DC Characteristics Item Symbol Pins PA, PB, PC, PD∗1, PE5, PE6, PF, PH0, VL (VOL only) PC IIHE IILE IIHT Input current IILT IILR IIL IIH I/O leakage current Common output impedance Segment output impedance IIZ TEX RST∗2 PA to PC∗3, PH∗3, PE0 to PE4, RST∗2 COM0 to COM3 EXTAL Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIH = 4.0V VDD = 5.5V, VI = 0, 5.5V 3 0.5 –0.5 0.1 –0.1 –1.5 (Ta = –10 to +75°C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 –40 10 –10 –400 –45 –2.78 ±10 Typ. Max. Unit V V V V V V µA µA µA µA µA µA µA kΩ High level VOH output voltage Low level output voltage VOL RCOM RSEG VDD = 5V, VLC1 = 3.75V SEG0 to SEG15, VLC2 = 2.5V VLC3 = 1.25V SEG16 to ∗1 SEG31 High-speed mode operation (1/2 frequency divider clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD SLEEP mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode 5 5 15 kΩ IDD1 18 40 mA IDD2 Supply current∗4 400 1000 µA IDDS1 1.1 8 mA IDDS2 9 30 µA IDDS3 VDD = 5.5V, termination of 10MHz and 32kHz crystal oscillation 30 µA – 15 – CXP834P16, CXP834P17 Item Input capacity Symbol CIN Pins PA to PC, PE1 to PE4, EXTAL, TEX, RST Conditions Clock 1MHz 0V for all pins excluding measured pins Min. Typ. 10 Max. 20 Unit pF ∗1 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24, PF7/SEG31, PD and PF are the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output. ∗2 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ∗3 PA to PC, and PH0 specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. (PE0 to PE4 specify the leakage current.) ∗4 When all output pins are left open. – 16 – CXP834P16, CXP834P17 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms tXL, tXH tCR, tCF tEH, tEL tER, tEF fC tsys+50∗ 32.768 kHz tTL, tTH tTR, tTF µs ms ∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control registor (CLC: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing 1/fc EXTAL VDD – 0.4V 0.4V tXH tCF tXL tCR Fig. 2. Clock applied conditions Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation EXTAL XTAL EXTAL XTAL TEX TX C1 C2 74HC04 C1 C2 Fig. 3. Event count clock timing TEX EC 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR – 17 – CXP834P16, CXP834P17 (2) Serial transfer Item CS0 ↓ → SCK0 (CS1 ↓ → SCK1) delay time CS0 ↑ → SCK0 (CS1 ↑ → SCK1) floating delay time CS0 ↓ → SO0 (CS1 ↓ → SO1) delay time CS0 ↑ → SO0 (CS1 ↑ → SO1) floating delay time CS0 (CS1) high level width SCK0 (SCK1) cycle time SCK0 (SCK1) high and low level widths SI0 (SI1) input setup time (for SCK0 ↑ (SCK1 ↑) ) SI0 (SI1) input hold time (for SCK0 ↑ (SCK1 ↑) ) SCK0 ↓ → SO0 (SCK1 ↓ → SO1) delay time Symbol Pin (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. Max. Unit tDCSK SCK0 Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) (SCK1) (SCK0 (SCK1) = output mode) SO0 (SO1) (SO1) (CS1) Chip select transfer mode Chip select transfer mode Chip select transfer mode tsys + 200 ns tsys + 200 ns tsys + 200 ns tsys + 200 ns tsys + 200 2tsys + 200 16000/fc ns ns ns ns ns ns ns ns ns tDCSKF SCK0 Chip select transfer mode tDCSO tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO SCK0 Input mode (SCK1) Output mode SCK0 Input mode (SCK1) Output mode SI0 (SI1) SI0 (SI1) SO0 (SO1) SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode tsys + 100 8000/fc – 50 100 200 tsys + 200 100 tsys + 200 100 ns ns Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL. – 18 – CXP834P16, CXP834P17 Fig. 4. Serial transfer CH0 timing tWHCS CS0 (CS1) 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 (SCK1) 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 (SI1) Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 (SO1) Output data 0.2VDD – 19 – CXP834P16, CXP834P17 (3) A/D converter characteristics (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = 0V reference) Item Resolution Linearity error Zero transition voltage VZT∗1 Full-scale transition voltage Conversion time Sampling time Analog input voltage VFT∗2 Ta = 25°C VDD = 5.0V VSS = 0V –10 4910 160/fADC∗3 12/fADC∗3 AN0 to AN7 0 VDD + 0.3 10 4970 Symbol Pin Conditions Min. Typ. Max. 8 ±3 70 5030 Unit Bits LSB mV mV µs µs V tCONV tSAMP VIAN Fig. 5. Definition of A/D converter terms FFH FEH Digital conversion value ∗1 VZT : Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT : Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to the contents of Linearity error 01H 00H VZT Analog input VFT bit 6 (CK3) of the A/D control registor (ADC: 00F9H) and bit 7 (PCK1) and bit 6 (PCK0) of the clock control registor (CLC: 00FEH) CKS PCK1, PCK0 00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16) 0 (φ/2 selection) fADC = fc/2 fADC = fc/4 fADC = fc/16 0 (φ selection) fADC = fc fADC = fc/2 fADC = fc/8 – 20 – CXP834P16, CXP834P17 (4) Interruption, reset input Item External interruption high and low level widths Reset input low level width (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 NMI/INT3 RST Conditions Min. Max. Unit tIH tIL tRSL 1 µs 32/fc µs Fig 6. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 NMI/INT3 (NMI is specified only for the falling edge) 0.2VDD tIL tIH Fig. 7. RST input timing tRSL RST 0.2VDD – 21 – CXP834P16, CXP834P17 Appendix Fig. 8. SPC700 Series recommended oscillation circuit (i) Main clock (ii) Main clock (iii) Sub clock EXTAL XTAL Rd EXTAL XTAL Rd ETEX XTAL XTAL TX Rd C1 C2 C 1 C2 C1 C2 Manufacturer Model CSA4.19MG CSA8.00MG fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 C1 (pF) C2 (pF) Rd (Ω) Circuit example (i) 30 30 0 (ii) MURATA MFG CO., LTD. CSA10.0MT CST4.19MGW∗ CST8.00MTW∗ CST10.00MTW∗ RIVER ELETEC CO., LTD. HC-49/U03 8.00 10.00 4.19 15 15 2.2k 470 22 18 22 18 560 0 (i) KINSEKI LTD. HC-49/U (-S) 8.00 10.00 Models with an asterisk (∗) have the built-in ground capacitance (C1, C2). Product List Optional Package ROM capacity Reset pin pull-up resistance Mask CXP83412 CXP83416 CXP83413 CXP83417 CXP834P16Q-180-pin plastic QFP/LQFP 80-pin plastic QFP (0.65mm pitch) 80-pin plastic QFP PROM CXP834P16R-180-pin plastic LQFP PROM 16K bytes Existent CXP834P17Q-180-pin plastic QFP (0.65mm pitch) 12K bytes 16K bytes 12K bytes 16K bytes Existent/Non-existent – 22 – CXP834P16, CXP834P17 Package Outline CXP834P16 Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE ∗QFP080-P-1420-A CXP834P16 80PIN LQFP (PLASTIC) 14.0 ± 0.2 ∗ 60 61 12.0 ± 0.1 41 40 A 80 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 20 21 (0.22) + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-80P-L01 ∗QFP080-P-1212-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.5g – 23 – 0.5 ± 0.2 (13.0) 0.8 ± 0.2 1 24 16.3 CXP834P16, CXP834P17 CXP834P17 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 0.1 41 40 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 61 80 1 0.65 20 21 + 0.15 0.1 – 0.1 ± 0.12 M 0° to 10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 LQFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.6g – 24 – 0.5 ± 0.2 + 0.15 0.3 – 0.1 (15.0)