CXP84120

CXP84120/84124 CMOS 8-bit Single Chip Microcomputer Description 80 pin QFP (Plastic) The CXP84120/84124 is a CMOS 8-bit single chip micro-computer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, remote control reception circuit and other servo systems besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP84120/84124 also provides a power-on reset function and a sleep/stop function that enables lower power consumption. Features • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation • Incorporated ROM capacity 20K bytes (CXP84120) 24K bytes (CXP84124) • Incorporated RAM capacity 624 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface SIO with 8-bit, 8-stage FIFO incorporated for data use (Auto transfer for 1 to 8 bytes), 1 channel 8-bit standard SIO, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter — Remote control reception circuit Incorporated noise elimination circuit Incorporated 8-bit, 6-stage FIFO for measurement data — PWM output 14 bits, 1 channel • Interruption 14 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 80-pin plastic QFP • Piggyback/evaluation chip CXP84100 80-pin ceramic QFP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92234A81-PS Block Diagram AVss PE3/NMI AVREF PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 TEX TX EXTAL XTAL RST VDD Vss PA0/AN0 to PA7/AN7 SPC700 CPU CORE CLOCK GEN./ SYSTEM CONTROL 8 A/D CONVERTER 8 PA0 to PA7 PE4/PWM 14 BIT PWM GENERATOR 7 PB0 to PB6 PB7 8 PC0 to PC7 PE2/RMC FIFO RAM 624 BYTES REMOCON PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 FIFO 22 PRESCALER/ TIME BASE TIMER INTERRUPT CONTROLLER ROM 20K BYTES (CXP84120) 24K BYTES (CXP84124) 8 4 2 PD0 to PD7 PE0 to PE3 PE4 to PE5 8 PF0 to PF7 SERIAL INTERFACE UNIT 0 PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A 32kHz TIMER/COUNTER 8 –2– 2 2 PB6/SI1 PB7/SO1 PB5/SCK1 SERIAL INTERFACE UNIT 1 PG0 to PG7 PE0/EC0 8 BIT TIMER/COUNTER 0 8 BIT TIMER 1 8 PH0 to PH7 PE5/TO PB0/CINT PE1/EC1 16 BIT CAPTURE TIMER/COUNTER2 8 PI0 to PI7 CXP84120/84124 CXP84120/84124 Pin Assignment (Top View) PF2 PF1 PF0 PG7 PG6 PG5 PG4 VDD PG3 PG2 PG1 PG0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5TO PE4/PWM PE3/NMI PE2/RMC PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CINT PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 NC PI7 PI6 PA1/AN1 Note) NC (Pin 73) must be connected to VDD. –3– PA0/AN0 PA2/AN2 EXTAL AVREF XTAL AVSS RST PH3 PH4 PH5 PH6 PH7 TEX VSS TX PI5 CXP84120/84124 Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bit. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) (Port B) 7-bit I/O port in which I/O can be set in a unit of single bit. Also, an uppermost bit (PB7) exclusively for output. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Description PA0/AN0 to PA7/AN7 I/O/Analog input Analog inputs to A/D converter. (8 pins) PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). PC0 to PC7 I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/counter. Output for 32kHz oscillation frequency division. (Port F) 8-bit I/O port. I/O can be set in a unit of single bit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PD0 to PD7 I/O PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PE4/PWM PE5/TO/ADJ Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output/ Output PF0 to PF7 I/O –4– CXP84120/84124 Symbol I/O Description (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit I/O ports. I/O can be set in a unit of single bit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. PG0 to PG7 I/O PH0 to PH7 I/O PI0/INT0 to PI3/INT3 PI4 to PI7 EXTAL XTAL TEX TX RST NC AVREF AVss VDD Vss I/O/Input I/O Input Output Input Output Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock generation circuit. Connect a 32kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and open TX. Low-level active, system reset. NC. Under normal operating conditions, connect to VDD. Input Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND –5– CXP84120/84124 Input/Output Circuit Formats for Pins Pin Port A Pull-up resistance "0" when reset Port A data Circuit format ∗ When reset PA0/AN0 to PA7/AN7 Data bus Port A direction "0" when reset IP Input protection circuit Hi-Z RD (Port A) Port A input selection "0" when reset A/D converter Input multiplexer ∗ Pull-up transistors approx. 10kΩ ∗ 8 pins Port B Pull-up resistance "0" when reset Port B data PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 Data bus Port B direction "0" when reset Schmitt input RD (Port B) IP Hi-Z 4 pins Port B Pull-up resistance "0" when reset SCK OUT Output enable Port B output selection CINT CS0 SI0 SI1 ∗ Pull-up transistors approx. 10kΩ ∗ PB2/SCK0 PB5/SCK1 "0" when reset Port B data Port B direction "0" when reset Schmitt input RD (Port B) IP Hi-Z Data bus 2 pins SCK in ∗ Pull-up transistors approx. 10kΩ –6– CXP84120/84124 Pin Port B Pull-up resistance SO Output enable Port B output selection "0" when reset Circuit format ∗ When reset PB4/SO0 Port B data Port B direction "0" when reset IP Hi-Z Data bus RD (Port B) ∗ Pull-up transistors approx. 10kΩ 1 pin Port B SO Output enable Port B output selection "1" when reset Port B data Internal reset signal ∗ PB7/SO1 High level Data bus 1 pin Port C RD (Port B) ∗ Pull-up transistors approx. 10kΩ Pull-up resistance "0" when reset Port C data ∗2 PC0 to PC7 Hi-Z Port C direction "0" when reset Data bus RD (Port C) ∗1 IP ∗1 Large current drive of 12mA possible ∗2 Pull-up transistors approx. 10kΩ 8 pins PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI 4 pins –7– Port E IP Schmitt input EC0 EC1 RMC/NMI Data bus RD (Port E) Hi-Z CXP84120/84124 Pin Port E PWM Circuit format When reset PE4/PWM Port E output selection "0" when reset Port E data Data bus "1" when reset RD (Port E) High level 1 pin Port E Ouput enable TO ADJ16K ADJ2K MPX PE5/TO/ADJ Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus RD (Port E) ∗ ADJ signals are frequency division outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. High level 1 pin Port D Port F Port G Port H PD0 to PD7 PF0 to PF7 PG0 to PG7 PH0 to PH7 PI4 to PI7 Port I Pull-up resistance "0" when reset Port data ∗ Port direction "0" when reset Data bus RD IP Hi-Z ∗ Pull-up transistors approx. 10kΩ 36 pins –8– CXP84120/84124 Pin Port I Circuit format Pull-up resistance "0" when reset Port data ∗ When reset PI0/INT0 to PI3/INT3 Port direction "0" when reset Data bus RD INT0 INT1 INT2 INT3 IP Hi-Z 4 pins ∗ Pull-up transistors approx. 10kΩ EXTAL XTAL EXTAL IP IP • Diagram shows circuit composition during oscillation. • Feedback resistor is removed during stop. Oscillation 2 pins XTAL TEX TX • Diagram shows circuit composition during oscillation. TEX IP IP • When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively. Oscillation 2 pins TX Pull-up resistor RST Mask option OP IP Low level 1 pin Schmitt input –9– CXP84120/84124 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage High level output current Symbol VDD AVSS VIN VOUT IOH Rating –0.3 to +7.0 –0.3 to +0.3 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –5 –50 15 20 100 –20 to +75 –55 to +150 600 Unit V V V V mA mA mA mA mA °C °C mW Output per pin Total for all output pins (Vss = 0V reference) Remarks High level total output current ∑IOH Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL IOLC ∑IOL Topr Tstg PD Value per pin, excluding large current outputs Value per pin∗2 for large current outputs Total for all output pins ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.7 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 VDD VDD V V V V V V °C V Unit (Vss = 0V reference) Remarks High-speed mode guaranteed operation range∗1 Low-speed mode guaranteed operation range∗1 Guaranteed operation range with TEX clock Guaranteed data hold range during stop ∗2 Hysteresis input∗3 EXTAL∗4 ∗2 Hysteresis input∗3 EXTAL∗4 VDD – 0.4 VDD + 0.3 0 0 –0.3 –20 0.3VDD 0.2VDD 0.4 +75 ∗1 High-speed mode is 1/2 frequency division clock selection; low-speed mode is 1/16 frequency division clock selection. ∗2 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7). ∗3 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3. ∗4 Specifies only during external clock input. – 10 – CXP84120/84124 Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage Symbol VOH PA to PD, PE4, PE5, PF to PI VOL PC IIHE IILE IIHT Input current IILT IILR IIL I/O leakage current IIZ TEX RST∗1 PA to PD∗2, PF to PI∗2 EXTAL Pins Conditions VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V 0.5 –0.5 0.1 –0.1 –1.5 (Ta = –20 to +75°C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 –40 10 –10 –400 –2.0 –10 ±10 Typ. Max. Unit V V V V V µA µA µA µA µA mA µA µA PE0 to PE3, VDD = 5.5V, VI = 0, 5.5V RST∗1 High-speed mode operation (1/2 frequency division clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD Sleep mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Stop mode 1.1 IDD1 18 40 mA IDD2 Power supply current∗3 35 100 µA IDDS1 8 mA IDDS2 9 30 µA IDDS3 VDD = 5.5V, termination of 10MHz and 32kHz crystal oscillation Pins other than PB7, Clock 1MHz PE4, PE5, 0V for all pins excluding measured AVREF, AVSS, pins VDD, VSS 10 µA Input capacity CIN 10 20 pF ∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗2 Pins PA to PD, and PF to PI specify the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. (Excludes output PB7) ∗3 When all pins are open. – 11 – CXP84120/84124 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock input pulse width Event count input clock rise time, fall time Symbol fC Pins (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms XTAL Fig. 1, Fig. 2 EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 TEX TX TEX TEX Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 tXL, tXH tCR, tCF tEH, tEL tER, tEF fC tsys + 50∗1 32.768 kHz tTL, tTH tTR, tTF 10 20 µs ms ∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) 1/fc EXTAL VDD – 0.4V 0.4V tXH tCF tXL tCR Fig. 1. Clock timing Crystal oscillation Ceramic oscillation 32kHz clock applied condition Crystal oscillation External clock EXTAL C1 XTAL C2 EXTAL XTAL TEX TX 74HC04 C1 C2 Fig. 2. Clock applied conditions – 12 – CXP84120/84124 TEX EC0 EC1 0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR Fig. 3. Event count clock timing (2) Serial transfer (CH0) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 float delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input setup time (for SCK0 ↑) SI0 input hold time (for SCK0 ↑) SCK0 ↓ → SO0 delay time Symbol Pin SCK0 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tDCSK tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH, tKL tSIK tKSI tKSO SCK0 SCK0 tsys + 100 8000/fc – 50 100 200 SI0 SI0 tsys + 200 100 SO0 tsys + 200 100 ns ns Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 13 – CXP84120/84124 tWHCS CS0 0.8VDD 0.2VDD tKCY tDCSK tKL tKH tDCSKF 0.8VDD SCK0 0.2VDD 0.8VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD Fig. 4. Serial transfer CH0 timing – 14 – CXP84120/84124 Serial transfer (CH1) Item SCK1 cycle time SCK1 High, Low level width SI1 input setup time (for SCK1 ↑) SI1 input hold time (for SCK1 ↑) SCK1 ↓ → SO1 delay time Symbol Pin SCK1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH, tKL tSIK tKSI tKSO Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD SO1 0.2VDD Output data Fig. 5. Serial transfer CH1 timing – 15 – CXP84120/84124 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT∗1 VFT∗2 Ta = 25°C VDD = 5.0V VSS = AVSS = 0V –10 4930 160/fADC∗3 12/fADC∗3 AVREF AN0 to AN7 Operation mode AVREF IREFS Sleep mode Stop mode 32kHz operation mode VDD – 0.5 0 0.6 VDD AVREF 1.0 10 70 5050 Symbol Pin Condition Min. Typ. Max. 8 ±5 150 5120 Unit Bits LSB mV mV µs µs V V mA µA tCONV tSAMP VIAN IREF Reference input voltage VREF Analog input voltage AVREF current FFH FEH Digital conversion value Linearity error 01H 00H VZT Analog input VFT ∗1 VZT : Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT : Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the below values due to ADC operation clock selection. During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc Fig. 6. Definition of A/D converter terms – 16 – CXP84120/84124 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 INT3 NMI PJ0 to PJ7 RST Condition Min. Max. Unit External interruption High, Low level width tIH tIL 1 µs Reset input Low level width tRSL 8/fc µs tIH tIL 0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge.) 0.2VDD tIL tIH Fig 7. Interruption input timing tRSL RST 0.2VDD Fig. 8. RST input timing – 17 – CXP84120/84124 Appendix (i) Main clock (ii) Main clock (iii) Sub clock EXTAL XTAL EXTAL XTAL ETEX XTAL XTAL TX Rd C1 C2 C1 C2 C1 C2 Fig. 9. SPC700 series recommended oscillation circuit Manufacturer Model CSA4.19MG CSA8.00MG fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 C1 (pF) C2 (pF) Circuit example (i) 30 30 (ii) MURATA MFG CO., LTD. CSA10.0MT CST4.19MGW∗ CST8.00MTW∗ CST10.00MTW∗ RIVER ELETEC CORPORATION HC-49/U03 8.00 10.00 4.19 15 15 (i) KINSEKI LTD. HC-49/U (-S) 8.00 10.00 27 27 Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Mask option table Item Reset pin pull-up resistance Content Non-existent Existent – 18 – CXP84120/84124 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.2 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 QFP080-P-1420 – 19 – 0.8 ± 0.2 1 24 16.3