CXP85632

CXP85632/85640 CMOS 8-bit Single Chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP85632/85640 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, I2C bus interface, PWM output, remote control receiver, HSYNC counter and watchdog timer as well as basic configuration like 8-bit CPU, ROM, RAM and I/O port. Also this IC provides power-on reset function and sleep function which enables to lower power consumption. 64 pin SDIP (PIastic) 64 pin QFP (PIastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) to cover various types of data. — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 333ns at 12MHz operation • Incorporated ROM 32K bytes (CXP85632) 40K bytes (CXP85640) • Incorporated RAM 1888 bytes (excluding the closed caption decoder and on-screen display VRAM) • Peripheral functions — A/D converter 8 bits, 6 channels, successive approximation method (Conversion time of 26.7µs/12MHz) — Serial interface 8-bit clock, sync type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer — Closed caption decoder Incorporated decode slicer, conforming to FCC, 8 × 13 dots, 192 character types, 15 character colors, 4 lines of 34 characters, italic, underline, vertical scroll, 15 frame background colors/half blanking — On-screen display (OSD) function 12 × 16 dots, 128 character types, 15 character colors, 4 lines of 24 characters, 8 frame background colors/half blanking, edging per line (half dot), vertical scroll jitter elimination circuit — I2C bus interface — PWM output 8 bits, 4 channels — Remote control receiver circuit Incorporated 6-stage FIFO 8-bit pulse measurement counter — HSYNC counter 2 channels — Watchdog timer • Interruption 15 factors, 15 vectors, multi-interruption possible • Standby mode SLEEP • Package 64-pin plastic SDIP/QFP • Piggyback/evaluation chip CXP85690 64-pin ceramic PSDIP (accommodates custom font) Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95510-PS XTAL RST MP VDD Vss INT0 INT1 INT2 VIN Rex Cap DATA SLICER CVDD CVss CC DECODER PORT A 8 2 SPC700 CPU CORE EXTAL Block Diagram CLOCK GENERATOR/ SYSTEM CONTROL PA0 to PA7 XLC EXLC R G 3 ROM 32K/40K BYTES RAM 1888 BYTES 2 INTERRUPT CONTROLLER ON SCREEN DISPLAY PORT B 8 PB0 to PB7 B I YS YM HSYNC VSYNC PRESCALER/ TIME BASE TIMER PORT C 8 PC0 to PC7 SI SO SCK RMC FIFO REMOCON PORT E HSC0 HSYNC COUNTER 0 8BIT PWM 4CH HSC1 HSYNC COUNTER 1 I2C BUS INTERFACE UNIT AN0 to AN5 A/D CONVERTER 6CH SCL0 SDA0 SDA1 SCL1 PWM0 to PWM3 PORT F –2– WATCHDOG TIMER SERIAL INTERFACE UNIT EC 8BIT TIMER/COUNTER 0 PORT D 8 PD0 to PD7 3 PE0 to PE2 TO 8BIT TIMER 1 8 PF0 to PF7 CXP85632/85640 CXP85632/85640 Pin Assignment (Top View) 64-pin SDIP PC3 PC2 PC1 PC0 EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST Vss XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 CVss Cap Rex VIN CVDD INT1/PB7 PB6 PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PC4 PC5 PC6 PC7 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 PE0/TO PE1 PE2/INT0 MP Vss VDD NC EXLC XLC YM YS I B G R PB0 PB1 PB2 PB3 PB4 Note) 1. NC (Pin 46) must be connected to VDD. 2. Vss (Pins 16 and 48) must be connected to GND. 3. MP (Pin 49) must be connected to GND. 4. Cap (Pin 26) must be connected to CVSS via a capacitor. 5. Rex (Pin 27) must be connected to CVDD via a resistor of 33kΩ. –3– CXP85632/85640 Pin Assignment (Top View) 64-pin QFP PD6/RMC PC0 64 63 62 61 60 59 58 57 56 55 54 53 52 HS1/PD5 HS0/PD4 SI/PD3 S0/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST Vss XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 CVss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF3/PWM3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 PE0/TO PE1 PE2/INT0 MP Vss VDD NC EXLC XLC YM YS I B G PC2 PC4 PB4 PF0/PWM0 PB0 Rex PF1/PWM1 PD7/EC PC5 PC6 PC7 INT1/PB7 PB3 CVDD Note) 1. NC (Pin 40) must be connected to VDD. 2. Vss (Pins 10 and 42) must be connected to GND. 3. MP (Pin 43) must be connected to GND. 4. Cap (Pin 20 ) must be connected to CVSS via a capacitor. 5. Rex (Pin 21) must be connected to CVDD via a resistor of 33kΩ. –4– PB6 PB5 PB2 PB1 Cap VIN R PF2/PWM2 PC1 PC3 CXP85632/85640 Pin Functions Pin name PA0/AN0 to PA5/AN5 PA6/VSYNC PA7/HSYNC PB0 to PB6 PB7/INT1 I/O I/O/Analog input I/O/Input I/O/Input I/O I/O/Input (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Functions Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input. (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Input for external interruption request. Active at the falling edge. (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Input for external interruption request. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Remote control receiver circuit input. External event input for timer/counter. (Port E) 3-bit I/O port. I/O can be set in a unit of single bits. (3 pins) (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits are 12V drive and upper 4 bits are 5V drive. Rectangular wave output for timer/counter. PC0 to PC7 I/O PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/TO PE1 PE2/INT0 PF0/PWM0 to PF3/PWM3 PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 R, G, B, I, YS, YM I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Output I/O I/O/Input Input for external interruption request. Active at the falling edge. 8-bit PWM outputs. (4 pins) Transfer clock I/O for I2C bus interface. (2 pins) Transfer data I/O for I2C bus interface. (2 pins) Output/Output Output/I/O Output/I/O Output OSD display 6-bit outputs. (6 pins) –5– CXP85632/85640 Pin name EXLC XLC VIN Cap Rex CVDD CVSS EXTAL XTAL RST MP NC VDD Vss Input Input I/O Functions OSD display clock oscillation I/O. Oscillator frequency is determined by external L and C. Input of external composite video signal. Input a 2Vp-p signal via a capacitor. Output Input — — Capacitor connection for the data slicer. Connect a capacitor between Cap and CVSS. Resistor connection for the data slicer. Connect a 33kΩ resistor between Rex and CVDD. Positive power supply for data slicer. GND for data slicer. System clock oscillator crystal connection. When using an external clock, input to EXTAL pin and leave XTAL pin open. Low level active system reset. This pin acts as I/O pin and outputs low level through incorporated power-on reset function when the power turned on. (Mask option) Test mode input. Must be connected to GND. Not connected. Under normal conditions, connect to VDD. Positive power supply. GND. Connect two VSS pins to GND. Output I/O Input –6– CXP85632/85640 I/O Circuit Format for Pins Pin Port A Port A data Circuit format When reset Port A direction IP PA0/AN0 to PA5/AN5 “0” when reset Data bus RD (Port A) Port A function selection “0” when reset A/D converter Input protection circuit Hi-Z 6 pins Port A Input multiplexer Port A data Port A direction IP PA6/VSYNC PA7/HSYNC Data bus RD (Port A) Hi-Z Schmitt input VSYNC, HSYNC 2 pins Port B Port C Port B, C data Input polarity "0" when reset PB0 to PB6 PB7/INT1 PC0 to PC7 Data bus Port B, C direction “0” when reset IP Hi-Z RD (Port B, C) INT1 Schmitt input 16 pins –7– CXP85632/85640 Pin Port D Circuit format When reset Port D data PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC Port D direction “0” when reset Schmitt input Data bus RD (Port D) ∗ IP Hi-Z 6 pins INT2, SI, HS0, HS1, RMC, EC ∗ Large current 12mA Port D SCK, SO Serial output enable Port D data PD1/SCK PD2/SO ∗ Port D direction “0” when reset Data bus Schmitt input IP Hi-Z RD (Port D) SCK only 2 pins Port E ∗ Large current 12mA TO Port E function selection “1” when reset PE0/TO PE1 PE2/INT0 Port E data “1” when reset for PE0, 1 Port E direction “1” when reset for PE0, 1 “0” when reset for PE2 Data bus RD (Port E) INT0 Schmitt input only for PE2 IP PE0, PE1: High PE2: Hi-Z 3 pins –8– CXP85632/85640 Pin Port F PF0/PWM0 to PF3/PWM3 PWM0 to PWM3 Port F selection “0” when reset Port F data “1” when reset Circuit format When reset Hi-Z ∗ ∗ 12V drive voltage Large current 12mA 4 pins Port F SCL, SDA I2C output enable PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 ∗ Port F data “1” when reset SCL, SDA (I2C circuit) Schmitt input Hi-Z IP BUS SW To internal I2C pins (To SCL1 for SCL0) 4 pins ∗ Large current 12mA R G B I YS YM 6 pins R, G, B, I, YS, YM Output polarity “0” when reset Output becomes active by data writing to output polarity register. Hi-Z EXLC XLC EXLC IP Oscillator control Oscillation halted XLC IP OSD display clock 2 pins –9– CXP85632/85640 Pin Circuit format When reset EXTAL XTAL • Diagram indicates equivalent circuit during oscillation. EXTAL IP • Feedback resistor is disconnected during STOP. (This device does not enter in the STOP mode.) Oscillation XTAL 2 pins Pull-up resistor Mask option RST Schmitt input OP Low level From power-on reset circuit (Mask option) 1 pin – 10 – CXP85632/85640 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium voltage tolerance output voltage High level output current High level total output current Symbol VDD VIN VOUT VOUTP IOH ΣIOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation ΣIOL Topr Tstg PD 20 100 –20 to +75 –55 to +150 1000 600 mA mA °C °C mW mW SDIP QFP Ratings –0.3 to +7.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +15.0 –5 –50 15 Unit V V V V mA mA mA (Vss = 0V reference) Remarks PF0 to PF3 pins Total of all output pins Excludes large current output port (value per pin) Large current output port (value per pin∗2) Total of all output pins ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.5 Data slicer supply voltage High level input voltage CVDD VIH VIHS VIHEX VIL Low level input voltage Operating temperature ∗1 ∗2 ∗3 ∗4 ∗5 VILS VILEX Topr 4.5 0.7VDD 0.8VDD VDD – 0.4 0 0 –0.3 –20 Max. 5.5 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 Unit V V V V V V V V V V °C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 or 1/4 frequency dividing mode Guaranteed operation range for 1/16 frequency dividing or SLEEP mode Guaranteed data hold range for STOP mode∗1 ∗5 ∗2 ∗3 EXTAL pin∗4 ∗2 ∗3 EXTAL pin∗4 This device does not enter in the STOP mode. PA, PB, PC, PE0, PE1, SCL0, SCL1, SDA0, SDA1 pins. INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins. Specifies only during external clock input. CVDD and VDD should be set to the same voltage. – 11 – CXP85632/85640 DC Characteristics Item High level output voltage Symbol (Ta = –20 to +75°C, Vss = 0V reference) Pin PA to PD, PE, R, G, B, I, YS, YM PA to PD, PE, R, G, B, I, YS, YM, PF0 to PF3, RST∗1 Condition VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V RST∗2 PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM, RST∗2 PF0 to PF3 ILOH PF4 to PF7 RBS SCL0: SCL1 SDA0: SDA1 VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing mode VDD = 5.5V 12MHz crystal oscillation (C1 = C2 = 15pF) VDD∗3 SLEEP mode VDD = 5.5V, 12MHz crystal oscillation (C1 = C2 = 15pF) STOP mode∗4 VDD = 5.5V, termination of 12MHz oscillation VDD = 5.5V 10 120 µA Ω VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V 0.5 –0.5 –1.5 Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 40 –40 –400 ±10 50 Typ. Max. Unit V V V V V V V µA µA µA µA µA VOH Low level output voltage VOL PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) IIHE Input current IIHL IILR I/O leakage current Open drain output leak current (N-ch Tr off case) I2C bus switch connection impedance (Output Tr off case) IIZ EXTAL IDD 18 30 mA Supply current IDDSL 0.9 3 mA IDDST — — — µA ICVDD Input capacitance CIN CVDD — 5.0 10 10.0 20 mA pF PA to PE, SCL, SDA, 1MHz clock EXLC, EXTAL, VIN, 0V for all pins excluding measured pins RST ∗1 RST pin is specified only when the power-on reset circuit is selected with mask option. ∗2 In RST pin, the input current is specified when the pull-up resistor is selected; the leakage current when no resistor is selected. ∗3 When all pins are open. Specifies only when the OSD oscillation stops. ∗4 This device does not enter in the STOP mode. – 12 – CXP85632/85640 AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock rise and fall times Event counter input clock pulse widtth Event counter input clock rise and fall times ∗1 System fC Pin XTAL EXTAL EXTAL EXTAL EC EC (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig 1, Fig 2 External clock drive Fig. 3 Fig. 3 Min. Typ. 12.0 Max. Unit MHz ns ns ns 20 ms tXL, tXH tCR, tCF tEH, tEL tER, tEF 37.5 200 tsys∗1 + 50 tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits. (CPU clock selection) tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied condition Crystal oscillator Ceramic oscillator External clock EXTAL XTAL EXTAL XTAL C1 C2 OPEN Fig. 3. Event count clock timing 0.8VDD EC 0.2VDD tEH tEF tEL tER – 13 – CXP85632/85640 (2) Serial transfer Item SCK cycle time SCK high and low level widths SI input set-up time (for SCK↑) SI input hold time (for SCK↑) SCK ↓ → SO delay time System Pin SCK (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns tKCY tKH tKL tSIK tKSI tKSO Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD SI Input data 0.2VDD tKSO 0.8VDD SO 0.2VDD Output data – 14 – CXP85632/85640 (3) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT∗1 VFT∗2 Symbol Pin (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Typ. Max. 8 ±1 Ta = 25°C VDD = 5.0V Vss = 0V –50 4910 160/fADC∗3 12/fADC∗3 10 4970 70 5030 Unit Bits LSB mV mV µs µs VDD V tCONV tSAMP VIAN AN0 to AN5 0 Fig. 5. Definitions for A/D converter terms FFH FEH Digital conversion value Linearity error ∗1 VZT: Digital conversion values change between 00H←→01H. ∗2 VFT: Digital conversion values change between 0EH←→0FH. ∗3 fADC indicates the below values due to the bit 6 (CKS) of A/D control registor (ADC: 00F9H) and the bit 7 (PCK1) and bit 6 (PCK0) of clock control registor (CLC: 00FEH) CKS PCK1, 0 0 (φ/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 (φ selection) fADC = fC fADC = fC/2 fADC = fC/8 01H 00H VZT Analog input VFT 00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16) – 15 – CXP85632/85640 (4) Interrupt, reset input Item External interrupt high and low level widths Reset input low level width (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 RST Condition Min. 1 32/fc Max. Unit µs µs tIH tIL tRSL Fig. 6. Interrupt input timing tIH INT0 INT1 INT2 (falling edge) tIL 0.8VDD 0.2VDD Fig. 7. RST input timing tRSL RST 0.2VDD (5) Power-on reset∗1 Item Power supply rise time Power supply cutt-off time Symbol Pin VDD (Ta = –20 to +75°C, Vss = 0V reference) Condition Power-on reset Repeated power-on reset Min. 0.05 1 Max. 50 Unit ms ms tR tOFF ∗1 Specified only when power-on reset function is selected. Fig. 8. Power-on reset VDD 4.5V 0.2V 0.2V tR Take care when turning on power. tOFF – 16 – CXP85632/85640 (6) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock low level width Clock high level width Set-up time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Set-up time for transfer completion (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 0∗1 250 1 300 Max. 100 Unit kHz µs µs µs µs µs µs ns µs ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO ∗1 For data hold time, the SCL rise time is not taken into account so that 300ns must be exceeded. Fig. 9. I2C bus transfer data timing SDA tBUF tR SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P tF tHD; STA Fig. 10. I2C device recommended circuit I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS I2C device R S RP RP • A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike noise caused by CRT flashover. – 17 – CXP85632/85640 (7) OSD (On Screen Display) timing Item OSD clock frequency HSYNC pulse width HSYNC after-write rise and fall times VSYNC before-write rise and fall times (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pin EXLC XLC HSYNC HSYNC VSYNC Condiiton Fig. 12 Fig. 11 Fig. 11 Fig. 11 Min. 4 1.2 200 1.0 Max. 16.5 Unit MHz µs ns µs Symbol fOSC tHWD tHCG tVCG Fig. 11. OSD timing tHWD tHCG HSYNC For OPOL register (01FDH) bit 7 at “0” 0.8VDD 0.2VDD tVCG VSYNC For OPOL register (01FDH) bit 6 at “0” 0.8VDD 0.2VDD Fig. 12. LC oscillator circuit connection EXLC XLC R∗1 L C1 C2 ∗1 The XLC series resistor can reduce the occurrence of undersired radiation. – 18 – CXP85632/85640 (8) Data slicer external circuit Item VIN pin coupling capacitor Symbol CVIN Pin VIN (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Min. Typ. 0.47 Max. Unit µF Remarks B or more of temperature characteristics is recommended. B or more of temperature characteristics is recommended. Cap pin capacitor Rex pin pull-up resistor Ccap Rrex Cap Rex 4700 33 2.0 pF kΩ Vp-p Composite video signal input Video In VIN Fig. 13. Data slicer external recommeded circuit 5.0V CVDD Rrex Rex CVIN R1 VIN Video In R2 C1 Cap Ccap CVss [Recommended Constant] R1 = 100Ω (error: 5%; allowable power dissipation: 1/8 W or more) R2 = 1MΩ (error: 5%; allowable power dissipation: 1/8 W or more) C1 = 820pF (ceramic), B or more of temperature characteristics is recommended. – 19 – CXP85632/85640 Supplement Fig. 14. SPC700 Series recommended oscillation circuit (i) EXTAL XTAL Rd C1 C2 Manufacturer RIVER ELETEC CO., LTD. KINSEKI LTD. Model HC-49/U03 HC-19/U (-S) fc (MHz) 12.0 12.0 C1 (pF) 5 15 C2 (pF) 5 15 Rd (Ω) 0∗1 0∗1 Circuit example (i) (i) ∗1 The XTAL series resistor can reduce the effect of electrostatic discharge noise. Mask Option Table Item Reset pin pull-up resistor Power-on reset circuit Inclusion Non-existent Non-existent Existent Existent – 20 – CXP85632/85640 Fig. 15. Characteristics curves IDD vs. VDD (fc = 12MHz, Ta = 25°C, Typical) 100 50 1 frequency 2 dividing mode 45 1 frequency 4 dividing mode 1 frequency 2 dividing mode IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 40 10 35 1 frequency 16 dividing mode IDD – Supply current [mA] IDD – Supply current [mA] 30 25 20 1 frequency 4 dividing mode 15 1 SLEEP mode 10 1 frequency 16 dividing mode 5 SLEEP mode 0.1 2 3 4 5 6 0 4 8 fc – System clock [MHz] 12 16 VDD – Supply voltage [V] Parameter curve for OSD oscillation L vs. C (theoretically calculated value) 100 L – Inductance [µH] 10 10MHz 12MHz 14MHz 16MHz fOSC = 0 1 2π LC 50 C1, C2 – Capacitance [pF] C = C1 // C2 100 – 21 – CXP85632/85640 Package Outline Unit: mm 64PIN SDIP (PLASTIC) 750mil + 0.4 57.6 – 0.1 64 33 19.05 + 0.3 17.1 – 0.1 + 0.1 0.05 0.25 – 0° to 15° 32 0.5 ± 0.1 0.9 ± 0.15 1 1.778 PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 51 33 3 MIN 0.5 MIN + 0.4 4.75 – 0.1 + 0.1 0.15 – 0.05 0.15 52 32 17.9 ± 0.4 + 0.4 14.0 – 0.1 64 20 + 0.2 0.1 – 0.05 1 1.0 + 0.15 0.4 – 0.1 19 + 0.35 2.75 – 0.15 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP–64P–L01 ∗ QFP064–P–1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g – 22 – 0.8 ± 0.2 16.3