AM29LV640ML112RPCI

Am29LV640MH/L Data Sheet RETIRED PRODUCT This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M H/L and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. April 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 26191 Revision F Amendment +3 Issue Date December 14, 2005 THIS PAGE LEFT INTENTIONALLY BLANK. Am29LV640MH/L 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M H/L and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation — 3 V for read, erase, and program operations VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages on the DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V Manufactured on 0.23 µm MirrorBit process technology SecSi™ (Secured Silicon) Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer Flexible sector architecture — One hundred twenty-eight 32 Kword/64-Kbyte sectors Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/byte updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current Package options — 56-pin TSOP — 64-ball Fortified BGA SOFTWARE FEATURES — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices HARDWARE FEATURES — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: VID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects first or last sector regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26191 Rev: F Amendment/3 Issue Date: December 14, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. DATASHEET GENERAL DESCRIPTION The Am29LV640MH/L is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words or 8,388,608 bytes. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Ordering Information sections. The device is offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a s ingle 3.0 volt power supply for both read and write functions. In addition to a V CC i nput, a high-voltage a ccelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The P rogram Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin. The protected sector will still be protected even during accelerated programming. The S ecSi ™ ( Secured Silicon) Sector p rovides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. 2 Am29LV640MH/L December 14, 2005 DATASHEET MIRRORBIT 64 MBIT DEVICE FAMILY Device LV065MU LV640MT/B LV640MH/L LV641MH/L LV640MU Bus x8 x8/x16 x8/x16 x16 x16 Sector Architecture Uniform (64 Kbyte) Boot (8 x 8 Kbyte at top & bottom) Uniform (64 Kbyte) Uniform (32 Kword) Uniform (32 Kword) Packages 48-pin TSOP (std. & rev. pinout), 63-ball FBGA 48-pin TSOP, 63-ball Fine-pitch BGA, 64-ball Fortified BGA 56-pin TSOP (std. & rev. pinout), 64-ball Fortified BGA 48-pin TSOP (std. & rev. pinout) 64-ball Fortified BGA, 64-Ball Fine-Pitch BGA VIO Yes No Yes Yes Yes RY/BY# Yes Yes Yes No Yes WP#, ACC ACC only WP#/ACC pin WP#/ACC pin Separate WP# and ACC pins ACC only WP# Protection No WP# 2 x 8 Kbyte top or bottom 1 x 64 Kbyte high or low 1 x 32 Kword top or bottom No WP# Related Documents To download related documents, click on the following links or go to www.amd.com→Flash Memory→Product Information→MirrorBit→Flash Information→Technical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs AMD MirrorBit™ White Paper December 14, 2005 Am29LV640MH/L 3 DATASHEET TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations .....................................................10 Erase Suspend/Erase Resume Commands ........................... 32 Command Definitions ............................................................. 33 Command Definitions (x16 Mode, BYTE# = VIH) ............................ 33 Command Definitions (x8 Mode, BYTE# = VIL)............................... 34 Write Operation Status . . . . . . . . . . . . . . . . . . . . 35 DQ7: Data# Polling ................................................................. 35 Figure 8. Data# Polling Algorithm .................................................. 36 Word/Byte Configuration ........................................................ 11 VersatileIO™ (VIO) Control ..................................................... 11 Requirements for Reading Array Data ................................... 11 Page Mode Read .................................................................... 11 Writing Commands/Command Sequences ............................ 11 Write Buffer ............................................................................. 11 Accelerated Program Operation ............................................. 11 Autoselect Functions .............................................................. 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12 Autoselect Mode ..................................................................... 16 Table 2. Autoselect Codes, (High Voltage Method) .......................16 RY/BY#: Ready/Busy# ............................................................ 37 DQ6: Toggle Bit I .................................................................... 37 Figure 9. Toggle Bit Algorithm........................................................ 38 DQ2: Toggle Bit II ................................................................... 38 Reading Toggle Bits DQ6/DQ2 ............................................... 39 DQ5: Exceeded Timing Limits ................................................ 39 DQ3: Sector Erase Timer ....................................................... 39 DQ1: Write-to-Buffer Abort ..................................................... 39 Table 10. Write Operation Status ................................................... 40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 41 Figure 10. Maximum Negative Overshoot Waveform .................... 41 Figure 11. Maximum Positive Overshoot Waveform ..................................................................... 41 Sector Group Protection and Unprotection ............................. 16 Table 3. Sector Group Protection/Unprotection Address Table ......16 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 12. Test Setup..................................................................... 43 Table 1. Test Specifications ........................................................... 43 Write Protect (WP#) ................................................................ 18 Temporary Sector Group Unprotect ....................................... 18 Figure 1. Temporary Sector Group Unprotect Operation................ 18 Figure 2. In-System Sector Group Protect/Unprotect Algorithms .......................................................... 19 Key to Switching Waveforms. . . . . . . . . . . . . . . . 43 Figure 13. Input Waveforms and Measurement Levels...................................................................... 43 SecSi (Secured Silicon) Sector Flash Memory Region .......... 20 Figure 3. SecSi Sector Protect Verify.............................................. 21 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 Read-Only Operations ........................................................... 44 Figure 14. Read Operation Timings ............................................... 44 Figure 15. Page Read Timings ...................................................... 45 Hardware Data Protection ...................................................... 21 Low VCC Write Inhibit ............................................................ 21 Write Pulse “Glitch” Protection ............................................... 21 Logical Inhibit .......................................................................... 21 Power-Up Write Inhibit ............................................................ 21 Common Flash Memory Interface (CFI) . . . . . . . 21 CFI Query Identification String........................................................ 22 System Interface String................................................................... 22 Table 6. Device Geometry Definition .............................................. 23 Table 7. Primary Vendor-Specific Extended Query ........................ 24 Hardware Reset (RESET#) .................................................... 46 Figure 16. Reset Timings ............................................................... 46 Erase and Program Operations .............................................. 47 Figure 17. Program Operation Timings.......................................... Figure 18. Accelerated Program Timing Diagram.......................... Figure 19. Chip/Sector Erase Operation Timings .......................... Figure 20. Data# Polling Timings (During Embedded Algorithms)...................................................... Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... Figure 22. DQ2 vs. DQ6................................................................. 48 48 49 50 51 51 Command Definitions . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ................................................................ 24 Reset Command ..................................................................... 25 Autoselect Command Sequence ............................................ 25 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25 Word/Byte Program Command Sequence ............................. 25 Unlock Bypass Command Sequence ..................................... 26 Write Buffer Programming ...................................................... 26 Accelerated Program .............................................................. 27 Figure 4. Write Buffer Programming Operation............................... 28 Figure 5. Program Operation .......................................................... 29 Temporary Sector Unprotect .................................................. 52 Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 52 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 53 Alternate CE# Controlled Erase and Program Operations ..... 54 Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 55 Program Suspend/Program Resume Command Sequence ... 29 Figure 6. Program Suspend/Program Resume............................... 30 Chip Erase Command Sequence ........................................... 30 Sector Erase Command Sequence ........................................ 30 Figure 7. Erase Operation............................................................... 31 Erase And Programming Performance . . . . . . . 56 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 56 TSOP Pin and BGA Package Capacitance . . . . . 56 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57 TS056/TSR056—56-Pin Standard and Reverse Pinout Thin Small Outline Package (TSOP) ...................................... 57 LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package .................................................................................. 58 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 59 4 Am29LV640MH/L December 14, 2005 DATASHEET PRODUCT SELECTOR GUIDE Part Number VCC = 3.0–3.6 V Speed Option VCC = 2.7–3.6 V Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (tPACC) Max. OE# Access Time (ns) 90 90 25 25 90R (VIO = 3.0– 3.6 V) 101R (VIO = 2.7– 3.6 V) 101 (VIO = 2.7– 3.6 V) 100 100 30 30 Am29LV640MH/L 112R (VIO = 1.65– 3.6 V) 112 (VIO = 1.65 –3.6 V) 110 110 30 30 40 40 120R (VIO = 1.65 –3.6 V) 120 (VIO = 1.65– 3.6 V) 120 120 30 30 40 40 Notes: 1. See “AC Characteristics” for full specifications. 2. For the Am29LV640MH-L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. Please use OPNs as listed on p. 9 when placing orders. BLOCK DIAGRAM RY/BY# VCC VSS Sector Switches Erase Voltage Generator DQ0–DQ15 (A-1) VIO Input/Output Buffers RESET# WE# WP#/ACC BYTE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE# OE# STB VCC Detector Timer Address Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A21–A0 December 14, 2005 26191F3 Am29LV640MH/L 5 DATASHEET CONNECTION DIAGRAMS NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO 56-Pin Standard TSOP NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin Reverse TSOP 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 6 Am29LV640MH/L 26191F3 December 14, 2005 DATASHEET CONNECTION DIAGRAMS 64-Ball Fortified BGA Top View, Balls Facing Down A8 NC A7 A13 A6 A9 A5 WE# A4 B8 NC B7 A12 B6 A8 B5 RESET# B4 C8 NC C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 NC D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 NC E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 NC F8 NC F7 G8 NC G7 H8 NC H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 NC BYTE# DQ15/A-1 F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 NC RY/BY# WP#/ACC A3 A7 A2 A3 A1 NC B3 A17 B2 A4 B1 NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The pack- age and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. December 14, 2005 Am29LV640MH/L 7 DATASHEET PIN DESCRIPTION A21–A0 = 22 Address inputs DQ14–DQ0 = 15 Data inputs/outputs DQ15/A-1 CE# OE# WE# WP#/ACC = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) = Chip Enable input = Output Enable input = Write Enable input = Hardware Write Protect input/Programming Acceleration input RESET# RY/BY# BYTE# VCC = Hardware Reset Pin input = Ready/Busy output = Selects 8-bit or 16-bit mode = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Output Buffer power = Device Ground = Pin Not Connected Internally VIO VSS NC Logic Symbol 22 A21–A0 CE# OE# WE# WP#/ACC RESET# VIO BYTE# RY/BY# DQ15–DQ0 (A-1) 16 or 8 8 Am29LV640MH/L December 14, 2005 DATASHEET ORDERING INFORMATION Standard Products Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV640M H 120R PC I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE TYPE E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PC = 64-Ball Fortified Ball Grid Array, 1.0 mm pitch, 13 x 11 mm package (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV640MH/L 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory with VersatileIO™ Control, 3.0 Volt-only Read, Program, and Erase Valid Combinations for TSOP Package (Note 2) Am29LV640MH90R Am29LV640ML90R Am29LV640MH112 Am29LV640ML112 Am29LV640MH120 Am29LV640ML120 Am29LV640MH101R Am29LV640ML101R Am29LV640MH112R Am29LV640ML112R Am29LV640MH120R Am29LV640ML120R EI, FI Speed (ns) 90 110 120 100 110 120 VIO Range (V) 3.0–3.6 1.65–3.6 VCC Range (V) 3.0–3.6 Valid Combinations for Fortified BGA Package (Note 2) Order Number Am29LV640MH90R Am29LV640ML90R Am29LV640MH101 Am29LV640ML101 Am29LV640MH112 Am29LV640ML112 Package Marking L640MH90NI L640ML90NI L640MH01PI L640ML01PI L640MH11PI L640ML11PI PCI L640MH12PI L640ML12PI L640MH01NI L640ML01NI L640MH11NI L640ML11NI L640MH12NI L640ML12NI VIO VCC Speed Range Range (ns) (V) (V) 90 100 110 120 100 110 120 3.0– 3.6 2.7– 3.6 1.65– 3.6 1.65– 3.6 2.7– 3. 1.65– 3.6 1.65– 3.6 3.0– 3.6 2.7– 3.6 3.0– 3.6 2.7–3.6 1.65–3.6 2.7–3.6 1.65–3.6 1.65–3.6 3.0–3.6 Am29LV640MH120 Am29LV640ML120 Am29LV640MH101R Am29LV640ML101R Am29LV640MH112R Am29LV640ML112R Am29LV640MH120R Am29LV640ML120R Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Notes: 1. For the Am29LV640MH-L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. 2. To select product with ESN factory-locked into the SecSi Sector: 1) select order number from the valid combinations given above, 2) add designator “N” at the end of the order number, and 3) modify the speed option indicator as follows [101R = 10R, 112R = 11R, 120R = 12R, 90R, 101, 112, 120 = no change] Example: Am29LV640MH12RPCIN. For Fortified BGA packages, the designator “N” will also appear at the end of the package marking. Example: L640MH12NIN. December 14, 2005 Am29LV640MH/L 9 DATASHEET DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Device Bus Operations Addresses (Note 2) AIN AIN AIN X X X SA, A6 =L, A3=L, A2=L, A1=H, A0=L SA, A6=H, A3=L, A2=L, A1=H, A0=L AIN DQ8–DQ15 DQ0– BYTE# BYTE# DQ7 = VIL = VIH DOUT DOUT DQ8–DQ14 (Note 4) (Note 4) = High-Z, (Note 4) (Note 4) DQ15 = A-1 High-Z High-Z High-Z (Note 4) High-Z High-Z High-Z X High-Z High-Z High-Z X Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Sector Group Protect (Note 2) Sector Group Unprotect (Note 2) Temporary Sector Group Unprotect CE# L L L VCC ± 0.3 V L X L OE# L H H X H X H WE# RESET# WP# H H X L H (Note 3) L H (Note 3) VCC ± X X 0.3 V H H X X L X L VID H ACC X X VHH H X X X L X H X L X VID VID H H X X (Note 4) X X High-Z (Note 4) (Note 4) Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0 in word mode; A21:A-1 in byte mode. Sector addresses are A21:A15 in both modes. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section. 3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). 10 Am29LV640MH/L December 14, 2005 DATASHEET Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC o r tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses. VersatileIO™ (VIO) Control The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See “Ordering Information” on page 9 for VIO options on this device. For example, a VI/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be 11 Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an December 14, 2005 Am29LV640MH/L DATASHEET at VHH for operations other than accelerated programming, or device damage may result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables 12 Am29LV640MH/L December 14, 2005 DATASHEET 8-bit Address Range (in hexadecimal) 000000–00FFFF 010000–01FFFF 020000–02FFFF 030000–03FFFF 040000–04FFFF 050000–05FFFF 060000–06FFFF 070000–07FFFF 080000–08FFFF 090000–09FFFF 0A0000–0AFFFF 0B0000–0BFFFF 0C0000–0CFFFF 0D0000–0DFFFF 0E0000–0EFFFF 0F0000–0FFFFF 100000–10FFFF 110000–11FFFF 120000–12FFFF 130000–13FFFF 140000–14FFFF 150000–15FFFF 160000–16FFFF 170000–17FFFF 180000–18FFFF 190000–19FFFF 1A0000–1AFFFF 1B0000–1BFFFF 1C0000–1CFFFF 1D0000–1DFFFF 1E0000–1EFFFF 1F0000–1FFFFF 200000–20FFFF 210000–21FFFF 220000–22FFFF 230000–23FFFF 240000–24FFFF 250000–25FFFF 260000–26FFFF 270000–27FFFF 280000–28FFFF 290000–29FFFF 2A0000–2AFFFF 2B0000–2BFFFF 2C0000–2CFFFF 2D0000–2DFFFF 2E0000–2EFFFF 2F0000–2FFFFF 300000–30FFFF 310000–31FFFF 320000–32FFFF 330000–33FFFF 340000–34FFFF 350000–35FFFF 360000–36FFFF 370000–37FFFF 16-bit Address Range (in hexadecimal) 000000–007FFF 008000–00FFFF 010000–017FFF 018000–01FFFF 020000–027FFF 028000–02FFFF 030000–037FFF 038000–03FFFF 040000–047FFF 048000–04FFFF 050000–057FFF 058000–05FFFF 060000–067FFF 068000–06FFFF 070000–077FFF 078000–07FFFF 080000–087FFF 088000–08FFFF 090000–097FFF 098000–09FFFF 0A0000–0A7FFF 0A8000–0AFFFF 0B0000–0B7FFF 0B8000–0BFFFF 0C0000–0C7FFF 0C8000–0CFFFF 0D0000–0D7FFF 0D8000–0DFFFF 0E0000–0E7FFF 0E8000–0EFFFF 0F0000–0F7FFF 0F8000–0FFFFF 100000–107FFF 108000–10FFFF 110000–117FFF 118000–11FFFF 120000–127FFF 128000–12FFFF 130000–137FFF 138000–13FFFF 140000–147FFF 148000–14FFFF 150000–157FFF 158000–15FFFF 160000–167FFF 168000–16FFFF 170000–177FFF 178000–17FFFF 180000–187FFF 188000–18FFFF 190000–197FFF 198000–19FFFF 1A0000–1A7FFF 1A8000–1AFFFF 1B0000–1B7FFF 1B8000–1BFFFF Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A21–A15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 December 14, 2005 Am29LV640MH/L 13 DATASHEET 8-bit Address Range (in hexadecimal) 380000–38FFFF 390000–39FFFF 3A0000–3AFFFF 3B0000–3BFFFF 3C0000–3CFFFF 3D0000–3DFFFF 3E0000–3EFFFF 3F0000–3FFFFF 400000–40FFFF 410000–41FFFF 420000–42FFFF 430000–43FFFF 440000–44FFFF 450000–45FFFF 460000–46FFFF 470000–47FFFF 480000–48FFFF 490000–49FFFF 4A0000–4AFFFF 4B0000–4BFFFF 4C0000–4CFFFF 4D0000–4DFFFF 4E0000–4EFFFF 4F0000–4FFFFF 500000–50FFFF 510000–51FFFF 520000–52FFFF 530000–53FFFF 540000–54FFFF 550000–55FFFF 560000–56FFFF 570000–57FFFF 580000–58FFFF 590000–59FFFF 5A0000–5AFFFF 5B0000–5BFFFF 5C0000–5CFFFF 5D0000–5DFFFF 5E0000–5EFFFF 5F0000–5FFFFF 600000–60FFFF 610000–61FFFF 620000–62FFFF 630000–63FFFF 640000–64FFFF 650000–65FFFF 660000–66FFFF 670000–67FFFF 680000–68FFFF 690000–69FFFF 6A0000–6AFFFF 6B0000–6BFFFF 6C0000–6CFFFF 6D0000–6DFFFF 6E0000–6EFFFF 6F0000–6FFFFF 16-bit Address Range (in hexadecimal) 1C0000–1C7FFF 1C8000–1CFFFF 1D0000–1D7FFF 1D8000–1DFFFF 1E0000–1E7FFF 1E8000–1EFFFF 1F0000–1F7FFF 1F8000–1FFFFF 200000–207FFF 208000–20FFFF 210000–217FFF 218000–21FFFF 220000–227FFF 228000–22FFFF 230000–237FFF 238000–23FFFF 240000–247FFF 248000–24FFFF 250000–257FFF 258000–25FFFF 260000–267FFF 268000–26FFFF 270000–277FFF 278000–27FFFF 280000–287FFF 288000–28FFFF 290000–297FFF 298000–29FFFF 2A0000–2A7FFF 2A8000–2AFFFF 2B0000–2B7FFF 2B8000–2BFFFF 2C0000–2C7FFF 2C8000–2CFFFF 2D0000–2D7FFF 2D8000–2DFFFF 2E0000–2E7FFF 2E8000–2EFFFF 2F0000–2F7FFF 2F8000–2FFFFF 300000–307FFF 308000–30FFFF 310000–317FFF 318000–31FFFF 320000–327FFF 328000–32FFFF 330000–337FFF 338000–33FFFF 340000–347FFF 348000–34FFFF 350000–357FFF 358000–35FFFF 360000–367FFF 368000–36FFFF 370000–377FFF 378000–37FFFF Sector SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A21–A15 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 14 Am29LV640MH/L December 14, 2005 DATASHEET 8-bit Address Range (in hexadecimal) 700000–70FFFF 710000–71FFFF 720000–72FFFF 730000–73FFFF 740000–74FFFF 750000–75FFFF 760000–76FFFF 770000–77FFFF 780000–78FFFF 790000–79FFFF 7A0000–7AFFFF 7B0000–7BFFFF 7C0000–7CFFFF 7D0000–7DFFFF 7E0000–7EFFFF 7F0000–7FFFFF 16-bit Address Range (in hexadecimal) 380000–387FFF 388000–38FFFF 390000–397FFF 398000–39FFFF 3A0000–3A7FFF 3A8000–3AFFFF 3B0000–3B7FFF 3B8000–3BFFFF 3C0000–3C7FFF 3C8000–3CFFFF 3D0000–3D7FFF 3D8000–3DFFFF 3E0000–3E7FFF 3E8000–3EFFFF 3F0000–3F7FFF 3F8000–3FFFFF Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21–A15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Note: The address range is A21:A-1 in byte mode (BYTE# = VIL) or A21:A0 in word mode (BYTE# = VIH). December 14, 2005 Am29LV640MH/L 15 DATASHEET Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 3. Table 2. Description Manufacturer ID: AMD Device ID Cycle 1 Cycle 2 Cycle 3 L L L L H H SA X X X VID VID X X L L L L H X X VID X L CE# L In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tables 10 and 11. This method does not require VID. Refer to the Autoselect Command Sequence section for more information. Autoselect Codes, (High Voltage Method) A9 VID A8 to A7 X A6 L A5 to A4 X X A3 to A2 L L H H X X L L DQ8 to DQ15 A21 A14 OE# WE# to to A15 A10 L H X X A1 L L H H H H A0 L H L H L H BYTE#= BYTE# = VIH VIL DQ7 to DQ0 01h 7Eh 0Ch 01h 01h (protected), 00h (unprotected) 98h (factory locked), 18h (not factory locked) 88h (factory locked), 08h (not factory locked) 00 22 22 22 X X X X X X X X Sector Protection Verification SecSi Sector Indicator Bit (DQ7), WP# protects highest address sector SecSi Sector Indicator Bit (DQ7), WP# protects lowest address sector L L H X X VID X L X L H H X X Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Sector Group Protection and Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows Table 3. the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Autoselect Mode section for details. Sector Group Protection/Unprotection Address Table A21–A15 0000000 0000001 0000010 0000011 00001xx 00010xx 00011xx SA0 SA1 SA2 SA3 SA4–SA7 SA8–SA11 SA12–SA15 Sector Group 16 Am29LV640MH/L December 14, 2005 DATASHEET Table 3. Sector Group Protection/Unprotection Address Table A21–A15 00100xx 00101xx 00110xx 00111xx 01000xx 01001xx 01010xx 01011xx 01100xx 01101xx 01110xx 01111xx 10000xx 10001xx 10010xx 10011xx 10100xx 10101xx 10110xx 10111xx 11000xx 11001xx 11010xx 11011xx 11100xx 11101xx 11110xx 1111100 1111101 1111110 1111111 SA16–SA19 SA20–SA23 SA24–SA27 SA28–SA31 SA32–SA35 SA36–SA39 SA40–SA43 SA44–SA47 SA48–SA51 SA52–SA55 SA56–SA59 SA60–SA63 SA64–SA67 SA68–SA71 SA72–SA75 SA76–SA79 SA80–SA83 SA84–SA87 SA88–SA91 SA92–SA95 SA96–SA99 SA100–SA103 SA104–SA107 SA108–SA111 SA112–SA115 SA116–SA119 SA120–SA123 SA124 SA125 SA126 SA127 Sector Group December 14, 2005 Am29LV640MH/L 17 DATASHEET Write Protect (WP#) The Write Protect function provides a hardware method of protecting the first or last sector without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in “DC Characteristics”. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note: No external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Temporary Sector Group Unprotect (Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Group Unprotect Completed (Note 2) Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again. Figure 1. Temporary Sector Group Unprotect Operation 18 Am29LV640MH/L December 14, 2005 DATASHEET START PLSCNT = 1 RESET# = VID Wait 1 μs Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address START PLSCNT = 1 RESET# = VID Wait 1 μs Temporary Sector Group Unprotect Mode No First Write Cycle = 60h? First Write Cycle = 60h? No Temporary Sector Group Unprotect Mode Yes Set up sector group address No Yes All sector groups protected? Yes Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6–A0 = 1xx0010 Reset PLSCNT = 1 Sector Group Protect: Write 60h to sector group address with A6–A0 = 0xx0010 Wait 150 µs Increment PLSCNT Verify Sector Group Protect: Write 40h to sector group address with A6–A0 = 0xx0010 Wait 15 ms Read from sector group address with A6–A0 = 0xx0010 No No PLSCNT = 25? Data = 01h? Increment PLSCNT Verify Sector Group Unprotect: Write 40h to sector group address with A6–A0 = 1xx0010 Yes Yes Protect another sector group? No Remove VID from RESET# Yes Read from sector group address with A6–A0 = 1xx0010 No Set up next sector group address Data = 00h? No PLSCNT = 1000? Yes Device failed Yes Device failed Write reset command Last sector group verified? Yes Remove VID from RESET# No Sector Group Protect Algorithm Sector Group Protect complete Sector Group Unprotect Algorithm Write reset command Sector Group Unprotect complete Figure 2. In-System Sector Group Protect/Unprotect Algorithms December 14, 2005 Am29LV640MH/L 19 DATASHEET SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words/256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. SecSi Sector Address Range x16 000000h– 000007h 000008h– 00007Fh x8 000000h– 00000Fh 000010h– 0000FFh Standard Factory Locked ESN Unavailable AMD offers the device with the SecSi Sector either factor y locked o r custo mer lockable. The factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The SecSi sector address space in this device is allocated as follows: ExpressFlash Factory Locked ESN or determined by customer Determined by customer Customer Lockable Determined by customer The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. See Table 5 for SecSi Sector addressing. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may pro- gram and protect the 128-word/256 bytes SecSi sector. See Table 5 for SecSi Sector addressing. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. 20 Am29LV640MH/L December 14, 2005 DATASHEET START RESET# = VIH or VID Wait 1 ms Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Figure 3. SecSi Sector Protect Verify pins to prevent unintentional writes when V CC i s greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 10 and 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6–9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6–9. The system must write the reset command to return the device to reading array data. December 14, 2005 Am29LV640MH/L 21 DATASHEET For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. AlternaTable 4. Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (x8) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h tively, contact a sales office or representative for copies of these documents. CFI Query Identification String Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 5. Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (x8) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0001h 0005h 0004h 0000h System Interface String Description VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N µs Typical timeout for Min. size buffer write 2N µs (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) 22 Am29LV640MH/L December 14, 2005 DATASHEET Table 6. Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (x8) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0017h 0002h 0000h 0005h 0000h 0001h 007Fh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 Information (refer to CFI publication 100) Erase Block Region 4 Information (refer to CFI publication 100) December 14, 2005 Am29LV640MH/L 23 DATASHEET Table 7. Addresses (x16) 40h 41h 42h 43h 44h 45h Addresses (x8) 80h 82h 84h 86h 88h 8Ah Data 0050h 0052h 0049h 0031h 0033h 0008h Primary Vendor-Specific Extended Query Description Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word/8 Byte Page, 02 = 8 Word/16 Byte Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 0002h 0001h 0001h 0004h 0000h 0000h 0001h 00B5h 00C5h 4Fh 9Eh 0004h/ 0005h 50h A0h 0001h COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values o r writing them in the i mproper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data 24 Am29LV640MH/L December 14, 2005 DATASHEET The Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. Identifier Code Manufacturer ID Device ID, Cycle 1 Device ID, Cycle 2 Device ID, Cycle 3 SecSi Sector Factory Protect Sector Protect Verify Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: A7:A0 (x16) 00h 01h 0Eh 0Fh 03h (SA)02h A6:A-1 (x8) 00h 02h 1Ch 1Eh 06h (SA)04h Note: The device ID is read over three cycles. SA = Sector Address Tables 10 and 11 show the address requirements and codes. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend). Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word/byte program command sequence, respectively. Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi December 14, 2005 Am29LV640MH/L 25 DATASHEET When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. N ote that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A b it cannot be programmed from “0” back to a “1.” A ttempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX–A4. All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host s y s t e m m u s t t h e r e fo r e a c c o u n t fo r l o a d i n g a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: 26 Am29LV640MH/L December 14, 2005 DATASHEET ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. December 14, 2005 Am29LV640MH/L 27 DATASHEET Write “Write to Buffer” command and Sector Address Write number of addresses to program minus 1(WC) and Sector Address Part of “Write to Buffer” Command Sequence Write first address/data Yes WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write “Write-to-buffer Abort Reset” command sequence to return to read mode. Write to a different sector address (Note 1) Write next address/data pair WC = WC - 1 Write program buffer to flash sector address Notes: 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. Read DQ7 - DQ0 at Last Loaded Address 2. 3. Yes DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. See Table 11 for command sequences required for write buffer programming. DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? No 4. Yes Read DQ7 - DQ0 with address = Last Loaded Address (Note 2) DQ7 = Data? No Yes (Note 3) FAIL or ABORT PASS Figure 4. Write Buffer Programming Operation 28 Am29LV640MH/L December 14, 2005 DATASHEET START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 11 for program command sequence. Figure 5. Program Operation autoselect, and CFI functions are unavailable when an program operation is in progress. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 μs maximum (5 μs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. Note that the SecSi Sector, December 14, 2005 Am29LV640MH/L 29 DATASHEET Program Operation or Write-to-Buffer Sequence in Progress Write address/data XXXh/B0h Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Wait 15 μs Read data as required Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors No Done reading? Yes Write address/data XXXh/30h Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend Figure 6. Program Suspend/Program Resume mediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. N ote that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 10 and 11 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Tables 10 and 11 show the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for December 14, 2005 30 Am29LV640MH/L DATASHEET an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Tables 10 and 11 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 7. Erase Operation December 14, 2005 Am29LV640MH/L 31 DATASHEET Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 (typical 5 µs) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance will not be significantly impacted. 32 Am29LV640MH/L December 14, 2005 DATASHEET Command Definitions Table 8. Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Autoselect (Note 7) Manufacturer ID Device ID (Note 8) SecSi™ Sector Factory Protect (Note 9) Sector Group Protect Verify (Note 10) Cycles Command Definitions (x16 Mode, BYTE# = VIH) Bus Cycles (Notes 2–5) First Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Addr RA XXX 555 555 555 555 555 555 555 555 SA 555 555 XXX XXX 555 555 XXX XXX 55 Data RD F0 AA AA AA AA AA AA AA AA 29 AA AA A0 90 AA AA B0 30 98 1 1 4 6 4 4 3 4 4 6 1 3 3 2 2 6 6 1 1 1 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 55 55 55 55 55 55 PD 00 55 55 555 555 555 555 555 555 555 SA 555 555 90 90 90 90 88 90 A0 25 F0 20 X00 X01 X03 (SA)X02 0001 227E (Note 10) 00/01 X0E 220C X0F 2201 Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 12) Unlock Bypass Unlock Bypass Program (Note 13) Unlock Bypass Reset (Note 14) Chip Erase Sector Erase Program/Erase Suspend (Note 15) Program/Erase Resume (Note 16) CFI Query (Note 17) Legend: XXX PA SA 00 PD WC PA PD WBL PD 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 X = Don’t care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address . Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes: 1. 2. 3. 4. See Table 1 for description of bus operations. All values are in hexadecimal. Shaded cells indicate read cycles. All others are write cycles. During unlock and command cycles, when lower address bits are 555 or 2AA as shown in table, address bits above A11 and data bits above DQ7 are don’t care. No unlock or command cycles required when device is in read mode. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device is providing status information. Fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD and WC. See Autoselect Command Sequence section for more information. Device ID must be read in three cycles. 9. If WP# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. If WP# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. Data is 00h for an unprotected sector group and 01h for a protected sector group. Total number of cycles in command sequence is determined by number of words written to write buffer. Maximum number of cycles in command sequence is 21, including "Program Buffer to Flash" command. Command sequence resets device for next command after aborted write-to-buffer operation. Unlock Bypass command is required prior to Unlock Bypass Program command. Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only during a sector erase operation. Erase Resume command is valid only during Erase Suspend mode. 10. 11. 5. 6. 12. 13. 14. 15. 7. 8. 16. December 14, 2005 Am29LV640MH/L 33 DATASHEET Table 9. Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSi™ Sector Factory Protect (Note 10) Sector Group Protect Verify (Note 11) Cycles Command Definitions (x8 Mode, BYTE# = VIL) Bus Cycles (Notes 2–5) First Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Addr RA XXX AAA AAA AAA AAA AAA AAA AAA AAA SA AAA AAA XXX XXX AAA AAA XXX XXX AA Data RD F0 AA AA AA AA AA AA AA AA 29 AA AA A0 90 AA AA B0 30 98 1 1 4 6 4 4 3 4 4 6 1 3 3 2 2 6 6 1 1 1 555 555 555 555 555 555 555 555 555 555 PA XXX 555 555 55 55 55 55 55 55 55 55 55 55 PD 00 55 55 AAA AAA AAA AAA AAA AAA AAA SA AAA AAA 90 90 90 90 88 90 A0 25 F0 20 X00 X02 X06 (SA)X04 01 7E (Note 10) 00/01 X1C 0C X1E 01 Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 12) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Unlock Bypass Unlock Bypass Program (Note 14) Unlock Bypass Reset (Note 15) Chip Erase Sector Erase Program/Erase Suspend (Note 16) Program/Erase Resume (Note 17) CFI Query (Note 18) Legend: XXX PA SA 00 PD BC PA PD WBL PD AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA SA 10 30 X = Don’t care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address . Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page as PA. BC = Byte Count. Number of write buffer locations to load minus 1. Notes: 1. 2. 3. 4. See Table 1 for description of bus operations. All values are in hexadecimal. Shaded cells indicate read cycles. All others are write cycles. During unlock and command cycles, when lower address bits are 555 or AAA as shown in table, address bits above A11 are don’t care. Unless otherwise noted, address bits A21–A11 are don’t cares. No unlock or command cycles required when device is in read mode. Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device is providing status information. Fourth cycle of autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect Command Sequence section or more information. Device ID must be read in three cycles. 10. If WP# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. If WP# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. 11. Data is 00h for an unprotected sector group and 01h for a protected sector group. 12. Total number of cycles in command sequence is determined by number of bytes written to write buffer. Maximum number of cycles in command sequence is 37, including "Program Buffer to Flash" command. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. Unlock Bypass command is required prior to Unlock Bypass Program command. 15. Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode. 16. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only during a sector erase operation. 17. Erase Resume command is valid only during Erase Suspend mode. 5. 6. 7. 8. 9. 34 Am29LV640MH/L December 14, 2005 DATASHEET WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 20 in the AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase December 14, 2005 Am29LV640MH/L 35 DATASHEET START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 8. Data# Polling Algorithm 36 Am29LV640MH/L December 14, 2005 DATASHEET RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. December 14, 2005 Am29LV640MH/L 37 DATASHEET START Read DQ7–DQ0 Read DQ7–DQ0 Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 9. Toggle Bit Algorithm whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ6. Figure 9 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 21 shows the toggle bit timing diagram. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish 38 Am29LV640MH/L December 14, 2005 DATASHEET Figure 22 shows the differences between DQ2 and DQ6 in graphical form. grammed to “0.” O nly an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). Reading Toggle Bits DQ6/DQ2 Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 relative to the other status bits. DQ5: Exceeded Timing Limits DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Programming section for more details. December 14, 2005 Am29LV640MH/L 39 DATASHEET Table 10. Write Operation Status DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/BY# 0 0 1 1 N/A Data Toggle Toggle Toggle 0 0 0 N/A N/A N/A N/A N/A N/A N/A 0 1 Toggle N/A 1 1 0 0 0 Standard Mode Program Suspend Mode Erase Suspend Mode Write-toBuffer DQ7 Status (Note 2) Embedded Program Algorithm DQ7# Embedded Erase Algorithm 0 Program-Suspended Program- Sector Suspend Non-Program Read Suspended Sector Erase-Suspended 1 EraseSector Suspend Non-Erase Suspended Read Sector Erase-Suspend-Program DQ7# (Embedded Program) Busy (Note 3) DQ7# Abort (Note 4) DQ7# Invalid (not allowed) Data No toggle 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation. 40 Am29LV640MH/L December 14, 2005 DATASHEET ABSOLUTE MAXIMUM RATINGS Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . .–0.5 V to +12.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 10. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 11. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns +0.8 V –0.5 V –2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns Figure 10. Maximum Negative Overshoot Waveform Figure 11. Maximum Positive Overshoot Waveform OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7–3.6 V VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6 V Notes: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. See Ordering Information section for valid VCC/VIO range combinations. The I/Os will not operate at 3 V when VIO = 1.8 V. December 14, 2005 Am29LV640MH/L 41 DATASHEET DC CHARACTERISTICS CMOS Compatible Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL1 VIH1 VIL2 VIH2 VHH VID VOL VOH1 VOH2 VLKO Low VCC Lock-Out Voltage (10) Parameter Description (Notes) Input Load Current (1) A9, ACC Input Load Current Reset Leakage Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VCC = VCC max; RESET# = 12.5 V VOUT = VSS to VCC, VCC = VCC max 5 MHz VCC Active Read Current (2, 3) VCC Initial Page Read Current (2, 3) VCC Intra-Page Read Current (2, 3) VCC Active Write Current (3, 4) VCC Standby Current (3) VCC Reset Current (3) Automatic Sleep Mode (3, 5) Input Low Voltage 1(6, 7) Input High Voltage 1 (6, 7) Input Low Voltage 2 (6, 8) Input High Voltage 2 (6, 8) Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V CE# = VIL, OE# = VIH, CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE#, RESET# = VCC ± 0.3 V, WP# = VIH RESET# = VSS ± 0.3 V, WP# = VIH VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH –0.5 1.9 –0.5 1.9 11.5 11.5 1 MHz 15 15 30 10 50 1 1 1 Min Typ Max ±1.0 35 35 ±1.0 20 mA 20 50 20 60 5 5 5 0.8 VCC + 0.5 0.3 x VIO VIO + 0.5 12.5 12.5 0.15 x VIO 0.85 VIO VIO–0.4 2.3 2.5 mA mA mA µA µA µA V V V V V V V V V V Unit µA µA µA µA Voltage for Autoselect and Temporary Sector VCC = 2.7 –3.6 V Unprotect Output Low Voltage (9) Output High Voltage IOL = 4.0 mA, VCC = VCC min = VIO IOH = –2.0 mA, VCC = VCC min = VIO IOH = –100 µA, VCC = VCC min = VIO Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. 3. 4. 5. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V. VCC voltage requirements. VIO voltage requirements. Includes RY/BY# 7. 8. 9. 10. Not 100% tested. 42 Am29LV640MH/L December 14, 2005 DATASHEET TEST CONDITIONS Table 11. Test Specifications All Speeds 1 TTL gate 30 5 0.0–3.0 1.5 0.5 VIO Unit 3.3 V Device Under Test CL 6.2 kΩ 2.7 kΩ Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels pF ns V V V Note: If VIO < VCC, the reference level is 0.5 VIO. Note: Diodes are IN3064 or equivalent Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS 3.0 V 0.0 V Input 1.5 V Measurement Level 0.5 VIO V Output Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 13. Input Waveforms and Measurement Levels December 14, 2005 Am29LV640MH/L 43 DATASHEET AC CHARACTERISTICS Read-Only Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tRC Description Read Cycle Time (Note 1) CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min 90R 90 90 90 25 25 101, 101R 100 100 100 30 30 30 30 16 16 0 0 10 Speed Options 112R 110 110 110 40 40 30 30 112 120R 120 120 120 40 40 120 Unit ns ns ns ns ns ns ns ns ns ns tACC Address to Output Delay tCE tOE tDF tDF tOH tOEH Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Read Output Enable Hold Toggle and Time (Note 1) Data# Polling tPACC Page Access Time Notes: 1. Not 100% tested. 2. See Figure 12 and Table 13 for test specifications. 3. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC 0V Figure 14. Read Operation Timings 44 Am29LV640MH/L December 14, 2005 DATASHEET AC CHARACTERISTICS A21-A2 Same Page A1-A0 Aa tACC Ab tPACC Ac tPACC tPACC Ad Data Bus CE# OE# Qa Qb Qc Qd * Figure shows device in word mode. Addresses are A1–A-1 for byte mode. Figure 15. Page Read Timings December 14, 2005 Am29LV640MH/L 45 DATASHEET AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. tReady tReady tRP tRH tRPD tRB Notes: 1. Not 100% tested. 2. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Input Low to Standby Mode RY/BY# Output High to CE#, OE# pin Low All Speed Options Max Max Min Min Min Min 20 500 500 50 20 0 Unit μs ns ns ns µs ns RY/BY# CE#f, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#f, OE# RESET# tRP Figure 16. Reset Timings 46 Am29LV640MH/L December 14, 2005 DATASHEET AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Single Word/Byte Program Operation (Note 2, 5) Single Word/Byte Accelerated Programming Operation (Note 2, 5) tWHWH2 tWHWH2 tVHH tVCS tBUSY tPOLL Notes: 1. 2. 3. 4. 5. Not 100% tested. See the “Erase and Programming Performance” section for more information. For 1–16 words/1–32 bytes programmed. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. 7. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO VCC. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Speed Options 90R Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ 90 101, 101R 100 0 15 45 0 45 0 20 0 0 0 35 30 352 11 22 8.8 17.6 100 100 90 90 0.5 250 50 90 100 4 110 120 112, 112R 110 120, 120R 120 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs µs µs µs µs µs µs µs sec ns µs ns µs Per Byte Per Word Per Byte Per Word Byte Word Byte Word tWHWH1 tWHWH1 Typ Typ Min Min Min Max Sector Erase Operation (Note 2) VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) WE# High to RY/BY# Low Program Valid Before Status Polling (Note 7) ≠ December 14, 2005 Am29LV640MH/L 47 DATASHEET AC CHARACTERISTICS Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tPOLL tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles) tCH A0h VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. ILLUSTRATION SHOWS DEVICE IN WORD MODE. Figure 17. VHH Program Operation Timings ACC VIL or VIH tVHH tVHH VIL or VIH Figure 18. Accelerated Program Timing Diagram 48 Am29LV640MH/L December 14, 2005 DATASHEET AC CHARACTERISTICS Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase In Progress Complete tBUSY RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”. 2. Illustration shows device in word mode. tRB Figure 19. Chip/Sector Erase Operation Timings December 14, 2005 Am29LV640MH/L 49 DATASHEET AC CHARACTERISTICS tRC Addresses tPOLL CE# tCH OE# tOEH WE# tOH DQ15 and DQ7 Complement Complement True Valid Data High Z VA tACC tCE VA VA tOE tDF DQ14–DQ8, DQ6–DQ0 tBUSY RY/BY# Status Data Status Data True Valid Data High Z Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Data# Polling Timings (During Embedded Algorithms) 50 Am29LV640MH/L December 14, 2005 DATASHEET AC CHARACTERISTICS tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status tAS tCEPH tOE Valid Status Valid Status Valid Data (first read) RY/BY# (second read) (stops toggling) Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 21. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 22. DQ2 vs. DQ6 December 14, 2005 Am29LV640MH/L 51 DATASHEET AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std tVIDR tRSP Notes: 1. Not 100% tested. 2. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect All Speed Options 500 4 Unit ns µs Min Min VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR VID VSS, VIL, or VIH WE# tRSP RY/BY# tRRB Figure 23. Temporary Sector Group Unprotect Timing Diagram 52 Am29LV640MH/L December 14, 2005 DATASHEET AC CHARACTERISTICS VID VIH RESET# SA, A6, A3, A2, A1, A0 Data 60h Valid* Sector Group Protect or Unprotect 60h Sector Group Protect: 150 µs, Sector Group Unprotect: 15 ms Valid* Verify 40h Valid* Status 1 µs CE# WE# OE# Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.N Figure 24. Sector Group Protect and Unprotect Timing Diagram December 14, 2005 Am29LV640MH/L 53 DATASHEET AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Per Byte Effective Write Buffer Program Operation (Notes 2, 4) Per Word Per Byte Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Word Byte Single Word/Byte Program Operation (Note 2, 5) Word Single Word/Byte Accelerated Byte Programming Operation (Note 2, Word 5) Sector Erase Operation (Note 7) RESET# High Time Before Write Program Valid Before Status Polling (Note 7) Speed Options 101, 112, 120, 90R 101R 112R 120R 90 100 110 120 0 45 45 0 0 0 0 45 30 352 11 22 8.8 17.6 100 100 90 90 0.5 50 4 Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Typ Typ Min Max Unit ns ns ns ns ns ns ns ns ns ns µs µs µs µs µs µs µs µs µs sec ns µs tWHWH1 tWHWH1 tWHWH2 tWHWH2 tRH tPOLL Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. 54 Am29LV640MH/L December 14, 2005 DATASHEET AC Characteristics 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tPOLL tWHWH1 or 2 tBUSY DQ7#, DQ15 DOUT RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 4. Illustration shows device in word mode. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings December 14, 2005 Am29LV640MH/L 55 DATASHEET ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Single Word/Byte Program Time (Note 3) Accelerated Single Word/Byte Program Time (Note 3) Total Write Buffer Program Time (Note 4) Effective Write Buffer Program Time (Note 5) Total Accelerated Effective Write Buffer Program Time (Note 4) Effective Accelerated Write Buffer Program Time (Note 4) Chip Program Time, using the Write Buffer Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. Per Byte Per Word Per Byte Per Word Byte Word Byte Word Typ (Note 1) 0.5 64 100 100 90 90 352 11 22 282 8.8 17.6 92 Max (Note 2) 15 128 800 800 720 720 1800 57 113 1560 49 98 170 Unit sec sec µs µs µs µs µs µs µs µs µs µs sec Comments Excludes 00h programming prior to erasure (Note 6) Excludes system level overhead (Note 7) 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 8 and 9 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min –1.0 V –1.0 V –100 mA Max 12.5 V VCC + 1.0 V +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN AND BGA PACKAGE CAPACITANCE Parameter Symbol CIN COUT CIN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 TSOP Fine-pitch BGA TSOP Fine-pitch BGA TSOP Fine-pitch BGA Typ 6 4.2 8.5 5.4 7.5 3.9 Max 7.5 5.0 12 6.5 9 4.7 Unit pF pF pF pF pF pF DATA RETENTION Parameter Description Minimum Pattern Data Retention Time Test Conditions 150°C 125°C Min 10 20 Unit Years Years 56 Am29LV640MH/L December 14, 2005 DATASHEET PHYSICAL DIMENSIONS TS056/TSR056—56-Pin Standard and Reverse Pinout Thin Small Outline Package (TSOP) PACKAGE JEDEC SYMBOL A A1 A2 b1 b c1 c D D1 E e L O TS/TSR 56 MO-142 (B) EC MIN. --0.05 0.95 0.17 0.17 0.10 0.10 19.90 18.30 13.90 0.50 0˚ 0.08 NOM. ----1.00 0.20 0.22 ----20.00 18.40 14.00 0.50 BASIC 0.60 3˚ --56 0.70 5˚ 0.20 MAX. 1.20 0.15 1.05 0.23 0.27 0.16 0.21 20.20 18.50 14.10 NOTES: 1 2 3 4 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm. THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3160\38.10A 5 6 7 8. 9 R N December 14, 2005 Am29LV640MH/L 57 DATASHEET PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package 58 Am29LV640MH/L December 14, 2005 DATASHEET REVISION SUMMARY Revision A (March 19, 2002) Initial release as abbreviated Advance Information data sheet. This document contains information that was previously released in publication number 25301. Ordering Information The package marking for the Fortified BGA option has been updated. Physical Dimensions Added drawing that shows both TS056 and TSR056 specifications. Revision D+1 (September 10, 2002) Product Selector Guide Added Note 2. Ordering Information Added Note 1. Sector Erase Command Sequence Deleted statement that describes the outcome of when the Embedded Erase operation is in progress. Revision E (December 5, 2002) Product Selector Guide and Read-Only Characteristics Added a 30 ns option to tPACC and tOE standard for the 112R and 120R speed options. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Noted that the SecSi Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed CFI website address Figure 6. Program Suspend/Program Resume Change wait time to 15 μs. CMOS Compatible Added ILR row to table. Changed VIH1 and VIH2 minimum to 1.9. Removed typos in notes. Hardware Reset, CMOS Tables, Erase and Program Operations, Temporary Sector Unprotect, and Alternate CE# Controlled Erase and Program Operations Added Note. Revision B (April 26, 2002) Expanded data sheet to full specification version. Revision C (May 23, 2002) Changed packaging from 63-ball FBGA to 64-ball Fortified BGA. Changed Block Diagram: Moved VIO from RY/BY# to Input/Output Buffers. Changed note about WP#/ACC pin to indicate internal pullup to VCC. Modified Table 4: Sector Group Protection/Unprotection Address Table. Changed 47h Address data from 0004h to 0001h in Table 9. Revision D (August 8, 2002) Alternate CE# Controlled Erase and Program Operations Added tRH parameter to table. Erase and Program Operations Added tBUSY parameter to table. TSOP and BGA PIN Capacitance Added the FBGA package. Program Suspend/Program Resume Command Sequence Changed 15 μs typical to maximum and added 5 μs typical. Erase Suspend/Erase Resume Commands Changed typical from 20 μs to 5 μs and added a maximum of 20 μs. Special package handling instructions Modified the special handling wording. DC Characteristics table Deleted the Iacc specification row. CFI Changed text in the third paragraph of CFI to read “reading array data.” Revision E+1 (February 16, 2003) Distinctive Characteristics Corrected performance characteristics. December 14, 2005 Am29LV640MH/L 59 DATASHEET Product Selector Guide Added note 2. Ordering Information Corrected Valid Combinations table. Added Note. AC Characteristics Removed 90, 90R speed option. Added Note Input values in the tWHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previously TBD. Also, added note 5. Input values in the tWHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Options table that were previously TBD. Also, added note 5. Erase and Programming Performance Input values into table that were previously TBD. Added notes 3 and 4. DC Characteristics table Corrected note reference number on VOL specification. Hardware Reset (RESET#) Added tRB specification to table. Revision F+1 (February 17, 2004) Erase Suspend/Erase Resume Commands Added note (last paragraph) in reference to erase operation. AC Characteristics - Erase and Program Operations, and Alternate CE# Controlled Erase and Program Operations Added tPOLL information. AC Characteristics - Program Operation Timings, Data# Polling Timings, and Alternate CE# Controlled Write (Erase/Program) Operation Timings Updated figures to show tPOLL information. Trademarks Updated. Revision E+2 (June 11, 2003) Ordering Information Added 90R speed grade, modified note. Erase and Programming Performance Modified table, supplied values for Typical. Revision F+2 (August 23, 2004) Added Max programming specifications. Added notation referencing superseding documentation. Revision F (August 14, 2003) Global Converted document to new Spansion template. Ordering Information Added note for ordering and marking information related to “N” (factory-protected SecSi Sector) devices. Command Definitions Corrected Program Erase/Suspend addressing from BA to don’t care. Revision F+3 (December 14, 2005) Global This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M H/L and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Trademarks Copyright © 2002-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 60 Am29LV640MH/L December 14, 2005