MB84VD22191FM-70

FUJITSU SEMICONDUCTOR DATA SHEET DS05-50229-2E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 32M (×16) FLASH MEMORY & 4M (×16) STATIC RAM MB84VD22181FM-70/MB84VD22191FM-70 s FEATURES • Power Supply Voltage of 2.7 V to 3.1 V • High Performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM) • Operating Temperature –30 °C to +85 °C • Package 56-ball FBGA (Continued) s PRODUCT LINE UP Part No. Supply Voltage(V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MB84VD22181FM/VD22191FM VCCf= 3.0 V 70 70 30 +0.1 V –0.3 V VCCs= 3.0 V 70 70 35 +0.1 V –0.3 V Note: Both VCCf and VCCs must be in recommended operation range when either part is being accessed. s PACKAGE 56-ball plastic FBGA (BGA-56P-M03) MB84VD22181FM/VD22191FM-70 (Continued) — FLASH MEMORY • Simultaneous Read/Write Operations (Dual Bank) • FlexBankTM *1 Bank A : 4 Mbit (8 KB × 7 and 64 KB × 7) Bank B : 12 Mbit (64 KB × 24) Bank C : 12 Mbit (64 KB × 24) Bank D : 4 Mbit (64 KB × 8) Two virtual Banks are chosen from the combination of four physical banks Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program • Minimum 100,000 Write/Erase Cycles • Sector Erase Architecture Eight 4K word and sixty-three 32K word sectors in word mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD22181: Top sector MB84VD22191: Bottom sector • Embedded EraseTM *2 Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCCf Write Inhibit ≤ 2.5 V • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection status. At VIH, allows removal of boot sector protection At VACC, increases program performance • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to “MBM29DL32TF/BF” Datasheet in Detailed Function — SRAM • Power Dissipation Operating : 40 mA Max Standby : 10 µA Max • Power Down Features using CE1s and CE2s • Data Retention Supply Voltage: 1.5 V to 3.1 V • CE1s and CE2s Chip Select • Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8) *1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84VD22181FM/VD22191FM-70 s PIN ASSIGNMENT (Top View) Marking side B8 A15 A7 A11 A6 A8 A5 WE A4 B7 A12 B6 A19 B5 CE2s B4 C8 N.C. C7 A13 C6 A9 C5 A20 C4 RY/BY C3 A18 C2 A5 C1 A2 D8 N.C. D7 A14 D6 A10 E8 A16 E7 N.C. E6 DQ6 F8 N.C. F7 DQ15 F6 DQ13 F5 DQ4 F4 DQ3 G8 Vss G7 DQ7 G6 DQ12 G5 Vccs G4 Vccf G3 DQ10 G2 DQ0 G1 CE1s H7 DQ14 H6 DQ5 H5 N.C. H4 DQ11 H3 DQ2 H2 DQ8 WP/ACC RESET A3 LB A2 A7 B3 UB B2 A6 B1 A3 D3 A17 D2 A4 D1 A1 E3 DQ1 E2 VSS E1 A0 F3 DQ9 F2 OE F1 CEf (BGA-56P-M03) 3 MB84VD22181FM/VD22191FM-70 s PIN DESCRIPTION Pin Name A17 to A0 A20 to A18 DQ15 to DQ0 CEf CE1s CE2s OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCs Function Address Inputs (Common) Address Inputs (Flash) Data Inputs / Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin / Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) Input/Output I I I/O I I I I I O I I I I — Power Power Power 4 MB84VD22181FM/VD22191FM-70 s BLOCK DIAGRAM VCCf A20 to A0 A20 to A0 VSS RY/BY WP/ACC RESET CEf 32 M bit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs A17 to A0 DQ15 to DQ0 VSS LB UB WE OE CE1s CE2s 4 M bit Static RAM 5 MB84VD22181FM/VD22191FM-70 s DEVICE BUS OPERATIONS • User Bus Operations Operation*1, *3 CEf CE1s CE2s OE H X L H X H X H X X L H X L X L X L WE LB UB WP/ DQ7 to DQ0 DQ15 to DQ8 RESET ACC *5 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H X H X Full Standby H X H X H X H X H X X H X X X H X H Output Disable L Read from Flash*2 L L H X X DOUT DOUT H X Write to Flash L H L X L X L L H L L H X X DIN DOUT High-Z DOUT DIN High-Z DIN X High-Z DIN DOUT DOUT High-Z DIN DIN High-Z X High-Z X H X Read from SRAM H L H L H H L L H X Write to SRAM H L H X L H L H X Temporary Sector Group Unprotection*4 Flash Hardware Reset X X X H X X X L X X X X X X VID L X X X L Boot Block Sector Write X X X X X X X X Protection Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. 6 MB84VD22181FM/VD22191FM-70 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCs Supply *1 RESET * 2 3 Symbol Tstg TA VIN, VOUT VCCf, VCCs VIN VIN Rating Min –55 –30 –0.3 –0.3 –0.5 –0.5 Max +125 +85 VCCf + 0.3 VCCs + 0.4 +3.3 +13.0 +10.5 Unit °C °C V V V V V WP/ACC * *1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns. *2 : Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol TA Vccf, Vccs Value Min –30 +2.7 Max +85 +3.1 Unit °C V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 7 MB84VD22181FM/VD22191FM-70 s ELACTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Flash VCC Active Current (Read) *1 Flash VCC Active Current (Program/Erase) *2 Flash VCC Active Current (Read-While-Program)*5 Flash VCC Active Current (Read-While-Erase) *5 Flash VCC Active Current (Erase-Suspend-Program) ACC Input Leakage Current SRAM VCC Active Current Symbol ILI ILO ILIT ICC1f ICC2f ICC3f ICC4f ICC5f ILIA ICC1s Test Conditions VIN = VSS to VCCf, VCCs VOUT = VSS to VCCf, VCCs VCCf = VCCf Max, VCCs = VCCs Max, RESET = 12.5 V CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCf = VCCf Max, VCCs = VCCs Max, WP/ACC = VACC Max VCCs = VCCs Max, CE1s = VIL, CE2s = VIH tCYCLE =10 MHz tCYCLE = 5 MHz tCYCLE = 1 MHz Value Min –1.0 –1.0 — — — — — — — — — — — — — Typ — — — — — — — — — — — — — — — Max +1.0 +1.0 35 18 4 25 43 43 25 20 40 40 8 5 5 Unit µA µA µA mA mA mA mA mA mA mA mA mA mA µA µA µA SRAM VCC Active Current ICC2s tCYCLE = 10 MHz CE1s = 0.2 V, CE2s = VCCs – 0.2 V tCYCLE = 1 MHz VCCf = VCCf Max, CEf = VCCf ± 0.3 V RESET = VCCf ± 0.3 V, WP/ACC = VCCf± 0.3 V VCCf = VCCf Max, RESET = VSS ± 0.3 V, WP/ACC = VCCf± 0.3 V VCCf = VCCf Max, CEf = VSS ± 0.3 V RESET = VCCf ± 0.3 V, WP/ACC = VCCf± 0.3 V VIN = VCCf± 0.3 V or VSS ± 0.3 V CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V LB = UB > VCCs–0.2 V or < 0.2V CE1s > VCCs – 0.2 V or < 0.2V, CE2s < 0.2 V LB = UB > VCCs–0.2 V or < 0.2V Flash VCC Standby Current Flash VCC Standby Current (RESET) Flash VCC Current (Automatic Sleep Mode) *3 SRAM VCC Standby Current SRAM VCC Standby Current ISB1f ISB2f ISB3f — — 5 ISB1s ISB2s — — — — 10 10 µA µA (Continued) 8 MB84VD22181FM/VD22191FM-70 (Continued) Parameter Input Low Level Input High Level Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 Voltage for Program Acceleration (WP/ACC) *4 SRAM Output Low Level SRAM Output High Level Flash Output Low Level Flash Output High Level Flash Low VCCf Lock-Out Voltage Symbol VIL VIH Test Conditions — — Value Min –0.3 2.0 Typ — — Max 0.5 VCC+0.3*6 Unit V V VID — 11.5 — 12.5 V VACC VOL VOH VOL VOH VLKO — VCCs = VCCs Min, IOL = 0.1 mA VCCs = VCCs Min, IOH = –0.1 mA VCCf = VCCf Min, IOL = 4.0 mA VCCf = VCCf Min, IOH = –0.1 mA — 8.5 — VCCs–0.1 — VCCs–0.4 2.3 9.0 — — — — — 9.5 0.1 — 0.45 — 2.5 V V V V V V *1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : Applicable for only VCCf applying. *5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6 : VCC indicates lower of VCCf or VCCs. 9 MB84VD22181FM/VD22191FM-70 2. AC CHARACTERISTICS • CE Timing Symbol Parameter JEDEC CE Recover Time • Timing Diagram for alternating SRAM to Flash — Standard tCCR Test Setup — Value Unit Min 0 ns CEf tCCR tCCR CE1s tCCR tCCR CE2s • Flash Characteristics Please refer to “s32M Flash Memory for MCP”. • SRAM Characteristics, Please refer to “s4M SRAM for MCP”. 10 MB84VD22181FM/VD22191FM-70 s 32 M FLASH MEMORY for MCP 1. Flexible Sector-erase Architecture on Flash Memory • Eight 4 K words, and sixty three 32 K words. • Individual-sector, multiple-sector, or bulk-erase capability. SA70 : 8KB (4KW) SA69 : 8KB (4KW) SA68 : 8KB (4KW) SA67 : 8KB (4KW) SA66 : 8KB (4KW) SA65 : 8KB (4KW) SA64 : 8KB (4KW) SA63 : 8KB (4KW) SA62 : 64KB (32KW) SA61 : 64KB (32KW) SA60 : 64KB (32KW) SA59 : 64KB (32KW) SA58 : 64KB (32KW) SA57 : 64KB (32KW) SA56 : 64KB (32KW) SA55 : 64KB (32KW) SA54 : 64KB (32KW) SA53 : 64KB (32KW) SA52 : 64KB (32KW) SA51 : 64KB (32KW) SA50 : 64KB (32KW) SA49 : 64KB (32KW) SA48 : 64KB (32KW) SA47: 64KB (32KW) SA46: 64KB (32KW) SA45: 64KB (32KW) SA44: 64KB (32KW) SA43: 64KB (32KW) SA42: 64KB (32KW) SA41: 64KB (32KW) SA40: 64KB (32KW) SA39: 64KB (32KW) SA38 : 64KB (32KW) SA37 : 64KB (32KW) SA36 : 64KB (32KW) SA35 : 64KB (32KW) SA34 : 64KB (32KW) SA33 : 64KB (32KW) SA32 : 64KB (32KW) SA31 : 64KB (32KW) SA30 : 64KB (32KW) SA29 : 64KB (32KW) SA28 : 64KB (32KW) SA27 : 64KB (32KW) SA26 : 64KB (32KW) SA25 : 64KB (32KW) SA24 : 64KB (32KW) SA23 : 64KB (32KW) SA22 : 64KB (32KW) SA21 : 64KB (32KW) SA20 : 64KB (32KW) SA19 : 64KB (32KW) SA18 : 64KB (32KW) SA17 : 64KB (32KW) SA16 : 64KB (32KW) SA15 : 64KB (32KW) SA14 : 64KB (32KW) SA13 : 64KB (32KW) SA12 : 64KB (32KW) SA11 : 64KB (32KW) SA10 : 64KB (32KW) SA9 : 64KB (32KW) SA8 : 64KB (32KW) SA7 : 64KB (32KW) SA6 : 64KB (32KW) SA5 : 64KB (32KW) SA4 : 64KB (32KW) SA3 : 64KB (32KW) SA2 : 64KB (32KW) SA1 : 64KB (32KW) SA0 : 64KB (32KW) 1FFFFFh 1FF000h 1FE000h 1FD000h 1FC000h 1FB000h 1FA000h 1F9000h 1F8000h 1F0000h 1E8000h 1E0000h 1D8000h 1D0000h 1C8000h 1C0000h 1B8000h 1B0000h 1A8000h 1A0000h 198000h 190000h 188000h 180000h 178000h 170000h 168000h 160000h 158000h 150000h 148000h 140000h 138000h 130000h 128000h 120000h 118000h 110000h 108000h 100000h 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 000000h SA70 : 64KB (32KW) SA69 : 64KB (32KW) SA68 : 64KB (32KW) SA67 : 64KB (32KW) SA66 : 64KB (32KW) SA65 : 64KB (32KW) SA64 : 64KB (32KW) SA63 : 64KB (32KW) SA62 : 64KB (32KW) SA61 : 64KB (32KW) SA60 : 64KB (32KW) SA59 : 64KB (32KW) SA58 : 64KB (32KW) SA57 : 64KB (32KW) SA56 : 64KB (32KW) SA55 : 64KB (32KW) SA54 : 64KB (32KW) SA53 : 64KB (32KW) SA52 : 64KB (32KW) SA51 : 64KB (32KW) SA50 : 64KB (32KW) SA49 : 64KB (32KW) SA48 : 64KB (32KW) SA47 : 64KB (32KW) SA46 : 64KB (32KW) SA45 : 64KB (32KW) SA44 : 64KB (32KW) SA43 : 64KB (32KW) SA42 : 64KB (32KW) SA41 : 64KB (32KW) SA40 : 64KB (32KW) SA39 : 64KB (32KW) SA38 : 64KB (32KW) SA37 : 64KB (32KW) SA36 : 64KB (32KW) SA35 : 64KB (32KW) SA34 : 64KB (32KW) SA33 : 64KB (32KW) SA32 : 64KB (32KW) SA31 : 64KB (32KW) SA30 : 64KB (32KW) SA29 : 64KB (32KW) SA28 : 64KB (32KW) SA27 : 64KB (32KW) SA26 : 64KB (32KW) SA25 : 64KB (32KW) SA24 : 64KB (32KW) SA23 : 64KB (32KW) SA22 : 64KB (32KW) SA21 : 64KB (32KW) SA20 : 64KB (32KW) SA19 : 64KB (32KW) SA18 : 64KB (32KW) SA17 : 64KB (32KW) SA16 : 64KB (32KW) SA15 : 64KB (32KW) SA14 : 64KB (32KW) SA13 : 64KB (32KW) SA12 : 64KB (32KW) SA11 : 64KB (32KW) SA10 : 64KB (32KW) SA9 : 64KB (32KW) SA8 : 64KB (32KW) SA7 : 8KB (4KW) SA6 : 8KB (4KW) SA5 : 8KB (4KW) SA4 : 8KB (4KW) SA3 : 8KB (4KW) SA2 : 8KB (4KW) SA1 : 8KB (4KW) SA0 : 8KB (4KW) 1FFFFFh 1F8000h 1F0000h 1E8000h 1E0000h 1D8000h 1D0000h 1C8000h 1C0000h 1B8000h 1B0000h 1A8000h 1A0000h 198000h 190000h 188000h 180000h 178000h 170000h 168000h 160000h 158000h 150000h 148000h 140000h 138000h 130000h 128000h 120000h 118000h 110000h 108000h 100000h 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h Bank D Bank A Bank C Bank B Bank B Bank C Bank A Bank D (Top Boot Block) (Bottom Boot Block) 11 MB84VD22181FM/VD22191FM-70 FlexBankTM Architecture Table Bank Splits 1 2 3 4 Bank 1 Volume 4 Mbit 12 Mbit 12 Mbit 4 Mbit Combination Bank A Bank B Bank C Bank D Volume 28 Mbit 20 Mbit 20 Mbit 28 Mbit Bank 2 Combination Bank B, C, D Bank A, C, D Bank A, B, D Bank A, B, C Example of Virtual Banks Combination Table Bank 1 Bank Splits Volume Combination Bank 2 Sector Size Volume Combination Bank B + Bank C + Bank D Bank B + Bank C Bank C + Bank D Sector Size 1 4 Mbit Bank A 8 × 8 Kbyte/4 Kword + 7 × 64 Kbyte/32 Kword 28 Mbit 56 × 64 Kbyte/32 Kword 2 8 Mbit Bank A + Bank D Bank A + Bank B 8 × 8 Kbyte/4 Kword + 24 Mbit 15 × 64 Kbyte/32 Kword 8 × 8 Kbyte/4 Kword + 16 Mbit 31 × 64 Kbyte/32 Kword 48 × 64 Kbyte/32 Kword 3 16 Mbit 32 × 64 Kbyte/32 Kword Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D. 12 MB84VD22181FM/VD22191FM-70 Sector Address Table (Top Boot Type) B a Sector n k SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 Sector address Bank address A20 A19 A18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Sector size (Kwords) A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address range B a n k D B a n k C 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) 13 MB84VD22181FM/VD22191FM-70 (Continued) B a Sector n k SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Sector address Bank address A20 A19 A18 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Sector size (Kwords) A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address range B a n k B B a n k A 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh 14 MB84VD22181FM/VD22191FM-70 Sector Address Table (Bottom Boot Type) B a Sector n k SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 Sector address Bank address A20 A19 A18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Sector size (Kwords) A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address range B a n k D B a n k C 1F8000h to 1FFFFFh 1F0000h to 1F7FFFh 1E8000h to 1EFFFFh 1E0000h to 1E7FFFh 1D8000h to 1DFFFFh 1D0000h to 1D7FFFh 1C8000h to 1CFFFFh 1C0000h to 1C7FFFh 1B8000h to 1BFFFFh 1B0000h to 1B7FFFh 1A8000h to 1AFFFFh 1A0000h to 1A7FFFh 198000h to 19FFFFh 190000h to 197FFFh 188000h to 18FFFFh 180000h to 187FFFh 178000h to 17FFFFh 170000h to 177FFFh 168000h to 16FFFFh 160000h to 167FFFh 158000h to 15FFFFh 150000h to 157FFFh 148000h to 14FFFFh 140000h to 147FFFh 138000h to 13FFFFh 130000h to 137FFFh 128000h to 12FFFFh 120000h to 127FFFh 118000h to 11FFFFh 110000h to 117FFFh 108000h to 10FFFFh 100000h to 107FFFh (Continued) 15 MB84VD22181FM/VD22191FM-70 B a Bank Sector n address k A20 A19 A18 SA38 0 1 1 SA37 0 1 1 SA36 0 1 1 SA35 0 1 1 SA34 0 1 1 SA33 0 1 1 SA32 0 1 1 SA31 0 1 1 SA30 0 1 0 SA29 0 1 0 B SA28 0 1 0 a SA27 0 1 0 n SA26 0 1 0 k 0 1 0 B SA25 SA24 0 1 0 SA23 0 1 0 SA22 0 0 1 SA21 0 0 1 SA20 0 0 1 SA19 0 0 1 SA18 0 0 1 SA17 0 0 1 SA16 0 0 1 SA15 0 0 1 SA14 0 0 0 SA13 0 0 0 SA12 0 0 0 SA11 0 0 0 SA10 0 0 0 SA9 0 0 0 B SA8 0 0 0 a SA7 0 0 0 n k SA6 0 0 0 A SA5 0 0 0 SA4 0 0 0 SA3 0 0 0 SA2 0 0 0 SA1 0 0 0 SA0 0 0 0 16 Sector address Sector size (Kwords) A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address range 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh MB84VD22181FM/VD22191FM-70 Sector Group Addresses Table (Top Boot Type) Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 A20 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 X X X SA1 to SA3 A14 X A13 X A12 X Sectors SA0 17 MB84VD22181FM/VD22191FM-70 Sector Group Addresses Table (Bottom Boot Type) Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X SA70 X X X SA67 to SA69 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 X X X SA8 to SA10 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 18 MB84VD22181FM/VD22191FM-70 Sector Group Protection Verify Autoselect Codes Table (Top Boot Type) Type Manufacture’s Code Device Code Extended Device Code Sector Group Protection A20 to A12 BA BA BA BA SA A6 VIL VIL VIL VIL VIL A3 VIL VIL VIH VIH VIL A2 VIL VIL VIH VIH VIL A1 VIL VIL VIH VIH VIH A0 VIL VIH VIL VIH VIL Code (HEX) 04h 227Eh 220Ah 2201h 01h* * : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Expanded Autoselect Code Table (Top Boot Type) Type Manufacture’s Code Device Code Extended Device Code Sector Group Protection Code 04h 227Eh 220Ah 2201h 01h DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 Sector Group Protection Verify Autoselect Codes Table (Bottom Boot Type) Type Manufacture’s Code Device Code Extended Device Code Sector Group Protection A20 to A12 BA BA BA BA SA A6 VIL VIL VIL VIL VIL A3 VIL VIL VIH VIH VIL A2 VIL VIL VIH VIH VIL A1 VIL VIL VIH VIH VIH A0 VIL VIH VIL VIH VIL Code (HEX) 04h 227Eh 220Ah 2200h 01h* * : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Expanded Autoselect Code Table (Bottom Boot Type) Type Manufacture’s Code Device Code Extended Device Code Sector Group Protection Code 04h 227Eh 220Ah 2200h 01h DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 19 MB84VD22181FM/VD22191FM-70 Command Definitions Table Command sequence Read/Reset*1 Read/Reset*1 Autoselect Program Program Suspend Program Resume Chip Erase Sector Erase Erase Suspend Erase Resume Set to Fast Mode Fast Program *2 Reset from Fast Mode *2 Extended Sector Group Protection *3 Query *4 HiddenROM Entry HiddenROM Program *5 HiddenROM Exit *5 Bus First bus write write cycle cycles req’d Addr. Data 1 XXXh F0h 3 555h AAh 3 4 1 1 6 6 1 1 3 2 2 4 1 3 4 4 555h 555h BA BA 555h 555h BA BA 555h XXXh BA XXXh (BA) 55h 555h 555h 555h AAh AAh B0h 30h AAh AAh B0h 30h AAh A0h 90h 60h 98h AAh AAh AAh Second bus write cycle Addr.  2AAh 2AAh 2AAh   2AAh 2AAh   2AAh PA XXXh SPA  2AAh 2AAh 2AAh Data  55h 55h 55h   55h 55h   55h PD F0h*6 60h  55h 55h 55h Third bus write cycle Addr.  555h (BA) 555h 555h   555h 555h   555h   SPA  555h 555h (HRBA) 555h Fourth bus read/write cycle Data Addr. Data    F0h RA RD 90h A0h   80h 80h   20h   40h  88h A0h 90h  PA   555h 555h      SPA   (HRA) PA XXXh  PD   AAh AAh      SD   PD 00h Fifth bus write cycle Addr.       2AAh 2AAh           Data       55h 55h           Sixth bus write cycle Addr.       555h SA           Data       10h 30h           (Continued) 20 MB84VD22181FM/VD22191FM-70 (Continued) *1 : Both of these reset commands are equivalent. *2 : This command is valid during Fast Mode. *3 : This command is valid while RESET = VID. *4 : The valid address are A6 to A0. *5 : This command is valid during HiddenROM mode. *6 : The date “00h” is also acceptable. Notes: • Address bits A20 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector Address (SA) , Bank Address (BA) . • Bus operations are defined in “User Bus Operations Tables” (s DEVICE BUS OPERATION). • RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A20 to A18) • RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. • SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. • HRA = Address of the HiddenROM area Top Boot Type Word Mode : 1FF000h to 1FF07Fh Bottom Boot Type Word Mode : 000000h to 00007Fh • HRBA = Bank Address of the HiddenROM area Top Boot Type : A20 = A19 = A18 = 1 Bottom Boot Type : A20 = A19 = A18 = 0 • The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. • The command combinations not described in “Command Definitions Table” are illegal. 21 MB84VD22181FM/VD22191FM-70 2. AC Characteristics • Read Only Operations Characteristics Symbol Parameter JEDEC Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time from Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode * : Test Conditions: Output Load : 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 0.5 × Vccf Output : 0.5 × Vccf tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX — Standard tRC tACC tCE tOE tDF tDF tOH tREADY Test setup — CEf = VIL OE = VIL OE = VIL — — — — — Value* Unit Min 70      0  Max  70 70 30 25 25  20 ns ns ns ns ns ns ns µs 22 MB84VD22181FM/VD22191FM-70 • Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC tAVAV tAVWL — tWLAX — tDVWH tWHDX — — — tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH2 — 2 2 2 Value Min 70 0 12 45 0 30 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25  50 500 500 4 100 4 4 0 500 200   50  Typ                      0.5               Max                                 90 70  20 tWC tAS tASO tAH tAHT tDS tDH tOEH Standard Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s µs ns ns µs µs µs µs ns ns ns ns ns µs µs CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CEf Setup Time WE Setup Time CEf Hold Time WE Hold Time Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Sector Erase Operation*1 VCCf Setup Time Rise Time to VID * Rise Time to VID * tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP tRB tRP tRH tBUSY tEOE tTOW tSPD — — — — — — — — — — — — — 2 Voltage Transition Time * Write Pulse Width * OE Setup Time to WE Active *2 CEf Setup Time to WE Active *2 Recover Time from RY/BY RESET Pulse Width RESET High Level Period before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-Out Time Erase Suspend Transition Time *1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. 23 MB84VD22181FM/VD22191FM-70 • Read Cycle (Flash) tRC Address Address Stable tACC CEf tOE tDF OE tOEH WE tCEf DQ High-Z Output Valid High-Z tRC Address tACC Address Stable CEf tRH tRP tRH tCEf RESET tOH DQ High-Z Output Valid 24 MB84VD22181FM/VD22191FM-70 • Write Cycle (WE control) (Flash) 3rd Bus Cycle Address 555h tWC tAS PA tAH Data Polling PA tRC CEf tCS tCH tCEf OE tGHWL tWP tWPH tWHWH1 tOE WE tDS tDH tOH DQ A0h PD DQ7 DOUT DOUT Notes : • PA is address of the memory location to be programmed. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. 25 MB84VD22181FM/VD22191FM-70 • Write Cycle (CEf control) (Flash) 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CEf tDS tDH DQ A0h PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. 26 MB84VD22181FM/VD22191FM-70 • AC Waveforms Chip/Sector Erase Operations (Flash) Address 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CEf tCS tCH OE tGHWL tWP tWPH WE tDS tDH AAh 55h 80h AAh 55h 30h for Sector Erase 10h/ 30h DQ tVCS VCCf * : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase. Note : These waveform are for the ×16 mode. 27 MB84VD22181FM/VD22191FM-70 • AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tOE tDF OE tOEH WE tCEf * DQ7 Data In DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 High-Z DQ (DQ6 to DQ0) Data In tBUSY DQ6 to DQ0 = Output Flag DQ8 to DQ0 Valid Data tEOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation.) 28 MB84VD22181FM/VD22191FM-70 • AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Address tAHT tASO tAHT tAS CEf tCEPH WE tOEH tOEPH tOEH OE tDH tOE Toggle Data Toggle Data tCEf * Toggle Data Stop Toggling Output Valid DQ6/DQ2 Data tBUSY RY/BY * : DQ6 stops toggling (The device has completed the Embedded operation). 29 MB84VD22181FM/VD22191FM-70 • Back-to-back Read/Write Timing Diagram (Flash) Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC Address BA1 tAS BA2 (555h) tAH BA1 tACC tCE BA2 (PA) BA1 tAS tAHT BA2 (PA) CEf tOE tCEPH OE tGHWL tWP tOEH tDF WE tDS tDH tDF DQ Valid Output Valid Intput (A0h) Valid Output Valid Intput (PD) Valid Output Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2. 30 MB84VD22181FM/VD22191FM-70 • RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf Rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY • RESET, RY/BY Timing Diagram (Flash) WE RESET tRP tRB RY/BY tREADY 31 MB84VD22181FM/VD22191FM-70 • Temporary Sector Unprotection (Flash) VCCf tVCS VID 3V RESET CEf tVIDR tVLHT 3V WE tVLHT Program or Erase Command Sequence RY/BY Unprotection Period tVLHT 32 MB84VD22181FM/VD22191FM-70 • Extended Sector Group Protection (Flash) VCCf tVCS RESET tVIDR Address tVLHT tWC tWC SGAx SGAx SGAy A0 A1 A6 CEf OE TIME-OUT tWP WE Data 60h 60h 40h tOE 01h 60h SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 33 MB84VD22181FM/VD22191FM-70 • Accelerated Program (Flash) VCCf tVCS VACC 3V WP/ACC tVACCR tVLHT 3V CEf WE tVLHT RY/BY Acceleration period Program Command Sequence tVLHT 34 MB84VD22181FM/VD22191FM-70 3. Erase and Programming Performance Limits Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Program/Erase Cycle    100,000 Typ 0.5 6.0   Max 2.0 100 100  s µs s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead  Unit Comments 35 MB84VD22181FM/VD22191FM-70 s 4 M SRAM for MCP 1. AC Characteristics • Read Cycle (SRAM) Parameter Read Cycle Time Address Access Time Chip Enable (CE1s) Access Time Chip Enable (CE2s) Access Time Output Enable Access Time LB, UB to Output Valid Chip Enable (CE1s Low and CE2s High) to Output Active Output Enable Low to Output Active UB, LB Enable Low to Output Active Chip Enable (CE1s High or CE2s Low) to Output High-Z Output Enable High to Output High-Z UB, LB Output Enable to Output High-Z Output Data Hold Time Note: Test Conditions– Output Load:1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCs Timing measurement reference level Input: 0.5×VCCs Output: 0.5×VCCs Symbol tRC tAA tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Value Min 70 — — — — — 5 0 0 — — — 10 Max — 70 70 70 35 70 — — — 25 25 25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 36 MB84VD22181FM/VD22191FM-70 • Read Cycle (SRAM) tRC Address tAA tCO1 CE1s tCOE tCO2 CE2s tOD tOE OE tOEE tODO tOD tOH LB, UB tBA tBE tCOE DQ Valid Data Output tBD Note: WE remains HIGH for the read cycle. 37 MB84VD22181FM/VD22191FM-70 • Write Cycle (SRAM) Parameter Write Cycle Time Write Pulse Width Chip Enable to End of Write Address valid to End of Write UB, LB to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Symbol tWC tWP tCW tAW tBW tAS tWR tODW tOEW tDS tDH Value Min 70 50 55 55 55 0 0 — 0 30 0 Max — — — — — — — 25 — — — Unit ns ns ns ns ns ns ns ns ns ns ns 38 MB84VD22181FM/VD22191FM-70 • Write Cycle*1 (WE control) (SRAM) tWC Address tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LB, UB tODW tOEW DOUT *2 tDS tDH *3 DIN *4 Valid Data Input *4 *1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance. *2 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. *3 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. *4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 39 MB84VD22181FM/VD22191FM-70 • Write Cycle*1 (CE1s control) (SRAM) tWC Address tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LB, UB tBE tCOE DOUT tDS tDH tODW DIN *2 Valid Data Input *2 *1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 40 MB84VD22181FM/VD22191FM-70 • Write Cycle *1 (CE2s Control) (SRAM) tWC Address tAS tWP tWR WE tCW CE1s tAW CE2s tCW tBW LB, UB tBE tCOE DOUT tDS DIN *2 tDH tODW Valid Data Input *2 *1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 41 MB84VD22181FM/VD22191FM-70 • Write Cycle *1 (LB, UB Control) (SRAM) tWC Address tWP WE tWR tCW CE1s tCW CE2s tAW tAS tBW LB, UB tBE tCOE DOUT tDS *2 tDH *2 tODW DIN Valid Data Input *1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 42 MB84VD22181FM/VD22191FM-70 2. Data Retention Characteristics (SRAM) Parameter Data Retention Supply Voltage Standby Current Chip Deselect to Data Retention Mode Time Recovery Time Note : tRC: Read cycle time • CE1s Controlled Data Retention Mode *1 VCCs 2.7 V Data Retention Mode Symbol VDH VDH = 3.0 V IDDS2 tCDR tR Value Min 1.5 — 0 tRC Typ — — — — Max 3.1 10 — — Unit V µA ns ns VIH VDH CE1s *2 *2 VCCs – 0.2 V tCDR tR GND *1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to Vccs+0.3 V. *2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition of VCCs from VCCs Max to VIH Min level. • CE2s Controlled Data Retention Mode * VCCs Data Retention Mode 2.7 V VDH VIH CE2s VIL tCDR tR 0.2 V GND * : In CE2s controlled data retention mode, input and input/output pins can be used between –0.3 V to Vccs+0.3 V. 43 MB84VD22181FM/VD22191FM-70 s PIN CAPACITANCE Value Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup Typ VIN = 0 VOUT = 0 VIN = 0 VIN = 0 11 12 14 21.5 Max 14 16 16 26 pF pF pF pF Unit Note : Test conditions TA = + 25°C, f = 1.0 MHz s HANDLING OF PACKAGE Please handle this package carefully since the sides of package create acute angles. s CAUTION • The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. • Without the high voltage (VID) , sector group protection can be achieved by using “Extended Sector Group Protection” command. 44 MB84VD22181FM/VD22191FM-70 s ORDERING INFORMATION MB84VD2218 1 FM -70 PBS PACKAGE TYPE PBS = 56-ball FBGA SPEED OPTION See Product Selector Guide Device Revision Bank Architecture 1 = 4Mbit / 12Mbit / 12Mbit / 4Mbit (Flex Bank) DEVICE NUMBER/DESCRIPTION 32Mega-bit (2M × 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 4Mega-bit (256K × 16-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2218 = Top sector 84VD2219 = Bottom sector 45 MB84VD22181FM/VD22191FM-70 s PACKAGE DIMENSION 56-ball plastic FBGA (BGA-56P-M03) 9.00±0.10(.354±.004) 1.2(.047) (Mounting height) MAX. 0.30±0.10 (Stand off) (.012±.004) 5.60(.220) 0.80 (.031) 8 7 6 5 4 3 2 1 KJHGFEDCBA 7.00±0.10 (.276±.004) 5.60(.220) 0.80 (.031) INDEX-MARK AREA 56-ø0.45 56-ø.018 +0.10 –0.05 +.004 –.002 0.08(.003) M 0.10(.004) C 2002 FUJITSU LIMITED BGA560030Sc-1-1 Dimensions in mm (inches) Note: The values in parentheses are reference values. 46 MB84VD22181FM/VD22191FM-70 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0311 © FUJITSU LIMITED Printed in Japan